U.S. patent application number 10/785094 was filed with the patent office on 2004-08-26 for noise eliminating system on chip and method of making same.
This patent application is currently assigned to VIA TECHNOLOGIES INC.. Invention is credited to Yang, Chih An.
Application Number | 20040164408 10/785094 |
Document ID | / |
Family ID | 21688327 |
Filed Date | 2004-08-26 |
United States Patent
Application |
20040164408 |
Kind Code |
A1 |
Yang, Chih An |
August 26, 2004 |
Noise eliminating system on chip and method of making same
Abstract
A noise eliminating system on chip and method of fabricating the
same are provided. A noise eliminating system is connected to a
chip. There are guiding units provided on the chip for connecting
with the noise eliminating system, thereby reducing simultaneous
switching noise of the chip.
Inventors: |
Yang, Chih An; (Hsin Tien
City, TW) |
Correspondence
Address: |
BIRCH STEWART KOLASCH & BIRCH
PO BOX 747
FALLS CHURCH
VA
22040-0747
US
|
Assignee: |
VIA TECHNOLOGIES INC.
|
Family ID: |
21688327 |
Appl. No.: |
10/785094 |
Filed: |
February 25, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10785094 |
Feb 25, 2004 |
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10407231 |
Apr 7, 2003 |
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6756664 |
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Current U.S.
Class: |
257/724 ;
257/738; 257/782; 257/784; 257/E23.114; 257/E25.029 |
Current CPC
Class: |
H01L 23/3128 20130101;
H01L 2224/85399 20130101; H01L 2224/73265 20130101; H01L 2924/19104
20130101; H01L 2224/45099 20130101; H01L 2924/00014 20130101; H01L
2924/00012 20130101; H01L 2224/32225 20130101; H01L 2924/00014
20130101; H01L 2924/00012 20130101; H01L 2924/00 20130101; H01L
2224/32225 20130101; H01L 2224/48227 20130101; H01L 2924/207
20130101; H01L 2224/73265 20130101; H01L 2224/48227 20130101; H01L
2224/45015 20130101; H01L 2924/00014 20130101; H01L 2224/32225
20130101; H01L 2224/85399 20130101; H01L 2924/15311 20130101; H01L
2224/45099 20130101; H01L 2224/05599 20130101; H01L 2924/181
20130101; H01L 2924/30107 20130101; H01L 2224/48227 20130101; H01L
2924/00014 20130101; H01L 24/73 20130101; H01L 2224/05599 20130101;
H01L 2924/15311 20130101; H01L 23/552 20130101; H01L 2924/181
20130101; H01L 2924/19105 20130101; H01L 2924/00014 20130101; H01L
2924/3011 20130101; H01L 2924/19041 20130101; H01L 25/16 20130101;
H01L 2224/73265 20130101; H01L 24/48 20130101; H01L 2924/15184
20130101 |
Class at
Publication: |
257/724 ;
257/738; 257/782; 257/784 |
International
Class: |
H01L 029/00; H01L
023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 22, 2002 |
TW |
91134103 |
Claims
What is claimed is:
1. A noise eliminating system on chip, comprising: a chip; and at
least one noise eliminating system built in on a surface of the
chip.
2. The noise eliminating system on chip as claimed in claim 1
wherein the noise eliminating system is a de-coupling
capacitor.
3. A noise eliminating system on chip, comprising: a chip; and at
least one noise eliminating system built in on a surface of the
chip; wherein the noise eliminating system has two terminals which
are electrically connected to guiding devices on the upper layer of
the chip and are electrically connected to power supply unit and
grounding unit of the chip respectively.
4. A noise eliminating system on chip, comprising: a chip; and at
least one noise eliminating system built in on a surface of the
chip; wherein the two terminals of the noise eliminating system are
electrically connected to an additional guiding device on the chip
and are connected to respective power supply and grounding.
5. The noise eliminating system on chip as claimed in claim 4
wherein the additional guiding device on the chip is a
redistribution layer.
Description
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is a Divisional of co-pending application
Ser. No. 10/407,231, filed on Apr. 7, 2003, the entire contents of
which are hereby incorporated by reference and for which priority
is claimed under 35 U.S.C. .sctn. 120; and this application claims
priority of Application No. 091134103 filed in Taiwan, R.O.C. on
Nov. 22, 2002 under 35 U.S.C. .sctn. 119.
FIELD OF THE INVENTION
[0002] The present invention relates to a packaged chip or die with
a noise-suppressing system. More particularly, the present
invention relates to a noise-suppressing system, which is
electrically connected to a chip, capable of reducing or
eliminating excess noise.
DESCRIPTION OF THE PRIOR ART
[0003] Please refer to FIG. 1. FIG. 1 illustrates a cross section
of a conventional leadframe package structure 10 mounted on a
printed circuit board 11. The printed circuit board 11 comprises an
upper surface 12 and a lower surface 13. For a four-layer printed
circuit board 11, the upper surface 12 and the lower surface 13 may
be one of the power supply layer, grounded layer, signal layer, or
device layer. Passive components 14 and 15 are mounted on either
upper surface 12 or lower surface 13 by surface mount technology
(SMT) known in the art. For example, the passive components 14 and
15 may be de-coupling capacitors used to reduce or eliminate
undesired coupling between circuits or simultaneous switching noise
(SSN) between the power supply layer and the grounded layer of a
high-frequency circuit.
[0004] Please refer to FIG. 2. FIG. 2 is a cross-sectional view of
a prior art ball grid array (BGA) package 20. As shown in FIG. 2, a
trace 22 is provided in a substrate 21 of the BGA package 20. A
chip 23 is mounted on the substrate 21 and is connected with the
trace 22 of the substrate 21 via a wire bonding 24. A passive
component 14 is mounted on an upper surface of the substrate 21 by
SMT. The chip 23 and the passive component 14 on the substrate 21
are encapsulated with encapsulant 25. Again, the passive component
14 may be a de-coupling capacitor used to reduce or eliminate
undesired coupling between circuits or SSN between the power supply
layer and the grounded layer of a high-frequency circuit.
[0005] Typically, the de-coupling capacitor is preferably mounted
in the proximity of the chip 23 to enhance the performance of the
de-coupling capacitor to reduce SSN of the chip 23. However, as the
prior art examples shown in FIG. 1 and FIG. 2, the chip 23 and the
de-coupling capacitor(s) are rested on the substrate 21 or the
printed circuit board 11. In such case, referring to FIG. 3, the
efficiency of the de-coupling capacitor is reduced by the
accumulated inductance and resistance in the coupling path. This
causes a significant performance reducing of the de-coupling
capacitor. Further, with reference to FIG. 1, in practice, the
passive components 14 and 15 occupy a portion of the area of the
upper surface 12 or the lower surface 13 of the printed circuit
board 11. With reference to FIG. 2, the passive component 14 is
disposed on the substrate 21. Under the above-described
circumstance, when the number of the passive components 14 and 15
increases, there will be no more capacity for additional bonding
route or other devices on the printed circuit board 11 or on the
substrate 21. In other words, the prior art packaging geometry
limits the possibility of shrinking the dimension of the printed
circuit board 11 or the substrate 21.
[0006] Thus, there is a strong need for an improved chip package,
which is reliable, cost-effective and is capable of effectively
eliminating SSN.
SUMMARY OF THE INVENTION
[0007] Accordingly, the main object of the invention is to provide
an improved chip package in combination with a noise-eliminating
system and a fabrication method thereof to solve the
above-mentioned problems. The noise eliminating system is mounted
on the upper surface of the chip, such that the noise eliminating
system can approach the power supply unit and the grounding unit as
close as possible, thereby enhancing the performance of the passive
component.
[0008] Another object of the present invention is to provide a
noise eliminating system on chip and method of making the same to
minimize the number of devices needed to be installed between the
chip and the noise eliminating system, thereby decreasing
accumulated impedance caused by high-frequency circuit between the
chip and the noise eliminating system, thereby enhancing the
performance of the passive component.
[0009] Still another object of the present invention is to provide
a noise eliminating system on chip and method of making the same,
in which the noise eliminating system is directly mounted on the
upper surface of the chip, thereby saving a great deal of substrate
space and making it possible to shrink the size of the printed
circuit board or the substrate, and thus reduce the cost.
[0010] To achieve the above goals, a noise eliminating system on
chip and method of fabricating the same are provided. A noise
eliminating system is connected to a chip. There are guiding units
provided on the chip for connecting with the noise eliminating
system, thereby reducing simultaneous switching noise of the
chip.
[0011] According to one aspect of this invention, a noise
eliminating system on chip is provided. The noise eliminating
system on chip comprises a chip; a power supply unit provided on
the chip and being electrically connected to the chip; a grounding
unit provided on the chip and being electrically connected to the
chip; a guiding unit installed on an upper surface of the chip and
being electrically connected to the power supply unit and the
grounding unit; and at least one noise eliminating system
comprising a connecting unit and a noise eliminating unit, wherein
the connecting unit is electrically connected to the noise
eliminating unit, and wherein the connecting unit is electrically
connected to the guiding unit.
[0012] According to one aspect of this invention, a method for
fabricating a noise eliminating system on chip, which comprises the
steps of:
[0013] providing a chip having thereon a power supply unit and a
grounding unit;
[0014] forming a guiding device layer on an upper surface of the
chip;
[0015] etching the guiding device layer to form the guiding
devices;
[0016] providing a noise eliminating system;
[0017] using surface mount technology to install the noise
eliminating system on the upper surface of the chip, and the noise
eliminating system connects to the guiding devices; and
[0018] jointing the junction between the noise eliminating system
and the guiding devices such that the noise eliminating system is
electrically connected to the guiding devices.
[0019] Other objects, advantages and novel features of the
invention will become more clearly and readily apparent from the
following detailed description when taken in conjunction with the
accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIG. 1 illustrates a cross section of a conventional
leadframe package structure mounted on a printed circuit board.
[0021] FIG. 2 is a cross-sectional view of a prior art ball grid
array (BGA) package.
[0022] FIG. 3 illustrates the simultaneous switching noise (SSN)
accumulated from the chip, the wire bonding, and the trace.
[0023] FIG. 4 is a cross-sectional diagram illustrating the BGA
package according to the present invention.
[0024] FIG. 5 is a cross sectional view of this invention.
[0025] FIG. 6 is a cross sectional view of this invention.
[0026] FIG. 7 is a circuit diagram of this invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0027] Please refer to FIG. 4 to FIG. 6. The present invention is
directed to chip package in combination with a noise eliminating
system and a fabrication method thereof. As shown in FIG. 4, power
supply unit 30, grounding unit 40, and noise eliminating system 50
are directly disposed on the chip 60 and electrically connected to
each other, such that the noise eliminating system 50 can eliminate
undesired coupling between circuits or SSN between the power supply
layer and the grounded layer of a high-frequency circuit in a more
effective way. Such chip 60 with the noise eliminating system 50
directly built thereon is then mounted on a substrate 70. Necessary
electric connection is provided. Finally, the chip 60 with the
noise eliminating system 50 is packaged on the substrate 70 by
using encapsulant 80.
[0028] As shown in FIG. 4 to FIG. 6, in the chip 60, the power
supply unit 30 and the grounding unit 40 are provided. Both of the
power supply unit 30 and the grounding unit 40 have corresponding
bonding pads 41 and wire bonds 42. The bonding pads 41 are disposed
on the chip 60 and electrically connected to each other. The wire
bonds 42, which are electrically connected to conductive traces
(not shown) on the substrate 70, are soldered on the corresponding
bonding pads 41.
[0029] As best seen in FIG. 5, in accordance with the first
preferred embodiment of this invention, a first guiding device 61
and a second guiding device 62 are installed in the chip 60. The
first guiding device 61 is installed in a first region 63 in the
chip 60 and the second guiding device 62 is installed in the second
region 64 in the chip 60, where the first and second regions 63 and
64 are connected with outer environment. The first guiding device
61 is connected to the bonding pad 41 of the power supply unit 30
and the second guiding device 62 is connected to the bonding pad 41
of the grounding unit 40 (not shown). On the upper surface 67 of
the chip 60 there is provided a protection layer. A first guiding
device opening 65 and a second guiding device opening 66 are formed
in the protection layer, wherein the first guiding device opening
65 is connected to the first guiding device 61 in the first region
63, and the second guiding device opening 66 is connected to the
second guiding device 62 in the second region 64, wherein the first
region 63 and the second region 64 are located on the chip 60, such
that the first and second guiding devices 61 and 62 are connected
to outer environment. The noise eliminating system 50 comprises
connecting unit 51 and noise eliminating unit 52 and both are
electrically connected to each other. The connecting unit 51
comprises two connecting ports 53, which are respectively protrude
from the first guiding device openings 65 and 66 and are
respectively connected to the first guiding device 61 in the first
region 63 and the second guiding device 62 in the second region 64.
The noise eliminating system 50 may be a passive component such as
a de-coupling capacitor, and the above-described guiding devices 61
and 62 are inner circuits of the chip 60. The power supply unit 30,
the grounding unit 40, and the noise eliminating system 50 can be
installed at one side of the chip 60.
[0030] As best seen in FIG. 6, in accordance with the second
preferred embodiment of this invention, a noise eliminating system
50 and an additional guiding unit 90 are installed on the upper
surface 67 of the chip 60. The guiding unit 90 comprises a first
guiding device 61' and a second guiding device 62', which are
respectively located in the first region 63' and second region 64'
of the chip 60. The first guiding device 61' is electrically
connected to the bonding pad 41 of the power supply unit 30 and the
second guiding device 62' is electrically connected to the bonding
pad 41 of the grounding unit 40. A protection layer 100 is provided
over the guiding devices 61' and 62' and over the chip 60. A first
guiding device opening 65' and a second guiding device opening 66'
are formed in the protection layer 100. The first guiding device
opening 65' and the second guiding device opening 66' correspond to
the first guiding device 61' in the first region 63' and the second
guiding device 62' in the second region 64', respectively. The
first and second regions 63' and 64' are located on the chip 60.
The connecting unit 51 of the noise eliminating unit 52 comprises
two connecting ports 53, which respectively protrude from the first
and second guiding device openings 65' and 66', and are
electrically connected to the first guiding device 61' in the first
region 63' and the second guiding device 62' in the second region
64', respectively. The above-described guiding devices 61' and 62'
may be circuit, and the noise eliminating system 50 may be a
de-coupling capacitor.
[0031] As shown in FIG. 4, a chip 60 in combination with a noise
eliminating system 50 is installed on a ball grid array (BGA)
substrate 70. The substrate 70 comprises conductive traces (not
shown) connecting to respective power supply and grounding.
Alternatively, the substrate 70 can be a flip chip type substrate.
The power supply unit 30 and the grounding unit 40 of the chip 60
are electrically connected to the power trace and the grounding
trace of the substrate 70 through the wire bonding 42. The chip 60
with the noise eliminating system 50 is encapsulated on the
substrate 70 with encapsulant 80. Preferably, the guiding device 90
is a metal redistribution layer.
[0032] FIG. 7 illustrates an equivalent circuit showing the noise
eliminating system 50 on chip 60. The simultaneous switching noise
(SSN) caused by rapid switching between the wire bonding 42 and the
trace of the substrate 70 is eliminated.
[0033] In accordance with the present invention, a method for
fabricating the noise eliminating system on chip comprising the
steps of:
[0034] providing a chip having a grounding unit and a power supply
unit;
[0035] forming a guiding layer on the upper surface of the
chip;
[0036] etching the guiding layer to form the guiding devices;
[0037] providing a noise eliminating system;
[0038] using surface mount technology to install the noise
eliminating system on the upper surface of the chip, and the noise
eliminating system connects to the guiding devices; and
[0039] jointing the junction between the noise eliminating system
and the guiding devices such that the noise eliminating system is
electrically connected to the guiding devices.
[0040] The guiding layer is made of conductive materials sputtered
on the upper surface of the chip and is selectively etched away to
form a plurality of guiding devices.
[0041] To sum up, the present invention has the following
advantages:
[0042] 1. The noise eliminating system is directly installed on the
chip and is electrically connected to the chip, thereby shrinking
the connecting distance between the chip and the noise eliminating
system.
[0043] 2. The simultaneous switching noise (SSN) is effectively
eliminated.
[0044] 3. The number of devices that are needed on the substrate or
printed circuit board is reduced, such that the size of the
substrate or printed circuit board is shrinkable, thereby reducing
cost.
[0045] It is to be understood, however, that even though numerous
characteristics and advantages of the present invention have been
set forth in the foregoing description, together with details of
the structure and function of the invention, the disclosure is
illustrative only, and changes may be made in detail, especially in
matters of shape, size, and arrangement of parts within the
principles of the invention to the full extent indicated by the
broad general meaning of the terms in which the appended claims are
expressed.
* * * * *