U.S. patent application number 10/762013 was filed with the patent office on 2004-08-05 for flip chip interconnection using no-clean flux.
Invention is credited to Maeda, Michihisa, Takahashi, Kenji.
Application Number | 20040152238 10/762013 |
Document ID | / |
Family ID | 25231108 |
Filed Date | 2004-08-05 |
United States Patent
Application |
20040152238 |
Kind Code |
A1 |
Maeda, Michihisa ; et
al. |
August 5, 2004 |
Flip chip interconnection using no-clean flux
Abstract
A flip chip method of joining a chip and a substrate is
described. A thermo-compression bonder is utilized to align the
chip and substrate and apply a contact force to hold solder bumps
on the substrate against metal bumps on the chip. The chip is
rapidly heated from its non-native side by a pulse heater in the
head of the bonder until the re-flow temperature of the solder
bumps is reached. Proximate with reaching the re-flow temperature
at the solder bumps, the contact force is released. The solder is
held above its re-flow temperature for several seconds to
facilitate wetting of the substrate's metal protrusions and
joining. A no-clean flux that has a volatilization temperature
below the melting point of the solder bumps is utilized to minimize
or eliminate the need for a post interconnection de-flux
operation.
Inventors: |
Maeda, Michihisa;
(Ibaraki-ken, JP) ; Takahashi, Kenji;
(Ibaraki-ken, JP) |
Correspondence
Address: |
BLAKELY SOKOLOFF TAYLOR & ZAFMAN
12400 WILSHIRE BOULEVARD, SEVENTH FLOOR
LOS ANGELES
CA
90025
US
|
Family ID: |
25231108 |
Appl. No.: |
10/762013 |
Filed: |
January 21, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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10762013 |
Jan 21, 2004 |
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09820547 |
Mar 28, 2001 |
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6713318 |
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Current U.S.
Class: |
438/108 ;
257/E21.511; 438/613; 438/615 |
Current CPC
Class: |
H01L 2924/0105 20130101;
H01L 2924/01082 20130101; B23K 35/3618 20130101; H01L 2924/15312
20130101; H01L 2924/01322 20130101; B23K 35/262 20130101; H01L
2924/01051 20130101; H01L 2224/75 20130101; H01L 2924/01006
20130101; H01L 2224/05573 20130101; H01L 2924/01047 20130101; H05K
3/3489 20130101; H01L 24/05 20130101; H01L 2224/13147 20130101;
H01L 2224/75252 20130101; H01L 2924/01029 20130101; H01L 2924/01033
20130101; H01L 2924/01075 20130101; H01L 24/81 20130101; H01L
2224/056 20130101; H05K 3/3436 20130101; H01L 2224/81801 20130101;
H01L 2224/05568 20130101; H01L 2924/014 20130101; H01L 2224/056
20130101; H01L 2924/00014 20130101 |
Class at
Publication: |
438/108 ;
438/615; 438/613 |
International
Class: |
H01L 021/44; H01L
021/48; H01L 021/50 |
Claims
What is claimed is:
1. A method, comprising: applying a flux to a first surface of a
substrate, the first surface of the substrate having attached
thereto solder bumps, the solder bumps having a melting
temperature, and the flux substantially comprising ingredients that
have a volatilization temperature less than the melting
temperature; generally aligning the solder bumps with corresponding
metal bumps, the metal bumps being attached to a first surface of a
chip; bringing the solder bumps into contact with the corresponding
metal bumps; and heating the solder bumps to a first temperature,
the first temperature being equal to or greater than the melting
temperature.
2. The method of claim 1, wherein the first surface of the chip
comprises copper.
3. The method of claim 1, wherein the bringing of the solder bumps
into contact with the corresponding metal bumps, further includes
applying a contact force.
4. The method of claim 3, wherein the contact force is removed just
after the solder bumps have been heated to at least the melting
temperature.
5. The method of claim 1, wherein the solder bumps are comprised of
a 96.5% tin, 3.5% silver solder.
6. The method of claim 1, wherein the flux includes a carboxylic
acid and has a volatilization temperature of approximately 200
degrees Celsius.
7. The method of claim 1, further comprising: joining the solder
bumps to the metal bumps by cooling the solder bumps to a
temperature below the melting temperature; heating the first
surfaces of the chip and substrate to within a temperature range,
the temperature range being equal to or greater than the
volatilization temperature but less than or equal to the melting
temperature; and maintaining the chip and substrate first surfaces
within the temperature range for a first period of time.
8. The method of claim 1, wherein the heating of the solder bumps
comprises heating the solder bumps through a second surface of the
chip, the second surface of the chip being opposite the first
surface of the chip.
9. The method of claim 8, wherein the heating of the solder bumps
to a first temperature further includes rapidly increasing the
temperature of the second surface to a second temperature, the
second temperature being greater than the first temperature,
wherein a temperature gradient is established through the chip from
the second surface at the second temperature to the first surface
of the chip at the first temperature.
10. The method of claim 8, wherein the heating of the solder bumps
to the first temperature comprises providing a heater in contact
with the second surface.
11. The method of claim 9, wherein a third temperature at a second
substrate surface opposite the first substrate surface is
significantly below the first temperature, when the first surface
of the chip is at the first temperature.
12. The method of claim 9, further comprises maintaining the second
surface at the second temperature for a period of time.
13. The method of claim 12, wherein the period of time is
approximately 1 to 5 seconds.
14. An apparatus, comprising: a substrate placed against a first
fixture, the substrate having deposited thereon a plurality of
solder bumps and a flux, each of the plurality of solder bumps
having a melting point at a first temperature, and the flux having
a volatilization temperature at which substantially all of the
constituents of the flux volatilize, the volatilization temperature
being less than or equal to the first temperature, the first
fixture being maintained at a second temperature below the first
temperature; a chip placed against a second fixture, the chip
having affixed thereto a plurality of metal protrusions, the second
fixture coupled with a heater, the heater being maintained at a
third temperature, the third temperature being less than the first
temperature; the plurality of solder bumps placed into contact with
the plurality of metal protrusions by moving one or both of the
first and second fixtures towards each other; the heater having a
temperature rapidly increased from a third temperature to a fourth
temperature, the fourth temperature being higher than the first
temperature; and a pulse heat tool held approximately at or above
the fourth temperature until the plurality of solder bumps have
melted and wetted the plurality of metal protrusions.
15. The apparatus of claim 14, wherein the substrate has deposited
thereon the plurality of solder bumps, and the chip has affixed
thereto a plurality of metal protrusions.
16. The apparatus of claim 14, wherein the second temperature is
approximately within a range of 100 to 170 degrees Celsius.
17. The apparatus of claim 14, wherein the third temperature is
approximately between 30 to 100 degrees Celsius, and the fourth
temperature is approximately between 250 to 400 degrees
Celsius.
18. The apparatus of claim 14, wherein the temperature is rapidly
increased from the third to fourth temperature at a rate of 50
degrees Celsius per second or faster.
19. The apparatus of claim 14, wherein the plurality of solder
bumps and the plurality of bump metal protrusions are placed in
contact with each other by applying a contact force.
20. The apparatus of claim 19, wherein the contact force is removed
once the plurality of solder bumps reach the first temperature.
21. The apparatus of claim 14, wherein the first and second
fixtures and the heater comprise a thermo-compression bonder.
22. A system for interconnecting a chip and a substrate,
comprising: metal protrusions applied to electrical interconnect
pads on an active surface of the chip, the chip also having second
surface opposite the active surface; solder bumps applied to
electrical interconnect pads on a top surface of the substrate, the
substrate also having a bottom surface, the solder bumps having a
melting temperature; the solder bumps coated with a no-clean flux,
the no-clean flux comprised primarily of constituents having
volatilization temperatures that are less than the melting
temperature; the bottom surface of the substrate placed on a platen
of a thermo-compression bonder, the platen being maintained at a
first temperature that is less than the volatilization and melting
temperatures; the second surface of the chip affixed to a head of
the thermo-compression bonder, the head including a heater; the
solder bumps generally aligned with corresponding metal
protrusions; the head is lowered or the platen is raised to bring
the solder bumps into contact with the metal protrusions; a contact
force applied to hold the solder bumps and corresponding metal
protrusions together; the heater having a temperature increased
until the second surface of the substrate reaches a second
temperature, the second temperature being greater than the melting
temperature; and the second surface held at the second temperature
for a period of time until the solder bumps have melted.
23 The system of claim 22, wherein the contact force is removed
once the solder bumps begin to melt.
24. The system of claim 22, wherein the temperature of the heater
is increased at a heat-up rate in excess of 30 degree Celsius a
second.
25. The system of claim 22, wherein the heater is a pulse heat
tool.
26. A method, comprising: providing a chip, the chip having an
active surface comprised of a plurality of chip pads; providing a
substrate, the substrate having a top surface comprised of a
plurality of substrate pads corresponding to the plurality of chip
pads; applying a first plurality of solder bumps or a first
plurality of metal bumps to the plurality of chip pads; applying a
second plurality of solder bumps or a second plurality of metal
bumps to the plurality of substrate pads, wherein the corresponding
pluralities of chip and substrate pads do not both have a plurality
metal bumps attached thereto; substantially covering the solder
bumps with a no-clean flux, the no-clean flux substantially
consisting of components having volatilization temperatures below a
melting temperature; generally aligning the plurality of chip pads
and the plurality of substrate pads; bringing the first plurality
of solder bumps into contact with the second plurality of metal
bumps, and applying a contact force; and heating the first
plurality of solder bumps to a first temperature in excess of the
melting temperature.
27. The method of claim 26, wherein the first plurality of metal
bumps are applied to the plurality of chip pads, and the second
plurality of solder bumps are applied to the plurality of substrate
pads.
28. The method of claim 26, wherein the first plurality of solder
bumps are applied to the plurality of chip pads, and the second
plurality of solder bumps are applied to the plurality of substrate
pads.
29. The method of claim 26, wherein the first plurality of solder
bumps are applied to the plurality of chip pads, and the second
plurality of metal bumps are applied to the plurality of substrate
pads.
30. The method of claim 26, further comprises heating the first
plurality of solder bumps to the melting temperature at a rate in
excess of 50 degrees Celsius per second.
31. The method of claim 26, further comprises heating the second
plurality of solder bumps to the melting temperature at a rate in
excess of 50 degrees Celsius per second.
32. An apparatus, comprising: a first surface of a substrate, the
first surface of the substrate having attached thereto solder
bumps, the solder bumps having a melting temperature; a flux
applied to the first surface of the substrate, the flux
substantially comprising ingredients that have a volatilization
temperature less than the melting temperature; and metal bumps
having aligned with the solder bumps, bringing the solder bumps
into contact with the corresponding metal bumps.
33. The apparatus of claim 32, further comprises a first surface of
a chip, wherein the metal bumps being attached to the first surface
of the chip.
34. The apparatus of claim 33, wherein the first surface of the
chip comprises copper.
35. The apparatus of claim 32, wherein the solder bumps are heated
to a first temperature, the first temperature being equal to or
greater than the melting temperature.
36. A system, comprising: a first surface of a substrate, the first
surface of the substrate having attached thereto solder bumps, the
solder bumps having a melting temperature; a flux applied to the
first surface of the substrate, the flux substantially comprising
ingredients that have a volatilization temperature less than the
melting temperature; metal bumps having aligned with the solder
bumps, bringing the solder bumps into contact with the
corresponding metal bumps; and a first surface of a chip, wherein
the metal bumps being attached to the first surface of the
chip.
37. The system of claim 36, wherein the solder bumps are heated to
a first temperature, the first temperature being equal to or
greater than the melting temperature.
38. The system of claim 36, wherein the solder bumps are comprised
of a 96.5% tin, 3.5% silver solder.
39. The system of claim 36, wherein the flux comprises a carboxylic
acid and has a volatilization temperature of approximately 200
degrees Celsius.
Description
RELATED APPLICATION AND CLAIM OF PRIORITY
[0001] This is continuation of U.S. application Ser. No.
09/820,547, filed on Mar. 28, 2001, now allowed, and priority is
claimed thereof.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The invention relates generally to the field of
semiconductor chip packaging. More particularly, the invention
relates to the joining of the semi-conductor chip and a substrate
using a flip chip process.
[0004] 2. Description of the Related Art
[0005] Traditionally, semi-conductor chips have been electrically
coupled to electrical traces on a substrate via wire interconnects
that are soldered on one end to the top area of a chip and soldered
to trace pads on the substrate that surround the chip on the other
end. These types of interconnects are not particularly space
efficient, requiring area for both the footprint of the chip and a
trace pad perimeter. To more efficiently utilize the substrate
surface and facilitate smaller chip packages, the flip chip
interconnection process was developed. Essentially, the active
surface of the semi-conductor chip is flipped over to face the
substrate and the chip is soldered directly to trace pads located
adjacent to the active surface. The result is a more compact and
space efficient package.
[0006] One of the most successful and effective methods of
electrically connecting a flipped chip to a substrate utilizes
controlled-collapse chip connection technology (the C4 process
developed by Intel Corporation of Santa Clara Calif.). Details of
this process will be described below with reference to FIG. 1.
Briefly, the process consists of applying solder bumps to pads on
the substrate. A flux is applied to at least one of the surfaces to
be joined to isolate the surface from the atmosphere and provide an
adhesive force to hold the chip to the substrate during the
process. The solder is then re-flowed. Finally, a wash and bake
cycle may be used to clean the package.
[0007] An epoxy under-fill is applied between the active surface of
the chip and the top surface of the substrate to surround and
support the solder interconnects. Under-filling significantly
increases the reliability and fatigue resistance of the package's
interconnections. The under-fill helps to more evenly distribute
stress caused by thermally induced strains due to the differences
in coefficients of thermal expansion (CTE) between the chip and
substrate across the entire surface of the chip and substrate. If
the gap between the interconnected chip and substrate were not
under-filled, the stress would be carried by the relatively thin
solder interconnects, often resulting in premature package failure.
However, in order for the under-fill to perform properly, it must
be well adhered to the chip and substrate surfaces. Even a thin
film of flux residue can cause premature delamination of a bonded
surface, eventually resulting in failure in one or more of the
interconnects. Accordingly, one of the great challenges using C4
technology has been to completely remove all flux residues from the
package. This has become especially troublesome as the thickness of
the gap between the chip and the substrate has decreased.
[0008] The total throughput time (TPT), or the time it takes to
create a soldered chip, is affected significantly by the time
required to remove absorbed water from chip and substrate which can
be particularly time-consuming. For instance, chemical defluxing
may take minutes, while a post-bake to remove absorbed water from
chip and substrate may take several hours. Fluxes have been
developed that completely volatilize at elevated temperature.
However, because the flux is required in the C4 process to hold the
chip and substrate together before re-flow, only those fluxes that
have volatilization temperature at or above the solder melting
point are suitable for use with the C4 process. The small thickness
of the gap distance between the chip and the substrate coupled with
the flux's high volatilization temperatures, however, make it
difficult, if not impossible, to boil off all of the flux residues
during the re-flow process or in a subsequent post-bake operation
at a temperature slightly below solder melting temperature. The
long post-bake times and defluxing operations required to volatize
the flux eliminate any opportunity for significant TPT
reductions.
BRIEF DESCRIPTION THE DRAWINGS
[0009] The present invention is illustrated by way of example, and
not by way of limitation, in the figures of the accompanying
drawings and in which like reference numerals refer to similar
elements and in which:
[0010] FIG. 1 is a prior art flow diagram illustrating the
operations typically required to create a flip chip bond using a C4
joining process.
[0011] FIG. 2 is a flow diagram of one embodiment of a joining
process.
[0012] FIG. 3 illustrates one embodiment a solder bump that has
been applied to a bonding pad on a substrate and re-flowed, as well
as a copper base metal bump that has been applied to a bonding pad
on the top surface of a chip.
[0013] FIG. 4A-D illustrates embodiments of a chip and substrate
during various operations during the interconnection process.
[0014] FIG. 5 illustrates one embodiment of a diagram for a joining
cycle.
[0015] FIG. 6A is an illustration of one embodiment of a
chip/substrate package.
[0016] FIG. 6B is a chart derived from experimentation indicating
the temperatures observed at several locations on the chip and
substrate during a chip interconnection process performed according
to an embodiment of the present invention.
[0017] FIG. 7 illustrates a cross-sectional view of an interconnect
joint.
DETAILED DESCRIPTION
[0018] A flip chip method for the interconnection of a chip to a
substrate utilizing a no-clean flux having a low volatilization
temperature is described. Through the use of a thermo-compression
bonder (or a similarly equipped apparatus) that uses contact
pressure to hold the chip and the associated substrate in general
alignment prior to re-flow of the solder bumps, the need to use a
flux that can adhesively hold the chip and substrate together until
solder bump re-flow is eliminated. Accordingly, a no-clean flux
having a volatilization temperature below the melting temperature
of the solder may be specified whereby most, if not substantially
all, of the flux is volatilized during a brief hold at the solder
re-flow temperature. In alternative embodiments, a short post-heat
period may be utilized to ensure the no-clean flux has been
completely volatilized. Advantageously, the use of the low
volatilization no-clean flux in conjunction with a
thermo-compression bonder results in significantly reduced TPT's,
as well as higher integrity bonds than is typical using
conventional C4 processing. For purposes of this disclosure, a
no-clean flux is one that includes constituents that completely
volatilize at a specific temperature, leaving no solid residue.
[0019] FIG. 1 illustrates the C4 process. First, as shown in
processing block 105, solder bumps are typically applied to pads on
the substrate using any number of suitable processes including
printing (using solder paste for the C4 process), plating and vapor
deposition. Generally, lead-tin solders having melting points below
200 degrees Celsius are used. Next, in processing block 110, the
solder bumps are re-flowed by heating the solder bumps to a
temperature above the solder's melting point to fully wet the
solder bumps to their respective pads. Typically, metal bumps, or
protrusions having a high lead content, are deposited on the
corresponding chip pads.
[0020] In processing block 115, a flux is applied to at least one
of the surfaces to be joined. Typically, the flux includes a
vehicle and an activator. The flux vehicle acts to isolate the
surface of the solder from the atmosphere during a second re-flow,
minimizing the risks of oxidation while the solder is hot and/or
molten. The flux vehicle is generally tacky and provides an
adhesive force to hold the chip and substrate together prior to the
second re-flow. The activator is typically an organic or inorganic
acid that removes any oxides or surface films present on the
solder, facilitating solder wetting of the metallic surfaces to be
joined. In processing block 120, the flux bearing surfaces of the
chip and substrate are placed in contact with each other in general
alignment.
[0021] Next, as illustrated in processing block 125, the second
re-flow is performed by heating the chip and substrate package to a
temperature above the solder's melting point. The molten solder
bumps wet the corresponding metal bumps and the surface tension of
the molten solder causes the metal bumps to self-align with each of
the corresponding substrate pads. The newly formed interconnects
are then cooled to solidify the solder.
[0022] Any flux or flux residue is removed from the chip and
substrate package in a defluxing operation as indicated in
processing block 130. This operation will typically include solvent
washing the package to remove flux residue. A post-interconnection
bake cycle may also be specified to volatilize any remaining
solvent or low boiling point flux constituents. Water-soluble
fluxes are commonly used for C4 application and water is used for
defluxing. The primary purpose of the bake cycle is to remove the
water, which is absorbed into chip and substrate during defluxing,
since such absorbed water would be the cause of voids during
under-filling.
[0023] FIG. 2 is a flow diagram for one embodiment of a joining
process utilized according to one embodiment of the present
invention. First, as indicated in processing block 205, a solder is
applied to bond pads on the top surface of the substrate. One of
ordinary skill in the art will appreciate that in alternative
embodiments the solder may be applied to bond pads on the chip
(die) as well. The solder may be applied to the bond pads using any
number of suitable techniques known to those skilled in the art,
including, but not limited to, printing, vapor deposition and
electroplating. After the solder is applied, the substrate is
heated to beyond the solder's melting point to re-flow the solder
as indicated in processing block 210 to facilitate complete wetting
of the bond pads. In one embodiment, a 96.5% tin/3.5% silver
eutectic solder with a melting point of around 221 degrees Celsius
is specified, although any number of suitable solder compounds may
be utilized. Ideally, lead-free solders are specified, eliminating
the potential environmental problems caused by lead.
[0024] Typically, a metal bump is applied to the bond pads on the
chip, although in alternative embodiments the bump metal pad may be
applied to the substrate instead. The bump metal pad may be applied
to the bonding pad by any number of methods as would be known to
one skilled in the art. Ideally, the bump metal has good electrical
conductivity and reasonable resistance to oxidation at the elevated
joining temperatures. Traditionally, an oxidation-resistant,
lead-based bump metal such as a 97% Pb/3% Sn alloy has been
utilized in conventional C4 flip chip joining processes. Lead-based
bump metals, and solders for that matter, provide necessary
oxidation resistance during the furnace temperature ramp up and
hold times utilized in a conventional C4 process. In embodiments of
the present invention, the ramp up and hold times are relatively
short (e.g. 100 degrees@second ramp and 1-5 second hold). Thus, the
potential for significant oxidation is minimized and a more
reactive base metal with superior electrical properties may be
utilized in the metal bumps. In one embodiment, a copper base metal
bump is specified. FIG. 3 illustrates a solder bump 305 that has
been applied to a bonding pad 310 on a substrate 315 and re-flowed,
as well as a copper base metal bump 320 that has been applied to a
bonding pad on the top surface of a chip 325.
[0025] Referring back to FIG. 2, in processing block 215 a no-clean
flux is applied to the solder bumped surface of the substrate. A
solder bumped substrate 315 is illustrated in FIG. 4A with a
no-clean flux 405 applied to its top surface, substantially
encapsulating the solder bumps 305. The primary functions of the
no-clean flux 405 is to remove oxide and other contaminants from
the surface of the solder bumps 305 and the base metal bumps 320,
and prevent new oxide films from forming on the base metal and
solder bumps during the interconnection process. In typical C4
bonding processes, fluxes serve an additional purpose of adhesively
holding the chip and substrate together until the re-flow
temperature was reached during joining. Accordingly, even no-clean
fluxes used in the C4 process have constituents that have boiling
points above the melting points of the solder bumps. Since pressure
applied by the thermo-compression bonder is used to hold the chip
and substrate together prior to re-flow in the preferred
embodiments of the invention, no-clean fluxes consisting entirely
of constituents with boiling points of less than the melting point
of the solder may be utilized. In one embodiment, a carboxylic acid
no-clean flux is utilized having a boiling point of around 200
degrees Celsius.
[0026] Referring to processing block 220 of FIG. 2, the chip 320 is
picked up by the head of the thermo-compression bonder and aligned
with the substrate 315. The substrate 315 is typically placed on a
heated platen 330 as shown in FIG. 4B. The platen 330 is generally
held at a constant temperature below the melting point of the
solder 305. In one embodiment, a temperature of around 135 degrees
Celsius is specified. Likewise, the die head 335 may be maintained
at an intermediate temperature, typically between 30 to 100 degrees
Celsius. The die head 335 may comprise an internal heating element
or, as shown in FIG. 4B, a pulse heat tool 340 capable of very
rapid heating (e.g., greater than 25 degrees Celsius@second) may be
utilized.
[0027] Next, in processing block 230, the interconnection cycle is
commenced. First, as shown in FIG. 4C, the base metal bumps 325 of
the chip 315 are brought into contact with corresponding solder
bumps 305 on the substrate 315 and pressure is applied as the pulse
heat tool 340 is rapidly heated to a temperature well in excess of
the melting point of the solder bumps 305. As illustrated in FIG.
4D, the interconnection cycle is then ended.
[0028] FIG. 5 illustrates one embodiment of a joining. Line 540
represents the temperature of the pulse heat tool 340 at a given
time during the cycle. Line 545 is a pressure curve indicating the
amount of force applied to the interface between the metal bumps
325 and the solder bumps 305 at a given time. Initially, as
discussed supra, the pulse heat tool is maintained at an
intermediate temperature such as 30 degrees Celsius. The chip is
picked up by the thermo-compression bonder head at time 525. The
chip and substrate are aligned and the chip is brought into contact
with the substrate and pressure is applied at around time 530.
Typically, a force of 2 to 5 kilograms is applied depending on the
dimensions of the chip and the number of flip chip connections to
be made. Also at time 530, the pulse heat tool is energized and
rapidly heated to its hold temperature. In one embodiment, heat-up
rates on the order of 100 degrees Celsius are specified. The peak
hold temperature 515 is typically on the order of 250 to 400
degrees Celsius depending on several factors, including the
thickness of the chip, the thermal conductivity of the chip, and
the melting point and desired re-flow temperature of the solder
bumps 305.
[0029] Typically, a temperature gradient will be established
through the chip such that the temperature at the interface with
the solder bumps 305 will be less than the temperature at the
interface with the pulse heat tool 340. Accordingly, the hold
temperature 515 of the pulse heat tool will typically be greater
than the re-flow temperature of the solder bumps 305. At about time
550 when the hold temperature 515 has been reached, the pressure
applied to the chip is nearly reduced to zero as indicated by
pressure curve 545. At about or just prior to time 550, the melting
temperature of the solder is reached at the interface between the
chip and the substrate and pressure is no longer required to hold
the chip and substrate together. While the pulse heat tool is held
at temperature 515, the solder bumps melt and re-flow. The pulse
heat tool is maintained at temperature 515 for a short period of
time, typically 1 to 5 seconds, after which the pulse heat tool 340
is de-energized and the solder solidifies shortly thereafter. Once
the pulse heat tool has reached a temperature 510, the bonded chip
and substrate are removed from the thermo-compression bonder,
freeing the bonder to perform another chip join.
[0030] During the heat-up phase of the chip join, the interface
between the chip and substrate reaches a temperature in excess of
the boiling point (or volatilization point) of the no-clean flux.
As discussed supra, the no-clean flux of the preferred embodiment
is comprised of carboxylic acid which boils at a temperature of 200
degrees Celsius. Ideally, substantially all of the flux volatilizes
during the heat-up phase and is not present during the re-flow of
the solder. A lack of flux to protect the solder and base metal
from the oxidizing effects of elevated temperatures would normally
be of concern. However, given the rapid heat-up rate of the pulse
tool, the time in which the solder and base metal are unprotected
prior to melting and re-flow is generally insignificant.
Furthermore, the gaseous flux volatiles form a temporary protective
cloud around the solder bumps substantially preventing oxygen
molecules from impinging on the joining surfaces prior to melting
and re-flow.
[0031] In one embodiment, as mentioned supra, a 96.5% Sn 3.5% Ag
solder is utilized to form the solder bumps. This solder has a
melting point of approximately 221 degrees Celsius and requires a
re-flow temperature at least a few degrees greater than the melting
point. As discussed supra, typical methods such as C4 utilize lead
based solders (such as 37% lead 63% tin) that have melting points
of less than 190 degrees Celsius. The lower melting point solders
are especially necessary when joining a chip to a pinned substrate
using a C4 process since temperatures in excess of 210 degrees
Celsius can cause softening of the pinning solder (typically, 95%
tin 5% antimony which begins melting around 232 degrees Celsius),
resulting in movement of the pins. In one embodiment using a 96.5%
Sn 3.5% Ag solder, the temperature of the pinning solder does not
exceed 200 degrees Celsius. The temperature gradient between the
chip-to-pulse heat tool interface at the high end and the
platen-to-substrate interface at the low end never has the
opportunity to equalize in the short time the pulse heat tool is
energized. FIG. 6A is an illustration of a chip/substrate package
wherein the substrate includes a pin grid array (PGA). The pins 620
of the PGA are held in place by pinning solder 620. FIG. 6B is a
chart derived from experimentation indicating the temperatures
observed at several locations on the chip and substrate during a
chip join performed according to one embodiment. The temperatures
listed along the horizontal axis indicate the temperature at the
center of the chip join region 605. It is noted that the melt and
re-flow of the preferred solder typically occurs at temperatures
between 220 and 235 degrees Celsius. The top line indicates the
corresponding temperature at the center of the pin grid array side
of the substrate. The bottom line indicates the corresponding
temperature at the edge of the pin grid array side of the
substrate. As is indicated by FIG. 6B, the temperature on the pin
grid array side of the substrate never exceeds 165 degrees Celsius,
while the melt temperature of the solder bumps are reached and
exceeded to facilitate re-flow and joining.
[0032] Referring back to FIG. 2, the gap between the chip and the
substrate is typically under-filled with an epoxy resin to
substantially increase the longevity, environmental resistance, and
fatigue strength of the interconnects as indicated by block 240. In
order to obtain the maximum benefits from the under-filling
operation, the surfaces to be bonded should be free of flux or
other residue. Accordingly, in certain embodiments, a post-heat
operation may be performed to ensure that any residual flux that
could negatively impact the subsequent under-fill bond is removed.
The interconnected chip and substrate may be heated in an oven for
an appropriate period of time at or slightly above the
volatilization temperature of the no-clean flux as indicated in
block 235. For example, a chip substrate package joined according
to one embodiment where a carboxylic acid flux with a 200 degrees
boiling point is used will be baked at least 200 degrees Celsius
for 10 minutes. Unlike with typical flip chip joining processes in
which the flux does not volatize below the re-flow temperature of
the solder bumps, little or no time-consuming, solvent-based
defluxing operations need be performed, significantly reducing the
TPT. Additionally, the volatilization of the flux prior to melt and
re-flow helps facilitate a low porosity bond with high integrity as
shown in FIG. 7, a cross-sectional view of an interconnect
joint.
[0033] Testing has been performed of under-filled surfaces of a
chip/substrate package in which a carboxylic having a boiling point
of 235 degrees Celsius was used during interconnection. No
solvent-based deflux operation was performed on the package prior
to under-fill. After 168 hours in a steam atmosphere, nearly 13.6%
of the under-fill bonds have delaminated due primarily to flux
residue that was unable to volatilize during the re-flow process. A
post-heat bake performed at the boiling point of the 235 degree
carboxylic acid flux is not feasible as the flux's boiling point is
above the melting point of the solder, not to mention the melting
point of the pinning solder. Testing of the under-filled surfaces
of a chip/substrate package has also been performed in which a
carboxylic having a boiling point of 200 degrees Celsius was used
during interconnection and a 10 minute post heat at 200 degrees
Celsius was performed prior to under-filling. In these tests,
almost no delamination (0.6%) is present after the 168 hours in a
steam atmosphere, indicating very little, if any, flux residue was
present during the under-fill operation.
[0034] Alternative Embodiments
[0035] In the foregoing description, for the purposes of
explanation, numerous specific details have been set forth in order
to provide a thorough understanding of the present invention. The
detailed description and embodiments discussed herein are not
intended to limit the scope of the invention as claimed. To the
contrary, embodiments of the claims have been contemplated that
encompass the full breadth of the claim language. Accordingly, the
present invention may be practiced without some of the specific
detail provided herein.
[0036] For instance, the embodiments of the invention have been
described above primarily in terms of a flip chip joining process
using a thermo-compression bonder. It is conceivable that other
apparatus may be used to accomplish the limitations of the claims
as would be obvious to one of ordinary skill in the art. Likewise,
although the process has been described in terms of an exemplary
embodiment wherein a 96.5% tin/3.5% silver solder is used along
with a carboxylic acid flux having a 200 degree boiling point,
other suitable solder and flux combinations are contemplated. In
one embodiment, the pressure applied to the chip against the
substrate is removed once the solder bumps have begun to melt,
however alternative embodiments are contemplated wherein at least
some pressure is maintained against the chip throughout the
interconnection process.
* * * * *