U.S. patent application number 10/748328 was filed with the patent office on 2004-08-05 for method for driving plasma display panel.
This patent application is currently assigned to FUJITSU LIMITED. Invention is credited to Asao, Shigeharu, Kanazawa, Yoshikazu, Setoguchi, Noriaki.
Application Number | 20040150354 10/748328 |
Document ID | / |
Family ID | 26402722 |
Filed Date | 2004-08-05 |
United States Patent
Application |
20040150354 |
Kind Code |
A1 |
Setoguchi, Noriaki ; et
al. |
August 5, 2004 |
Method for driving plasma display panel
Abstract
Disclosed is a method for driving a plasma display panel in
which a plurality of first electrodes and second electrodes are
arranged parallel to each other, a plurality of third electrodes
are arranged to cross the first and second electrodes, and
discharge cells defined with areas in which the electrodes cross
mutually are arranged in the form of a matrix. According to the
driving method, a reset period is a period during which the
distribution of wall charges in the plurality of discharge cells is
uniformed. An addressing period is a period during which wall
charges are produced in the discharge cells according to display
data. A sustain discharge period is a period during which sustain
discharge is induced in the discharge cells in which wall charges
are produced during the addressing period. The driving method in
accordance with the present invention comprises a step of applying
a first pulse in which an applied voltage varies with time so as to
induce first discharge in the lines defined by the first and second
electrodes, and a step of applying a second pulse in which an
applied voltage varies with time so as to induce second discharge
as erase discharge in the lines defined by the first and second
electrodes. These steps are carried out during the reset
period.
Inventors: |
Setoguchi, Noriaki;
(Satsuma-gun, JP) ; Asao, Shigeharu;
(Kawasaki-shi, JP) ; Kanazawa, Yoshikazu;
(Kawasaki-shi, JP) |
Correspondence
Address: |
STAAS & HALSEY LLP
SUITE 700
1201 NEW YORK AVENUE, N.W.
WASHINGTON
DC
20005
US
|
Assignee: |
FUJITSU LIMITED
Kawasaki
JP
|
Family ID: |
26402722 |
Appl. No.: |
10/748328 |
Filed: |
December 31, 2003 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10748328 |
Dec 31, 2003 |
|
|
|
09334623 |
Jun 17, 1999 |
|
|
|
6707436 |
|
|
|
|
Current U.S.
Class: |
315/169.4 |
Current CPC
Class: |
G09G 2310/04 20130101;
G09G 3/2932 20130101; G09G 3/2927 20130101; G09G 3/296 20130101;
G09G 2310/0224 20130101; G09G 2320/0238 20130101; G09G 3/2925
20130101; G09G 3/28 20130101; G09G 2310/066 20130101; G09G 3/2922
20130101; G09G 5/18 20130101; G09G 3/2022 20130101 |
Class at
Publication: |
315/169.4 |
International
Class: |
G09G 003/10 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 18, 1998 |
JP |
10-170825 |
Mar 9, 1999 |
JP |
11-61660 |
Claims
1. A method for driving a plasma display panel which performs a
reset discharge, an addressing discharge for writing display data
and a sustain discharge for allowing a display image to glow,
according to the display data, said reset discharge including a
first discharge induced by a first pulse in which an applied
voltage varies with time in a first direction and a second
discharge induced by a second pulse in which an applied voltage
varies with time in a second direction, wherein said second pulse
is applied after said first pulse rises and falls.
2. A method for driving a plasma display panel according to claim
1, wherein said second pulse is applied after said first pulse
falls but before an applied voltage of said first pulse reaches a
potential that was attained before the application of said first
pulse.
3. A method for driving a plasma display panel according to claim
1, wherein said second pulse is applied after said first pulse
falls and an applied voltage of said first pulse reaches a
potential that was attained before the application of said first
pulse.
4. A method for driving a plasma display panel which performs a
reset discharge, an addressing discharge for writing display data
and a sustain discharge for allowing a display image to glow,
according to the display data, said reset discharge including a
first discharge induced by a first pulse in which an applied
voltage varies with time in a positive direction and a second
discharge induced by a second pulse in which an applied voltage
varies with time in a negative direction; wherein said first
discharge is induced by said first pulse applied to a second
electrode and which rises from a predetermined potential in the
positive direction while a first electrode, arranged in parallel to
the second electrode, is set to a lower potential than the
predetermined potential.
5. A method for driving a plasma display panel, comprising:
producing a reset discharge including inducing a first discharge by
a first pulse in which an applied voltage varies with time in a
first direction and inducing a second discharge by a second pulse
in which an applied voltage varies with time in a second direction,
and wherein said second pulse is applied after said first pulse
rises and falls.
6. A method for driving a plasma display panel according to claim
5, further comprising applying said second pulse after said first
pulse falls but before an applied voltage of said first pulse
reaches a potential that was attained before the application of
said first pulse.
7. A method for driving a plasma display panel according to claim
5, further comprising applying said second pulse after said first
pulse falls and an applied voltage of said first pulse reaches a
potential that was attained before the application of said first
pulse.
8. A method for driving a plasma display panel having first and
second parallel electrodes, comprising: producing a reset
discharge, including inducing a first discharge by a first pulse in
which an applied voltage varies with time in a positive direction
and inducing a second discharge by a second pulse in which an
applied voltage varies with time in a negative direction, the first
discharge being induced by said first pulse applied to the second
electrode and which rises from a predetermined potential in the
positive direction while the first electrode is set to a lower
potential than the predetermined potential; and producing an
addressing discharge to write display data and a sustain discharge
to cause a display image to glow, according to the display data.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a method for driving a
plasma display panel (PDP).
[0003] The PDP is a self-luminous type display device with a
characteristic good discernment (i.e., high resolution) and with a
thin and large display screen. The PDP is attracting attention as a
display device with which CRTs will be replaced in the near future.
In particular, a surface discharge AC type PDP is highly expected
to be a display device compatible with high-quality digital
broadcasting, because it can be designed to have a large display
screen. The surface discharge AC type PDP will be required to
provide a higher quality than a CRT.
[0004] A high-quality display may be construed as a high-definition
display, a display with a large number of gray-scale levels, a
high-luminance display, or a high-contrast display. A
high-definition display is accomplished by setting the pitch
between pixels to a small value. A display with a large number of
gray-scale levels is accomplished by increasing the number of
sub-fields within a frame. Moreover, a high-luminance display is
accomplished by increasing the amount of visible light permitted by
certain power or increasing the number of times of sustain
discharge. Furthermore, a high-contrast display is accomplished by
minimizing the reflectance of extraneous light from the surface of
a display panel or minimizing an amount of glow that occurs during
black display which does not contribute to the display.
[0005] 2. Description of the Related Art
[0006] The structure of a conventional plasma display panel and a
conventional method for driving a plasma display panel will be
described with reference to FIG. 1 to FIG. 4 to be described later
in "BRIEF DESCRIPTION OF THE DRAWINGS". This is intended to
facilitate an understanding of problems underlying the conventional
method for driving a plasma display panel.
[0007] FIG. 1 schematically shows the structure of a surface
discharge type PDP in which a method, filed for a patent by the
present applicant, is implemented. According to the method, lines
defined by all sustain discharge electrodes are involved in
display. The structure of the PDP has been disclosed in, for
example, the specification and drawings of Japanese Unexamined
Patent Publication No. 9-160525 published on Jun. 20, 1997.
[0008] A PDP 1 consists of sustain discharge electrodes X1 to X3
(hereinafter abbreviated to X1 to X3 electrodes) and Y1 to Y3
(hereinafter abbreviated to Y1 to Y3 electrodes), addressing
electrodes A1 to A4, and barriers 2. The above sustain discharge
electrodes are juxtaposed in parallel with each other on one
substrate. The addressing electrodes are formed to cross the
sustain discharge electrodes on the other substrate. The barriers 2
are arranged in parallel with the addressing electrodes, thus
separating discharge spaces from each other. A discharge cell is
formed in areas defined by the mutually adjoining sustain discharge
electrodes and the addressing electrodes crossing the sustain
discharge electrodes. Phosphors used to produce visible light are
placed in the discharge cells. A gas for bringing about discharge
is sealed in a space between the substrates. In this drawing, for
brevity's sake, the sustain discharge electrodes are arranged
parallel to each other in threes, and the addressing electrodes
number four.
[0009] In the PDP having the foregoing structure, sustain discharge
is induced in lines defined by each sustain discharge electrode and
sustain discharge electrodes on both sides thereof. Interspaces or
lines (L1 to L5) defined by all the electrodes therefore can work
as display lines. For example, the X1 electrode and Y1 electrode
define a display line L1, and the Y1 electrode and X2 electrode
define a display line L2.
[0010] FIG. 2 shows a sectional view of the PDP shown in FIG. 1
along an addressing electrode. There are shown a front substrate 3,
a back substrate 4, and discharges D1 to D3 induced in lines
defined by electrodes. In practice, a voltage is applied to the Y1
electrode and X1 electrode. This induces the discharge D1. When a
voltage is applied to the Y1 electrode and X2 electrode, the
discharge D2 is induced. The discharge D3 is induced by applying a
voltage to the X2 electrode and Y2 electrode. Thus, one electrode
is utilized for providing display lines on both sides thereof.
Consequently, a high-definition display can be achieved owing to a
decreased number of electrodes. Besides, the number of drive
circuits for driving the electrodes can be reduced accordingly.
[0011] FIG. 3 shows a frame configuration employed in the PDP shown
in FIG. 1. One frame is composed of two fields of a first field and
second field. During the first field, odd-numbered lines (L1, L3
and L5) are used as display lines to be involved in the display.
During the second field, even-numbered lines (L2, L4) are used as
display lines to be involved in the display. Thus, a picture for
one screen is displayed during one frame. Each field consists of a
plurality of sub-fields for which luminance levels are set in a
predetermined ratio. Cells constituting display lines are
selectively allowed to glow according to display data during the
sub-fields. Thus, gray-scale levels construed as differences in
luminance among pixels are expressed. Each sub-field consists of a
reset period, an addressing period, and a sustain discharge period.
During the reset period, the states of cells that are mutually
different depending on the display situation over an immediately
preceding sub-field are uniformed. During the addressing period,
new display data is written. During the sustain discharge period,
sustain discharge is induced in the cells constituting display
lines so that the cells are allowed to glow according to display
data.
[0012] FIG. 4 is a waveform diagram concerning a conventional
driving method implemented in the PDP shown in FIG. 1. FIG. 4 is
concerned with any sub-field within the first field.
[0013] During the reset period, a reset pulse of a voltage Vw
exceeding a discharge start voltage is applied to all the X
electrodes. Discharge is initiated in the lines defined by the X
electrodes and adjoining Y electrodes. As a result, first discharge
(reset discharge) is induced in all the lines (L1 to L5). Wall
charges including positively-charged ions and electrons are
produced in the discharge cells. Thereafter, the reset pulse is
removed and the electrodes are retained at the same potential.
Second discharge (self-erase discharge) is then induced due to the
potential difference generated by the wall charges produced on the
electrodes. At this time, since the electrodes are retained at the
same potential, positively-charged ions and electrons stemming from
discharge are recombined with each other within the discharge
spaces. Consequently, the wall charges disappear. The magnitude of
wall charges in all the display cells can be uniformed with the
discharge (the distribution of wall charges is uniformed).
[0014] During the next addressing period, a scanning pulse of a
voltage -Vy is applied successively to the electrodes starting with
the Y1 electrode. An addressing pulse of a voltage Va is applied to
the addressing electrodes according to display data. Consequently,
addressing discharge is initiated. At this time, a pulse of a
voltage Vx is applied to the X1 electrode to be paired with the Y1
electrode to participate in the display within the first field.
Discharge having been induced in the spaces defined by the
addressing electrodes and the Y1 electrode shifts to the line
between the X1 electrode and Y1 electrode. Consequently, wall
charges needed to initiate sustain discharge are produced near the
X1 electrode and Y1 electrode. The potential at the X2 electrode to
be paired with the Y1 electrode to define a line not involved in
the display is retained at 0 V. It is therefore prevented that
discharge is induced in the line defined by the X2 electrode.
Likewise, addressing discharge is induced successively in the
odd-numbered Y electrodes.
[0015] After the addressing discharge induced in the odd-numbered Y
electrodes is completed, a scanning pulse is applied to the Y2
electrode. At this time, a pulse of a voltage Vx is applied to the
X2 electrode to be paired with the Y2 electrode to thus participate
in the display. The X3 electrode that is not shown is, like the X1
electrode, retained at 0 V. Likewise, addressing discharge is
induced successively in the even-numbered Y electrodes.
Consequently, addressing discharge is induced in the odd lines in
the whole screen.
[0016] Thereafter, during the sustain discharge period, a sustain
pulse of a voltage Vs is applied alternately to the X electrodes
and Y electrodes. At this time, the phase of the sustain pulse is
set so that a potential difference between paired electrodes
defining a line not involved in display will be 0 V. It is thus
prevented that discharge is induced in non-display lines. For
example, sustain pulses that are mutually out of phase are applied
to the pair of the X1 and Y1 electrodes participating in the
display over the first field. In contrast, sustain pulses that are
mutually in phase are applied to the pair of the Y1 and X2
electrodes defining a non-display line. Display is thus achieved
over the first sub-field.
[0017] In FIG. 4, the voltage Vs is a voltage needed to induce
sustain discharge and is usually set to about 170 V. Moreover, the
voltage Vw is a voltage exceeding the discharge start voltage and
set to about 350 V. The voltage -Vy of the scanning pulse is set to
about -150 V, and the voltage Va of the addressing pulse is set to
about 60 V. The sum of the absolute values of the voltages Va and
Vy will be equal to or larger than the discharge start voltage with
which discharge is initiated in the spaces defined by the
addressing electrodes and each Y electrode. Moreover, the voltage
Vx is set to about 50 V or a value causing discharge induced in the
line defined by the addressing electrodes and each Y electrode to
shift to the line defined by an X electrode. The value must enable
production of sufficient wall charges.
[0018] However, according to the foregoing conventional driving
method, reset discharge is adopted. The pulse of the voltage Vw
exceeding the discharge start voltage, with which discharge is
initiated in discharge cells, is applied to the X electrodes. This
results in intense discharge. Light emission stemming from the
discharge is background light emission having no relation to the
display of a picture. This leads to a deterioration in the contrast
of the picture.
[0019] Moreover, in the foregoing driving method using the lines
defined by all the sustain discharge electrodes as display lines,
there is a possibility that reset discharge may not be induced
stably in all the discharge cells. In other words, the reset pulse
is applied to all the X electrodes in order to induce discharge in
all display lines. A discharge start time at which discharge is
initiated in each discharge cell differs from discharge cell to
discharge cell. There is a possibility that discharge may not be
induced in some cells.
[0020] Referring back to FIG. 2, the X2 electrode will be
discussed. If discharge D2 is induced first in the line between the
X2 electrode and Y1 electrode, charges stemming from the discharge
start to be accumulated near the electrodes. The wall charges
generate a bias voltage of the opposite polarity to the voltage Vw
and an effective voltage in the discharge space decreases. More
particularly, wall charges are produced on the X2 electrode due to
electrons. The wall charges cause the effective voltage of the
voltage Vw applied to the X2 electrode in the discharge space to
drop. The drop in the effective voltage may precede the initiation
of discharge in the line between the X2 electrode and Y2 electrode.
In this case, although discharge is not induced in the line between
the X2 electrode and Y2 electrode, the reset period may come to an
end. If reset discharge is not induced in some discharge cells, the
states of the cells are not uniformed. Consequently, addressing
discharge cannot be induced stably in the discharge cells. This
leads to erroneous display.
[0021] Even if reset discharge is induced in all the cells,
subsequent self-erase discharge may not be induced stably. The
self-erase discharge is induced due to the potential difference
generated by the wall charges stemming from reset discharge. The
self-erase discharge may often be smaller in scale that the reset
discharge. Depending on a difference in characteristics from
discharge cell to discharge cell, the self-erase discharge may not
be induced but wall charges stemming from the reset discharge may
remain intact. Otherwise, when the reset discharge is completed,
sufficient wall charges may not be produced and the self-erase
discharge may not be induced. Consequently, subsequent addressing
discharge is not induced normally in discharge cells that have not
undergone erase discharge. This causes erroneous display.
[0022] As a method for solving the above problems, it is
conceivable to raise the voltage of the reset pulse to induce
discharge reliably in all cells. However, a further rise in
discharge voltage will intensify the aforesaid background light
emission and deteriorate the contrast of the picture.
[0023] If the reset period shifts to the addressing period with
wall charges remaining intact in discharge cells because of the
aforesaid cause, another problem arises. During the addressing
period, as mentioned above, the voltage Vx is applied to x
electrodes defining display lines. The other X electrodes defining
non-display lines are held at 0 V, thus preventing the occurrence
of addressing discharge. However, if unnecessary wall charges
remain intact, discharge may be induced in the non-display
lines.
[0024] For example, referring to FIG. 2, the scanning pulse of the
voltage -Vy is applied to the Y1 electrode. The addressing pulse of
the voltage Va is applied to the addressing electrodes, whereby
addressing discharge is induced. At this time, since the voltage Vx
is applied to the X1 electrode, the addressing discharge is
succeeded by discharge to be induced in the line between the Y1
electrode and X1 electrode. Namely, discharge D1 is induced. At
this time, the X2 electrode adjoining the Y1 electrode is held at 0
V. Induction of discharge D2 can be avoided in principle. However,
the discharge D2 may be induced due to deflection of residual
charges deriving from uncertainty of reset discharge. Consequently,
wall charges of negative polarity are accumulated on the X2
electrode. Subsequent addressing discharge D3 is affected by the
wall charges. Incidentally, there is a possibility that erroneous
discharge caused by electrodes not participating in the display may
also be caused by a difference in discharge start voltage from
discharge cell to discharge cell.
[0025] Moreover, sustain discharge induced during each sub-field
may spread depending on the sustain discharge voltage Vs or cell
structure. Referring to FIG. 6, when sustain discharge is induced
in the lines between the X1 and Y1 electrodes and between the X2
and Y2 electrodes, wall charges are accumulated over the electrodes
Y1 and X2 to some extent. These wall charges are erased during the
reset period within each sub-field. Wall charges formed on the
addressing electrodes may not be erased but remain intact. The wall
charges do not affect subsequent discharge to be induced within a
field within which the lines between the X1 and Y1 electrodes and
the X2 and Y2 electrodes are involved in display. The wall charges
destabilize addressing discharge to be induced within the next
field within which the line between the Y1 and X2 electrodes is
involved in the display.
SUMMARY OF THE INVENTION
[0026] The present invention attempts to solve the above problems.
An object of the present invention is to provide a method for
driving a plasma display panel in which reset discharge and erase
discharge can be induced reliably without deterioration in the
contrast of the picture, and addressing discharge can be induced
stably.
[0027] For accomplishing the above object, according to the present
invention, there is provided a method for driving a plasma display
panel. In the plasma display panel, pluralities of first electrodes
and second electrodes are arranged parallel to each other, and a
plurality of third electrodes are arranged to cross the first and
second electrodes. Moreover, discharge cells defined by areas in
which the electrodes cross mutually are arranged in the form of a
matrix. According to the driving method, during a reset period, the
distribution of wall charges in the plurality of discharge cells
are uniformed. During an addressing period, wall charges are
produced in discharge cells according to display data. During a
sustain discharge period, sustain discharge is induced in the
discharge cells in which the wall charges are produced during the
addressing period. The driving method comprises a step of applying
a first pulse in which an applied voltage varies with time so as to
induce first discharge in the lines defined by the first and second
electrodes, and a step of applying a second pulse in which an
applied voltage varies with time so as to induce second discharge
as erase discharge in the lines defined by the first and second
electrodes. Herein, these steps are carried out during the reset
period.
[0028] According to the above driving method, a quite feeble
discharge can be induced as reset discharge. An amount of light
emission is limited. Despite the reset discharge, the contrast of
the picture does not deteriorate remarkably. Subsequent erase
discharge is not self-erase discharge but is induced by applying a
pulse in which an applied voltage varies with time. The erase
discharge can be induced irrespective of a difference in
characteristics from discharge cell to discharge cell or the
magnitude of residual wall charges. Moreover, since the discharge
is feeble, the amount of glow is limited and the contrast of the
picture does not deteriorate remarkably.
[0029] The above-mentioned effects of the present invention can be
exerted even when the present invention is adapted to any
conventional PDP in which each pair of sustain discharge electrodes
provides one display line. Namely, the present invention is not
limited to a PDP in which, as described mainly in the present
specification, the lines defined by all electrodes are involved in
the display.
BRIEF DESCRIPTION OF THE DRAWINGS
[0030] The above object and features of the present invention will
be more apparent from the following description of the preferred
embodiment with reference to the accompanying drawings,
wherein:
[0031] FIG. 1 schematically shows the structure of a surface
discharge type PDP;
[0032] FIG. 2 is a sectional view of the PDP shown in FIG. 1 along
an A1 addressing electrode;
[0033] FIG. 3 shows a frame configuration employed in the PDP shown
in FIG. 1;
[0034] FIG. 4 is a waveform diagram concerning a conventional
driving method implemented in the PDP shown in FIG. 1;
[0035] FIG. 5 is a waveform diagram concerning a first embodiment
of the present invention;
[0036] FIG. 6 shows a frame configuration employed in the first
embodiment of the present invention;
[0037] FIG. 7 is a waveform diagram concerning field reset employed
in the first embodiment of the present invention;
[0038] FIG. 8 is a waveform diagram concerning a second embodiment
of the present invention;
[0039] FIG. 9 is a waveform diagram concerning a third embodiment
of the present invention;
[0040] FIG. 10 is a waveform diagram concerning a fourth embodiment
of the present invention;
[0041] FIG. 11 is a waveform diagram concerning a fifth embodiment
of the present invention;
[0042] FIG. 12 shows a frame configuration employed in a sixth
embodiment of the present invention; and
[0043] FIG. 13 is a waveform diagram concerning the sixth
embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0044] Preferred embodiments of the present invention will be
described with reference to the appended drawings (FIG. 5 to FIG.
13).
[0045] FIG. 5 is a waveform diagram concerning a first embodiment
of the present invention. In FIG. 5, there are shown the waveforms
of voltages to be applied to addressing electrodes, an X1
electrode, a Y1 electrode, an X2 electrode, and a Y2 electrode
during a sub-field within a first field. Odd lines are involved in
display within the first field. The sub-field consists of a reset
period, an addressing period, and a sustain discharge period.
Hereinafter, the X1 and X2 electrodes shall be referred to as X
electrodes, the Y1 and Y2 electrodes shall be referred to as Y
electrodes, and all of them shall be referred to as sustain
discharge electrodes.
[0046] During the reset period, the addressing electrodes are set
to 0 V, and pulses of positive and negative polarities are applied
to the sustain discharge electrodes. Specifically, a pulse of a
voltage -Vwx is applied to the X electrodes, and a pulse of a
voltage Vwy is applied to the Y electrodes. The pulse to be applied
to the Y electrodes is a pulse of gentle slope that reaches the
voltage Vwy with its voltage variation per unit time changed.
Consequently, first feeble discharge is induced in the lines
defined by the x electrodes and Y electrodes.
[0047] When a rectangular wave Vw similar to a conventional one is
applied as an applied voltage, intense discharge is induced
proportional to a difference Vw-Vf from a discharge start voltage
Vf to be applied to initialize discharge in discharge cells. Excess
wall charges are produced to affect adjoining discharge cells.
However, since a slope pulse is adopted, when the applied voltage
exceeds the discharge start voltage Vf to be applied to each
discharge cell, each discharge cell starts discharging. The induced
discharge is merely feeble. The magnitude of produced wall charges
is small. Consequently, even if reset discharge is induced earlier
in a certain discharge cell, the reset discharge will not affect
adjoining discharge cells. Moreover, since the discharge is feeble,
background glow is weak.
[0048] Thereafter, a pulse of a voltage Vex is applied to the X
electrodes, and a pulse of a voltage -Vey is applied to the Y
electrodes. The pulse applied to the Y electrodes is a slope pulse
that reaches a voltage -Vey while changing in magnitude its voltage
variation per unit time. This induces second discharge, whereby
wall charges stemming from the immediately preceding discharge are
erased.
[0049] When self-erase discharge is employed as it is
conventionally, discharge may not be induced depending on the
magnitude of wall charges produced or the characteristic of
discharge cells. According to the present invention, discharge is
forcibly induced by applying a voltage Vex+Vey. Erase discharge is
therefore induced reliably. Furthermore, since an applied pulse is
a slope pulse, discharge is feeble. The contrast of the picture
will not deteriorate. Moreover, the voltage Vex+Vey is set to be
slightly lower than the discharge start voltage Vf. Wall charges of
diminutive magnitude stemming from the first discharge are
superimposed on the voltage, whereby erase discharge is
induced.
[0050] Sustain discharge is induced fundamentally in the lines
defined by the X and Y electrodes. Meanwhile, the addressing
electrodes are retained at a potential lower than a sustain
discharge voltage Vs. Wall charge of positive polarity are
therefore produced on the addressing electrodes. For the first
discharge in this embodiment, the pulse of negative polarity is
applied to the X electrodes. Discharge is induced in the spaces
defined by the addressing electrodes and X electrodes, and released
charges are superimposed on the wall charges remaining on the
addressing electrodes. Consequently, the wall charges remaining on
the addressing electrodes above the X electrodes are erased. For
the subsequent second discharge, the pulse of negative polarity is
applied to the Y electrodes. Wall charges remaining on the
addressing electrodes above the Y electrodes are erased.
[0051] Thereafter, during the addressing period, addressing
discharge is induced by applying a scanning pulse successively to
the Y electrodes. A voltage Vx is, conventionally, applied to X
electrodes that are paired with the Y electrodes, to which the
scanning pulse has been applied, to define display lines.
Consequently, addressing discharge is induced. In contrast, a
voltage -Vux is applied to X electrodes defining non-display lines.
A potential difference from the Y electrodes is thus limited in
order to prevent addressing discharge from being induced in the
non-display lines. The scanning pulse is applied successively to
the odd-numbered Y electrodes in order to induce addressing
discharge. Thereafter, the scanning pulse is applied successively
to the even-numbered Y electrodes in order to induce addressing
discharge. This procedure is the same as that in the conventional
method.
[0052] After the addressing period elapses, the sustain discharge
period starts. A sustain pulse is applied alternately to the X
electrodes and Y electrodes. Sustain discharge is induced
repeatedly in cells having undergone addressing discharge during
the addressing period. At this time, the phase of the sustain
discharge pulse is determined as it conventionally is, so that
sustain discharge will not be induced in non-display lines.
[0053] Referring to FIG. 5, the sum of the absolute values of the
voltages -Vwx and Vwy to be applied during the reset period is set
to a value exceeding the value of a discharge start voltage. The
discharge start voltage is a voltage with which discharge is
initiated in the lines defined by X and Y electrodes. For example,
the voltage -Vwx is set to -130 V, and the voltage Vwy is set to
220 V. For the subsequent erase discharge, for example, the voltage
Vex is set to 60 V, and the voltage -Vey is set to -160 V.
Moreover, for the addressing period, the voltage Va is set to, for
example, 60 V, the voltage -Vy of the scanning pulse is set to, for
example, -150 V. The voltage Vx to be applied to the X electrodes
is set to, for example, 50 V, and the voltage -Vux is set to, for
example, -80 V. Moreover, the voltage Vs of the sustain pulse is
set to, for example, 170 V. Moreover, the voltages Vex and Vx or
-Vey and -Vy may be set to the same voltage. In this case, a
circuit can be used in common, and the scale of circuitry can be
suppressed.
[0054] FIG. 6 shows a frame configuration employed in the first
embodiment of the present invention. A difference from the one
shown in FIG. 3 lies in a point that a field reset period is
defined at the start of each field. The field reset period is a
period during which wall charges remaining on the addressing
electrodes are erased at the time of a field-to-field
transition.
[0055] FIG. 7 is a waveform diagram concerning field reset employed
in the first embodiment of the present invention. At a time instant
t1, a voltage -Vy is applied to the Y electrodes, and a voltage Vs
is applied to the X2 electrodes. Consequently, discharge is induced
and wall charges are produced. Thereafter, the pulses are removed
and the potentials at the electrodes are held at the same value.
Self-erase discharge is induced due to potential differences among
the produced wall charges, whereby the wall charges are erased.
Similarly, reset discharge is induced sequentially in all the lines
defined by the electrodes at four times starting with a time
instant t2 and ending with a time instant t4. Wall charges are
reliably erased. In this embodiment, discharge is induced in the
lines defined by the odd-numbered Y electrodes and even-numbered X
electrodes at the time instant t1. Discharge is induced in the
lines defined by the odd-numbered X electrodes and even-numbered Y
electrodes at the time instant t2. Discharge is induced in the
lines defined by the odd-numbered X electrodes and odd-numbered Y
electrodes at the time instant t3. Discharge is induced in the
lines defined by the even-numbered X electrodes and even-numbered Y
electrodes at the time instant t4. It can be determined arbitrarily
as to in which lines discharge is induced at the time instants t1
to t4.
[0056] In the aforesaid first embodiment, a pulse to be applied to
the Y electrodes for first and second discharge is a slope pulse
whose voltage variation per unit time changes in magnitude. The
pulsating wave can be produced readily by constructing an RC
circuit that consists of resistors R connected to a switching
device for outputting a pulse and electrostatic capacitors C
created among electrodes. A curve plotted by tracing the slope
pulse is determined by the time constant defined by the RC
circuit.
[0057] However, when the slope pulse is employed, the voltage
variation of the pulse per unit time changes in magnitude with the
rise or fall of the pulse. This causes a problem in that the
intensity of discharge varies depending on at what time instant
discharge is initiated. When the pulse is saturated to approximate
a set voltage, if discharge is initiated, very feeble discharge can
be realized. However, discharge may be initiated in a relatively
early stage because of a difference in characteristics from
discharge cell to discharge cell, that is, discharge may be
initiated at the relatively sharp leading or trailing edge of the
pulse. In this case, intense discharge may be induced, and wall
charges of great magnitude may be produced.
[0058] FIG. 8 is a waveform diagram concerning the second
embodiment of the present invention. This embodiment is such that a
pulse to be applied to the Y electrodes for the first and second
discharge is a triangular wave whose voltage variation per unit
time is constant in magnitude. According to this embodiment, the
circuitry for producing the triangular wave is somewhat more
complex than that in the first embodiment. However, since the slope
of the pulse is constant, feeble discharge can be induced
reliably.
[0059] FIG. 9 is a waveform diagram concerning the third embodiment
of the present invention. FIG. 9 is concerned with a time instant
during a sustain discharge period within a sub-field, at which the
last pulse is applied, and a reset period within the next
sub-field. In this embodiment, a slope pulse whose voltage
variation per unit time changes in magnitude is adopted as a pulse
to be applied to the Y electrodes for the first and second
discharge. From this viewpoint, the third embodiment is identical
to the first embodiment. However, in this embodiment, it is
designed that sufficient time has elapsed from the leading edge of
the sustain discharge pulse to be applied during the sustain
discharge period within the sub-field, to the application of a
pulse during the reset period within the next sub-field.
[0060] When sustain discharge is induced with application of the
sustain pulse, wall charges of predetermined magnitude are
accumulated with the completion of discharge. When a certain time
has elapsed since the completion of discharge, produced wall
charges start neutralizing spatial charges existent in discharge
spaces. After sufficient time has passed since the application of
the last sustain pulse, reset discharge is induced. In this way,
wall charges remaining at the end of the sustain discharge period
can be erased to some extent. Consequently, the subsequent reset
discharge can be induced with fewer residual wall charges. The
reset discharge can therefore be induced stably. The time from the
trailing edge of the sustain discharge pulse to the initiation of
the next reset discharge, t1, should be longer than at least 1
.mu.s, or preferably, should be 10 .mu.s.
[0061] Moreover, in this embodiment, for the first discharge to be
induced during the reset period, a pulse of negative polarity is
applied to the X electrodes and a pulse of positive polarity is
applied to the Y electrodes. At this time, the timing of applying
the pulse of negative polarity is different from that of applying
the pulse of positive polarity.
[0062] As mentioned in relation to the first embodiment, a pulse of
negative polarity and a pulse of positive polarity are applied to
the X electrodes and Y electrodes respectively at the same time. In
this case, although a slope pulse is employed, intense discharge
may be induced. In this embodiment, the timing of applying a pulse
of negative polarity to the X electrodes is differentiated from the
one of applying a pulse of negative polarity to the Y
electrodes.
[0063] As mentioned above, a pulse of negative polarity to be
applied to the X electrodes for first discharge exerts the effect
of erasing wall charges remaining on the addressing electrodes.
When the erase discharge is induced earlier, wall charges of
positive polarity are produced on the X electrodes, to which the
pulse of negative polarity has been applied, along with the erasure
of wall charges on the addressing electrodes. If a second pulse of
positive polarity is applied to the Y electrodes in this state, an
effective voltage in the lines defined by the X and Y electrodes
drops to prevent intense discharge. For merely preventing intense
discharge, the voltage of negative polarity to be applied to the X
electrodes is lowered according to a method. In this case, it
becomes difficult to induce erase discharge in the spaces below the
addressing electrodes. This is not preferable.
[0064] A delay time t2 from the application of a pulse to the X
electrodes to application of a pulse to the Y electrodes should be
at least about 5 .mu.s.
[0065] FIG. 10 is a waveform diagram concerning the fourth
embodiment of the present invention, wherein only the waveform of a
voltage to be applied to the Y electrodes during the reset period
is illustrated. A pulse to be applied to the Y electrodes is a
slope pulse whose voltage variation per unit time changes in
magnitude.
[0066] In the aforesaid first to third embodiments, the potential
at the Y electrodes which has reached Vwy is lowered to 0 V at the
time of second discharge succeeding first discharge. Thereafter, a
pulse for inducing the second discharge is applied. However, when
the potential at the Y electrodes is lowered to 0 V, if high
voltages are concurrently applied to the electrodes, intense
discharge may be induced. When the application of a pulse of
positive polarity to the X electrodes and the application of a
pulse of negative polarity to the Y electrodes are concurrently
carried out for the second discharge, it means that the high
voltages are concurrently applied to the electrodes.
[0067] According to this embodiment, in the case of a portion "a"
of FIG. 10, the potential at the Y electrodes is not lowered to 0 V
but the pulse for inducing the second discharge is applied
immediately. This can prevent concurrent application of high
voltages to the electrodes. Consequently, intense discharge can be
avoided.
[0068] However, the case of the portion "a" of FIG. 10 poses a
problem in that the time required for the second discharge gets
longer. This is because the potential at the Y electrodes is
dropped from Vwy to -Vey using a slope pulse. For shortening the
time required for the second discharge, a voltage variation per
unit time must be increased in magnitude. Consequently, the scale
of the second discharge expands and the contrast of the picture
deteriorates.
[0069] The case of a portion "b" of FIG. 10 stands in the middle of
the first to third embodiments and the case of the portion "a" of
FIG. 10. Namely, the potential at the Y electrodes that has reached
Vwy is lowered to a potential higher than 0 V (for example, about
20 V). Thereafter, a pulse of negative polarity that is a slope
pulse is applied.
[0070] For example, the potential at the Y electrodes that has
reached Vwy is lowered to Vs by connecting the Y electrodes to a
power supply Vs for sustain discharge. Furthermore, a power
collection circuit connected to the Y electrodes is used to lower
the potential at the Y electrodes to a predetermined value. This
technique is readily adopted. The power collection circuit is
realized with a series resonant circuit composed of an inductor
connected to the Y electrodes (or X electrodes) and a panel
capacitor. The power collection circuit collects and reuses the
sustain voltage Vs applied to the electrodes. During the sustain
discharge period, the sustain voltage Vs is applied alternately to
the X and Y electrodes. This action is equivalent to charging and
discharging of the panel capacitor realized with the lines defined
by the X and Y electrodes. The power collection circuit effectively
utilizes the charging current and discharging current. The power
collection circuit is indispensable to low power consumption to be
attained in a PDP. By utilizing the power collection circuit, the
potential at the Y electrodes can be lowered without addition of a
new circuit.
[0071] After the potential at the Y electrodes is lowered to a
predetermined value, the Y electrodes are connected to a
conventional circuit for generating a slope erase pulse.
Consequently, in this case, neither intense discharge will be
induced nor the magnitude of a voltage variation per unit time will
be increased. Nevertheless, the time required for the second
discharge can be shortened.
[0072] FIG. 11 is a waveform diagram concerning the fifth
embodiment of the present invention. In this embodiment, when the
second discharge is completed, the potential at the Y electrodes
reaches a potential higher than -Vy that is the voltage of the
scanning pulse.
[0073] A slope pulse which is to be applied to the Y electrodes for
the second discharge has a negative polarity. Positive wall charges
are therefore produced on the Y electrodes. In the aforesaid first
to fourth embodiments, the potential at the Y electrodes is lowered
to -Vy that is the voltage of the scanning pulse. Produced wall
charges are of relatively great magnitude. During the subsequent
addressing period, the scanning pulse of negative polarity is
applied to the Y electrodes. At this time, if positive wall charges
remain intact, the effective voltage of the scanning pulse is
lowered. This leads to a possibility of hindering stable induction
of addressing discharge. In contrast, the potential at the Y
electrodes may be too high at the completion of the second
discharge (for example, the unselected potential -Vsc at Y
electrodes during the addressing period). In this case, negative
wall charges are produced on the Y electrodes. Consequently, when
the scanning pulse of negative polarity is applied to the Y
electrodes, the negative wall charges are superimposed on the
scanning pulse. Eventually, there arises a possibility that
discharge may be induced in cells in which the addressing pulse has
not been applied.
[0074] In this embodiment, the potential at the Y electrodes
attained at the completion of the second discharge is an
intermediate one between the selected potential -Vy at Y electrodes
during the addressing period and the unselected potential -Vsc at Y
electrodes. Addressing discharge can therefore be induced stably.
Otherwise, for ensuring the same margin for driving as a
conventionally ensured one, the applied voltage of the addressing
pulse may be lowered. The potential at the Y electrodes to be
attained should be set so that a rise .DELTA.V from the selected
potential -Vy at Y electrodes during the addressing period will
fall within a range of 0<.DELTA.V<20 V, or preferably, will
be approximately 10 V.
[0075] FIG. 12 shows a frame configuration employed in the sixth
embodiment of the present invention. FIG. 13 is a waveform diagram
concerning the sixth embodiment. The sixth embodiment is identical
to the first embodiment in a point that the field reset period
described in conjunction with FIG. 6 is adopted. The sixth
embodiment is characterized in that a field reset charge adjustment
period (i.e., field reset charge adjusting period) is adopted.
[0076] After the first field or second field elapses, the states of
charges in the cells are mutually different. This is because the
discharged states of the cells attained within each field are
mutually different. If wall charges whose polarity is opposite to
that of an applied pulse used to carry out field reset remain
intact at the start of the field reset period, the effective
voltage of the applied pulse is lowered. This makes it difficult to
carry out field reset stably. For example, in the example of FIG.
7, if positive wall charges remain intact on the Y1 electrode (or
negative wall charges remain intact on the X2 electrode), effective
voltages to be applied to the Y1 and X2 electrodes are lowered.
This disables stable discharge. In this embodiment, the field reset
period is preceded by the field reset charge adjustment period.
Wall charges whose polarity is the same as that of a pulse to be
applied during the field reset period are produced actively.
[0077] FIG. 13 is a practical waveform diagram. During the field
reset charge adjustment period, first, a pulse of negative polarity
is applied to the X1 electrode, and a pulse of positive polarity is
applied to the Y1 electrode. The sum of the voltage Vwx applied to
the X1 electrode and the voltage Vwy applied to the Y1 electrode
exceeds a discharge start voltage with which discharge is initiated
in each cell. Consequently, discharge is initiated in all the
cells. At this time, the pulse to be applied to the Y1 electrode is
a slope pulse whose voltage variation per unit time changes in
magnitude. The discharge is therefore, similarly to the first
discharge induced during the reset period, a feeble discharge. A
deterioration in the contrast of the picture can therefore be
suppressed. The whole-surface discharge causes negative wall
charges to be accumulated on the Y1 electrode. However, the
accumulated wall charges are of great magnitude. If the field reset
charge adjustment period is shifted to the field reset period in
this state, discharge becomes too large in scale due to
superimposition of wall charges. An erase pulse of negative
polarity is therefore applied to the Y1 electrode, whereby the
magnitude of accumulated wall charges is adjusted. The pulse of
negative polarity is a slope pulse whose voltage variation per unit
time changes in magnitude.
[0078] Consequently, negative wall charges of proper magnitude are
accumulated at the end of the field reset charge adjustment period.
When the field reset charge adjustment period is shifted to the
field reset period in this state, the produced wall charges are
superimposed on an applied pulse. Field reset can be carried out
reliably.
[0079] In summary, the method for driving a plasma display panel
according to one aspect of typical embodiments described above of
the present invention is such that the first pulse of positive
polarity is applied to the second electrodes, and a pulse of
negative polarity is applied to the first electrodes. Thereafter,
the second pulse of negative polarity is applied to the second
electrodes, and a pulse of positive polarity is applied to the
first electrodes.
[0080] According to the above driving method, the second pulse is
applied to be superimposed on wall charges stemming from first
discharge. Erase discharge can be induced reliably by utilizing the
voltages of the wall charges. Moreover, the pulse of negative
polarity is applied to the first electrodes for inducing the first
discharge, or the second pulse of negative polarity is applied to
the second electrodes for inducing second discharge. Wall charges
remaining on the addressing electrodes at the completion of sustain
discharge within a previous sub-field can be erased
successfully.
[0081] Preferably, the method for driving a plasma display panel is
such that the pulse to be applied for inducing first discharge is
applied when a period longer than at least 1 .mu.s has elapsed
since the end of the sustain discharge period.
[0082] According to the above driving method, residual wall charges
can be diminished prior to reset discharge.
[0083] Further, preferably, the method for driving a plasma display
panel is such that, for inducing first discharge, the pulse of
negative polarity is applied to the first electrodes before the
first pulse of positive polarity is applied to the second
electrodes.
[0084] According to the above driving method, wall charges
remaining on the addressing electrodes can be erased, and it can be
prevented that first discharge becomes intense.
[0085] Further, preferably, the method for driving a plasma display
panel is such that each of the first and second pulses in which an
applied voltage varies with time is a slope pulse whose voltage
variation per unit time changes in magnitude.
[0086] According to the above driving method, there is a
possibility that when a discharge start time differs with the state
of a discharge cell, the intensity of discharge may vary. However,
the method can be implemented with relatively simple circuitry.
[0087] Further, preferably, the method for driving a plasma display
panel is such that each of the first and second pulses in which an
applied voltage varies with time is a triangular wave whose voltage
variation per unit time is constant.
[0088] According to the above driving method, although the
circuitry is somewhat complex, feeble discharge can be induced
reliably in all the discharge cells.
[0089] Further, preferably, the method for driving a plasma display
panel is such that when the second pulse is applied, the potential
at electrodes having reached a first potential with application of
the first pulse is not lowered to a second potential that is the
potential at the electrodes attained prior to the application of
the first pulse.
[0090] According to the above driving method, it can be prevented
that the second discharge becomes intense.
[0091] Further, preferably, the method for driving a plasma display
panel is such that the potential at electrodes having reached the
first potential with the application of the first pulse is lowered
to a third potential higher than the second potential, and then the
second pulse is applied.
[0092] According to the above driving method, the second discharge
does not require a long time. Besides, it can be prevented that the
second discharge becomes intense.
[0093] Further, preferably, the method for driving a plasma display
panel is such that the potential at electrodes to be reached with
application of the second pulse is higher than the selected
potential at the second electrodes during the addressing period and
lower than the unselected potential at the second electrodes during
the addressing period.
[0094] According to the above driving method, wall charges of
proper magnitude can remain intact prior to addressing
discharge.
[0095] According to another aspect of typical embodiments described
above of the present invention, there is provided the method for
driving a plasma display panel. In the plasma display panel,
pluralities of first electrodes and second electrodes are arranged
parallel to each other, and a plurality of third electrodes are
arranged to cross the first and second electrodes. Discharge cells
defined with areas in which the electrodes cross mutually are
arranged in the form of a matrix. According to the driving method,
a first field and second field are temporally separated from each
other. Within the first field, discharge is induced in the lines
defined by the second electrodes and first electrodes adjoining one
sides of the second electrodes for the purpose of display. Within
the second field, discharge is induced in the lines defined by the
second electrodes and first electrodes adjoining the other sides of
the second electrodes for the purpose of display. The first and
second fields each include a reset period, an addressing period,
and a sustain discharge period. The reset period is a period during
which the distribution of wall charges in the plurality of display
cells is uniformed. The addressing period is a period during which
wall charges are produced in discharge cells according to display
data. The sustain discharge period is a period during which sustain
discharge is induced in the discharge cells in which wall charges
are produced during the addressing period. During the reset period,
discharge is induced by applying a pulse whose applied voltage
varies with the passage of time.
[0096] According to the above driving method, the lines defined by
all the sustain discharge electrodes are involved in the display. A
feeble discharge can be induced as reset discharge. The magnitude
of wall charges to be produced is limited. The produced wall
charges will not affect adjoining display lines. Moreover, since
the discharge is feeble, an amount of light emission is limited.
Despite reset discharge, the contrast of the picture will not
deteriorate remarkably.
[0097] Preferably, the method for driving a plasma display panel is
such that after discharge is induced by applying the pulse, a
second pulse in which an applied voltage varies with time is
applied for inducing erase discharge.
[0098] According to the above driving method, erase discharge is
not self-erase discharge but is induced by applying a pulse in
which an applied voltage varies with time. The erase discharge can
be induced reliably irrespective of a difference in characteristics
from discharge cell to discharge cell or the magnitude of residual
wall charges. Moreover, since the discharge is feeble, an amount of
light emission is limited. Despite the erase discharge, the
contrast of the picture will not deteriorate remarkably.
[0099] Further, preferably, the method for driving a plasma display
panel is such that during the addressing period within the first
field, a pulse of first polarity is applied to ones of the first
electrodes, a pulse of second polarity is applied to the others of
the first electrodes, and a scanning pulse of second polarity is
applied successively to the second electrodes. During the
addressing period within the second field, a pulse of first
polarity is applied to the others of the first electrodes, a pulse
of second polarity is applied to ones of the first electrodes, and
the scanning pulse of second polarity is applied successively to
the second electrodes.
[0100] According to the above driving method, the lines defined by
all the sustain discharge electrodes are involved in the display.
The potential difference among non-display lines occurring during
the addressing period is limited, whereby the occurrence of
erroneous discharge can be prevented.
[0101] According to still another aspect of typical embodiments
described above of the present invention, there is provided the
method for driving a plasma display panel. In the plasma display
panel, pluralities of first electrodes and second electrodes are
arranged parallel to each other, and a plurality of third
electrodes are arranged to cross the first and second electrodes.
Discharge cells defined with areas in which the electrodes cross
mutually are arranged in the form of a matrix. According to the
driving method, a first field and second field are temporally
separated from each other. Within the first field, discharge is
induced in the lines defined by the second electrodes and first
electrodes adjoining one sides of the second electrodes for the
purpose of display. Within the second field, discharge is induced
in the lines defined by the second electrodes and first electrodes
adjoining the other sides of the first electrodes for the purpose
of display. The first and second fields are each composed of a
field reset period and a plurality of sub-fields. Each sub-field
includes a reset period, an addressing period, and a sustain
discharge period. The field reset period is a period during which
discharge is induced for erasing wall charges remaining at the end
of a previous field. The reset period is a period during which the
distribution of wall charges in a plurality of discharge cells is
uniformed. The addressing period is a period during which wall
charges are produced in discharge cells according to display data.
The sustain discharge period is a period during which sustain
discharge is induced in the discharge cells in which wall charges
are produced during the addressing period.
[0102] According to the above driving method, the lines defined by
all the sustain discharge electrodes are involved in display. Wall
charges remaining at the end of a previous field can be erased.
[0103] Preferably, the method for driving a plasma display panel is
such that the field reset period is composed of four periods.
During one of the four periods, discharge is induced in the lines
defined by first even-numbered electrodes and second odd-numbered
electrodes. During another period, discharge is induced in the
lines defined by first odd-numbered electrodes and second
even-numbered electrodes. During still another period, discharge is
induced in the lines defined by the first odd-numbered electrodes
and second odd-numbered electrodes. During the other period,
discharge is induced in the lines between the first even-numbered
electrodes and second even-numbered electrodes.
[0104] According to the above driving method, wall charges produced
on the electrodes, especially, on the addressing electrodes can be
erased reliably.
[0105] Further, preferably, the method for driving a plasma display
is such that the discharge to be induced during the field reset
period is accompanied by self-erase discharge. The self-erase
discharge is induced by the potential difference generated by the
wall charges. The wall charges are produced with the potential at
the electrodes set to the same value after reset discharge is
induced by applying a pulse to the electrodes.
[0106] According to the above driving method, after reset discharge
is induced, wall charges can be erased stably by self-erase
discharge.
[0107] Further, preferably, the method for driving a plasma display
panel is such that the first and second fields each include a field
reset charge adjustment period preceding the field reset period.
The field reset charge adjustment period is a period during which
wall charges are produced to be superimposed on charges released
during the field reset period.
[0108] According to the above driving method, field reset can be
achieved stably irrespective of the states of discharge cells
attained at the end of an immediately preceding field.
[0109] Further, preferably, the method for driving a plasma display
panel comprises a step of applying a first pulse in which an
applied voltage varies with time, so as to induce discharge, and a
step of applying a second pulse, in which an applied voltage varies
with time, so as to adjust the magnitude of wall charges produced
with the first pulse. These two steps are carried out during the
field reset charge adjustment period.
[0110] According to the above driving method, wall charges to be
superimposed on charges released during field reset can be left at
a proper magnitude. Discharge to be induced in the field reset
charge adjustment period is therefore a feeble discharge.
[0111] As explained above, according to typical embodiments of the
present invention, a deterioration in the contrast of the picture
can be suppressed. Besides, reset discharge and subsequent erase
discharge can be induced reliably in all display lines.
Consequently, the states of all the cells can be reliably uniformed
during the reset period. Eventually, addressing discharge can be
induced stably and erroneous display can be prevented.
* * * * *