U.S. patent application number 10/687300 was filed with the patent office on 2004-07-29 for analog-to-digital converter.
This patent application is currently assigned to ESS Technology, Inc.. Invention is credited to Mallinson, Andrew Martin.
Application Number | 20040145509 10/687300 |
Document ID | / |
Family ID | 29780491 |
Filed Date | 2004-07-29 |
United States Patent
Application |
20040145509 |
Kind Code |
A1 |
Mallinson, Andrew Martin |
July 29, 2004 |
Analog-to-digital converter
Abstract
An analog-to-digital converter in which each of a plurality of
comparators is, in a successive approximation manner, selectively
enabled or disabled and the outputs from those comparators summed
together to produce a digital signal therefrom. By weighting and
mixing outputs of adjacent comparators in proportions calculated to
provide an interpolated output of a virtual comparator between the
actual comparators, many such virtual comparators can be created
without the need for additional fixed hardware elements in the
converter. By doing so, the converter is able to produce a digital
output having n bits using only N actual hardware elements for
comparing signals, where N<2.sup.n-1. Each of the plurality of
comparators in the converter has an input for an enabling signal,
which enabling signal can be manipulated to enable or disable
individual comparators and to modify their outputs. A method for
converting an analog input signal into a digital signal using such
a converter.
Inventors: |
Mallinson, Andrew Martin;
(Fremont, CA) |
Correspondence
Address: |
David R. Stevens
Stevens Law Group
P.O. Box 1667
San Jose
CA
95109
US
|
Assignee: |
ESS Technology, Inc.
Fremont
CA
|
Family ID: |
29780491 |
Appl. No.: |
10/687300 |
Filed: |
October 15, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10687300 |
Oct 15, 2003 |
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10351267 |
Jan 23, 2003 |
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6677874 |
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Current U.S.
Class: |
341/159 |
Current CPC
Class: |
H03M 1/206 20130101;
H03M 1/0854 20130101; H03M 1/144 20130101; H03M 1/367 20130101;
H03M 1/1235 20130101 |
Class at
Publication: |
341/159 |
International
Class: |
H03M 001/36 |
Claims
1. An analog-to-digital converter comprising: a converter input for
receiving an analog input signal to be converted; an input
impedance network for creating a plurality of reference signals; a
plurality of comparators corresponding to said plurality of
reference signals, each of said comparators having a first
comparator input connected to said input impedance network to
provide said comparator with one of said plurality of reference
signals, a second comparator input connected to said converter
input for receiving said analog input signal, a third comparator
input connected to its own enabling signal source for receiving an
enabling signal, and a comparator output that outputs a signal only
when signals are received at the same time at the first, second,
and third comparator inputs; and a converter output connected to a
comparator output of each of said plurality of comparators.
2. An analog-to-digital converter as claimed in claim 1, wherein
the first comparator input and second comparator input of each of
said plurality of comparators control the transfer of an enabling
signal at the third comparator input to a signal at the comparator
output, and wherein the transfer characteristic of each comparator
between the third comparator input to the comparator output is
linear.
3. An analog-to-digital converter as claimed in claim 2 wherein
each of said plurality of comparators comprises a first and a
second three-terminal semiconductor device, said first
semiconductor device having its base or gate connected to said
first comparator input and said second semiconductor device having
its base or gate connected to said second comparator-input, and the
low impedance connection of said first and second semiconductor
devices connected in common to said third comparator input.
4. An analog-to-digital converter as claimed in claim 3 wherein
each of said first and second semiconductor devices is a
field-effect transistor device.
5. An analog-to-digital converter as claimed in claim 3 wherein
each of said first and second semiconductor devices is a bipolar
junction transistor device.
6. An analog-to-digital converter comprising: a converter input for
receiving an analog input signal to be converted; an input
impedance network connected to said converter input for creating a
plurality of reference signals having a parabolic profile, said
profile having a zero which varies as a function of said analog
input signal; a plurality of comparators corresponding to said
plurality of reference signals, each of said comparators having a
first comparator input connected to said input impedance network to
provide said comparator with one of said plurality of reference
signals, a second comparator input connected to said input
impedance network to provide said comparator with a different one
of said plurality of reference signals, a third comparator input
connected to its own enabling signal source for receiving an
enabling signal, and a comparator output that outputs a signal only
when signals are received at the same time at the first, second,
and third comparator inputs; and a converter output connected to a
comparator output of each of said plurality of comparators.
7. An analog-to-digital converter as claimed in claim 6, wherein
the first comparator input and second comparator input of each of
said plurality of comparators control the transfer of an enabling
signal at the third comparator input to a signal at the comparator
output, and wherein the transfer characteristic of each comparator
between the third comparator input to the comparator output is
linear.
8. An analog-to-digital converter as claimed in claim 7 wherein
each of said plurality of comparators comprises a first and a
second three-terminal semiconductor device, said first
semiconductor device having its base or gate connected to said
first comparator input and said second semiconductor device having
its base or gate connected to said second comparator input, and the
low impedance connection of said first and second semiconductor
devices connected in common to said third comparator input.
9. An analog-to-digital converter as claimed in claim 8 wherein
each of said first and second semiconductor devices is a
field-effect transistor device.
10. An analog-to-digital converter as claimed in claim 8 wherein
each of said first and second semiconductor devices is a bipolar
junction transistor device.
11. An analog-to-digital converter as claimed in claim 6 wherein
said analog input signal is a differential signal applied across
said impedance network.
12. A method for converting an analog input signal into a digital
output signal, comprising: providing a converter having an input
for receiving an analog input signal and a plurality of comparators
for comparing said analog input signal directly or indirectly to a
plurality of reference signals; providing a plurality of reference
signals corresponding to each of said plurality of comparators;
applying an analog input signal to said converter; repeatedly, in a
successive approximation manner, selectively enabling or disabling
each of said plurality of comparators to compare said signals and
then summing the outputs of said comparators together; and
producing said digital output signal from said summed outputs of
said comparators.
13. A method as claimed in claim 12 further comprising creating a
virtual comparator during an iteration of said repeated comparisons
in a successive approximation manner by enabling more than one of
said plurality of comparators at the same time and modifying the
outputs of said enabled comparators prior to summing said outputs
together, such modifications in proportions that linearly
interpolate between the outputs of said comparators so as to
simulate a virtual comparator having an interstitial output between
the outputs of said enabled comparators.
14. A method as claimed in claim 12 wherein said analog input
signal is differential.
15. An analog-to-digital converter comprising: a converter input
for receiving an analog input signal to be converted to digital
data; a parabolic impedance network, the network including a bank
of resistors, a plurality of nodes occurring between each resistor
a plurality of current sources, where each current source
corresponds to each node, wherein each resistor and corresponding
current source is configured to create an individual voltage
reference having a value that occurs in a parabolic manner in
relation to other voltage references occurring across the impedance
network; a plurality of comparators corresponding to said plurality
of reference signals, wherein the parabolic impedance network
provides parabolic reference voltage inputs summed together with an
input voltage to an input of each corresponding comparator, wherein
each comparator includes an enablement signal input connected to an
enabling signal source for receiving an enabling signal, and a
comparator output that outputs a signal when the comparator is
enabled; and a converter output connected to a common output of
each of said plurality of comparators, wherein the output is
configured to output a value that is interpolated between two nodes
to create a virtual comparator occurring between two nodes.
16. A voltage to current converter according to claim 15, wherein
the converter output connected to a common output of each of said
plurality of comparators is configured to output a value that is
interpolated between two nodes according to the formula
V.sub.i,out=V.sub.i.multidot.E- .sub.i, where 1.ltoreq.i.ltoreq.N,
V.sub.i is the difference between the input signal V.sub.in and the
reference signal applied to comparator C.sub.i, and E.sub.i is the
value of an enabling signal that can be varied between two
consecutive integers to create a virtual comparator occurring
between two nodes.
17. A voltage to current converter according to claim 15, wherein
the parabolic impedance network is configured to provide a
reference voltage to the an input of a comparator of each of the
plurality of comparators in a manner that would produce reference
voltages in a parabolic manner, where the reference voltage
provided to one comparator is of a relatively lower value than the
reference voltage provided to an intermediately located comparator,
and where the reference voltage of the intermediately located
comparator receives a maximum voltage value relative to the other
comparators.
18. A voltage to current converter according to claim 15, wherein
the parabolic impedance network is configured to provide a
reference voltage to the an input of a comparator of each of the
plurality of comparators in a manner that would produce reference
voltages in a parabolic manner, where the reference voltage
provided to one comparator is of a relatively higher value than the
reference voltage provided to an intermediately located comparator,
and where the reference voltage of the intermediately located
comparator receives a minimum voltage value relative to the other
comparators.
19. A voltage to current converter according to claim 15, wherein
the comparators each include a pair of transistors, wherein the
parabolic impedance network is configured to provide a reference
voltage to the drain of one of a pair of transistors of each of the
plurality of comparators in a manner that would produce reference
voltages in a parabolic manner, where the reference voltage
provided to one comparator is of a relatively higher value than the
reference voltage provided to an intermediate comparator, and where
the intermediate comparator receives of a minimum voltage value
relative to the other comparators.
Description
BACKGROUND
[0001] This invention relates to analog-to-digital converters, and
more particularly, to an analog-to-digital converter configured
with virtual comparators to produce an increased number of output
bits with relatively low hardware requirements.
[0002] Analog-to-digital converters are well known in the art. One
type of analog-to-digital converter, is a "successive
approximation" converter. A successive approximation converter is
configured to collect bits of information pertaining to the level
of the input analog signal successively in time. Each individual
collection of bits is compiled with the other collected bits to
characterize the input signal to a desired accuracy or resolution
determined by the analog-to-digital converter. Typically, a
successive approximation converter uses a single comparator to
derive a single bit of information at a time on each clock cycle.
In operation, during each clock cycle, a single comparator compares
the input signal to a single reference signal and provides one bit
of information. That reference signal is then adjusted based on
this one bit. On the second clock cycle, an additional bit is
derived using the adjusted reference signal. This process is
repeated for a predetermined number of clock cycles sufficient to
provide the number of bits required for a digital output of a
desired resolution and accuracy. The collected bits are then
assembled at the end of the process to deliver a digital output
with the desired resolution and accuracy of the converter.
[0003] Attempts have been made to create an effective
analog-to-digital converter that can produce a digital output
having n bits using less than 2.sup.n-1 comparators to do so. In
one conventional example, an analog-to-digital converter purports
to use less than 2.sup.n-1 comparators by employing a plurality of
"pseudo-comparators". These pseudo-comparators are placed between
each pair of distantly-spaced actual comparators in order to
generate interstitial outputs. These outputs are tailored to
simulate the output of an actual comparator in that position based
on weighted averages of the comparator outputs. Although such a
circuit decreases the number of "primary" comparators on the input
reference nodes, these pseudo-comparators are still actual discrete
"hardware" elements in the converter circuitry. These elements
exist at all times in fixed, predetermined and interpolative
intervals, even though they are not actually connected to the input
reference nodes. Thus, there is no real reduction in circuit
elements. Another problem is that predetermined pseudo-comparator
hardware elements are not variable, making them inflexible.
[0004] Therefore, there exists a need for a device and method for
simultaneously collecting multiple bits of data but with relatively
fewer circuit elements. As will be seen, the invention accomplishes
this in an elegant manner.
SUMMARY OF INVENTION
[0005] The invention provides an analog-to-digital converter and
related method where a plurality of comparators is arranged in a
successive approximation manner. In operation, the converter is
configured to selectively enable or disable the outputs from the
individual comparators and sum the outputs together to produce a
digital signal output. Furthermore, interpolated outputs may be
derived by weighting and mixing outputs of adjacent comparators in
proportions calculated to provide an interpolated output of a
virtual comparator between actual comparators. Accordingly, many
such virtual comparators can be created without the need for
additional fixed hardware elements in the converter. By doing so,
the converter is able to produce a digital output having a
relatively larger number of bits using relatively few actual
hardware elements for comparing signals.
[0006] Each of the plurality of comparators in the converter has
additional inputs for a reference signal and/or an analog input
signal. Each comparator further includes an input for an enablement
signal and is configured to enable and disable the operation of a
comparator in response to such a signal. Each comparator also
includes components that produce a linear output in proportion to
the enablement signal. Thus, according to the invention, a
comparator output can be modified over a range by modifying the
enablement signal by the desired proportions.
[0007] The invention also provides a method for converting an
analog input signal into a digital signal in a successive
approximation method to selectively enable or disable individual
comparators over an input range and to sum the outputs of the
comparators together. Virtual comparators can be created simply by
varying the enabling signal to enable and disable comparators to
varying degrees. Accordingly, the outputs of adjacent comparators
together may be weighted and mixed together in proportions. This
gives rise to virtual comparators created by operation of an
interstitial output between the outputs of the actual
comparators.
BRIEF DESCRIPTION OF DRAWINGS
[0008] FIG. 1 is a diagrammatic view of a circuit for an
analog-to-digital converter having a plurality of comparators each
of which compares an input signal against one of a plurality of
reference signals defined by an impedance network;
[0009] FIG. 2 is a diagrammatic view of a circuit for an
analog-to-digital converter having a plurality of comparators each
of which compares two points within a parabolic profile of
reference signals defined by an impedance network, where the
profile of the output shifts as a function of an input signal;
[0010] FIG. 3 is a diagrammatic view of a circuit showing a
plurality of comparators in an analog-to-digital converter, each
comparator having an input for an enabling signal to selectively
enable and disable the comparator and to modify its output to
generate an interstitial output occurring between two
comparators;
[0011] FIG. 4 is a graph showing the output signals of a comparator
versus the input signals;
[0012] FIG. 5 is a graph showing the overall differential output of
a converter when it is enabled, versus the difference in its input
signals; and
[0013] FIG. 6 is a graph showing the overall output of converter
when two comparators are enabled, versus the difference in input
signals to those comparators.
DETAILED DESCRIPTION
[0014] An analog-to-digital converter according to the invention is
operated in a successive approximation manner. Unlike conventional
successive approximation analog-to-digital converters, a converter
configured according to the invention includes a plurality of
comparators rather than just one. According to the invention, the
converter uses many comparators, although only a small number of
those comparators will be enabled at any given time. Furthermore,
any two comparator outputs may be interpolated to produce digital
data information from a signal range that may fall between the two
comparators. Thus, a virtual comparator is created. The invention
is described below in the context of a successive approximation
comparator for use in converting analog signals to digital output.
It will be appreciated by those skilled in the art, however, that
other useful applications of the invention may be implemented
without departing from the spirit and scope of the invention, where
the scope is defined in the appended claims.
[0015] FIG. 1 is a schematic diagram of a circuit that is
conventionally used as a flash analog-to-digital converter. The
circuit may also be used as a successive approximation converter in
accordance with one embodiment of this invention. A successive
approximation converter 100 includes a plurality of comparators
connected to a corresponding plurality of reference signals at
nodes defined by an input impedance network. This is an improvement
over a single comparator that is typically used in such a converter
because no DAC is required to settle in a feedback path. As
illustrated in FIG. 1, an input impedance network in the form of a
serially-connected resistor chain includes N resistors R.sub.1,
R.sub.2, R.sub.3, . . . R.sub.N. These resistors have interstitial
nodes defined between them that provide reference signals for a
plurality of N comparators C.sub.1, C.sub.2, C.sub.3, . . .
C.sub.N. In the example specifically illustrated in FIG. 1, N=6,
giving 6 resistors and 6 comparators. However, N may be any integer
greater than 1 without deviating from the invention. Still
referring to FIG. 1, the voltage level of the plurality of
reference signals is set by signals(s) V.sub.left, V.sub.right
applied across the resistor chain. The input voltage V.sub.right
may represent ground potential, but may represent another voltage
level depending on the particular application. Those skilled in the
art will appreciate that different voltage levels occurring on
either voltage reference may vary without departing from the
invention. Each of the comparators C.sub.1, C.sub.2, C.sub.3, . . .
C.sub.N has a first input connected to a terminal configured to
receive the analog input signal V.sub.in. Each comparator also
includes a second input connected to one of the nodes in the
impedance network defined by resistors R.sub.1, R.sub.2, R.sub.3, .
. . R.sub.N. The outputs V.sub.1,out, V.sub.2,out, V.sub.3,out, . .
. V.sub.N,out of the respective comparators C.sub.1, C.sub.2,
C.sub.3, . . . C.sub.N are combined and converted, for example by
an encoder or data converter (not shown), into a digital output
word having a desired number of bits n. Alternatively, they may be
combined and converted into n separate digital signal outputs. The
number of comparators, N, would typically be equal to at least
2.sup.n-1 in conventional systems. According to the invention,
however, the finite number of nodes may be used to interpolate
digital data bit values between any two nodes. Thus, virtual
comparators may be created to produce a larger number of samples of
information related to data bits than the number of actual
comparators.
[0016] According to the invention, still referring to FIG. 1, the
converter 100 is operated in a successive approximation manner. In
particular, according to one embodiment of the invention, only one
comparator of the plurality of comparators C.sub.1, C.sub.2,
C.sub.3, . . . C.sub.N is enabled at any given time while the
remainder are disabled. In this way, the converter 100 operates in
a conventional successive approximation manner, where one bit
sample is collected for each clock cycle rather than collecting
multiple data bits simultaneously.
[0017] Each of the plurality of comparators C.sub.1, C.sub.2, C3, .
. . C.sub.N outputs a quantity
V.sub.i,out=V.sub.i.multidot.E.sub.i, where 1.ltoreq.i.ltoreq.N,
and V.sub.i is the difference between the input signal V.sub.in and
the reference signal applied to comparator C.sub.i. In this
equation, E.sub.i is the value of an enabling signal. In one
embodiment, E.sub.i=0 to disable the comparator and E.sub.i=1 to
enable the comparator. If the outputs V.sub.i,out of all of the
comparators C.sub.1, C.sub.2, C.sub.3, . . . C.sub.N are added
together as a group, the total output V.sub.out is: 1 V out = i = 1
N V i , out ( 1 )
[0018] The aforementioned selective enabling process causes the
value of the enabled comparator outputs to be available at the
group output point. Therefore, if the converter 100 selectively
enables individual comparators and then sums together the outputs
of all the comparators, only the output of the enabled comparators
will be represented. Accordingly, the equivalent of a conventional
successive approximation converter is created simply by selectively
enabling each of the comparators C.sub.1, C.sub.2, C.sub.3, . . .
C.sub.N in this manner. According to the invention, if the value of
E for any one comparator is varied between two integers, 1.5 and 2
for example, a value may be obtained from a portion of a signal
that occurs between nodes 1 and 2. Thus, a virtual comparator is
created that occurs between nodes 1 and 2.
[0019] An analog-to-digital converter 100 according to one
embodiment of the invention is operated as follows. First, the
comparator is enabled at the half-way point, namely, C.sub.0.5N.
Then, if the output V.sub.0.5N,out indicates the level of the input
signal V.sub.in is above the level of the reference signal at this
half-way point, the half-way point comparator C.sub.0.5N is
disabled and the 3/4-point comparator C.sub.0.75N is then enabled.
Conversely, if the output V.sub.0.5N,out indicates the level of the
input signal is below the level of the reference signal at this
half-way point, the half-way point comparator C.sub.0.5N is
disabled and the 1/4-point comparator C.sub.0.25N is then enabled.
This procedure may be repeated in successive approximation
sequence. Establishing virtual comparators is accomplished by
interpolating between nodes. They may be created between two
adjacent nodes, or between any two nodes. In a preferred
embodiment, interpolations are performed between adjacent nodes to
collect samples of data bits occurring between such nodes. In this
way, multiple virtual comparators may be created between any two
adjacent nodes of the converter circuit.
[0020] According to the invention, the array of N comparators
C.sub.1, C.sub.2, C.sub.3, . . . C.sub.N is essentially "probed" by
the action of setting the E.sub.i enabling signal parameters for
one of those comparators to 1 and keeping the others at 0. For
example, if E.sub.5=1 and E.sub.i=0, for all i.noteq.5, the input
signal V.sub.in is effectively compared with only the reference
signal of the 5.sup.th comparator C.sub.5. The process of
successive approximation proceeds by setting one of the E.sub.i
parameters to 1, and setting the other E parameters to 0. In
conventional successive approximation converters, upon exhausting
this process, n bits will have been derived and the input now lies
between, for example, the 23.sup.rd comparator C.sub.23 and the
24.sup.th comparator C.sub.24. It would appear that because there
is now no comparator at the point half-way between the comparators
C.sub.23 and C.sub.24, no output can be produced. However,
referring again to equation (1), if E.sub.23=0.5 and E.sub.24=0.5,
then converter 100 provides an output representative of a further
comparison relative to a virtual 231/2 comparator C.sub.23.5. Thus,
converter 100 is able to linearly interpolate between the actual
comparators. For measuring an input voltage signal, if one chooses
to use a current that can be divided, for example, into 64 parts,
then one can interpolate in {fraction (1/64)}.sup.th increments
from:
E.sub.23={fraction (63/64)}.sup.th, E.sub.24={fraction
(1/64)}.sup.th
to
E.sub.23={fraction (1/64)}.sup.th, E.sub.24={fraction
(63/64)}.sup.th
[0021] By interpolating in this matter, an additional 64 virtual
comparators appear to occur between comparators C.sub.23 and
C.sub.24. Accordingly, 12 bits of information can be derived by
converter 100 using only 64 (that is, 2.sup.6) actual comparators.
A conventional converter having 64 comparators would be able to
derive only 6 bits. Deriving these 12 bits is accomplished
according to the invention without any additional hardware
elements. The derived interstitial comparators are virtual, and
there are no additional comparators or other components. In a
preferred embodiment of the invention, two or more adjacent
comparators are each enabled. The outputs of the comparators are
then weighted and mixed in proportions calculated to provide an
interpolated output of an interstitial virtual comparator. This
method, according to the invention, best simulates the input signal
V.sub.in by providing more samples of information related to the
input signal and without the need for additional hardware
elements.
[0022] Therefore, according to the invention, the outputs of actual
comparators are appropriately interpolated in a manner to create
the output of a virtual comparator. Furthermore, the virtual
comparator, because it does not exist as a discrete hardware
element, can be modified in time such that its virtual output
signal is time varying. For the actual comparators C.sub.1,
C.sub.2, C.sub.3, . . . C.sub.N, the manner in which their outputs
are mixed creates virtual comparators at various comparison
reference signal levels and in a sequential manner.
[0023] One embodiment of invention provides an analog-to-digital
converter able to produce a digital output having more bits than
the number of comparators that exist as actual hardware elements to
compare signals. For example, where N comparators are employed, n
output bits may be produced, where N<2.sup.n-1. However, the
invention is not limited to a series-connected resistor chain as
illustrated in FIG. 1. It will be appreciated by those skilled in
the art that the invention is readily adaptable to use with any
analog-to-digital converter circuitry having a plurality of
comparators. This is also possible whether or not the input signal
is differential or non-differential. For example, the invention may
be applied to a conventional input impedance network that
transforms an analog input voltage signal into a parabolic profile
of reference voltage signals.
[0024] Referring to FIG. 2, an input impedance network and
comparator section of a converter 200 is illustrated that is
similar to that in FIG. 1. In this case, however, the plurality of
comparators C.sub.1, C.sub.2, C.sub.3, C.sub.4, and C.sub.5, is
each placed across a corresponding resistor bank 202 including
resistors R.sub.1, R.sub.2, R.sub.3, R.sub.4, or R.sub.5. This bank
of resistors 202 has resistors defining between them nodes N.sub.1,
N.sub.2, N.sub.3, and N.sub.4. From each node, a corresponding
current source G.sub.1, G.sub.2, G.sub.3, and G.sub.4 draws an
equal current. The input signal V.sub.in, expressed as the
difference between the signals V.sub.left and V.sub.right, is
inherently differential. Also the input impedance network
illustrated in FIG. 2 creates a parabolic profile of reference
voltage signals. Accordingly, a zero voltage value of the profile
of reference signals occurs at different times along the nodes
N.sub.1, N.sub.2, N.sub.3, and N.sub.4 as a function of the input
signal V.sub.in. Implementations of the invention are suitable for
any converter having an input impedance network similar to that
illustrated in FIG. 2. In such a circuit, a differential input
signal V.sub.in is applied across the input impedance network and a
plurality of comparators C.sub.1, C.sub.2, C.sub.3, . . . C.sub.N
measures differences between nodes N.sub.1, N.sub.2, N.sub.3, . . .
N.sub.N-1 within that network. In conventional systems,
measurements are taken between a node and the input signal V.sub.in
itself. In fact, the invention is suitable in respect of any
reference signal profile and impedance network for an
analog-to-digital converter where the converter uses more than one
comparator, where each comparator includes an input for an enabling
signal.
[0025] FIG. 3 is a schematic diagram of a circuit embodying the
invention. Converter circuit 300 is an example of a plurality of
comparators 304, C.sub.1, C.sub.2, C.sub.3, . . . C.sub.N in a
converter 300 that can be selectively enabled. The outputs of
comparators C.sub.1, C.sub.2, C.sub.3, . . . C.sub.N can then be
compounded together to form the output of the converter 300. Each
of the plurality of comparators C.sub.1, C.sub.2, C.sub.3, . . .
C.sub.N consists of a connection of components that has a linear
output in proportion to a given input, in particular an input for
an enabling signal. The specific components making up the plurality
of comparators, 304, C.sub.1, C.sub.2, C.sub.3, . . . C.sub.N in
FIG. 3 is not limiting. It should be apparent to those skilled in
the art in light of the following detailed description of the
circuit in FIG. 3 that the comparators C.sub.1, C.sub.2, C.sub.3, .
. . C.sub.N may be configured differently according to the
invention so long as they display a similarly linear input-output
characteristic. Once the invention embodied in the converter 300 of
FIG. 3 is understood, those principles can be applied to any
analog-to-digital converter having a plurality of comparators that
are selectively enabled or disabled to varying degrees to produce
virtual comparators. According to the invention, these virtual
comparators are configured to produce interpolated voltage values
that occur between adjacent nodes.
[0026] In the example illustrated in FIG. 3, a converter 300
includes a bank 304 of N comparators C.sub.i. Each comparator
includes a pair of three-terminal semiconductor devices M.sub.i,1
and M.sub.i,2, 1.ltoreq.i.ltoreq.N. In a preferred embodiment, the
low-impedance connection of the two devices are connected in common
to one of a bank 306 current sources, S.sub.i, 306. The bank of
current sources 306 provides enabling signals for the individual
comparators C.sub.i. The three-terminal devices M.sub.i,1 and
M.sub.i,2 can be, for example, field-effect transistor ("FET") or
bipolar junction transistor ("BJT") devices. In any such specific
configuration, the comparator C.sub.i will be responsive to the
voltage difference at the gates or bases of the pair of devices,
depending on how the device is configured. Where each of M.sub.i,1
and M.sub.i,2 consists of an n-channel-type
metal-oxide-semiconductor FET ("NMOS") device as illustrated in
FIG. 3, the sources of those devices would be connected together to
a current source S.sub.i. In operation, the current from current
source S.sub.i would be split between the two devices M.sub.i,1 and
M.sub.i,2 depending on the relative gate voltage of devices
M.sub.i,1 and M.sub.i,2. Each pair of devices M.sub.i,1 and
M.sub.i,2 together form a comparator C.sub.i responsive to the
voltage difference applied between the gates of the pair of devices
M.sub.i,1 and M.sub.i,2. The voltage difference is in turn provided
by an input impedance network. The drains of all devices M.sub.i,1
are connected together to provide an output current I.sub.left, and
the drains of all devices M.sub.i,2 are connected together to
provide an output current I.sub.right. The output of converter 300
can be considered the difference between the output currents
I.sub.left and I.sub.right, which are at nodes comprising
sufficiently low impedance points to hold the appropriate voltage
bias conditions.
[0027] In this example, each of the comparators C.sub.1, C.sub.2,
C.sub.3, . . . C.sub.N is placed across a corresponding resistor
R.sub.1, R.sub.2, R.sub.3, . . . R.sub.N, each having a value R.
These resistors are connected in series and define between them
nodes from each of which a corresponding current source G.sub.1,
G.sub.2, G.sub.3, . . . G.sub.N draws an equal current having a
value I.sub.s. Drawing from a bank of current sources and
corresponding resistors 302 creates a parabolic profile of
reference voltage signals having a zero voltage value that occurs
as a function of the input signal V.sub.in. The input voltage
V.sub.in is the difference between the signals V.sub.left and
V.sub.right. The comparator at the vertex of the parabolic profile
will vary as the input signal V.sub.in is varied. In this way, the
comparators C.sub.1, C.sub.2, C.sub.3, . . . C.sub.N are responsive
to the input signal V.sub.in. Even though FIG. 3 shows the
comparators connected to an input impedance network 302 configured
to produce parabolic profile of reference voltage signals the
comparators C.sub.1, C.sub.2, C.sub.3, . . . C.sub.N can easily
also be connected to an input impedance network in the same manner
other input impedance networks known in the art, without deviating
from the principles of this invention.
[0028] Referring again to the circuit in FIG. 3, in operation, each
of the current sources S.sub.i is able to provide an enabling
signal in the form of a "probe" current that selectively enables
the pair of devices M.sub.i,1 and M.sub.i,2 that make up comparator
C.sub.i. For example, if only current source S.sub.6 is active and
set to 10.0 .mu.A, and all other current sources S.sub.i,
i.noteq.6, set to 0 .mu.A, then the difference in the output
currents I.sub.left and I.sub.right will be simply the divisional
function of current that is present in the outputs of the
comparator C.sub.6, where the outputs emanate from the drains of
devices M.sub.6,1 and M.sub.6,2 respectively.
[0029] FIG. 4 is a graph showing on its vertical axis the currents
present at the drains of devices M.sub.6,1 and M.sub.6,2 in
response to a 10.0 .mu.A current from current source S.sub.6 versus
a range of input voltage differences between the gates of devices
M.sub.6,1 and M.sub.6,2 which are shown on the horizontal axis. It
can be seen that, when viewed over the entire range of possible
input voltage differences, the output current in the drain of the
devices M.sub.6,1 and M.sub.6,2 is not linear--from one extreme of
all the current from current source S.sub.6 flowing to the drain of
device M.sub.6,1 to all of the current flowing to the drain of
M.sub.6,2; however, in the circuitry making up converter 300 (FIG.
3), this pairing of devices M.sub.6,1 and M.sub.6,2 operates only
near the "center" of the transfer characteristic where the current
splits approximately equally between the devices M.sub.6,1 and
M.sub.6,2. This occurs where slight deviations from the "center"
are linear, recognizing that there is a limited range of voltage
differences that can be applied to the gates of the devices
M.sub.6,1 and M.sub.6,2 before one or the other of those devices
saturates. When the drains of all devices M.sub.i,1 are compounded
together to provide output current I.sub.left and the drains of all
devices M.sub.i,2 are compounded together to provide output current
I.sub.right, 1.ltoreq.i.ltoreq.N. This compounding increases the
region of linearity in the overall transfer characteristic.
[0030] In the present example, since the output of the converter
300 can be considered the difference between the total output
currents I.sub.left and I.sub.right, and since only current source
S.sub.6 is providing a non-zero current resulting in only the
comparator C.sub.6 being enabled, it is clear that the output of
the converter 300 is the difference of the two output currents from
the comparator C.sub.6. These are the outputs present at the drains
of devices M.sub.6,1 and M.sub.6,2, as shown in the graph in FIG.
4. In this regard, FIG. 5 is a graph showing the total output of
the converter 300 as being the difference in the output currents
from the only enabled comparator C.sub.6.
[0031] When the voltage difference between the gates of devices
M.sub.6,1 and M.sub.6,2 is zero, the output of converter 300 is
also zero. A circuit responsive to the difference in output
currents of converter 300 would therefore have a zero input only
when the voltage at the gate of device M.sub.6,1 is the same as the
voltage at the gate of device M.sub.6,2. Referring again to FIG. 3,
it can be seen that this condition is present only when the voltage
difference across resistor R.sub.6 is zero. This is possible when
the difference between signals V.sub.left and V.sub.right causes
zero current to flow through resistor R.sub.6. Using V.sub.R6 to
represent the voltage that is present at the nodes on either end of
R.sub.6, it can be seen from basic circuit analysis of FIG. 3
that:
V.sub.right=V.sub.R6+R.multidot.I.sub.s (2)
[0032] where R is the value of each of the resistors R.sub.1,
R.sub.2, R.sub.3, . . . R.sub.N and I.sub.s is the value of the
equal current flowing through each of the current sources G.sub.1,
G.sub.2, G.sub.3, . . . G.sub.N. Again using basic circuit analysis
and making use of superposition of linear equations, it can be seen
that signal V.sub.left must be equal to:
V.sub.left=V.sub.R6+5R.multidot.I.sub.s+4R.multidot.I.sub.s+3R.multidot.I.-
sub.s+2R.multidot.I.sub.s+R.multidot.I.sub.s
[0033] and therefore:
V.sub.left=V.sub.R6+15R.multidot.I.sub.s (3)
[0034] Accordingly, if V.sub.in=V.sub.left-V.sub.right, the value
of input signal V.sub.in, in order for the only enabled comparator
C.sub.6 to produce a zero output, must be equal to the
following:
V.sub.in=14R.multidot.I.sub.s (4)
[0035] Therefore, in situations where only current source S.sub.6
provides a non-zero current, only the comparator C.sub.6 is
enabled. C.sub.6 compares the input signal V.sub.in to a reference
voltage signal having a value of 14R.multidot.I.sub.s.
[0036] A similar analysis will show that if only current source
S.sub.5 provides a non-zero current, only the comparator C.sub.5
will be enabled. And, the voltage difference across resistor
R.sub.5 must be zero for the comparator C.sub.5 to produce a zero
output. It follows that:
V.sub.right=V.sub.R5+2R.multidot.I.sub.s+R.multidot.I.sub.s
[0037] and therefore:
V.sub.right=V.sub.R5+3R.multidot.I.sub.s (5)
[0038] It also follows that:
V.sub.left=V.sub.R5+4R.multidot.I.sub.s+3R.multidot.I.sub.s+2R.multidot.I.-
sub.s+R.multidot.I.sub.s
[0039] and therefore:
V.sub.left=V.sub.R5+10R.multidot.I.sub.s (6)
[0040] Given that V.sub.in=V.sub.left-V.sub.right, the value of the
input signal V.sub.in, in order for the only enabled comparator
C.sub.5 to produce a zero output, must be equal to:
V.sub.in=7R.multidot.I.sub.s (7)
[0041] Therefore, in situations where only current source S.sub.5
provides a non-zero current, only the comparator C.sub.5 is
enabled. Comparator C.sub.5 compares the input signal V.sub.in to a
reference voltage signal having a value of 7R.multidot.I.sub.s.
[0042] The virtual comparators of the invention are based on the
following observation: if both current source S.sub.6 and current
source S.sub.5 are set to provide non-zero currents at the same
time, then both the comparators C.sub.6 and C.sub.5 are enabled at
the same time. The overall effective comparison point for the
converter 300 will then fall between 14R.multidot.I.sub.s and
7R.multidot.I.sub.s. If the two non-zero currents provided by
current source S.sub.6 and current source S.sub.5, added together,
are equivalent in value to the single non-zero current provided by
the single non-zero current source S.sub.6 or S.sub.5, then the
output of the converter 300 will be the difference in the output
currents I.sub.left and I.sub.right, illustrated in FIG. 6.
[0043] The combined effect of allowing currents from both current
source S.sub.6 and current source S.sub.5 to flow is that the
output of the converter 300 is zero only when the difference in the
output currents from the comparator C.sub.6 is equal and opposite
to the difference in the output currents from the comparator
C.sub.5. Within a narrow region, the outputs of a comparator
C.sub.5 or C.sub.6 are linearly related to the inputs thereto. For
this reason, in order for the output of the converter 300 to be
zero, it is also necessary for the difference between the input
signal V.sub.in and the voltage reference signal to which
comparator C.sub.5 compares the input signal V.sub.in to be equal
and opposite to the difference between the input signal V.sub.in
and the voltage reference signal to which comparator C.sub.5
compares the input signal V.sub.in. Applying equations (4) and (7)
to this principle, when both current sources S.sub.5 and S.sub.6
provide equal non-zero currents (for example, each providing 5.0
.mu.A of the original 10.0 .mu.A single probe current), the
following must be true:
V.sub.in-14R.multidot.I.sub.s=7R.multidot.I.sub.s-V.sub.in (8)
[0044] and therefore:
V.sub.in=10.5R.multidot.I.sub.s (9)
[0045] which is halfway between the respective voltage reference
signal levels of the two comparators C.sub.5 and C.sub.6. Thus
activating current sources S.sub.5 and S.sub.6 to provide enabling
signals to enable comparators C.sub.5 and C.sub.6 at the same time
has resulted in the converter 300 comparing the input signal
V.sub.in to a voltage reference signal level between those against
which the comparators C.sub.5 and C.sub.6 would normally compare
the input signal V.sub.in were either of them enabled alone.
[0046] Based on the linearity of the transfer characteristic within
the normal operation of the comparators C.sub.1, C.sub.2, C.sub.3,
. . . C.sub.N, further analysis shows that if the currents provided
by current sources S.sub.5 and S.sub.6 are both non-zero but not
equal, further interstitial reference signal levels result as a
function of the ratio between the unequal non-zero currents. For
example, if the current provided by current source S.sub.6 is 7.5
.mu.A and the current provided by current source S.sub.5 is only
2.5 .mu.A, a 3:1 ratio, then the voltage difference between the
input signal V.sub.in and the reference signal level of the
comparator C.sub.6 (which would normally need to be equal and
opposite to the difference between the input signal V.sub.in and
the reference signal level of the comparator C.sub.5 for the
converter 300 to produce a zero output overall) would now need only
to be one-third of the difference between the input signal V.sub.in
and the reference signal level of the comparator C.sub.5 and the
following will be true:
3.multidot.(V.sub.in-14R.multidot.I.sub.s)=7R.multidot.I.sub.s-V.sub.in
(10)
[0047] and therefore:
V.sub.in=12.25R.multidot.I.sub.s (11)
[0048] which makes up three-quarters of the difference between the
reference signal level of the comparator C.sub.5 and the reference
signal level of the comparator C.sub.6.
[0049] It can be seen from these examples that the circuit is
operating proportionately and that any virtual comparison point may
be selected between the respective comparison points of comparators
C.sub.1, C.sub.2, C.sub.3, . . . C.sub.N, whichever of them should
be enabled at any given time, simply by weighting the current
proportionately through the corresponding current sources S.sub.1,
S.sub.2, S.sub.3, . . . S.sub.N.
[0050] As will be apparent to those skilled in the art in the light
of the foregoing disclosure, many alterations and modifications are
possible in the practice of this invention without departing from
the spirit or scope thereof.
[0051] In one embodiment, only one or two comparators may be
enabled at a time. It is conceivable that more than two comparators
may be advantageously employed to further reduce the error of using
only a pair. For example, in the circuit in FIG. 3, the current
sources can be manipulated such that current source S.sub.3
provides 1.0 .mu.A, current source S.sub.4 provides 4.0 .mu.A,
current source S.sub.5 provides 4.0 .mu.A, and current source
S.sub.6 provides 1.0 .mu.A (of the original 10.0 .mu.A) so as to
enable comparators C.sub.3, C.sub.4, C.sub.5, and C.sub.6 in a
desired manner. The inclusion of four appropriately weighted
enabled comparators causes a partial "mean of means" reduction of
DC offset.
[0052] In other embodiments, invention is applicable regardless of
how the plurality of comparators is arranged within the circuitry
for the converter. The invention is readily applied to add virtual
comparators to any grouping of comparators within a circuit. Such a
configuration allows for the simulation of additional comparators
to provide interstitial outputs. This improves the resolution of
the converter without requiring additional hardware elements for
making further comparisons.
[0053] In other embodiments, the invention may be even used in
association with a converter circuit partially operated as a flash
analog-to-digital converter and partially operated as a successive
approximation converter. For example, after a flash
analog-to-digital converter having the properties described above
has simultaneously collected one bit of information per comparator
and produced a digital word of a given number of bits. The same
converter can then be adapted to proceed in a successive
approximation mode according to the invention to produce a digital
word of a greater number of bits and resolution. Using the same
circuitry as the flash analog-to-digital converter, but in
accordance with the preferred successive approximation method
described above, the two comparators that are closest to the
initial digital output produced by the flash method are then
selectively enabled. Their outputs may then be interpolated,
weighted and mixed in appropriate proportions, to produce virtual
comparators as described above. By applying this method
successively, a greater number of bits and resolution will be
achieved by the converter without modifying the converter circuitry
or adding further hardware elements.
[0054] The invention has been described with reference to a
comparator circuit configured to produce outputs of greater
resolution, better linearity and better accuracy. This is
accomplished by producing outputs from virtual comparators derived
between nodes of actual comparators by interpolating output values.
It will be appreciated by those skilled in the art that the
invention has broader utility. Other embodiments may be implemented
according to the invention without departing from the spirit and
scope of the invention. The scope of the invention is to be
construed in accordance with the substance defined by the following
claims.
* * * * *