U.S. patent application number 10/744717 was filed with the patent office on 2004-07-15 for methods of manufacturing semiconductor devices.
Invention is credited to Lee, Ki Min.
Application Number | 20040137715 10/744717 |
Document ID | / |
Family ID | 36757143 |
Filed Date | 2004-07-15 |
United States Patent
Application |
20040137715 |
Kind Code |
A1 |
Lee, Ki Min |
July 15, 2004 |
Methods of manufacturing semiconductor devices
Abstract
Methods of manufacturing semiconductors are disclosed. One
example method includes forming a trench through a dual damascene
process, depositing a barrier metal layer on the overall surface,
and depositing copper in the trench to form a copper line. The
example method may also include performing a wet etching process to
remove the top portion of the copper line, depositing a barrier
layer on the etched copper line, and performing a planarization
process to flatten the barrier layer.
Inventors: |
Lee, Ki Min; (Seoul,
KR) |
Correspondence
Address: |
GROSSMAN & FLIGHT LLC
Suite 4220
20 North Wacker Drive
Chicago
IL
60606-6357
US
|
Family ID: |
36757143 |
Appl. No.: |
10/744717 |
Filed: |
December 23, 2003 |
Current U.S.
Class: |
438/627 ;
257/E21.576; 257/E21.58 |
Current CPC
Class: |
H01L 21/76834 20130101;
H01L 21/76819 20130101 |
Class at
Publication: |
438/627 |
International
Class: |
H01L 021/4763 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 30, 2002 |
KR |
10-2002-0087370 |
Claims
What is claimed is:
1. A method for manufacturing a semiconductor device comprising:
forming a trench through a dual damascene process; depositing a
barrier metal layer on an overall surface, the barrier metal layer
preventing diffusion of copper; depositing copper in the trench to
form a copper line; performing a wet etching process to remove a
top portion of the copper line; depositing a barrier layer on the
etched copper line; and performing a planarization process such as
chemical mechanical polishing (CMP) or an etch back process to
flatten the barrier layer.
2. A method as defined by claim 1, wherein the barrier layer is
formed of SiN or SiC.
3. A method as defined by claim 1, wherein the copper is deposited
by at least one of electroplating and chemical vapor deposition
(CVD).
4. A method as defined by claim 1, wherein the wet etching is
performed using hydrochloric acid, dilute sulfuric acid, or aqueous
ammonia.
Description
TECHNICAL FIELD
[0001] The present disclosure relates to semiconductor devices and,
more particularly, to a methods of manufacturing semiconductor
devices.
BACKGROUND
[0002] Generally, in a copper damascene process, a trench is formed
in a substrate and a barrier metal layer is deposited on the
overall surface of the substrate and the trench. Then, a copper
layer is deposited over the barrier metal layer so that the trench
is completely filled. A chemical mechanical polishing process is
performed to flatten the copper layer. As a result, a copper
interconnect is formed. Next, a barrier layer is formed over the
copper interconnect.
[0003] However, most barrier layers used as an etch-stop layer in a
damascene process have high capacitance, thereby increasing the
delay time of electrons. Such increase in the delay time of
electrons makes it difficult to enhance processing speed of the
device.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIGS. 1a through 1f illustrate, in cross-sectional views,
the results of process steps for fabricating a semiconductor
device.
DETAILED DESCRIPTION
[0005] Disclosed herein is an example semiconductor device
manufacturing process that reduces capacitance of an interlayer
dielectric (ILD), thereby reducing delay time of electron by
forming a barrier layer only on a copper line, and, therefore, can
enhance processing speed of a device produced by a copper damascene
process.
[0006] Referring to FIG. 1a, a trench 10 of a dual damascene
structure is formed in an interlayer dielectric (ILD) through a
predetermined patterning process so that a portion of a lower metal
interconnect is exposed. Then, a barrier metal layer 12 to prevent
diffusion of copper is deposited on the surface of the ILD
including the trench 10.
[0007] Referring to FIG. 1b, a copper layer 14 is deposited so that
the trench 10 is completely filled with copper. The copper is
deposited by means of at least one of electroplating and chemical
vapor deposition (CVD). Referring to FIG. 1c, a planarization
process is performed to flatten the copper layer. The planarization
process may be, for example, a chemical mechanical polishing (CMP)
process or an etch back process. As a result, a copper line 11 is
formed.
[0008] Referring to FIG. 1d, an etching process such as wet etching
is performed to remove some part of the copper line 11 in the
trench 10. In one example, the etching may be wet etching performed
using an etching solution such as hydrochloric acid, dilute
sulfuric acid, or aqueous ammonia, which have relatively low
etching speeds.
[0009] Referring to FIG. 1e, a barrier layer 16 is deposited on the
etched copper line 11. The barrier layer may be formed of SiN or
SiC. Referring to FIG. 1f, a planarization process is performed to
flatten the barrier layer. The planarization process may employ CMP
or an etch back process.
[0010] The foregoing describes how a barrier layer is formed only
on the copper line using SiN or SiC to reduce capacitance of the
ILD, thereby reducing delay time of electrons, which is
proportional to resistance-capacitance (RC). Therefore, the
disclosed techniques can increase processing speed of device.
[0011] Although certain example methods are disclosed herein, the
scope of coverage of this patent is not limited thereto. On the
contrary, this patent covers every apparatus, method and article of
manufacture fairly falling within the scope of the appended claims
either literally or under the doctrine of equivalents.
* * * * *