U.S. patent application number 10/624680 was filed with the patent office on 2004-07-15 for interconnect substrate, semiconductor device, methods of manufacturing the same, circuit board, and electronic equipment.
This patent application is currently assigned to Seiko Epson Corporation. Invention is credited to Otsuki, Tetsuya.
Application Number | 20040135269 10/624680 |
Document ID | / |
Family ID | 31936161 |
Filed Date | 2004-07-15 |
United States Patent
Application |
20040135269 |
Kind Code |
A1 |
Otsuki, Tetsuya |
July 15, 2004 |
Interconnect substrate, semiconductor device, methods of
manufacturing the same, circuit board, and electronic equipment
Abstract
A first conductive layer is formed. An insulating layer is
formed so that at least a part of the insulating layer is disposed
on the first conductive layer. A second conductive layer is formed
so that at least a part of the second conductive layer is disposed
on the insulating layer over the fist conductive layer. Each of the
first and second conductive layers is formed by discharging drops
of a solvent containing fine particles of a conductive material.
The insulating layer is formed by discharging drops of a solvent
containing fine particles of an insulating material.
Inventors: |
Otsuki, Tetsuya; (Suwa-gun,
JP) |
Correspondence
Address: |
OLIFF & BERRIDGE, PLC
P.O. BOX 19928
ALEXANDRIA
VA
22320
US
|
Assignee: |
Seiko Epson Corporation
Tokyo
JP
|
Family ID: |
31936161 |
Appl. No.: |
10/624680 |
Filed: |
July 23, 2003 |
Current U.S.
Class: |
257/791 ;
257/E23.004; 257/E23.07 |
Current CPC
Class: |
H01L 2924/14 20130101;
H01L 2924/01078 20130101; H01L 2924/01033 20130101; H01L 21/4857
20130101; H01L 2224/20 20130101; H01L 2924/01006 20130101; H01L
2224/92244 20130101; H01L 2221/68345 20130101; H05K 3/4697
20130101; H01L 21/4867 20130101; H05K 3/207 20130101; H01L
2924/19043 20130101; H01L 2224/16 20130101; H01L 2224/32245
20130101; H01L 2224/73253 20130101; H01L 2924/15157 20130101; H01L
2224/04105 20130101; H05K 3/125 20130101; H05K 3/4664 20130101;
H01L 2224/73267 20130101; H01L 2924/01079 20130101; H01L 23/49838
20130101; H01L 2924/15788 20130101; H01L 2224/0401 20130101; H01L
2924/01027 20130101; H01L 2924/09701 20130101; H01L 2224/16225
20130101; H01L 2924/01073 20130101; H01L 2224/24227 20130101; H01L
2924/01005 20130101; H01L 23/13 20130101; H01L 24/24 20130101; H01L
2924/19041 20130101; H01L 2924/1517 20130101; H05K 1/183 20130101;
H05K 2203/013 20130101; H01L 2924/1532 20130101; H01L 2224/82102
20130101; H01L 2924/01024 20130101; H01L 2924/15153 20130101; H05K
2203/016 20130101; H01L 2924/01013 20130101; H01L 2924/15311
20130101; H01L 2924/01004 20130101; H01L 2224/76155 20130101; H01L
2924/01029 20130101; H01L 2224/12105 20130101; H01L 24/19 20130101;
H01L 2924/01082 20130101; H01L 2924/30105 20130101; H01L 2924/15165
20130101; H05K 3/4682 20130101; H01L 2924/0104 20130101; H01L
2924/01047 20130101; H01L 2924/15787 20130101; H01L 2924/1517
20130101; H01L 2924/15153 20130101; H01L 2224/24227 20130101; H01L
2924/1517 20130101; H01L 2924/15787 20130101; H01L 2924/00
20130101; H01L 2924/15788 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/791 |
International
Class: |
H01L 023/29 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 23, 2002 |
JP |
2002-213606 |
Claims
What is claimed is:
1. A method of manufacturing an interconnect substrate comprising:
forming a first conductive layer; forming an insulating layer so
that at least a part of the insulating layer is disposed on the
fins conductive layer; and forming a second conductive layer so
that at least a part of the second conductive layer is disposed on
the insulating layer over the first conductive layer, wherein each
of the first and second conductive layers is formed by discharging
drops of a solvent containing fine particles of a conductive
material, and wherein the insulating layer is formed by discharging
drops of a solvent containing fine particles of an insulating
material.
2. The method of manufacturing an interconnect substrate as defined
in claim 1, wherein the second conductive layer is formed so that a
part of the second conductive layer is electrically connected with
a part of the first conductive layer.
3. The method of manufacturing an interconnect substrate as defined
in claim 1, wherein the insulating layer is formed on the first
conductive layer and in a region adjacent to the first conductive
layer.
4. The method of manufacturing an interconnect substrate as defined
in claim 3, wherein the insulating layer is formed of a plurality
of layers, wherein a lower layer of the insulating layer is formed
in a region adjacent to a region in which the first conductive
layer is formed, and wherein an upper layer of the insulating layer
is formed on the first conductive layer and the lower layer of the
insulating layer.
5. The method of manufacturing an interconnect substrate as defined
in claim 4, wherein the lower layer of the insulating layer is
formed after forming the first conductive layer.
6. The method of manufacturing an interconnect substrate as defined
in claim 4, wherein the first conductive layer is formed after
forming the lower layer of the insulating layer.
7. The method of manufacturing an interconnect substrate as defined
in claim 1, further comprising: forming one or more posts on the
first conductive layer by discharging drops of a solvent containing
fine particles of a conductive material, wherein the insulating
layer is formed to avoid a region in which the posts are
formed.
8. The method of manufacturing an interconnect substrate as defined
in claim 7, wherein the insulating layer is formed so that a height
of an upper surface of the insulating layer is substantially equal
to a height of an upper surface of at least one of the posts.
9. The method of manufacturing an interconnect substrate as defined
in claim 7, wherein the second conductive layer is formed to pass
over at least one of the posts.
10. The method of manufacturing an interconnect substrate as
defined in claim 7, wherein the second conductive layer is formed
to avoid at least one of the posts.
11. The method of manufacturing an interconnect substrate as
defined in claim 10, further comprising: forming a second
insulating layer so that at least a part of the second insulating
layer is disposed on the second conductive layer, and forming a
third conductive layer so that at least a pant of the third
conductive layer is disposed on the second insulating layer over
the second conductive layer, wherein the third conductive layer is
formed by discharging drops of a solvent containing fine particles
of a conductive material, and wherein the second insulating layer
is formed by discharging drops of a solvent containing fine
particles of an insulating material.
12. The method of manufacturing an interconnect substrate as
defined in claim, 11, wherein the second insulating layer is formed
to avoid a region in which at least one of the posts is formed, and
wherein the third conductive layer is formed to pass over at least
one of the posts.
13. The method of manufacturing an interconnect substrate as
defined in claim 12, wherein at least one of the posts is formed by
a plurality of steps.
14. The method of manufacturing an interconnect substrate as
defined in claim 11, further comprising: forming one or more
electronic components, wherein each of a plurality of components
forming one of the electronic components is formed by discharging
drops of a solvent containing fine particles of a material.
15. The method of manufacturing an interconnect substrate as
defined in claim 14, wherein each of the electronic components is
one of a capacitor, a resistor, a diode, and a transistor.
16. The method of manufacturing an interconnect substrate as
defined in claim 14, wherein at least one of the electronic
components is formed on a surface on which the first conductive
layer is formed.
17. The method of manufacturing an interconnect substrate as
defined in claim 14, wherein at least one of the electronic
components is formed on the insulating layer.
18. The method of manufacturing an interconnect substrate as
defined in claim 14, wherein at least one of the electronic
components is formed on the second insulating layer.
19. The method of manufacturing an interconnect substrate as
defined in claim 1, wherein the first conductive layer is formed on
a substrate.
20. The method of manufacturing an interconnect substrate as
defined in claim wherein the substrate includes a depression
section, and wherein the first conductive layer is formed to pass
through the depression section.
21. The method of manufacturing an interconnect substrate as
defined in claim 19, wherein at least a top surface of the
substrate is formed of an insulating material.
22. The method of manufacturing an interconnect substrate as
defined in claim 19, wherein the substrate includes an insulating
section and a conductive section which is formed through the
insulating section, and wherein the first conductive layer is
formed over the insulating section and the conductive section so
that the first conductive layer is electrically connected with the
conductive section.
23. The method of manufacturing an interconnect substrate as
defined in claim 19, further comprising removing the substrate from
the first conductive layer.
24. A method of manufacturing a semiconductor device comprising:
manufacturing an interconnect substrate; and mounting a
semiconductor chip on the interconnect substrate, the manufacturing
of an interconnect substrate including: forming a first conductive
layer, forming an insulating layer so that at least a part of the
insulating layer is disposed on the first conductive layer; and
forming a second conductive layer so that at least a part of the
second conductive layer is disposed on the insulating layer over
the first conductive layer, wherein each of the first and second
conductive layers is formed by discharging drops of a solvent
containing fine particles of a conductive material, and wherein the
insulating layer is formed by discharging drops of a solvent
containing fine panicles of an insulating material.
25. The method of manufacturing a semiconductor device as defined
in claim 24, wherein the interconnect substrate is manufactured
with a part of the first conductive layer being exposed, and
wherein the exposed part of the first conductive layer is
electrically connected with the semiconductor chip.
26. The method of manufacturing a semiconductor device as defined
in claim 24, wherein a conductive layer other than the first and
second conductive layers is electrically connected with the
semiconductor chip.
27. The method of manufacturing a semiconductor device as defined
in claim 24, wherein the fit conductive layer is formed over a
substrate.
28. The method of manufacturing a semiconductor device as defined
in claim 27, wherein the substrate includes a depression section,
wherein the first conductive layer is formed to pass through the
depression section, and wherein the semiconductor chip is mounted
in the depression section.
29. The method of manufacturing a semiconductor device as defined
in claim 27, wherein the substrate includes an insulating section
and a conductive section which is formed through the insulating
section, and wherein the first conductive layer is formed over the
insulating section and the conductive section so that the first
conductive layer is electrically connected with the conductive
section.
30. The method of manufacturing a semiconductor device as defined
in claim 27, further comprising removing the substrate from the
first conductive layer.
31. A method of manufacturing a semiconductor device comprising:
mounting a semiconductor chip over a substrate with a surface of
the semiconductor chip on which an electrode is formed facing
upward; forming a first conductive layer over the substrate and the
semiconductor chip so that the first conductive layer is
electrically connected with the electrode of the semiconductor
chip; forming an insulating layer so that at least a part of the
insulating layer is disposed on the first conductive layer; and
forming a second conductive layer so that at least a part of the
second conductive layer is disposed on the insulating layer over
the first conductive layer, wherein each of the first and second
conductive layers is formed by discharging drops of a solvent
containing fine particles of a conductive material, and wherein the
insulating layer is formed by discharging drops of a solvent
containing fine particles of an insulating material.
32. The method of manufacturing a semiconductor device as defined
in claim 31, wherein the substrate includes a depression section,
and wherein the semiconductor chip is mounted in the depression
section.
33. The method of manufacturing a semiconductor device as defined
in claim 32, further comprising: forming a resin layer by filling
the depression section in which the semiconductor chip is mounted
with a resin, wherein the first conductive layer is formed to pass
over the resin layer.
34. The method of manufacturing a semiconductor device as defined
in claim 31, wherein the second conductive layer is formed so that
a part of the second conductive layer is electrically connected
with a part of the first conductive layer.
35. The method of manufacturing a semiconductor device as defined
in claim 31, wherein the insulating layer is formed on the first
conductive layer and in a region adjacent to the first conductive
layer.
36. The method of manufacturing a semiconductor device as defined
in claim 35, wherein the insulating layer is formed of a plurality
of layers, wherein a lower layer of the insulating layer is formed
in a region adjacent to a region in which the first conductive
layer is formed, and wherein an upper layer of the insulating layer
is formed on their fist conductive layer and the lower layer of the
insulating layer.
37. The method of manufacturing a semiconductor device as defined
in claim 36, wherein the lower layer of the insulating layer is
formed after forming the first conductive layer.
38. The method of manufacturing a semiconductor device as defined
in claim 36, wherein the first conductive layer is formed after
forming the lower layer of the insulating layer.
39. The method of manufacturing a semiconductor device as defined
in claim 31, further comprising: forming one or more posts on the
first conductive layer by discharging drops of a solvent containing
fine particles of a conductive material, wherein the insulating
layer is formed to avoid a region in which the posts are
formed.
40. The method of manufacturing a semiconductor device as defined
in claim 39, wherein the insulating layer is formed so that a
height of an upper surface of the insulating layer is substantially
equal to a height of an upper surface of at least one of the
posts.
41. The method of manufacturing a semiconductor device as defined
in claim 39, wherein the second conductive layer is formed to pass
over at least one of the posts.
42. The method of manufacturing a semiconductor device as defined
in claim 39, wherein the second conductive layer is formed to avoid
at least one of the posts.
43. The method of manufacturing a semiconductor device as defined
in claim 42, further comprising: forming a second insulating layer
so that at least a part of the second insulating layer is disposed
on the second conductive layer; and forming a third conductive
layer so that at least a part of the third conductive layer is
disposed on the second insulating layer over the second conductive
layer, wherein the third conductive layer is formed by discharging
drops of a solvent containing fine particles of a conductive
material, and wherein the second insulating layer is formed by
discharging drops of a solvent containing fine particles of an
insulating material.
44. The method of manufacturing a semiconductor device as defined
in claim 43, wherein the second insulating layer is formed to avoid
a region in which at least one of the posts is formed, and wherein
the third conductive layer is formed to pass over at least one of
the posts.
45. The method of manufacturing a semiconductor device as defined
in claim 44, wherein at least one of the posts is formed by a
plurality of steps.
46. The method of manufacturing a semiconductor device as defined
in claim 43, further comprising: forming one or more electronic
components, wherein each of a plurality of components forming one
of the electronic components is formed by discharging drops of a
solvent containing fine particles of a material.
47. The method of manufacturing a semiconductor device as defined
in claim 46, wherein each of the electronic components is one of a
capacitor, a resistor, a diode, and a transistor.
48. The method of manufacturing a semiconductor device as defined
in claim 46, wherein at least one of the electronic components is
formed on a surface on which the first conductive layer is
formed.
49. The method of manufacturing a semiconductor device as defined
in claim 46, wherein at least one of the electronic components is
formed on the insulating layer.
50. The method of manufacturing a semiconductor device as defined
in claim 46, wherein at least one of the electronic components is
formed on the second insulating layer.
51. A method of manufacturing a semiconductor device comprising:
mounting a semiconductor chip over a first substrate with a surface
of the semiconductor chip on which an electrode is formed facing
upward; attaching a second substrate to the first substrate, the
second substrate having a shape which avoids the semiconductor
chip; forming a first conductive layer over the second substrate
and the semiconductor chip so that the first conductive layer is
electrically connected with the electrode of the semiconductor
chip; forming an insulating layer so that at least a part of the
insulating layer is disposed on the fist conductive layer; and
forming a second conductive layer so that at least a part of the
second conductive layer is disposed on the insulating layer over
the first conductive layer, wherein each of the first and second
conductive layers is formed by discharging drops of a solvent
containing fine particles of a conductive material, and wherein the
insulating layer is formed by discharging drops of a solvent
containing fine particles of an insulating material.
52. The method of manufacturing a semiconductor device as defined
in claim 51, wherein the second substrate has a coefficient of
thermal expansion closer to a coefficient of thermal expansion of
the semiconductor chip than a coefficient of thermal expansion or
the first substrate.
53. The method of manufacturing a semiconductor device as defined
in claim 51, wherein the second conductive layer is formed so that
a part of the second conductive layer is electrically connected
with a part of the first conductive layer.
54. The method of manufacturing a semiconductor device as defined
in claim 51, wherein the insulating layer is formed on the first
conductive layer and in a region adjacent to the first conductive
layer.
55. The method of manufacturing a semiconductor device as defined
in claim 54, wherein the insulating layer is formed of a plurality
of layers, wherein a lower layer of the insulating layer is formed
in a region adjacent to a region in which the first conductive
layer is formed, and wherein an upper layer of the insulating layer
is formed on the first conductive layer and the lower layer of the
insulating layer.
56. The method of manufacturing a semiconductor device as defined
in claim 55, wherein the lower layer of the insulating layer is
formed after forming the first conductive layer.
57. The method of manufacturing a semiconductor device as defined
in claim 55, wherein the first conductive layer is formed after
forming the lower layer of the insulating layer.
58. The method of manufacturing a semiconductor device as defined
in claim 51, further comprising: forming one or more posts on the
first conductive layer by discharging drops of a solvent containing
fine particles of a conductive material, wherein the insulating
layer is formed to avoid a region in which the posts are
formed.
59. The method of manufacturing a semiconductor device as defined
in claim 58, wherein the insulating layer is formed so that a
height of an upper surface of the insulating layer is substantially
equal to a height of an upper surface of at least one of the
posts.
60. The method of manufacturing a semiconductor device as defined
in claim 58, wherein the second conductive layer is formed to pass
over at least one of the posts.
61. The method of manufacturing a semiconductor device as defined
in claim 58, wherein the second conductive layer is formed to avoid
at least one of the posts.
62. The method of manufacturing a semiconductor device as defined
in claim 61, further comprising: forming a second insulating layer
so that at least a part of the second insulating layer is disposed
on the second conductive layer; and forming a third conductive
layer so that at least a part of the third conductive layer is
disposed on the second insulating layer over the second conductive
layer, wherein the third conductive layer is formed by discharging
drops of a solvent containing fine particles of a conductive
material, and wherein the second insulating layer is formed by
discharging drops of a solvent containing fine particles of an
insulating material.
63. The method of manufacturing a semiconductor device as defined
in claim 62, wherein the second insulating layer is formed to avoid
a region in which at least one of the posts is formed, and wherein
the third conductive layer is formed to pass over at least one of
the posts.
64. The method of manufacturing a semiconductor device as defined
in claim 63, wherein at least one of the posts is formed by a
plurality of steps.
65. The method of manufacturing a semiconductor device as defined
in claim 62, further comprising: forming one or more electronic
components, wherein each of a plurality of components forming one
of the electronic components is formed by discharging drops of a
solvent containing fine particles of a material.
66. The method of manufacturing a semiconductor device as defined
in claim 65, wherein each of the electronic components is one of a
capacitor, a resistor a diode, and a transistor.
67. The method of manufacturing a semiconductor device as defined
in claim 65, wherein at least one of the electronic components is
formed on a surface on which the first conductive layer is
formed.
68. The method of manufacturing a semiconductor device as defined
in claim 65, wherein at least one of the electronic components is
formed on the insulating layer.
69. The method of manufacturing a semiconductor device as defined
in claim 65, wherein at least one of the electronic components is
formed on the second insulating layer.
70. A method of manufacturing a semiconductor device comprising:
forming a first conductive layer over a semiconductor wafer on
which a plurality of integrated circuits are formed so that the
first conductive layer is electrically connected with electrodes of
the semiconductor wafer; forming an insulating layer so that at
lest a part of the insulating layer is disposed on the first
conductive layer; forming a second conductive layer so that at
least a part of the second conductive layer is disposed on the
insulating layer over the fir conductive layer; and cutting the
semiconductor wafer, wherein each of the first and second
conductive layers is formed by discharging drops of a solvent
containing fine particles of a conductive material, and wherein the
insulating layer is formed by discharging drops of a solvent
containing fine particles of an insulating material.
71. The method of manufacturing a semiconductor device as defined
in claim 70, wherein the second conductive layer is formed so that
a part of the second conductive layer is electrically connected
with a part of the first conductive layer.
72. The method of manufacturing a semiconductor device as defined
in Claim 70, wherein the insulating layer is formed on the first
conductive layer and in a region adjacent to the first conductive
layer.
73. The method of manufacturing a semiconductor device as defined
in claim 72, wherein the insulating layer is formed of a plurality
of layers, wherein a lower layer of the insulating layer is formed
in a region adjacent to a region in which the first conductive
layer is formed, and wherein an upper layer of the insulating layer
is formed on the first conductive layer and the lower layer of the
insulating layer.
74. The method of manufacturing a semiconductor device as defined
in claim 73, wherein the lower layer of the insulating layer is
formed after forming the first conductive layer.
75. The method of manufacturing a semiconductor device as defined
in claim 73, wherein the first conductive layer is formed after
forming the lower layer of the insulating layer.
76. The method of manufacturing a semiconductor device as defined
in claim 70, further comprising: forming one or more posts on the
first conductive layer by discharging drops of a solvent containing
fine particles of a conductive material, wherein the insulating
layer is formed to avoid a region in which the posts are
formed.
77. The method of manufacturing a semiconductor device as defined
in claim 76, wherein the insulating layer is formed so that a
height of an upper surface of the insulating layer is substantially
equal to a height of an upper surface of at least one of the
posts.
78. The method of manufacturing a semiconductor device as defined
in claim 76, wherein the second conductive layer is formed to pass
over at least one of the posts.
79. The method of manufacturing a semiconductor device as defined
in claim 76, wherein the second conductive layer is formed to avoid
at least one of the posts.
80. The method of manufacturing a semiconductor device as defined
in claim 79, further comprising: forming a second insulating layer
so that at least a part of the second insulating layer is disposed
on the second conductive layer; and forming a third conductive
layer so that at least a part of the third conductive layer is
disposed on the second insulating layer over the second conductive
layer, wherein the third conductive layer is formed by discharging
drops of a solvent containing fine particles of a conductive
material, and wherein the second insulating layer is formed by
discharging drops of a solvent containing fine particles of an
insulating material.
81. The method of manufacturing a semiconductor device as defined
in claim 80, wherein the second insulating layer is formed to avoid
a region in which at least one of the posts is formed, and wherein
the third conductive layer is formed to pass over at least one of
the posts.
82. The method of manufacturing a semiconductor device as defined
in claim 81, wherein at least one of the posts is formed by a
plurality of steps.
83. The method of manufacturing a semiconductor device as defined
in claim 80, further comprising: forming one or more electronic
components, wherein each of a plurality of components forming one
of the electronic components is formed by discharging drops of a
solvent containing fine particles of a material.
84. The method of manufacturing a semiconductor device as defined
in claim 83, wherein each of the demonic components is one of a
capacitor, a resistor, a diode and a transistor.
85. The method of manufacturing a semiconductor device as defined
in claim 83, wherein at least one of the electronic components is
formed on a surface on which the first conductive layer is
formed.
86. The method of manufacturing a semiconductor device as defined
in claim 83, wherein at least one of the electronic components is
formed on the insulating layer.
87. The method of manufacturing a semiconductor device as defined
in claim 83, wherein at least one of the electronic components is
formed on the second insulating layer.
88. An interconnect substrate manufactured by the method as defined
in claim 1.
89. A semiconductor device manufactured by the method as defined in
claim 24.
90. A semiconductor device manufactured by the method as defined in
claim 31.
91. A semiconductor device manufactured by the method as defined in
claim 51.
92. A semiconductor device manufactured by the method as defined in
claim 70.
93. A semiconductor device comprising: a substrate including a
depression section; a first conductive layer formed to pass through
the depression section; an insulating layer, at least a part of the
insulating layer being disposed on the first conductive layer; a
second conductive layer, at least a part of the second conductive
layer being disposed on the insulating layer over the first
conductive layer; and a semiconductor chip mounted in the
depression section.
94. The semiconductor device as defined in claim 93, wherein the
semiconductor chip is electrically connected with the first
conductive layer.
95. The semiconductor device as defined in claim 93, wherein the
semiconductor chip is electrically connected with a conductive
layer other than the fit and second conductive layers.
96. A semiconductor device comprising: a substrate including a
depression section; a semiconductor chip mounted in the depression
section of the substrate with a surface of the semiconductor chip
on which an electrode is formed facing upward; a first conductive
layer formed over the substrate and the semiconductor chip so that
the first conductive layer is electrically connected with the
electrode of the semiconductor chip; an insulating layer, at least
a part of the insulating layer being disposed on the first
conductive layer; and a second conductive layer, at least a part of
the second conductive layer being disposed on the insulating layer
over the first conductive layer.
97. The semiconductor device as defined in claim 96, further
comprising: a resin layer formed in the depression section in which
the semiconductor chip is mounted, wherein the first conductive
layer is formed to pas over the resin layer.
98. A semiconductor device comprising: a first substrate; a
semiconductor chip mounted over the first substrate with a surface
of the semiconductor chip on which an electrode is formed facing
upward; a second substrate having a shape which avoids the
semiconductor chip and being attached to the first substrate; a
first conductive layer which is formed over the second substrate
and the semiconductor chip so that the first conductive layer is
electrically connected with the electrode of the semiconductor
chip; an insulating layer, at least a part of the insulating layer
being disposed on the first conductive layer; and a second
conductive layer, at least a part of the second conductive layer
being disposed on the insulating layer over the first conductive
layer.
99. The semiconductor device as defined in claim 98, wherein the
second substrate has a coefficient of thermal expansion closer to a
coefficient of thermal expansion of the semiconductor chip than a
coefficient of thermal expansion of the first substrate.
100. A circuit board on which the semiconductor device as defined
in claim 89 is mounted.
101. A circuit board on which the semiconductor device as defined
in claim 90 is mounted.
102. A circuit board on which the semiconductor device as defined
in claim 91 is mounted.
103. A circuit board on which the semiconductor device as defined
in claimed 92 is mounted.
104. A circuit board on which the semiconductor device as defined
in claim 93 is mounted.
105. A circuit board on which the semiconductor device as defined
in claim 96 is mounted.
106. A circuit board on which the semiconductor device as defined
in claim 98 is mounted.
107. Electronic equipment comprising the semiconductor device as
defined in claim 89.
108. Electronic equipment comprising the semiconductor device as
defined in claim 90.
109. Electronic equipment comprising the semiconductor device as
defined in claim 91.
110. Electronic equipment comprising the semiconductor device as
defined in claim 92.
111. Electronic equipment comprising the, semiconductor device as
defined in claim 93.
112. Electronic equipment comprising the semiconductor device as
defined in claim 96.
113. Electronic equipment comprising the semiconductor device as
defined in claim 98.
Description
[0001] Japanese Patent Application No. 2002-213606 filed on Jul.
23, 2002, is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to an interconnect substrate,
a semiconductor device, methods of manufacturing the same, a
circuit board and electronic equipment.
[0003] A multilayer substrate has been used in the case where a
high-density interconnect structure is necessary. For example, a
multilayer substrate has been used as an interposer in a package
capable of high density mounting such as ball grid array (BGA) and
chip scale/size package (CSP). As a conventional method of
manufacturing a multilayer substrate, there is known a method of
stacking substrates having an interconnect pattern formed by
etching copper foil, and electrically connecting the upper and
lower interconnect patterns by forming via holes in the substrates
and filling or plating the via holes with a conductive
material.
[0004] According to the conventional method, since a
photolithographic step must be performed for etching, a mask is
necessary. The mask is expensive. Moreover, since the via holes
must be formed larger for filling or plating the via holes with a
conductive material, an increase in density of the interconnect
structure is prevented. In the case of forming through holes by
plating the via holes, since a space is formed inside the through
holes, moisture removal must be taken into consideration. In the
case of mechanically forming the via holes after stacking three or
more substrates, the via holes cannot be formed in the substrate in
the intermediate layer.
BRIEF SUMMARY OF THE INVENTION
[0005] A method of manufacturing an interconnect substrate
according to one aspect of the present invention comprises:
[0006] forming a first conductive layer; forming an insulating
layer so that at least a part of the insulating layer is disposed
on the first conductive layer; and
[0007] forming a second conductive layer so that at least a part of
the second conductive layer is disposed on the insulating layer
over the first conductive layer,
[0008] wherein each of the first and second conductive layers is
formed by discharging drops of a solvent containing fine particles
of a conductive material, and
[0009] wherein the insulating layer is formed by discharging drops
of a solvent containing fine particles of an insulating
material.
[0010] A method of manufacturing a semiconductor device according
to another aspect of the present invention comprises:
[0011] manufacturing an interconnect substrate; and
[0012] mounting a semiconductor chip on the interconnect
substrate,
[0013] the manufacturing of an interconnect substrate
including:
[0014] forming a first conductive layer;
[0015] forming an insulating layer so that at least a part of the
insulating layer is disposed on the first conductive layer; and
[0016] forming a second conductive layer so that at least a part of
the second conductive layer is disposed on the insulating layer
over the lint conductive layer,
[0017] wherein each of the first and second conductive layers is
formed by discharging drops of a solvent containing fine particles
of a conductive material, and
[0018] wherein the insulating layer is formed by discharging drops
of a solvent containing fine particles of an insulating
material.
[0019] A method of manufacturing a semiconductor device according
to a further aspect of the present invention comprises:
[0020] mounting a semiconductor chip over a substrate with a
surface of the semiconductor chip on which an electrode is formed
facing upward;
[0021] forming a first conductive layer over the substrate and the
semiconductor chip so that the fist conductive layer is
electrically connected with the electrode of the semiconductor
chip;
[0022] forming an insulating layer so that at least a part of the
insulating layer is disposed on the first conductive layer; and
[0023] forming a second conductive layer so that at least a part of
the second conductive layer is disposed on the insulating layer
over the first conductive layer;
[0024] wherein each of the first and second conductive layers is
formed by discharging drops of a solvent containing fine particles
of a conductive material, and
[0025] wherein the insulating layer is formed by discharging drops
of a solvent containing fine particles of an insulating
material.
[0026] A method of manufacturing a semiconductor device according
to still another aspect of the present invention comprises:
[0027] mounting a semiconductor chip over a first substrate with a
surface of the semiconductor chip on which an electrode is formed
facing upward;
[0028] attaching a second substrate to the first substrate, the
second substrate having a shape which avoids the semiconductor
chip;
[0029] forming a first conductive layer over the second substrate
and the semiconductor chip so that the first conductive layer is
electrically connected with the electrode of the semiconductor
chip;
[0030] forming an insulating layer so that at least a part of the
insulating layer is disposed on the first conductive layer; and
[0031] forming a second conductive layer so that at least a part of
the second conductive layer is disposed on the insulating layer
over the first conductive layer;
[0032] wherein each of the first and second conducive layers is
formed by discharging drops of a solvent containing fine particles
of a conductive material, and
[0033] wherein the insulating layer is formed by discharging drops
of a solvent containing fine particles of an insulating
material.
[0034] A method of manufacturing a semiconductor device according
to a still further aspect of the present invention comprises:
[0035] forming a first conductive layer over a semiconductor wafer
on which a plurality of integrated circuits are formed so that the
first conductive layer is electrically connected with electrodes of
the semiconductor wafer;
[0036] forming an insulating layer so that at least a part of the
insulating layer is disposed on the first conductive layer;
[0037] forming a second conductive layer so that at least a part of
the second conductive layer is disposed on the insulating layer
over the first conductive layer; and
[0038] cutting the semiconductor wafer;
[0039] wherein each of the first and second conductive layers is
formed by discharging drops of a solvent containing fine particles
of a conductive material, and
[0040] wherein the insulating layer is formed by discharging drops
of a solvent containing fine particles of an insulating
material.
[0041] An interconnect substrate according to yet another aspect of
the present invention is manufactured by any of the above
methods.
[0042] A semiconductor device according to a yet further aspect of
the present invention is manufactured by any the above methods.
[0043] A semiconductor device according to a yet further aspect of
the present invention comprises:
[0044] a substrate including a depression section;
[0045] a first conductive layer formed to pass through the
depression section;
[0046] an insulating layer, at least a part of the insulating layer
being disposed on the first conductive layer;
[0047] a second conductive layer, at least a part of the second
conductive layer being disposed on the insulating layer over the
first conductive layer; and
[0048] a semiconductor chip mounted in the depression section.
[0049] A semiconductor device according to a yet further aspect of
the present invention comprises:
[0050] a substrate including a depression section;
[0051] a semiconductor chip mounted in the depression section of
the substrate with a surface of the semiconductor chip on which an
electrode is formed facing upward;
[0052] a first conductive layer formed over the substrate and the
semiconductor chip so that the first conductive layer is
electrically connected with the electrode of the semiconductor
chip;
[0053] an insulating layer, at least a part of the insulating layer
being disposed on the first conductive layer; and
[0054] a second conductive layer, at least a part of the second
conductive layer being disposed on the insulating layer over the
first conductive layer.
[0055] A semiconductor device according to a yet further aspect of
the present invention comprises:
[0056] a first substrate;
[0057] a semiconductor chip mounted over the first substrate with a
surface of the semiconductor chip on which an electrode is formed
facing upward;
[0058] a second substrate having a shape which avoids the
semiconductor chip and being attached to the first substrate;
[0059] a fist conductive layer which is formed over the second
substrate and the semiconductor chip so that the first conductive
layer is electrically connected with the electrode of the
semiconductor chip;
[0060] an insulating layer, at least a part of the insulating layer
being disposed on the first conductive layer; and
[0061] a second conductive layer, at least a part of the second
conductive layer being disposed on the insulating layer over the
fit conductive layer.
[0062] A circuit board according to a yet further aspect of the
present invention is equipped with any of the above semiconductor
devices.
[0063] Electronic equipment according to a yet further aspect of
the present invention comprises any of the above semiconductor
devices.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0064] FIG. 1 is a view illustrating a method of manufacturing an
interconnect substrate according to a first embodiment to which the
present invention is applied.
[0065] FIGS. 2A and 2B are views illustrating a method of
manufacturing an interconnect substrate according to the first
embodiment to which the present invention is applied.
[0066] FIGS. 3A and 3B are views illustrating a method of
manufacturing an interconnect substrate according to the first
embodiment to which the present invention is applied.
[0067] FIG. 4 is a view illustrating a method of manufacturing an
interconnect substrate according to the first embodiment to which
the present invention is applied.
[0068] FIG. 5 is a view illustrating a method of manufacturing an
interconnect substrate according to the first embodiment to which
the present invention is applied.
[0069] FIG. 6 is a view illustrating a method of manufacturing an
interconnect substrate according to the first embodiment to which
the present invention is applied.
[0070] FIG. 7 is a view illustrating a method of manufacturing an
interconnect substrate according to the first embodiment to which
the present invention is applied.
[0071] FIG. 7 is a view illustrating a method of manufacturing an
interconnect substrate according to the first embodiment to which
the present invention is applied.
[0072] FIGS. 9A and 9B are views illustrating a method of
manufacturing an interconnect substrate according to the first
embodiment to which the present invention is applied.
[0073] FIGS. 10A and 10B are views illustrating a method of
manufacturing an interconnect substrate according to the first
embodiment to which the present invention is applied.
[0074] FIG. 11 is a view illustrating a method of manufacturing a
semiconductor device according to the first embodiment to which the
present invention is applied.
[0075] FIG. 12 is a view illustrating a method of manufacturing a
semiconductor device according to the first embodiment to which the
present invention is applied.
[0076] FIG. 13 is a view illustrating an interconnect substrate
according to a second embodiment to which the present invention is
applied.
[0077] FIG. 14 is a view illustrating a semiconductor device
according to the second embodiment to which the present invention
is applied.
[0078] FIGS. 15A and 15B are views illustrating a method of
manufacturing an interconnect substrate according to the second
embodiment to which the present invention is applied.
[0079] FIGS. 16A and 16B are views illustrating a method of
manufacturing an interconnect substrate according to the second
embodiment to which the present invention is applied.
[0080] FIGS. 17A and 17B are views illustrating a method of
manufacturing an interconnect substrate according to the second
embodiment to which the present invention is applied.
[0081] FIGS. 18A and 18B art views illustrating a method of
manufacturing an interconnect substrate according to the second
embodiment to which the present invention is applied.
[0082] FIG. 19 is a view illustrating a method of manufacturing an
interconnect substrate according to the second embodiment to which
the present invention is applied.
[0083] FIG. 20 is a view illustrating a method of manufacturing an
interconnect substrate according to the second embodiment to which
the present invention is applied.
[0084] FIGS. 21A to 21C are views illustrating a method of
manufacturing a semiconductor device according to a third
embodiment to which the present invention is applied.
[0085] FIGS. 22A to 22C are views illustrating a method of
manufacturing a semiconductor device according to a fourth
embodiment to which the present invention is applied.
[0086] FIG. 23 is a view illustrating an interconnect substrate
according to a fifth embodiment to which the present invention is
applied.
[0087] FIG. 24 is a view illustrating a semiconductor device
according to the fifth embodiment to which the present invention is
applied.
[0088] FIGS. 25A and 25B are views illustrating a method of
manufacturing an interconnect substrate according to a sixth
embodiment to which the present invention is applied.
[0089] FIGS. 26A to 26C are views illustrating a method of
manufacturing a semiconductor device according to a seventh
embodiment to which the present invention is applied.
[0090] FIGS. 27A and 27B an views illustrating a method of
manufacturing an electronic component according to an eighth
embodiment to which the present invention is applied.
[0091] FIG. 28 is a view showing a circuit board on which a
semiconductor device according to an embodiment to which the
present invention is applied is mounted.
[0092] FIG. 29 is a view showing electronic equipment including a
semiconductor device according to an embodiment to which the
present invention is applied.
[0093] FIG. 30 is a view showing another piece of electronic
equipment including a semiconductor device according to an
embodiment to which the present invention is applied.
DETAILED DESCRIPTION OF THE EMBODIMENT
[0094] An objective of embodiments of the present invention is to
achieve reduction of cost, an increase in density of an
interconnect structure, an increase in reliability, and an increase
in the degrees of Whom of manufacture for an interconnect
substrate, a semiconductor device, methods of manufacturing the
same, a circuit board, and electronic equipment.
[0095] (1) A method of manufacturing an interconnect substrate
according to one embodiment of the present invention comprises:
[0096] forming a first conductive layer;
[0097] forming an insulating layer so that at least a part of the
insulating layer is disposed on the first conductive layer; and
[0098] forming a second conductive layer so that at least a part of
the second conductive layer is disposed on the insulating layer
over the first conductive layer;
[0099] wherein each of the first and second conductive layers is
formed by discharging drops of a solvent containing fine particles
of a conductive material, and
[0100] wherein the insulating layer is formed by discharging drops
of a solvent containing fine particles of an insulating
material.
[0101] According to this method of manufacturing an interconnect
substrate, since the first and second conductive layers and the
insulating layer are formed by discharging drops, an increase in
density of the interconnect structure can be achieved at low cost,
whereby reliability and the degrees of freedom of manufacture can
be increased.
[0102] (2) In this method of manufacturing an interconnect
substrate, the second conductive layer may be, formed so that a
part of the second conductive layer is electrically connected with
a part of the first conductive layer.
[0103] (3) In this method of manufacturing an interconnect
substrate the insulating layer may be formed on the first
conductive layer and in a region adjacent to the first conductive
layer.
[0104] (4) In this method of manufacturing an interconnect
substrate, the insulating layer may be formed of a plurality of
layers,
[0105] a lower layer of the insulating layer may be formed in a
region adjacent to a region in which the first conductive layer is
formed, and
[0106] an upper layer of the insulating layer may be formed on the
first conductive layer and the lower layer of the insulating
layer.
[0107] (5) In this method of manufacturing an interconnect
substrate, the lower layer of the insulating layer may be formed
after forming the first conductive layer.
[0108] (6) In this method of manufacturing an interconnect
substrate the first conductive layer may be formed after forming
the lower layer of the insulating layer.
[0109] (7) This method of manufacturing an interconnect substrate
may further comprise forming one or more posts on the first
conductive layer by discharging drops of a solvent containing fine
particles of a conductive material,
[0110] wherein the insulating layer may be formed to avoid a region
in which the posts are formed.
[0111] (8) In this method of manufacturing an interconnect
substrate, the insulating layer may be formed so that a height of
an upper surface of the insulating layer is substantially equal to
a height of an upper surface of at least one of the posts.
[0112] (9) In this method of manufacturing an interconnect
substrate, the second conductive layer may be formed to pass over
at least one of the posts.
[0113] (10) In this method of manufacturing an interconnect
substrate, the second conductive layer may be formed to avoid at
least one of the posts.
[0114] (11) This method of manufacturing an interconnect substrate
may further comprise:
[0115] forming a second insulating layer so that at least a part of
the second insulating layer is disposed on the second conductive
layer; and
[0116] forming a third conductive layer so that at least a part of
the third conductive layer is disposed on the second insulating
layer over the second conductive layer;
[0117] wherein the third conductive layer may be formed by
discharging drops of a solvent containing fine particles of a
conductive material; and
[0118] wherein the second insulating layer may be formed by
discharging drops of a solvent containing fine particles of an
insulating maternal.
[0119] (12) In this method of manufacturing an interconnect
substrate,
[0120] the second insulating layer may be formed to avoid a region
in which at least one of the posts is formed, and
[0121] the third conductive layer may be formed to pass over at
least one of the posts.
[0122] (13) Id this method of manufacturing an interconnect
substrate, at least one of the posts may be formed by a plurality
of steps.
[0123] (14) This method of manufacturing an interconnect substrate
may further comprise forming one or more electronic components,
[0124] wherein each of a plurality of components forming one of the
electronic components may be formed by discharging drops of a
solvent containing fine particles of a material.
[0125] (15) In this method of manufacturing an interconnect
substrate, each of the electronic components may be one of a
capacitor, a resistor, a diode, and a transistor.
[0126] (16) In this method of manufacturing an interconnect
substrate, at least one of the electronic components may be formed
on a surface on which the first conductive layer is formed.
[0127] (17) In this method of manufacturing an interconnect
substrate, at least one of the electronic components may be formed
on the insulating layer.
[0128] (18) In this method of manufacturing an interconnect
substrate, at least one of the electronic components may be formed
on the second insulating layer.
[0129] (19) In this method of manufacturing an interconnect
substrate, the first conductive layer may be formed on a
substrate.
[0130] (20) In this method of manufacturing an interconnect
substrate,
[0131] the substrate may include a depression section, and
[0132] the first conductive layer may be formed to pass through the
depression section.
[0133] (21) In this method of manufacturing an interconnect
substrate, at least a top surface of the substrate may be formed of
an insulating material.
[0134] (22) In this method of manufacturing an interconnect
substrate,
[0135] the substrate may include an insulating section and a
conductive section which is formed through the insulating section,
and
[0136] the first conductive layer may be formed over the insulating
section and the conductive section so that the first conductive
layer is electrically connected with the conductive section.
[0137] (23) This method of manufacturing an interconnect substrate
may further comprise removing the substrate from the first
conductive layer.
[0138] (24) A method of manufacturing a semiconductor device
according to another embodiment of the present invention
comprises:
[0139] manufacturing an interconnect substrate; and
[0140] mounting a semiconductor chip on the interconnect
substrate,
[0141] the manufacturing of an interconnect substrate
including:
[0142] forming a first conductive layer;
[0143] forming an insulating layer so that at least a part of the
insulating layer is disposed on the first conductive layer, and
[0144] forming a second conductive layer so that at least a part of
the second conductive layer is disposed on the insulating layer
over the first conductive layer,
[0145] wherein each of the first and second conductive layers is
formed by discharging drops of a solvent containing fine particles
of a conductive material, and
[0146] wherein the insulating layer is formed by discharging drops
of a solvent containing fine particles of an insulating
material.
[0147] According to this method of manufacturing a semiconductor
device, since the first and second conductive layers and the
insulating layer are formed by discharging drops, an increase in
density of the interconnect structure can be achieved at low cost,
whereby reliability and the degrees of freedom of manufacture can
be increased.
[0148] (25) In this method of manufacturing a semiconductor
device,
[0149] the interconnect substrate may be manufactured with a part
of the first conductive layer being exposed, and
[0150] the exposed part of the first conductive layer may be
electrically connected with the semiconductor chip.
[0151] (26) In this method of manufacturing a semiconductor device,
a conductive layer other than the first and second conductive
layers may be electrically connected with the semiconductor
chip.
[0152] (27) In this method of manufacturing a semiconductor device,
the first conductive layer may be formed over a substrate,
[0153] (28) In this method of manufacturing a semiconductor
device,
[0154] the substrate may include a depression section,
[0155] the first conductive layer may be formed to pass through the
depression section, and
[0156] the semiconductor chip may be mounted in the depression
section.
[0157] (29) In this method of manufacturing a semiconductor
device,
[0158] the substrate may include an insulating section and a
conductive section which is formed through the insulating section,
and
[0159] the first conductive layer may be formed over the insulating
section and the conductive section so that the first conductive
layer is electrically connected with the conductive section.
[0160] (30) This method of manufacturing a semiconductor device may
further comprise removing the substrate from the first conductive
layer.
[0161] (31) A method of manufacturing a semiconductor device
according to a further embodiment of the present invention
comprises:
[0162] mounting a semiconductor chip over a substrate with a
surface of the semiconductor chip on which an electrode is formed
facing upward;
[0163] forming a first conductive layer over the substrate and the
semiconductor chip so that the first conductive layer is
electrically connected with the electrode of the semiconductor
chip;
[0164] forming an insulating layer so that at least a part of the
insulating layer is disposed on the first conductive layer; and
[0165] forming a second conductive layer so that at least a part of
the second conductive layer is disposed on the insulating layer
over the first conductive layer,
[0166] wherein each of the first and second conductive layers is
formed by discharging drops of a solvent containing fine particles
of a conductive material, and
[0167] wherein the insulating layer is formed by discharging drops
of a solvent containing fine particles of an insulating
material.
[0168] According to this method of manufacturing a semiconductor
device, since the first and second conductive layers and the
insulating layer are formed by discharging drops, an increase in
density of the interconnect structure can be achieved at low cost,
whereby reliability and the degrees of freedom of manufacture can
be increased.
[0169] (32) In this method of manufacturing a semiconductor
device,
[0170] the substrate may include a depression section, and
[0171] the semiconductor chip may be mounted in the depression
section.
[0172] (33) This method of manufacturing a semiconductor device may
further comprise forming a resin layer by fig the depression
section in which the semiconductor chip is mounted with a
resin,
[0173] wherein the first conductive layer may be formed to pass
over the resin layer.
[0174] (34) A method of manufacturing a semiconductor device
according to still another embodiment of the present invention
comprises:
[0175] mounting a semiconductor chip over a first substrate with a
surface of the semiconductor chip on which an electrode is formed
facing upward;
[0176] attaching a second substrate to the first substrate, the
second substrate having a shape which avoids the semiconductor
chip;
[0177] forming a first conductive layer over the second substrate
and the semiconductor chip so that the first conductive layer is
electrically connected with the electrode of the semiconductor
chip;
[0178] forming an insulating layer so that at least a part of the
insulating layer is disposed on the first conducive layer; and
[0179] forming a second conductive layer so that at least a part of
the second conductive layer is disposed on the insulating layer
over the first conductive layer,
[0180] wherein each of the first and second conductive layers is
formed by discharging drops of a solvent containing fine particles
of a conductive material, and
[0181] wherein the insulating layer is formed by discharging drops
of a solvent containing fine particles of an insulating
material.
[0182] According to this method of manufacturing a semiconductor
device, since the first and second conductive layers and the
insulating layer are formed by discharging drops, an increase in
density of the interconnect structure can be achieved at low cost,
whereby reliability and the degrees of freedom of manufacture can
be increased
[0183] (35) In this method of manufacture a semiconductor device,
the second substrate may have a coefficient of thermal expansion
closer to a coefficient of thermal expansion of the semiconductor
chip than a coefficient of thermal expansion of the first
substrate.
[0184] (36) A method of manufacturing a semiconductor device
according to a still further embodiment of the present invention
comprises:
[0185] forming a first conductive layer over a semiconductor wafer
on which a plurality of integrated circuits are formed so that the
first conductive layer is electrically connected with electrodes of
the semiconductor wafer;
[0186] forming an insulating layer so that at least a part of the
insulating layer is disposed on the first conductive layer;
[0187] forming a second conductive layer so that at least a part of
the second conductive layer is disposed on the insulating layer
over the first conductive layer; and
[0188] cutting the semiconductor wafer,
[0189] wherein each of the first and second conductive layers is
formed by discharging drops of a solvent containing fine particles
of a conductive material, and
[0190] wherein the insulating layer is formed by discharging drops
of a solvent containing fine particles of an insulating
material.
[0191] According to this method of manufacturing a semiconductor
device, since the first and second conductive layers and the
insulating layer are formed by discharging drops, an increase in
density of the interconnect structure can be achieved at low cost,
whereby reliability and the degrees of freedom of manufacture can
be increased.
[0192] (37) In this method of manufacturing a semiconductor device,
the second conductive layer may be formed so that a part of the
second conductive layer is electrically connected with a part of
the first conductive layer.
[0193] (38) In this method of manufacturing a semiconductor device,
the insulating layer may be formed on the first conductive layer
and in a region adjacent to the first conductive layer.
[0194] (39) In this method of manufacturing a semiconductor device,
the insulating layer may be formed of a plurality of layers, a
lower layer of the insulating layer may be formed in a region
adjacent to a region in which the first conductive layer is formed,
and an upper layer of the insulating layer may be formed on the
first conductive layer and the lower layer of the insulating
layer.
[0195] (40) In this method of manufacturing a semiconductor device,
the lower layer of the insulating layer may be formed after forming
the first conductive layer.
[0196] (41) In this method of manufacturing a semiconductor device,
the first conductive layer may be formed after forming the lower
layer of the insulating layer.
[0197] (42) This method of manufacturing a semiconductor device may
further comprise forming one or more posts on the first conductive
layer by discharging drops of a solvent containing fine particles
of a conductive material,
[0198] wherein the insulating layer may be formed to avoid a region
in which the posts are formed.
[0199] (43) In this method of manufacturing a semiconductor device,
the insulating layer may be formed so that a height of an upper
surface of the insulating layer is substantially equal to a height
of an upper surface of at least one of the posts.
[0200] (44) In this method of manufacturing a semiconductor device,
the second conductive; layer may be formed to pass over at least
one of the posts.
[0201] (45) In this method of manufacturing a semiconductor device,
the second conductive layer may be formed to avoid at least one of
the posts.
[0202] (46) This method of manufacturing a semiconductor device may
further compose:
[0203] forming a second insulating layer so that at least a part of
the second insulating layer is disposed on the second conductive
layer; and forming a third conductive layer so that at least a part
of the third conductive layer is disposed on the second insulating
layer over the second conductive layer,
[0204] wherein the third conductive layer may be formed by
discharging drops of a solvent containing fine particles of a
conductive material, and
[0205] wherein the second insulating layer may be formed by
discharging drops of a solvent containing fine particles of an
insulating material.
[0206] (47) In this method of manufacturing a semiconductor
device,
[0207] the second insulating layer may be formed to avoid a region
kin which at least one of the posts is formed, and
[0208] the third conductive layer may be formed to pass over at
least one of the posts.
[0209] (48) In this method of manufacturing a semiconductor device,
at least one of the posts may be formed by a plurality of
steps.
[0210] (49) his method of manufacturing a semiconductor device may
further comprise forming one or more electronic components,
[0211] wherein each of a plurality of components forming one of the
electronic components may be formed by discharging drops of a
solvent containing fine particles of a material.
[0212] (50) In this method of manufacturing a semiconductor device,
each of the electronic components may be one of a capacitor, a
resistor, a diode, and a transistor.
[0213] (51) In this method of manufacturing a semiconductor device,
at least one of the electronic components may be formed on a
surface on which the first conductive layer is formed.
[0214] (52) In this method of manufacturing a semiconductor device,
at least one of the electronic components may be formed on the
insulating layer.
[0215] (53) In this method of manufacturing a semiconductor device,
at least one of the electronic components may be formed on the
second insulating layer.
[0216] (54) An interconnect substrate according to yet another
embodiment of the present invention is manufactured by any of the
above methods.
[0217] (55) A semiconductor device according to a yet further
embodiment of the present invention is manufactured by any of the
above methods.
[0218] (56) A semiconductor device according to a yet further
embodiment of the present invention comprises:
[0219] a substrate including a depression section;
[0220] a first conductive layer formed to pass through the
depression section;
[0221] an insulating layer, at least a part of the insulating layer
being disposed on the first conductive layer;
[0222] a second conductive layer, at least a part of the second
conductive layer being disposed on the insulating layer over the
first conductive layer; and
[0223] a semiconductor chip mounted in the depression section.
[0224] (57) In this semiconductor device, the semiconductor chip
may be electrically connected with the first conductive layer.
[0225] (58) In this semiconductor device, the semiconductor chip
may be electrically connected with a conductive layer other than
the first and second conductive layers.
[0226] (59) A semiconductor device according to a yet further
embodiment of the present invention comprises:
[0227] a substrate including a depression section;
[0228] a semiconductor chip mounted in the depression section of
the substrate with a surface of the semiconductor chip on which an
electrode is formed facing upward;
[0229] a first conductive layer formed over the substrate and the
semiconductor chip so that the first conductive layer is
electrically connected with the electrode of the semiconductor
chip;
[0230] an insulating layer, at least a part of the insulating layer
being disposed on the first conductive layer; and
[0231] a second conductive layer, at least a part of the second
conductive layer being disposed on the insulating layer over the
first conductive layer.
[0232] (60) This semiconductor device may further comprise a resin
layer formed in the depression section in which the semiconductor
chip is mounted,
[0233] wherein the first conductive layer may be formed to pass
over the resin layer.
[0234] (61) A semiconductor device according to a yet fitter
embodiment of the present invention comprises:
[0235] a first substrate;
[0236] a semiconductor chip mounted over the first substrate with a
surface of the semiconductor chip on which an electrode is formed
facing upward;
[0237] a second substrate having a shape which avoids the
semiconductor chip and being attached to the first substrate;
[0238] a first conductive layer which is formed over the second
substrate and the semiconductor chip so that the first conductive
layer is electrically connected with the electrode of the
semiconductor chip;
[0239] an insulating layer, at least a part of the insulating layer
being disposed on the first conductive layer; and
[0240] a second conductive layer, at least a part of the second
conductive layer being disposed on the insulating layer over the
first conductive layer.
[0241] (62) In this semiconductor device, the second substrate may
have a coefficient of thermal expansion closer to a coefficient of
thermal expansion of the semiconductor chip than that of the first
substrate.
[0242] (63) A circuit board according to a yet further embodiment
of the present invention is equipped with any of the above
semiconductor devices.
[0243] (64) Electronic equipment according to a yet hither
embodiment of the present invention comprises the any of above
semiconductor devices.
[0244] The embodiments of the present invention are described below
with reference to the drawings.
[0245] First Embodiment
[0246] FIGS. 1 to 10B are views illustrating a method of
manufacturing an interconnect, substrate according to a first
embodiment of the present invention. In the present embodiment, a
substrate 10 is provided as shown in FIG. 1. The shape of the
substrate 10 is not limited to that of a plate (rectangular plate,
for example) insofar as the substrate 10 can support a product
placed or formed on the substrate 10. The substrate 10 may be
formed of an insulating material (resin such as a polyimide or
glass, for example), a conductor (metal such as copper, for
example), or a semiconductor; The substrate 10 may be a radiator
(heat sink, for example) formed of a heat radiating material such
as a metal. In the case where the substrate 10 is formed of a
conductor, at least the surface of the substrate 10 may be formed
of an insulating film 12. The insulating film 12 may be formed by
applying a resin such as a polyimide and sintering the resin at
about 200-600.degree. C. for about 1 to 5 hours.
[0247] A depression section 14 may be formed in the substrate 10.
There are no specific limitations to the shapes of the opening and
the bottom of the depression section 14. The shapes of the opening
and the bottom of the depression section 14 may be rectangular. The
inner wall surface of the depression section 14 may be inclined
with respect to the upper side (surface surrounding the depression
section 14) of the substrate 10 or the bottom of the depression
section 14. Specifically, the inner wall surface of the depression
section 14 may be a tapered surface. A connection section 16 which
connects the inner wall surface of the depression section 14 with
the upper side (surface surrounding the depression section 14) of
the substrate 10 may be a curved surface (protruding surface), A
connection section 18 which connects the inner wall surface of the
depression section 14 with the bottom of the depression section 14
may be a curved surface (depressed surface). If the connection
sections 16 and 18 have such shapes, occurrence of breakage of a
first conductive layer 20 which passes over the connection sections
16 and 18 is reduced. The depression section 14 may be formed to
have a depth of about 0.5 to several millimeters by etching,
cutting, a stamping. The insulating film 12 may be formed on either
the entire surface of the depression section 14 (inner wall surface
and bottom of the depression section 14), or formed only on, a part
of the depression section 14 (region in which the first conductive
layer 20 is formed). The insulating film 12 maybe formed on the
entire area of the upper side of the substrate 10 (surface
surrounding the depression section 14), or formed only on a part of
the upper side of the substrate 10 (region in which the fir
conductive layer 20 is formed).
[0248] As shown in FIGS. 2A and 2B, the first conductive layer
(interconnect pattern including a plurality of lines, for example)
20 is formed. The first conductive layer 20 is formed on the
substrate 10. The first conductive layer 20 may be formed to pass
through the depression section 14. The first conductive layer 20 is
formed by discharging drops of a solvent containing fine particles
of a conductive material (metal such as gold, silver, or copper,
for example). An ink-jet method or a Bubble Jet (registered
trademark) method may be used. As a solvent containing fine
particles of gold, "Perfect Gold" (manufactured by Vacuum
Metallurgical Co., Ltd.) may be used. As a solvent containing fine
particles of silver, "Perfect Silver" (manufactured by Vacuum
Metallurgical Co., Ltd.) may be used. There are no specific
limitations to the size of the fine particles. The fine particles
used herein refer to particles which can be discharged together
with a solvent. The first conductive layer 20 may be formed by
sintering the discharged solvent containing fine particles of a
conductive material at about 200 to 600.degree. C. for about 1 to 5
hours.
[0249] An insulating layer 26 (see FIG. 3B) is formed. The
insulating layer 26 is formed by discharging drops of a solvent
containing fine particles of an insulating material (resin such as
a polyimide, for example). For example, an inkjet method or a
Bubble Jet (registered trademark) method may be used. The
insulating layer 26 may be formed by a plurality of layers (lower
layer 22 and upper layer 24, for example). In this case, a solvent
containing fine particles of an insulating material may be
discharged a plurality of times. The insulating layer 26 may be
formed by sintering a discharged solvent containing fine particles
of an insulating material at about 200 to 600.degree. C. for about
1 to 5 hours. The sintering may be performed each time the lower
layer 22 and the upper layer 24 are formed.
[0250] As shown in FIGS. 2A and 2B, the lower layer 22 may be
formed in a region adjacent to a region in which the first
conductive layer 20 is formed. The lower layer 22 may be formed
after forming the fist conductive layer 20. In this case, the lower
layer 22 may be formed to avoid the upper side of the first
conductive layer 20. The lower layer 22 may be formed to avoid the
region in which the first conductive layer 20 is formed, and the
first conductive layer 20 may be formed in the region in which the
lower layer 22 is not formed. The lower layer 22 may be formed so
that the upper side of the lower layer 22 has a height equal to the
height of the upper side of the first conductive layer 20. The
lower layer 22 may be formed so that the height of the upper side
of the lower layer 22 differs from the height of the upper side of
the first conductive layer 20.
[0251] As shown in FIGS. 3A and 3B, the upper layer 24 may be
formed on the first conductive layer 20 and the lower layer 22. The
upper layer 24 may be formed after forming the first conductive
layer 20 and the lower layer 22. The lower layer 22 may be formed
first, and a part of the upper layer 24 may be formed on the lower
layer 22 so as to avoid the first conductive layer 20. Then, the
first conductive layer 20 may be formed, and the remaining portion
of the upper layer 24 may be formed on the first conductive layer
20.
[0252] The insulating layer 26 is formed in this manner so that at
least a part (upper layer 24, for example) of the insulating layer
26 is disposed on the first conductive layer 20. The insulating
layer 26 may be formed to avoid a part of the first conductive
layer 20. The insulating layer 26 may be formed on the first
conductive layer 20 and in the region adjacent to the first
conductive layer 20. The insulating layer 26 may cover the surface
of the first conductive layer 20 (surface excluding the contact
area between the first conductive layer 20 and the substrate 10, an
area in which a post 30 is formed, and an electrical connection
section with a semiconductor chip 80 (see FIG. 11), for example).
The insulating layer 26 may be formed to avoid a region in which a
semiconductor chip is mounted (at least a part of the bottom of the
depression section 14, for example).
[0253] The above description illustrates an example in which the
insulating layer 26 is formed by a plurality of layers (a plurality
of processes). However the insulating layer 26 may be formed by a
single layer (single process). For example, after forming the first
conductive layer 20, the insulating layer 26 may be formed so that
at least a part of the insulating layer 26 is disposed on the first
conductive layer 20.
[0254] As shown in FIGS. 3A and 3B, at least one post 30 may be
formed on the first conductive layer 20. The post 30 is a section
which electrically connects upper and lower conductive layers. The
post 30 may be larger than the first conductive layer 20 insofar as
a part of the post 30 is placed on the first conductive layer 20.
The post 30 is formed by discharging drops of a solvent containing
fine particles of a conductive material. The insulating layer 26 is
formed to avoid a region in which the post 30 is formed. The
insulating layer 26 (upper layer 24, for example) may be formed so
that the height of the upper surface of the insulating layer 26 is
almost equal to the height of the upper side of at least one post
30.
[0255] The insulating layer 26 may be formed after forming the post
30 on the first conductive layer 20. The post 30 may be formed on
the first conductive layer 20 after forming at least a part (lower
layer 22, for example) of the insulating layer 26.
[0256] Examples of the post 30 formed on the first conductive layer
20 are given below. The post 30 shown in FIG. 3A consists only of a
post 31 formed on the first conductive layer 20. The post 30 shown
in FIG. 5 consists of the post 31 formed on the first conductive
layer 20 (see FIG. 3A), a post 32 formed on the post 31 (see FIG.
4), and a post 33 formed on the post 32. The post 30 shown in FIG.
7 consists of the post 31 formed on the first conductive layer 20
(see FIG. 3A), the post 32 formed on the post 31 (see FIG. 4), the
post 33 formed on the post 32 (see FIG. 5), a post 34 formed on the
post 33 (see FIG. 6), and a post 35 formed on the post 34. The post
30 may be formed of a single layer or a plurality of layers. Each
of the posts 31, 32, 33, 34, and 35 which makes up the post 30 may
be formed by discharging drops of a solvent containing fine
particles of a conductive material. The posts 31, 32, 33, 34, and
35 may be sequentially formed. Specifically, at least one post 30
may be formed by a plurality of steps.
[0257] As shown in FIG. 4, a second conductive layer (interconnect
pattern including a plurality of lines, for example) 40 is formed.
The second conductive layer 40 is formed so that a part of the
second conductive layer 40 is disposed on the insulating layer 26
over the first conductive layer 20. The details of the first
conductive layer 20 are applied to the second conductive layer 40.
The second conductive layer 40 may be formed so that a part of the
second conductive layer 40 is electrically connected with a part of
the first conductive layer 20. For example, the second conductive
layer 40 may be formed to pass over at least one post 30 (post 30
consisting only of the post 31, for example). This allows a part of
the first conductive layer 20 to be electrically connected with a
part of the second conductive layer 40 through the post 30. The
fist and second conductive layers 20 and 40 are electrically
insulated from each other by the insulating layer 26 in the area
other than the post 30. The second conductive layer 40 may be
formed to avoid at least one post 31 (post 31 on which the post 32
is formed (see FIG. 3A) in more detail).
[0258] According to the present embodiment, since the first and
second conductive layers 20 and 40 and the insulating layer 26 are
formed by discharging drops, an increase in density of the
interconnect structure can be achieved at low cost, whereby
reliability and the degrees of freedom of manufacture can be
increased.
[0259] As shown in FIG. 5, a second insulating layer 46 may be
formed so that at least a part of the second insulating layer 46 is
disposed on the second conductive layer 40. The second insulating
layer 46 may be formed to avoid a part of the second conductive
layer 40. The details of the insulating layer (first insulating
layer) 26 are applied to the second insulating layer 46. For
example, the second insulating layer 46 may be formed by a lower
layer 42 shown in FIG. 4 and an upper layer 44 shown in FIG. 5. The
details of the lower layer 22 and the upper layer 24 are applied to
the lower layer 42 and the upper layer 44. The second insulating
layer 46 may be formed to avoid a region in which the semiconductor
chip 80 (see FIG. 11) is mounted (at least a part of the bottom of
the depression section 14, for example).
[0260] The post 32 may be formed on any of the posts 31 shown in
FIG. 3A. In this case, the second insulating layer 46 is formed to
avoid a region in which at least one post 32 is formed. As shown in
FIG. 5, the post 33 may be formed on the post 32. A post 50 (see
FIG. 9) may be formed on the second conductive layer 40. The post
50 may consist of a post 51 shown in FIG. 5 formed on the second
conductive layer 40 and posts 52 to 55 shown in FIGS. 6 to 9A
formed on the post 51. The details of the post 30 are applied to
the post 50.
[0261] As shown in FIG. 6, a third conductive layer 60 may be
formed so that at least a part of the third conductive layer 66 is
disposed on the second insulating layer 46 over the second
conductive layer 40. The details of the first conductive layer 20
are applied to the third conductive layer 60. The third conductive
layer 60 may be formed so that a part of the third conductive layer
60 is electrically connected with a part of the first conductive
layer 20 or the second conductive layer 40. For example, the third
conductive layer 60 may be formed to pass over at least one post 30
(post 30 consisting of the posts 31, 32, and 33, for example). This
allows a part, of the first conductive layer 20 to be electrically
connected with a part of the td conductive layer 60 through the
post 30. The third conductive layer 60 may be formed to pass over
at least one post 51 (this example is not illustrated). This allows
a part of the second conductive layer 40 to be electrically
connected with a part of the third conductive layer 60 through the
post 51. The first and second conductive layers 20 and 40 are
electrically insulated from the third conductive section 60 by the
second insulating layer 46 in the area other than the posts 30 and
51. The third conductive layer 60 may be formed to avoid at least
one post 34 and at least one post 52.
[0262] As shown in FIGS. 7 and 8, a conductive layer and an
insulating layer are optionally stacked by repeating the above
steps. As shown in FIGS. 9A and 9B, an insulating layer 72 may be
formed so that the upper sides of the posts 50 and 70 are exposed.
The post 50 is formed on the second conductive layer 40 and the
post 70 is formed on the conductive layer other than the second
conductive layer 40 or the post (details are omitted). The posts 50
and 70 may be formed at positions at which external terminals are
formed. The number and arrangement of the posts 50 and 70 are not
limited to those shown in FIG. 9A. The posts 50 and 70 may be
arranged in the shape of a matrix (in a plurality of rows and
columns) or in the shape of an area array.
[0263] As shown in FIGS. 10A and 10B, lands 74 larger than the
upper sides of the posts 50 and 70 may be formed on the posts 50
and 70. The lands 74 are electrically connected with one of the
conductive layers (first conductive layer 20, for example) through
the posts 50 and 70. At least one land 74 is electrically connected
with the conductive layer which is electrically connected with the
semiconductor chip (first conductive layer 20, for example). An
insulating layer 76 may be formed so that at least a part of the
lands 74 is exposed. The details of the first conductive layer 20
may be applied to the lands 74. The details of the insulating layer
26 may be applied to the insulating layer 76.
[0264] An interconnect substrate is manufactured in this manner.
The interconnect substrate has a configuration derived from the
above description. As shown in FIGS. 10A and 10B, a part of the
first conductive layer 20 may be exposed. For example, a part of
the first conductive layer 20 may be exposed inside the depression
section 14 of the substrate 10. The exposed part of the first
conductive layer 20 may be used for electrical connection with the
semiconductor chip 80.
[0265] FIGS. 11 and 12 are views illustrating a method of
manufacturing a semiconductor device. In the present embodiment,
the semiconductor chip 80 is mounted on the above described
interconnect substrate. The semiconductor chip 80 has a peripheral
type pad arrangement in which pads are arranged on the periphery of
the semiconductor chip 80. The exposed part of the first conductive
layer 20 may be electrically connected with the semiconductor chip
80. The conductive layer other than the first conductive layer 20
(second conductive layer 40 or the conductive layer other than the
first and second conductive layers 20 and 40, for example) may be
electrically connected with the semiconductor chip 80. The
semiconductor chip 80 may be mounted by applying face-down bonding
as shown in FIG. 11, or applying face-up bonding in which the
semiconductor chip 80 is electrically connected with the conductive
layer through wires. The semiconductor chip 80 may be mounted in
the depression section 14 of the substrate 10.
[0266] As shown in FIG. 12, the depression section 14 in which the
semiconductor chip 80 is mounted may be filled with a resin 84 such
as an epoxy resin. A filler metal 82 such as solder (soft solder or
hard solder) may be provided to the land 74. The filler metal may
be a solder ball or solder paste.
[0267] A semiconductor device according to the present embodiment
includes the substrate 10 in which the depression section 14 is
formed. The first conductive layer 20 is formed to pass through the
depression section 14. At least a part of the insulating layer 26
is disposed on the first conductive layer 20. At least a part of
the second conductive layer 40 is disposed on the insulating layer
26 over the first conductive layer 20. The semiconductor chip 80 is
mounted in the depression section 14. The semiconductor chip 80 may
be electrically connected with the first conductive layer 20. The
semiconductor chip 80 may be electrically connected with the
conductive layer other than the first and second conductive layers
20 and 40.
[0268] According to the present embodiment, since the first and
second conductive layers and the insulating layers are formed by
discharging drops, an increase in density of the interconnect
structure can be achieved at low cost, whereby reliability and the
degrees of freedom of manufacture can be increased.
[0269] Second Embodiment
[0270] FIG. 13 is a plan view illustrating an interconnect
substrate according to a second embodiment of the present
invention. FIG. 14 is a cross-sectional view illustrating a
semiconductor device using the interconnect substrate shown in FIG.
13. In the present embodiment, the substrate 10 described in the
first embodiment is used. The depression section 14 is formed in
the substrate 10. The insulating film 12 is formed on the substrate
10.
[0271] The interconnect substrate shown in FIG. 13 includes a
plurality of lands 100. The lands 100 are formed in the uppermost
layer of the interconnect substrate. The lands 100 may be disposed
at the center (inside the depression section 14, for example) of
the interconnect substrate. The lands 100 are arranged in the shape
of an area array (in a plurality of rows and columns (three or more
rows and three or mow columns, for, example) in the shape of a
matrix, for example). The lands 100 are bonded to a semiconductor
chip 102. The interconnect substrate may include lands 104 on which
external terminals are formed in addition to the lands 100 bonded
to the semiconductor chip 102.
[0272] As shown in FIG. 14, the semiconductor device includes the
semiconductor chip 102. The semiconductor chip 102 has an area
array type pad arrangement. The semiconductor chip 102 may be
bonded face down to the interconnect substrate. Bumps may be formed
on pads of the semiconductor chip 102. The pads of the
semiconductor chip 102 are electrically connected with the lands
100.
[0273] The depression section 14 is formed in the substrate 10, and
the lands 100 are formed over the bottom of the depression section
14. Therefore, the region in which the lands 100 are formed (center
of the interconnect substrate for example) is lower than the other
region (end of the interconnect substrate, for example). The upper
side (side opposite to the side on which the pads are formed) of
the semiconductor chip 102 mounted on the interconnect substrate
may be lower than the surface of the uppermost layer (land 104, for
example) of the interconnect substrate outside the depression
section 14. The semiconductor chip 102 may be covered with a resin
106. For example, the resin 106 may be provided to a depression
which is formed corresponding to the depression section 14.
[0274] A filler metal 108 such as a solder (soft solder or hard
solder) may be provided to the lands 104. The filler metal may be a
solder ball or solder paste. At least one land 104 is electrically
connected with at least one land 100.
[0275] FIGS. 15A to 20 are views illustrating a method of
manufacturing the interconnect substrate according to the second
embodiment of the present invention. In the present embodiment, a
fit conductive layer 120 is formed as shown in FIGS. 15A and 15B.
The first conductive layer 120 may be formed on the insulating film
12. The first conductive layer 120 may be the lowermost conductive
layer among the conductive lays used for electrical connection. The
first conductive layer 120 may be made up of a plurality of lines.
A part (end, for example) of the line may be disposed to overlap a
position at which one of the lands 100 (see FIG. 13) is formed. In
more detail, a land 112 (see FIG. 13) among the plurality of lands
100 located on the inner side overlaps a pt (part 121 of the line,
for example) of the first conductive layer 120. The details
(material, formation method, and the like) of the first conductive
layer 20 described in the first embodiment are applied to the first
conductive layer 120.
[0276] As shown in FIGS. 16A and 16B, an insulating layer 126 and a
post 131 are formed. The details (material, formation method, and
the like) of the insulating layer 26 and the post 31 described in
the first embodiment are applied to the insulating layer 126 and
the post 131. A post 141 is formed on a part (part 121 of the line
shown in FIG. 15A, for example) of the first conductive layer 120.
The Post 141 is formed at a position corresponding to the pad of
the semiconductor chip 102 (position at which the land 100 is
formed). The post 141 may be formed only at a position
corresponding to the land 112 (see FIG. 13) among the plurality of
lands 100 located on the inner side. The details (material,
formation method, and the like) of the post 141 may be the same as
the details of the post 131.
[0277] As shown in FIGS. 17A and 17B, a second conductive layer 150
is formed. The second conductive layer 150 is formed on the
insulating layer 126. The details (material, formation method, and
the like) of the second conductive layer 40 described in the first
embodiment are applied to the second conductive layer 150. A part
(end, for example) 151 of one of the plurality of lines which make
up the second conductive layer 150 may be disposed at a position
corresponding to the land 100. The part 151 of the line is disposed
at a position corresponding to the land 114 (see FIG. 13) located
on the outer side of the part 121 (see FIG. 15A) of the line formed
in advance.
[0278] Posts 132 and 142 are respectively formed on the posts 131
and 141. The details (material, formation method, and the like) of
the posts 132 and 142 may be the same as the details of the posts
131 and 141. The second conductive layer 150 may be formed to pass
over at least one of the posts 141 and 131 (not shown in FIGS. 17A
and 17B).
[0279] As shown in FIGS. 18A and 18B, a second insulating layer 156
is formed. A post 133 may be formed on the post 132. The stacked
posts 131, 132, and 133 may be referred to as one post 130 in the
case where a post is not formed on the post 133. A post 160 may be
formed on the second conductive layer 150. A post 143 may be formed
on the post 142. A post 171 may be formed on the second conductive
layer 150 (end 151 of the line, for example). The details
(material, formation method, and the like) of the second insulating
layer 156 may be the same as the details of the second insulating
layer 46 described in the first embodiment. The details (material,
formation method, and the like) of the posts 133, 160, 143, and 171
may be the same as the details of the post 131.
[0280] As shown in FIG. 19, a third conductive layer 180 may be
formed, The third conductive layer 180 is formed on the second
insulating layer 156. The third conductive layer 180 may be formed
to pass over the post 130. The details (material, formation method,
and the like) of the second conductive layer 40 described in the
first embodiment are applied to the third conductive layer 180.
Posts 144 and 172 are respectively formed on the posts 143 and 171.
The details (material, formation method, and the like) of the posts
144 and 172 may be the same as the details of the post 141.
[0281] As shown in FIG. 20, a third insulating layer 186 may be
formed. A post 135 may be formed on the post 134. The stacked posts
131 to 135 may be referred to as one post 130 in the case where a
post is not formed on the post 135. A post 190 may be formed on the
third conductive layer 180. Posts 145 and 173 may be respectively
formed on the posts 144 and 172. The stacked posts 141 to 145 (or
posts 171 to 173) may be referred to as one post 140 (or post 170)
in the case where a post is not formed on the post 145 (or post
173). The details (material, formation method, and the like) of the
third insulating layer 186 may be the same as the details of the
second insulating layer 46 described in the first embodiment. The
details (material, formation method, and the like) of the posts
135, 190, 145, and 173 may be the same as the details of the post
131.
[0282] As shown in FIG. 13, the lands 104 may be formed on the
posts 130 and 190. The surfaces of the posts 140 and 170 may be the
lands 112 and 114, or the lands may be formed by forming a
conductive layer on the posts 140 and 170.
[0283] The details described in other embodiments may be applied to
the present embodiment. The details described in the present
embodiment may be applied to other embodiments.
[0284] Third Embodiment
[0285] FIGS. 21A to 21C are views illustrating a method of
manufacturing a semiconductor device according to a third
embodiment of the present invention. In the present embodiments a
semiconductor chip 210 is mounted on a substrate 200 so that the
surface of the semiconductor chip 210 on which electrodes 212 are
formed faces upward, as shown in FIG. 21A. An insulating layer 204
may be formed on the substrate 200. The substrate 200 may include a
depression section 202. The inner wall surface of the depression
section 202 may be formed perpendicularly to the substrate 200 or
inclined with respect to the substrate 200. The inner wall surface
of the depression section 202 may be a curved surface (protruding
surface or depressed surface). The semiconductor chip 210 may be
mounted in the depression section 202. The substrate 200 may be
bonded to the semiconductor chip 210 through an adhesive 214. The
depression section 202 in which the semiconductor chip 210 is
mounted may be filled with a resin 216. As shown in FIG. 21B, a
resin layer is formed in the depression section 202 in which the
semiconductor chip 210 is mounted by using the resin 216.
[0286] As shown in FIG. 21C, a first conductive layer 220 is formed
over the substrate 200 (region surrounding the depression section
202, for example) and the semiconductor chip 210. The first
conductive layer 220 is formed to be electrically connected with
the electrodes 212 of the semiconductor chip 210. For example,
bumps 218 may be formed on the electrodes 212, and the first
conductive layer 220 may be formed to pass over the bumps 218. The
first conductive layer 220 may be formed to pass over the resin
layer formed by the resin 216. An insulating material (film or
layer) may be interposed between the semiconductor chip 210 and the
first conductive layer 220. An insulating layer 226 is formed so
that at least a part of the insulating layer 226 is disposed on the
first conductive layer 220. A second conductive layer 230 is formed
so that at least a part of the second conductive layer 230 is
disposed on the insulating layer 226 over the first conductive
layer 220. The first and second conductive layers 220 and 230 may
be electrically connected (bonded) through posts 240.
[0287] The details (material, formation method, and the like) of
the first and second conductive layers 20 and 40 and the insulating
layer 26 described in the first embodiment are applied to the first
and second conductive layers 220 and 230 and the insulating layer
226. The bump 218 may be formed by using the same method as the
first conductive layer 220. An insulating layer, a conductive
layer, and a post may be further stacked on the second conductive
layer 230. The details are the same as described in the first and
second embodiments.
[0288] A semiconductor device is manufactured in this manner. The
semiconductor device has a configuration derived from the above
manufacturing method. In the present embodiment, the effects
described in the first embodiment can be achieved. The details
described in other embodiments may be applied to the present
embodiment. The details described in the present embodiment may be
applied to other embodiments.
[0289] Fourth Embodiment
[0290] FIGS. 22A to 22C are views illustrating a method of
manufacturing a semiconductor device according to a fourth
embodiment of the present invention. In the present embodiment, a
semiconductor chip 300 is mounted on a first substrate 310 so that
the surface of the semiconductor chip 300 on which electrodes 302
are formed faces upward, as shown in FIG. 22A. The first substrate
310 may include a protruding section 312. In this case, the
semiconductor chip 300 may be mounted on the protruding section
312. The first substrate 310 may be bonded to the semiconductor
chip 300 through an adhesive 314. In the case where the fist
substrate 310 is a conductor, an insulating film may be formed on
the surface of the first substrate 310, or the fist substrate 310
may be electrically insulated from the semiconductor chip 300 by
the adhesive 314.
[0291] A second substrate 320 having a shape so as to avoid the
semiconductor chip 300 (having a hole 322, for example) is attached
to the first substrate 310. The protruding section 312 of the first
substrate 310 may be disposed inside the hole 322. The first and
second substrates 310 and 320 may be bonded through the adhesive
314. The second substrate (glass plate or ceramic substrate, for
example) 320 may have a coefficient of thermal expansion closer to
the coefficient of thermal expansion of the semiconductor chip 300
than that of the first substrate (metal plate, for example) 310.
The first substrate 310 may be a heat sink.
[0292] The hole 322 may be filled with a resin 316. A resin layer
may be formed by the resin 316 inside the hole 322, as shown in
FIG. 22B.
[0293] As shown in FIG. 22C, the first conductive layer 220 is
formed over the second substrate 320 and the semiconductor chip 300
so that the first conductive layer 220 is electrically connected
with the electrodes 302 of the semiconductor chip 300. Since the
subsequent steps are the same as the steps described in the third
embodiment, further description is omitted. A semiconductor device
is manufactured in this manner. The semiconductor device has a
configuration derived from the above manufacturing method. In the
present embodiment, the effects described in the first embodiment
can also be achieved. The details described in other embodiments
may be applied to the present embodiment. The details described in
the present embodiment may be applied to other embodiments.
[0294] Fifth Embodiment
[0295] FIG. 23 is a view illustrating an interconnect substrate
according to a fifth embodiment of the present invention. In the
present embodiment, a substrate 400 includes an insulating section
(section formed of ceramic or a resin such as an epoxy resin or a
polyimide resin, for example) 402, and a conductive section
(section formed of a metal, for example) 404 which is formed
through the insulating section 402. The surface of the conductive
section 404 exposed from the insulating section 402 may be in the
shape of a land.
[0296] A first conductive layer 410 is formed over the insulating
section 402 and the conductive section 404 so that the fist
conductive layer 410 is electrically connected with the conductive
section 404. For example, a post 412 may be formed on the
conductive section 404, and the first conductive layer 410 may be
formed to pass over the post 412. The details described, in the
first to fourth embodiments are applied to the subsequent steps.
Specifically, insulating layers and conductive layers are stacked
on the first conductive layer 410 to form a high-density
interconnect structure.
[0297] As shown in FIG. 24, the semiconductor chip 420 is
electrically connected with pads 430. A semiconductor device is
manufactured in this manner. If necessary, a heat sink 440 may be
provided to the semiconductor chip 420. A filler metal 450 such as
a solder ball may be provided to the conductive section 404. In the
present embodiment, the effects described in the first embodiment
can also be achieved. The details described in other embodiments
may be applied to the present embodiment. The details described in
the present embodiment may be applied to other embodiments.
[0298] Sixth Embodiment
[0299] FIGS. 25A and 25B are views illustrating an interconnect
substrate according to a sixth embodiment of the present invention.
In the present embodiment, a first conductive layer 510 is formed
on a substrate (metal plate, glass substrate, or resist film) 500,
and insulating layers and conductive layers are stacked on the
first conductive layer 510 to form a high-density interconnect
structure, as shown in FIG. 25A. The details are the same as
described in the first to fifth embodiments.
[0300] As shown in FIG. 25B, the substrate 500 is removed from the
first conductive layer 510 (from the multilayer substrate including
the first conductive layer 510 in more detail). An interconnect
substrate is obtained in this manner. A semiconductor device can be
manufactured by mounting a semiconductor chip on the interconnect
substrate. In the present embodiment, the effects described in the
first embodiment can also be achieved. The details described in
other embodiments may be applied to the present embodiment. The
details descried in the present embodiment may be applied to other
embodiments.
[0301] Seventh Embodiment
[0302] FIGS. 26A to 26C are views illustrating a method of
manufacturing a semiconductor device according to a seventh
embodiment of the present invention. In the present embodiment, a
first conductive layer 610 is formed on a semiconductor wafer 600
on which a plurality of integrated circuits 602 are formed so that
the first conductive layer 610 is electrically connected with
electrodes 604 of the integrated circuits 602. Insulating layers
and conductive layers are stacked on the first conductive layer 610
to form a high density interconnect structure, as shown in FIG.
26A. The details are the same as described in the first to sixth
embodiments. A filler metal 620 such as a solder ball is optionally
provided.
[0303] The semiconductor wafer 600 is cut as shown in FIG. 26B,
whereby a semiconductor device is manufactured as shown in FIG.
26C. The semiconductor device includes a semiconductor chip 630, a
high-density interconnect structure which is formed by stacking
insulating layers and conductive layers on the semiconductor chip
630, and the filler metal 620. In the present embodiment, the
effects described in the first embodiment can also be achieved. The
details described in other embodiments may be applied to the
present embodiment. The details described in the present embodiment
may be applied to other embodiments.
[0304] Eighth Embodiment
[0305] FIGS. 27A and 27B are views illustrating a method of
manufacturing an electronic component which can be applied to the
embodiment of the present invention. An electronic component may be
formed on the surface on which a first conductive layer is formed,
an insulating layer, or a second insulating layer.
[0306] The method of manufacturing an electronic component
according to the present embodiment includes forming each of a
plurality of parts which make up one electric part by discharging
drops of a solvent containing fine particles of a material. As
shown in FIGS. 27A and 27B, fiat, second, and third layers 701,
702, and 703 are formed, for example. The first, second, and third
layers 701, 702, and 703 may be stacked or formed to be adjacent to
each other.
[0307] In the case of forming a capacitor, the first and third
layers 701 and 703 are formed, of a conductor and the second layer
702 is formed of an insulating material. In the case of forming the
first and third layers 701 and 703 by using gold, "Perfect Gold"
(manufactured by Vacuum Metallurgical Co., Ltd.) may be used. In
the case of forming the first and third layers 701 and 703 by using
silver, "Perfect Silver" (manufactured by Vacuum Metallurgical Co.,
Ltd.) may be used. As an insulating material for forming the second
layer 702, SiO.sub.2, Al.sub.2O.sub.3, dielectrics such as
SrTiO.sub.3, BaTiO.sub.3, and Pb(Zr,Ti)O.sub.3, and the like can be
given. As a solvent, PGMEA, cyclohexane, carbitol acetate, and the
like can be given. Glycerol, diethylene glycol, ethylene glycol, or
the like may optionally be added as a wetting agent or a binder. As
a fluid containing an insulating material, a polysilazane or a
metal alkoxide containing an insulating material may be used. In
his case, an insulating material may be formed by heating or a
chemical reaction. The width and length of the second layer 702 and
the dielectric constant of the insulating material are determined
depending on the capacitance of the capacitor to be formed. The
capacitance of the capacitor is determined depending on the areas
of the first and third layers 701 and 703 which become common
electrodes, the distance between the first and third layers 701 and
703, and the dielectric constant of the second layer 702. In the
case of increasing the thickness of the first layer 701, second
layer 702, or third layer 703, layers may be stacked by forming a
solidified layer of a fluid and discharging the same fluid onto the
solidified layer and solidifying the fluid.
[0308] At least one of the first, second, and third layers 701,
702, and 703 may be a resistor. As a resistance material, a mixture
of conductive powder and insulating powder. Ni--Cr, Cr--SiO,
Cr--MgF, Au--SiO.sub.2, AuGgF, PtTa.sub.2O.sub.5,
AnTa.sub.2O.sub.5Ta.sub.2, Cr.sub.3Si, TaSi.sub.2, and the like can
be given. As a solvent, PGMEA cyclohexane, carbitol acetate, and
the like can be given. Glycerol, diethylene glycol, ethylene
glycol, or the like may optionally be added as a wetting agent or a
binder. As a fluid containing an insulating material, a
polysilazane or a metal alkoxide containing an insulating material
may be used. In this case, an insulating material may be formed by
heating or a chemical reaction. The resistance material is
determined depending on the resistance value of the resistor to be
formed. The width, height, and length of the resistance film are
determined depending on the resistance value of the resistor to be
formed. This is because the resistance value of the resistor is in
proportion to the length and is in inverse proportion to the
cross-sectional area.
[0309] A part of the first conductive layer 20 described in the
first embodiment and the like may be formed by using a resistance
material. A diode and a transistor may be formed. In this case, the
first, second, and third layers 701, 702, and 703 are formed by
discharging drops of a solvent containing fine particles of a
semiconductor material.
[0310] FIG. 28 shows a circuit board 1000 on which a semiconductor
device 1 described in any of the above embodiments is mounted.
FIGS. 29 and 30 respectively show a notebook-type personal computer
2000 and a portable telephone 3000 as examples of electronic
equipment including the semiconductor device.
[0311] The present invention is not limited to the above described
embodiments. Various modifications and variations are possible. For
example, the present invention includes configurations essentially
the same as the configurations described in the embodiments (for
example, configurations having the same function, method, and
results, or configurations having the same object and results). The
present invention includes configurations in which any unessential
part of the configuration described in the embodiments is replaced.
The present invention includes configurations having the same
effects or achieving the same object as the configurations
described in the embodiments. The present invention includes
configurations in which conventional technology is added to the
configurations described in the embodiments.
* * * * *