U.S. patent application number 10/752000 was filed with the patent office on 2004-07-15 for thin film circuit.
This patent application is currently assigned to Semiconductor Energy Laboratory Co., Ltd, a Japan corporation. Invention is credited to Koyama, Jun, Ohtani, Hisashi, Yamazaki, Shunpei.
Application Number | 20040135174 10/752000 |
Document ID | / |
Family ID | 18461992 |
Filed Date | 2004-07-15 |
United States Patent
Application |
20040135174 |
Kind Code |
A1 |
Yamazaki, Shunpei ; et
al. |
July 15, 2004 |
Thin film circuit
Abstract
A practical operational amplifier circuit is formed using thin
film transistors. An operational amplifier circuit is formed by
thin film transistors formed on a quartz substrate wherein 90% or
more of n-channel type thin film transistors have mobility at a
value of 260 cm.sup.2/Vs or more and wherein 90% or more of
p-channel type thin film transistors have mobility at a value of
150 cm.sup.2/Vs or more. The thin film transistors have active
layers formed using a crystalline silicon film fabricated using a
metal element that promoted crystallization of silicon. The
crystalline silicon film is a collection of a multiplicity of
elongate crystal structures extending in a certain direction, and
the above-described characteristics can be achieved by matching the
extending direction and the moving direction of carriers.
Inventors: |
Yamazaki, Shunpei; (Tokyo,
JP) ; Koyama, Jun; (Kanagawa, JP) ; Ohtani,
Hisashi; (Kanagawa, JP) |
Correspondence
Address: |
FISH & RICHARDSON P.C.
1425 K STREET, N.W.
11TH FLOOR
WASHINGTON
DC
20005-3500
US
|
Assignee: |
Semiconductor Energy Laboratory
Co., Ltd, a Japan corporation
|
Family ID: |
18461992 |
Appl. No.: |
10/752000 |
Filed: |
January 7, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10752000 |
Jan 7, 2004 |
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09946723 |
Sep 4, 2001 |
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6677611 |
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09946723 |
Sep 4, 2001 |
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08998791 |
Dec 29, 1997 |
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6331718 |
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Current U.S.
Class: |
257/200 ;
257/E21.413; 257/E27.111; 257/E29.003; 257/E29.278;
257/E29.293 |
Current CPC
Class: |
H01L 29/66757 20130101;
H01L 29/04 20130101; H01L 29/78675 20130101; H01L 29/78621
20130101; H01L 21/02672 20130101; H01L 21/02532 20130101; H01L
27/12 20130101; H01L 27/1277 20130101 |
Class at
Publication: |
257/200 |
International
Class: |
H01L 031/109 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 30, 1996 |
JP |
8-358957 |
Claims
What is claimed is:
1. A semiconductor device comprising: n-channel type thin film
transistors provided over an insulating surface; p-channel type
thin film transistors provided over said insulating surface; and
operational amplifier circuits provided over said insulating
surface and comprising said n-channel type thin film transistors
and said p-channel type thin film transistors, wherein cumulative
distribution of mobilities of said n-channel type thin film
transistors is 90% or more at 260 cm.sup.2/Vs; and wherein
cumulative distribution of mobilities of said p-channel type thin
film transistors is 90% or more at 150 cm.sup.2/Vs.
2. A device according to claim 1 wherein said n-channel type thin
film transistors and said p-channel type thin film transistors are
provided over a quartz substrate.
3. A device according to claim 1 wherein an average S-value of said
p-channel type thin film transistors and said n-channel type thin
film transistors is 100 mV/dec or less.
4. A device according to claim 1 wherein each of said n-channel
type thin film transistors comprises a source region and a drain
region which are doped with phosphorus.
5. A device according to claim 1 wherein each of said p-channel
type thin film transistors comprises a source region and a drain
region which are doped with boron.
6. A device according to claim 1 wherein each of said p-channel
type thin film transistors and said n-channel type thin film
transistors has a channel length longer than a length of a lightly
doped drain thereof.
7. A semiconductor device comprising: n-channel type thin film
transistors provided over an insulating surface; p-channel type
thin film transistors provided over said insulating surface; and
differential circuits provided over said insulating surface and
comprising said n-channel type thin film transistors and said
p-channel type thin film transistors, wherein cumulative
distribution of mobilities of said n-channel type thin film
transistors is 90% or more at 260 cm.sup.2/Vs; and wherein
cumulative distribution of mobilities of said p-channel type thin
film transistors is 90% or more at 150 cm.sup.2/Vs.
8. A device according to claim 7 wherein a part of said
differential circuits constitutes an operational amplifier.
9. A device according to claim 7 wherein said n-channel type thin
film transistors and said p-channel type thin film transistors are
provided over a quartz substrate.
10. A device according to claim 7 wherein an average S-value of
said p-channel type thin film transistors and said n-channel type
thin film transistors is 100 mV/dec or less.
11. A device according to claim 7 wherein each of said n-channel
type thin film transistors comprises a source region and a drain
region which are doped with phosphorus.
12. A device according to claim 7 wherein each of said p-channel
type thin film transistors comprises a source region and a drain
region which are doped with boron.
13. A device according to claim 7 wherein each of said p-channel
type thin film transistors and said n-channel type thin film
transistors has a channel length longer than a length of a lightly
doped drain thereof.
14. A semiconductor device comprising: n-channel type thin film
transistors provided over an insulating surface; p-channel type
thin film transistors provided over said insulating surface; and
operational amplifier circuits provided over said insulating
surface and comprising said n-channel type thin film transistors
and said p-channel type thin film transistors, wherein cumulative
distribution of mobilities of said n-channel type thin film
transistors is 90% or more at 260 cm.sup.2/Vs, wherein cumulative
distribution of mobilities of said p-channel type thin film
transistors is 90% or more at 150 cm.sup.2/Vs, and wherein a
channel formation region of each of said n-channel type thin film
transistors and said p-channel type thin film transistors comprises
a columnar crystal extending in a direction which is aligned with a
direction of a moving direction of carriers in said channel
formation region.
15. A device according to claim 14 wherein said columnar crystal
has a width which is constant within a dimension of 0.2 .mu.m or
less.
16. A device according to claim 14 wherein said n-channel type thin
film transistors and said p-channel type thin film transistors are
provided over a quartz substrate.
17. A device according to claim 14 wherein an average S-value of
said p-channel type thin film transistors and said n-channel type
thin film transistors is 100 mV/dec or less.
18. A device according to claim 14 wherein each of said n-channel
type thin film transistors comprises a source region and a drain
region which are doped with phosphorus.
19. A device according to claim 14 wherein each of said p-channel
type thin film transistors comprises a source region and a drain
region which are doped with boron.
20. A device according to claim 14 wherein each of said p-channel
type thin film transistors and said n-channel type thin film
transistors has a channel length longer than a length of a lightly
doped drain thereof.
21. A semiconductor device comprising: n-channel type thin film
transistors provided over an insulating surface; p-channel type
thin film transistors provided over said insulating surface; and
differential circuits provided over said insulating surface and
comprising said n-channel type thin film transistors and said
p-channel type thin film transistors, wherein cumulative
distribution of mobilities of said n-channel type thin film
transistors is 90% or more at 260 cm.sup.2/Vs, wherein cumulative
distribution of mobilities of said p-channel type thin film
transistors is 90% or more at 150 cm.sup.2/Vs, and wherein a
channel formation region of each of said n-channel type thin film
transistors and said p-channel type thin film transistors comprises
a columnar crystal extending in a direction which is aligned with a
direction of a moving direction of carriers in said channel
formation region.
22. A device according to claim 21 wherein a part of said
differential circuits constitutes an operational amplifier.
23. A device according to claim 21 wherein said n-channel type thin
film transistors and said p-channel type thin film transistors are
provided over a quartz substrate.
24. A device according to claim 21 wherein an average S-value of
said p-channel type thin film transistors and said n-channel type
thin film transistors is 100 mV/dec or less.
25. A device according to claim 21 wherein each of said n-channel
type thin film transistors comprises a source region and a drain
region which are doped with phosphorus.
26. A device according to claim 21 wherein each of said p-channel
type thin film transistors comprises a source region and a drain
region which are doped with boron.
27. A device according to claim 21 wherein each of said p-channel
type thin film transistors and said n-channel type thin film
transistors has a channel length longer than a length of a lightly
doped drain thereof.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor circuit
utilizing a crystalline silicon film formed on a quartz substrate
or the like and, more particularly, to a semiconductor circuit
having the function of an operational amplifier.
[0003] 2. Description of the Related Art
[0004] Recently, researches are being carried out on techniques for
forming semiconductor devices utilizing a crystalline silicon film
on a quartz substrate in an integrated manner. A typical example of
such techniques is a technique for providing an active matrix
circuit and a peripheral driving circuit for driving the same
circuit on a single quartz substrate or glass substrate.
[0005] The required circuit configurations include active matrix
circuits, shift register circuits and buffer circuits.
[0006] An active layer of a thin film transistor forming a part of
a circuit is formed using a crystalline silicon film. A crystalline
silicon film can be fabricated by forming an amorphous silicon film
on a substrate and then heating the same or irradiating the same
with laser beams or performing both to anneal the same.
[0007] A thin film transistor having an active layer formed by a
crystalline silicon film is more excellent in characteristics such
as mobility than those having an active layer formed by an
amorphous silicon film.
[0008] There is a need for higher levels of integration and higher
performance also for circuits formed using thin film
transistors.
[0009] Recently, it is contemplated to use thin film transistors to
configure, on a substrate, not only logic circuits such as shift
registers but also circuits having computing functions such as
operational amplifiers which have conventionally been externally
attached to a substrate.
[0010] Operational amplifier circuits have been generally
configured using a single crystal silicon wafer.
[0011] An operational amplifier is basically comprised of a
differential amplifier circuit. A differential amplifier circuit is
formed by combining two transistors having similar
characteristics.
[0012] In the case of a differential amplifier circuit, a change in
temperature or power supply voltage affect the two transistors
simultaneously. Therefore, a change in temperature or power supply
voltage does not affect the output of the same.
[0013] In order for this, the two transistors forming the
differential amplifier circuit must have similar
characteristics.
[0014] In practice, since it is difficult to provide two
transistors having completely identical characteristics, efforts
are being made toward manufacturing techniques to provide
transistors as much similar to each other as possible in their
characteristics.
[0015] Thin film transistors utilizing a crystalline silicon film
have mobility lower than that of MOS transistors fabricated using a
single crystal silicon wafer. Further, they have a higher level of
variation in characteristics.
[0016] For this reason, it has been difficult in practice to form
an operation amplifier circuit using such thin film
transistors.
[0017] The present invention solves this problem. Specifically, it
is an object of the invention to form a practical operational
amplifier circuit using thin film transistors.
SUMMARY OF THE INVENTION
[0018] According to an aspect of the invention, there is provided a
group of operational amplifier circuits constituted by thin film
transistors formed on an insulating surface characterized in
that:
[0019] the operational amplifier circuits comprise a combination of
at least n-channel type thin film transistors and p-channel type
thin film transistors;
[0020] 90% or more of the n-channel type thin film transistors have
mobility at a value of 260 cm.sup.2/Vs or more; and
[0021] 90% or more of the p-channel type thin film transistors have
mobility at a value of 150/Vs or more.
[0022] The above-described structure is formed on an insulating
substrate represented by a quartz substrate. The use of a substrate
having insulating properties makes it possible to configure a
circuit suitable for operations at high speeds because it
eliminates effects of capacitance of a substrate. According to
another aspect of the invention, an active layer of a thin film
transistor is formed by a crystalline silicon film having a
structure in which a multiplicity of columnar crystal structures
extend in a direction that matches the moving direction of
carriers.
[0023] According to the invention, since a thin film semiconductor
is used for the active layer, the source and drain regions can be
activated (after doping) by irradiating them with laser beams or
intense beams.
[0024] This allows the use of aluminum which is a low-resistance
material or a material mainly composed of aluminum for the gate
electrode to improve adaptability to high speed operations.
[0025] Further, since the unique crystal structure suppresses the
short-channel effect, predetermined operational performance can be
achieved with dimensions larger than dimensions indicated by
conventional scaling rules.
[0026] For example, when the above-described crystalline silicon
film is used, a gate insulation film having a thickness on the
order of 500 .ANG. provides characteristics that have been
available with only a gate insulation film having a thickness on
the order of 200 .ANG. according to conventional scaling rules.
[0027] It is technically and economically difficult to form a thin
gate insulation film having preferable interface characteristics,
no pin hole and a high withstand voltage over a large surface
area.
[0028] From this point of view, it is advantageous to achieve
predetermined characteristics free of limitations placed by
conventional scaling rules.
[0029] In addition, the average S-value of thin film transistors
utilizing a crystalline silicon film having the above-described
unique crystal structure can be 100 mV/dec or less for either of p-
and n-channel type thin film transistors even when a multiplicity
of the same are formed on a substrate.
[0030] The S-value of a TFT fabricated using a general high
temperature process (a general term that refers to processes for
fabricating a TFT on a quartz substrate using an annealing step at
about 1000.degree. C.) is about 200 mV/dec or more when it is an
n-channel type TFT and about 350 mV/dec or more when it is a
p-channel type TFT.
[0031] The S-value of a TFT fabricated using a low temperature
process (a general term that refers to processes for fabricating a
TFT on a quartz substrate using a laser annealing step) is worse
than that of a TFT fabricated using a high temperature process.
[0032] According to another aspect of the invention, there is
provided a group of operational amplifier circuits constituted by
thin film transistors formed on an insulating surface characterized
in that:
[0033] the operational amplifier circuits comprise a combination of
at least n-channel type thin film transistors and p-channel type
thin film transistors; and
[0034] active layers of the thin film transistors comprise a
crystalline silicon film having a structure wherein a multiplicity
of columnar crystal structures extend in a direction that matches
the moving direction of carriers.
BRIEF DESCRIPTION OF THE DRAWINGS
[0035] FIG. 1 is a diagram showing an equivalent circuit of an
operational amplifier.
[0036] FIG. 2 illustrates the arrangement of patterns on an
operational amplifier constituted by thin film transistors formed
on a quartz substrate.
[0037] FIG. 3 is a sectional view taken along the line A-A' in FIG.
2.
[0038] FIG. 4 is a sectional view taken along the line B-B' in FIG.
2.
[0039] FIG. 5 illustrates the distribution of mobility of n-channel
type thin film transistors integrated on the same substrate.
[0040] FIG. 6 illustrates the distribution of mobility of p-channel
type thin film transistors integrated on the same substrate.
[0041] FIG. 7 illustrates the distribution of thresholds of
n-channel type thin film transistors integrated on the same
substrate.
[0042] FIGS. 8A through 8D illustrate steps for fabricating thin
film transistors.
[0043] FIG. 9 illustrates a schematic configuration of bottom-gate
type thin film transistors.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENT
[0044] An active layer is formed by a crystalline silicon film
having a structure wherein a multiplicity of crystal structures
extending in a certain direction are arranged in parallel, and the
direction in which the crystal structures extend is aligned with
the direction of the moving direction of carriers. This makes it
possible to provide advantages that can not be achieved by
conventional devices utilizing single crystal semiconductors and
polycrystalline semiconductors.
[0045] The short channel effect is less likely to occur on such a
crystalline silicon film formed by a multiplicity of crystal
structures extending in the form of columns in a certain direction
even if the dimension of a channel is reduced because the movement
of carriers is regulated in the direction in which they extend.
[0046] The reason is that the presence of a multiplicity of
elongate and substantially monocrystalline regions (columnar
regions) extending in parallel in the channel region suppresses the
expansion of a depletion layer in the channel between the source
and drain regions.
[0047] In normal IC processing, efforts toward a finer structure
result in a significant short channel effect, and measures must be
taken to dope or diffuse impurities in the vicinity of a channel in
order to suppress this (which results in a very complicated
structure). This increases technical and economical
difficulties.
[0048] However, a crystalline silicon film having a unique crystal
structure as described above is characterized in that it suppresses
the short channel effect without any complicated structure because
of the uniqueness of the crystal structure of itself.
[0049] Thin film transistors obtained using the same can be free of
variation in characteristics in a plane of the substrate as shown
in FIGS. 5 through 7.
[0050] Meanwhile, crystalline silicon films provided on a glass
substrate or quartz substrate using a conventional high temperature
process or low temperature process have had the so-called
polycrystalline structure which is an aggregation of a multiplicity
of crystal grains (particularly those having no anisotropism).
[0051] In this case, it becomes more difficult to control the state
of crystal interfaces (particularly, the direction in which they
extend and the quantity thereof) present in a channel as the device
structure becomes finer.
[0052] Specifically, the quantity and direction of crystal
interfaces that exist in a channel vary from device to device with
decreasing size of the channel, which results in variation in
device characteristics.
[0053] However, crystalline silicon films obtained according to the
method shown in FIGS. 8A through 8D have crystal grain boundaries
aligned in terms of the direction thereof and have widths which are
constant to some degree within a dimension of about 0.2 .mu.m or
less. Therefore, they are less likely to cause variation of
characteristics from device to device due to the presence of the
crystal grain boundaries when the moving direction of carriers
(especially in channels) is matched with the direction in which the
crystal interfaces extend.
[0054] The reason is that the state of the crystal structure in the
channel region is similar in every device.
[0055] FIG. 1 shows an internal equivalent circuit of an
operational amplifier formed by thin film transistors according to
the present embodiment. FIG. 2 shows a mask pattern for the
operational amplifier circuit represented by the equivalent circuit
in FIG. 1. 201 designates a positive input. 202 designates a
negative input. 203 designates a nickel-added region. 204
designates wiring on a first layer. 205 designates wiring on a
second layer.
[0056] FIG. 3 shows a sectional view taken along the line A-A' in
FIG. 2. FIG. 4 shows a sectional view taken along the line B-B' in
FIG. 2.
[0057] In this embodiment, nickel is introduced into the elongate
region specified as the nickel-added region to cause
crystallization of an amorphous silicon film to start there,
thereby forming thin film transistors using this region.
[0058] In the circuit configuration shown in FIG. 1, it is
important that transistors Tr.sub.8 and Tr.sub.4 forming a
differential circuit at the input portion have similar
characteristics. 101 designates bias, and 102 designates
output.
[0059] This embodiment has a pattern arrangement such that active
layers forming the transistors Tr.sub.8 and Tr.sub.4 are arranged
in positions at the same distance from the nickel-added region.
This suppresses variation in characteristics that otherwise occurs
due to a difference in the distance of crystal growth.
[0060] Referring to active layers forming transistors Tr.sub.6 and
Tr.sub.7, the active layers are formed in positions at different
distances of crystal growth (distances from the nickel-added
region) because they are formed utilizing crystal growth from the
same nickel-added region. This can result in a very slight
difference in characteristics between the transistors Tr.sub.6 and
Tr.sub.7, but such a difference in characteristics between the two
transistors will not create any serious problem in this circuit
configuration.
[0061] In this embodiment, thin film transistors having the
distribution of characteristics in a plane of the substrate as
shown in FIGS. 5 through 7 are utilized.
[0062] While the characteristics of a single thin film transistor
alone have been a matter of concern in the prior art, in the case
of a configuration of an operational amplifier circuit as shown in
FIG. 1, what is important is characteristics on a collective basis
(in other words, the distribution of characteristics or the
distribution of variation in characteristics).
[0063] The thin film transistors are formed on a quartz substrate
according to a method of fabrication to be described later.
[0064] FIG. 5 shows the distribution of mobility of n-channel type
thin film transistors. FIG. 6 shows the distribution of mobility of
p-channel type thin film transistors. FIG. 7 shows the distribution
of V.sub.th (threshold voltages) of the n-channel thin film
transistors.
[0065] FIGS. 5 through 7 show variation in the characteristics of
TFTs on a single substrate. The ordinate axes of FIGS. 5 through 7
indicate ratios of presence in terms of percentage. The TFTs have a
single gate structure fabricated according the method of
fabrication to be described later wherein the channel length is 8
.mu.m and the channel width is 8 .mu.m.
[0066] FIG. 5 shows that 90% or more of the n-channel type TFTs
formed on the same substrate have mobility of 260 cm.sup.2/Vs or
more.
[0067] FIG. 6 shows that 90% or more of the resultant p-channel
type TFTs have mobility of 150 cm.sup.2/Vs or more.
[0068] The above description means that 90 TFTs or more out of 100
TFTs which have been arbitrarily selected have the mobility as
described above on average.
[0069] When an integrated circuit such as an operational amplifier
is configured, it is important to use a group of elements having
small variation in characteristics as shown in FIGS. 5 through
7.
[0070] For example, variation of V.sub.th (threshold voltage) is an
important consideration when using a power supply voltage for
driving of 5 V or 3.3 V or 1.5 V which will be more frequently used
in the future.
[0071] [Method of Fabricating Thin Film Transistors]
[0072] FIGS. 8A through 8D schematically show steps for fabricating
thin film transistors used in an operational amplifier circuit
having a pattern arrangement as shown in FIG. 2.
[0073] First, an amorphous silicon film 802 is formed on a quartz
substrate 801 to a thickness of 500 .ANG. using low pressure
thermal CVD. It is important that the quartz substrate used has a
sufficiently smooth surface.
[0074] The thickness of the amorphous silicon film is preferably in
the range from about 100 .ANG. to about 1000 .ANG.. The reason is
that the thickness of an active layer is suppressed to some degree
in order to achieve an annealing effect by irradiation with laser
beams performed at a subsequent step of activating source and drain
regions.
[0075] After the amorphous silicon film 802 is formed, a mask
indicated by 803 is formed by a silicon oxide film which is formed
using plasma CVD. This mask is formed with a hole indicated by 805
to provide a structure wherein the amorphous silicon film 802 is
exposed in this region.
[0076] The hole 805 extends in the direction perpendicular to the
plane of the drawing (this hole corresponds to the nickel-added
region 203 in FIG. 2).
[0077] After the mask 803 is formed, a solution of nickel acetate
containing nickel of 10 ppm by weight is applied using spin
coating. Thus, a state as indicated by 804 is realized wherein
nickel is retained in contact with the surface (FIG. 8A).
[0078] While a method of introducing nickel utilizing a solution
has been described here, nickel may be introduced on to the surface
of the amorphous silicon film using methods such as CVD,
sputtering, plasma processing and gas adsorption.
[0079] Further, as a method of introducing nickel in a more
accurately controlled quantity and position, a method based on ion
implantation can be employed.
[0080] Instead of nickel, an element selected from among Fe, Co,
Ru, Rh, Pd, Os, Ir, Pt, Cu and Au may be used. Such elements have a
function of promoting crystallization of silicon.
[0081] Next, a heating process is performed in a nitrogen
atmosphere for eight hours at 600.degree. C. At this step, crystal
growth proceeds in a direction in parallel with the substrate as
indicated by 800.
[0082] After the crystallization achieved by this heating process,
there are defects in the film in a high density and the uniqueness
of the crystal structure to be detailed below is still
insignificant (FIG. 8A).
[0083] The above-described heating process may be performed within
a temperature range from 450.degree. C. to the temperature that the
substrate can withstand (about 1100.degree. C. in the case of a
quartz substrate).
[0084] Next, the mask 803 is removed. A heating process is then
performed for 20 minutes at 950.degree. C. in an oxygen atmosphere
containing 3% HCl by volume. This step forms a thermal oxidation
film having a thickness of 200 .ANG. on the surface of the silicon
film. The thickness of the silicon film is reduced to 400 .ANG. at
this step.
[0085] This step of heating process is important. This step of
heating process anneals the crystalline silicon film and removes
nickel from the film. This heating process provides a unique
crystalline silicon film formed by a multiplicity of columnar
crystal structures extending in a certain direction in the form of
columns having widths in the range from about 0.5 .mu.m to about 2
.mu.m.
[0086] The formation of the thermal oxidation film provides two
effects. One of the effects is a reduction of nickel in the silicon
film as a result of absorption of nickel into the thermal oxidation
film.
[0087] The other is an effect wherein silicon atoms which have been
redundant or unstably bonded are consumed as the thermal oxidation
film is formed to reduce defects greatly and consequently to
improve crystallinity.
[0088] Then, the thermal oxidation film thus formed is removed.
Since this thermal oxidation film contains nickel in a relatively
high density, the removal of the thermal oxidation film makes it
possible to eventually prevent nickel from adversely affecting the
device characteristics.
[0089] When the 400 .ANG. thick silicon film is thus obtained, it
is patterned to form active layers of thin film transistors. FIG.
8B shows active layers indicated by 806 and 807.
[0090] It is important here to set the direction in which the
sources and drains are connected or the moving direction of
carriers in the channels such that it matches the direction of the
above-described direction of crystal growth (which coincides with
the direction in which the above-described columnar crystal
structures extend).
[0091] In FIG. 8B, 806 designates an active layer of a p-channel
type thin film transistor, and 807 designates an active layer of an
n-channel type thin film transistor.
[0092] Although steps for fabricating only two thin film
transistors are illustrated here, in practice, a multiplicity of
nickel-added regions as illustrated in FIG. 2 are provided on the
substrate to form a multiplicity of thin film transistors
simultaneously.
[0093] After the active layers are formed, plasma CVD is performed
to form a silicon oxide film having a thickness of 300 .ANG. which
is to serve as a part of a gate insulation film. Further, the
second thermal oxidation is carried out in an oxygen atmosphere
containing 3% HCl by volume to form a thermal oxidation film to a
thickness of 300 .ANG.. This provides a gate insulation film having
a thickness of 600 .ANG. consisting of the CVD-oxidated silicon
film and the thermal oxidation film. As a result of this second
formation of a thermal oxidation film, the thickness of the active
layers is reduced to 250 .ANG..
[0094] Next, gate electrodes 808 and 809 made of aluminum are
formed. After the gate electrodes are formed, anodization is
carried out to first form porous anodic oxide films 810 and 811.
Further, the second anodization is carried out to form anodic oxide
films 812 and 813 having denser film properties. The difference in
the properties of the anodic oxide films may be selected depending
on the type of electrolyte used.
[0095] Next, the exposed gate insulation film is removed. FIG. 8B
shows gate insulation films 814 and 815 left thereon.
[0096] In this state, doping for providing conductivity types is
carried out using plasma doping. Here, doping of B (boron) is
carried out first with the region to become an n-channel type thin
film transistor masked with a resist mask. Then, doping of P
(phosphorus) is carried out with the region to become a p-channel
type thin film transistor masked with a resist mask.
[0097] The doping at this step is performed under conditions for
forming source and drain regions. At this step, a source region 816
and a drain region 817 of a p-channel type TFT and a source region
819 and a drain region 818 of an n-channel type TFT are formed on a
self-alignment basis.
[0098] Thus, the state shown in FIG. 8B is realized. Next, the
porous anodic oxide films 810 and 811 are removed.
[0099] Next, the second doping is carried out under conditions for
light doping. At this step, low density impurity regions 820, 821,
823 and 824 are formed on a self-alignment basis. Further, channel
formation regions 825 and 826 are formed on a self-alignment
basis.
[0100] The low density impurity regions toward the drain regions
become regions referred to as LDDs (lightly doped drains).
[0101] After the doping, laser beams are projected to activate the
doped elements and to anneal damage on the active layers caused by
the doping. This step may be performed using methods that employ
irradiation with ultraviolet beams and infrared beams.
[0102] Next, a silicon nitride film 827 as a layer insulation film
is formed using plasma CVD to a thickness of 1500 .ANG., and a
layer insulation film 828 made of polyimide resin is further
formed. The use of resin for the layer insulation film allows the
surface thereof to be planarized.
[0103] In addition to polyimide resin, it is possible to use
polyamide resin, polyimideamide resin, acrylic resin, epoxy resin
or the like.
[0104] Next, contact holes are formed to form a source electrode
(and source wiring) 829 and a drain electrode (and drain wiring)
830 of the p-channel type TFT. Further, there is formed a source
electrode (and source wiring) 832 and a drain electrode (and drain
wiring) 831 of the n-channel type TFT.
[0105] There is thus provided a configuration wherein a p-channel
type thin film transistor and an n-channel type thin film
transistor are integrated.
[0106] According to the fabrication steps described here, it is
possible to provide thin film transistors having excellent
characteristics as shown in FIGS. 5 through 7 with less variation
of characteristics by using a set of a multiplicity of columnar
crystal structures extending in parallel in a certain direction as
active layers.
[0107] Referring further to the characteristics, both of p- and
n-channel type thin film transistors can be provided with S-values
of 100 mV/dec or less on average.
[0108] The use of such thin film transistors makes it possible to
configure an operational amplifier circuit as shown in FIGS. 1 and
2.
[0109] [Another Configuration of Thin Film Transistor]
[0110] FIG. 9 shows another form of thin film transistors to which
the present invention can be applied.
[0111] The thin film transistor shown in FIG. 9 is a bottom gate
type thin film transistor and has a structure in which gate
electrodes 902 and 903 are formed on a quartz substrate 901; a gate
insulation film 904 is further formed; and an active layer is
formed thereon.
[0112] In the configuration shown in FIG. 9, the active layer must
be formed after forming the gate electrodes and gate insulation
film. Therefore, the active layer is formed in accordance with the
above-described steps for fabricating thin film transistors shown
in FIG. 8 after the gate insulation film is formed.
[0113] [Still Another Configuration of Thin Film Transistor]
[0114] The steps for fabricating thin film transistors shown in
FIGS. 8A through 8D represent an example wherein aluminum is used
for gate electrodes. Tantalum may be used instead of aluminum.
Tantalum can also be anodized and can be used for fabrication of
thin film transistors according to the fabrication steps shown in
FIGS. 8A through 8D.
[0115] Further, polysilicon and silicide having conductivity types
can be used for gate electrodes. In this case, however, it is not
possible to obtain the advantage of low resistance which is
available when aluminum is used.
[0116] The use of present invention makes it possible to fabricate
a practical operational amplifier circuit using thin film
transistors.
[0117] Although the present invention and its advantages have been
described in detail, it should be understood that various changes,
substitutions and alterations can be made herein without departing
from the spirit and scope of the invention as defined by the
appended claims.
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