U.S. patent application number 10/682838 was filed with the patent office on 2004-07-08 for semiconductor device and manufacturing method thereof.
Invention is credited to Nakamura, Makiko.
Application Number | 20040130028 10/682838 |
Document ID | / |
Family ID | 32451339 |
Filed Date | 2004-07-08 |
United States Patent
Application |
20040130028 |
Kind Code |
A1 |
Nakamura, Makiko |
July 8, 2004 |
Semiconductor device and manufacturing method thereof
Abstract
An adhesion layer for causing a plug for electrically connecting
a lower wiring and an upper wiring opposite to each other with an
interlayer insulating film interposed therebetween to adhere to the
interlayer insulating film is formed within a through hole for
forming the plug, based on a predetermined aspect ratio represented
by a ratio of a depth dimension of the through hole to a diameter
dimension of the through hole.
Inventors: |
Nakamura, Makiko; (Tokyo,
JP) |
Correspondence
Address: |
VOLENTINE FRANCOS, P.L.L.C.
Suite 150
12200 Sunrise Valley Drive
Reston
VA
20191
US
|
Family ID: |
32451339 |
Appl. No.: |
10/682838 |
Filed: |
October 10, 2003 |
Current U.S.
Class: |
257/758 ;
257/E23.145; 257/E23.16 |
Current CPC
Class: |
H01L 2924/0002 20130101;
H01L 23/53223 20130101; H01L 2924/0002 20130101; H01L 23/5226
20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/758 |
International
Class: |
H01L 023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 18, 2002 |
JP |
303670/2002 |
Claims
What is claimed is:
1. A semiconductor device comprising: a lower wiring and an upper
wiring opposite to each other via a through hole defined in an
interlayer insulating film; a plug for electrically connecting the
lower wiring and the upper wiring to each other within the through
hole; and an adhesion layer for causing the plug to adhere to the
interlayer insulating film within the through hole, wherein the
adhesion layer is formed by sputtering based on a predetermined
aspect ratio indicated by a ratio of a depth dimension of the
through hole to a diameter dimension thereof.
2. The semiconductor device according to claim 1, wherein the
adhesion layer lying within the through hole is formed only on a
sidewall of the through hole.
3. The semiconductor device according to claim 1, wherein a
thickness dimension of the adhesion layer on the lower wiring is
formed to a thickness dimension which causes gas having corrosion
behavior to be penetrable.
4. The semiconductor device according to claim 1, wherein each of
the lower wiring and the upper wiring is a laminated structure
wherein a cap metal layer is provided on an aluminum alloy
layer.
5. The semiconductor device according to claim 4, wherein each of
the lower wiring and the upper wiring has a high melting-point
metal layer provided below the aluminum alloy layer.
6. The semiconductor device according to claim 4, wherein the
aluminum alloy layer is an alloy made of aluminum and copper.
7. The semiconductor device according to claim 4, wherein the cap
metal layer is formed of a laminated layer of titanium nitride and
titanium, or a layer made of titanium nitride alone.
8. The semiconductor device according to claim 5, wherein the high
melting-point metal layer is formed of a laminated layer of
titanium nitride and titanium, or a layer made of titanium nitride
alone.
9. The semiconductor device according to claim 1, wherein a linear
dimension of the lower wiring is formed long.
10. The semiconductor device according to claim 1, wherein the
lower wiring is a first wiring on a semiconductor substrate having
a semiconductor element.
11. The semiconductor device according to claim 1, wherein the
lower wiring is a wiring held in a floating state of being not
directly connected to the semiconductor substrate having the
semiconductor element.
12. The semiconductor device according to claim 1, wherein the plug
is a tungsten plug.
13. The semiconductor device according to claim 1, wherein the
adhesion layer is formed using titanium nitride.
14. The semiconductor device according to claim 1, wherein the
adhesion layer is formed such that the relationship between a
thickness dimension of a material deposited on the interlayer
insulating film by said sputtering and the aspect ratio results in
the fact that when the aspect ratio is over 2.5 and less than 3,
the thickness dimension of the deposited material ranges from over
7.5 nm to under 10 nm, when the aspect ratio is over 3 and less
than 3.5, the thickness dimension of the deposited material ranges
from over 7.5 nm to under 20 nm, and when the aspect ratio is over
3.5 and less than 4, the thickness dimension of the deposited
material ranges from over 7.5 nm to under 30 nm.
15. The semiconductor device according to claim 1, wherein the
adhesion layer is formed by sputtering having directivity, and
sputtering is effected on an object to be sputtered from every
direction at an incident angle of 5.degree. or more.
16. The semiconductor device according to claim 15, wherein the
adhesion layer is formed such that the relationship between the
aspect ratio and the incident angle results in the fact that the
incident angle at the time that the aspect ratio is over 1 and less
than 1.5, is 45.degree. or more, the incident angle at the time
that the aspect ratio is over 1.5 and less than 2, is 26.degree. or
more, and the incident angle at the time that the aspect ratio is
over 2.5 and less than 3, is 18.degree. or more.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention:
[0002] The present invention relates to a semiconductor device and
a method of manufacturing the same, and more specifically to a
semiconductor device in which wiring is carried out in multilayered
form, and a manufacturing method thereof.
[0003] 2. Description of the Related Art:
[0004] A highly integrated semiconductor device has been formed
with wirings provided in multilayered form. The semiconductor
device includes wirings provided in multilayered form with an
interlayer insulating film low in dielectric constant interposed
therebetween. The wirings of the respective layers are electrically
connected to each other via a through hole defined in the
interlayer insulating film. Such a conventional semiconductor
device 200 will be explained using FIG. 10.
[0005] The semiconductor device 200 includes a semiconductor
substrate 211 formed with an unillustrated semiconductor element,
an insulating film 212 formed on the substrate 211, a high
melting-point metal layer 213 formed on the insulating film 212, a
lower wiring 216 made up of an aluminum alloy layer 214 made of
aluminum and copper, which is formed on the high melting-point
metal layer 213, and a cap metal layer 215 formed on the alloy
layer 214, an interlayer insulating film 217 formed on the
insulating film 212 so as to cover the lower wiring 216, a through
hole 218 defined in the interlayer insulating film located on the
lower wiring 216, an adhesion layer 219 provided within the through
hole 218, a plug 220 formed within the through hole 218 in which
the adhesion layer 219 is formed, and an upper wiring 221
electrically connected to the lower wiring 216.
[0006] A method of manufacturing the above-described conventional
semiconductor device 200 will next be described.
[0007] An insulating film 212 is deposited on a semiconductor
substrate 211 formed with an unillustrated semiconductor element.
Thereafter, a layer of a high melting-point metal, which is
obtained by laminating titanium nitride (TiN) and titanium (Ti), is
formed on the insulating film 212. Afterwards, a layer of an
aluminum alloy made of aluminum (Al) and copper (Cu) is formed on
the high melting-point metal layer. Further, a laminated layer of
titanium nitride and titanium, or a layer made of titanium alone is
formed on the aluminum alloy layer as a layer of a cap metal. These
high melting-point layer, aluminum alloy layer and a cap metal
layer are patterned to predetermined shapes to form a lower wiring
216 comprising a high melting-point layer 213, an aluminum alloy
layer 214 and a cap metal layer 215. After the formation of the
lower wiring 216, an interlayer insulating film 217 is formed on
the insulating film 212 so as to cover the lower wiring 216.
Thereafter, a concave hole, which reaches from the surface on the
interlayer insulating film 217 to the lower wiring 216, is formed
as a through hole 218.
[0008] Afterwards, a cleaning process is effected on a bottom
surface 222 of the through hole to remove a residual material
developed upon formation of the through hole 218. Thereafter, an
adhesion layer 219 using titanium nitride is formed on an inner
wall of the through hole 218. A plug 220 using tungsten is formed
within the through hole 218 in which the adhesion layer 219 is
formed. After the formation of the plug 220, an upper wiring 221 is
formed on the plug 220 by a process similar to that at the
formation of the lower wiring 216.
[0009] In addition the conventional semiconductor device 200, there
is known a conventional semiconductor device wherein respective
wirings of individual layers are electrically connected to each
other without using different types of metals to thereby reduce
resistance in a through hole (see Patent Document 1: Japanese
Unexamined Patent Publication No. Hei 05-047940 (FIG. 1)).
[0010] Although an alloy made of aluminum, silicon and copper is
formed as a plug within the through hole of the semiconductor
device disclosed in the patent document 1, it is difficult to scale
down or miniaturize the semiconductor device by use of the alloy in
today when the diameter of the through hole, which is less than or
equal to 0.5 .mu.m, be in the mainstream. Accordingly, a plug using
tungsten is formed in place of the above alloy nowadays.
SUMMARY OF THE INVENTION
[0011] Meanwhile, semiconductor devices faulty in operation were
subject to fabrication where semiconductor devices 200 having
various specs were manufactured by use of the above manufacturing
method.
[0012] It turned out that as a result of investigations of the
cause of a failure of each of such semiconductor devices faulty in
operation, the value (hereinafter called through hole resistance)
of resistance in a through hole of the semiconductor device was
large.
[0013] Accordingly, an object of the present invention is to
provide a semiconductor device low in through hole resistance, and
a method of manufacturing the semiconductor device.
[0014] The present invention adopts the following constitutions to
solve the above-described points.
[0015] An adhesion layer for causing a plug for electrically
connecting a lower wiring and an upper wiring opposite to each
other with an interlayer insulating film interposed therebetween to
adhere to the interlayer insulating film can be formed by
sputtering within a through hole for forming the plug, based on a
predetermined aspect ratio indicated by a ratio of a depth
dimension of the through hole to a diameter dimension of the
through hole.
[0016] The adhesion layer lying within the through hole can be
formed only on a sidewall of the through hole.
[0017] A thickness dimension of the adhesion layer on the lower
wiring can be formed to a thickness dimension which causes gas
having corrosion behavior to be penetrable.
[0018] Each of the lower wiring and the upper wiring can be formed
to a laminated structure wherein a cap metal layer is provided on
an aluminum alloy layer.
[0019] A high melting-point metal layer can be formed to a position
to form the aluminum alloy layer prior to the formation of the
aluminum alloy layer.
[0020] The aluminum alloy layer can be formed using an alloy made
of aluminum and copper.
[0021] The cap metal layer can be formed of a laminated layer of
titanium nitride and titanium, or a layer made of titanium nitride
alone.
[0022] The high melting-point metal layer can be formed of a
laminated layer of titanium nitride and titanium, or a layer made
of titanium nitride alone.
[0023] A linear dimension of the lower wiring can be formed
long.
[0024] The lower wiring can be formed as a first wiring on a
semiconductor substrate having a semiconductor element.
[0025] The lower wiring can be formed in a floating state of being
not directly connected to the semiconductor substrate having the
semiconductor element.
[0026] The plug can be formed using tungsten.
[0027] The adhesion layer can be formed using titanium nitride.
[0028] The sputtering can be performed in such a manner that the
relationship between a thickness dimension of a material deposited
on the interlayer insulating film by the sputtering and the aspect
ratio results in the fact that when the aspect ratio is over 2.5
and less than 3, the thickness dimension of the deposited material
ranges from over 7.5 nm to under 10 nm, when the aspect ratio is
over 3 and less than 3.5, the thickness dimension of the deposited
material ranges from over 7.5 nm to under 20 nm, and when the
aspect ratio is over 3.5 and less than 4, the thickness dimension
of the deposited material ranges from over 7.5 nm to under 30
nm.
[0029] The sputtering can be performed from every direction at an
incident angle of 5.degree. or more with respect to a target to be
sputtered.
[0030] The sputtering can be performed in such a manner that the
relationship between the aspect ratio and the incident angle
results in the fact that the incident angle at the time that the
aspect ratio is over 1 and less than 1.5, is 45.degree. or more,
the incident angle at the time that the aspect ratio is over 1.5
and less than 2, is 26.degree. or more, and the incident angle at
the time that the aspect ratio is over 2.5 and less than 3, is
18.degree. or more.
[0031] There is provided a semiconductor device comprising lower
wiring and an upper wiring opposite to each other via a through
hole defined in an interlayer insulating film, a plug for
electrically connecting the lower wiring and the upper wiring to
each other within the through hole, and an adhesion layer for
causing the plug to adhere to the interlayer insulating film within
the through hole, wherein the adhesion layer is formed based on a
predetermined aspect ratio represented by a ratio of a depth
dimension of the through hole to a diameter dimension thereof.
[0032] The adhesion layer lying within the through hole can be
formed only on a sidewall of the through hole.
[0033] A thickness dimension of the adhesion layer on the lower
wiring can be formed to a thickness dimension which causes gas
having corrosion behavior to be penetrable.
[0034] Each of the lower wiring and the upper wiring can be formed
to a laminated structure wherein a cap metal layer is provided on
an aluminum alloy layer.
[0035] Each of the lower wiring and the upper wiring can be formed
to a structure having a high melting-point metal layer provided
below the aluminum alloy layer.
[0036] The aluminum alloy layer can be formed of an alloy made of
aluminum and copper.
[0037] The cap metal layer can be formed of a laminated layer of
titanium nitride and titanium, or a layer made of titanium nitride
alone.
[0038] The high melting-point metal layer can be formed of a
laminated layer of titanium nitride and titanium, or a layer made
of titanium nitride alone.
[0039] A linear dimension of the lower wiring can be formed
long.
[0040] The lower wiring can be formed as a first wiring on a
semiconductor substrate having a semiconductor element.
[0041] The lower wiring can be formed as a wiring held in a
floating state of being not directly connected to the semiconductor
substrate having the semiconductor element.
[0042] The plug can be formed by a tungsten plug.
[0043] The adhesion layer can be formed using titanium nitride.
[0044] The adhesion layer can be formed such that the relationship
between a thickness dimension of a material deposited on the
interlayer insulating film by the sputtering and the aspect ratio
results in the fact that when the aspect ratio is over 2.5 and less
than 3, the thickness dimension of the deposited material ranges
from over 7.5 nm to under 10 nm, when the aspect ratio is over 3
and less than 3.5, the thickness dimension of the deposited
material ranges from over 7.5 nm to under 20 nm, and when the
aspect ratio is over 3.5 and less than 4, the thickness dimension
of the deposited material ranges from over 7.5 nm to under 30
nm.
[0045] The adhesion layer is formed by sputtering having
directivity. Sputtering can be effected on an object to be
sputtered from every direction at an incident angle of 5.degree. or
more.
[0046] The adhesion layer can be formed such that the relationship
between the aspect ratio and the incident angle results in the fact
that the incident angle at the time that the aspect ratio is over 1
and less than 1.5, is 45.degree. or more, the incident angle at the
time that the aspect ratio is over 1.5 and less than 2, is
26.degree. or more, and the incident angle at the time that the
aspect ratio is over 2.5 and less than 3, is 18.degree. or
more.
[0047] A prehistory of the present invention will be explained
below prior to the description of embodiments of the present
invention.
[0048] The present inventors have repeated experiments to determine
whether in a multilayered wiring type semiconductor device, the
resistant value of a through hole resistance of the semiconductor
device is large in any specs and to specify specs thereof. As a
result, the present inventors found out that the value of the
through hole resistance increased in particular in the case of a
certain specific wiring pattern. That is, the wiring pattern
corresponds to a wiring corresponding to a first layer on a
semiconductor substrate, which is very long, and is a wiring
pattern which is floated from the semiconductor substrate, i.e.,
which is not directly connected to the semiconductor substrate.
[0049] Next, the present inventors have considered that at the
wiring pattern, the whole wiring is charged when a wiring is
formed, so that some substances (hereinafter called foreign
substances) are adhered to the boundary (hereinafter called bottom
surface of a through hole) between the wiring and the through hole
formed on the wiring, or formed at the boundary, whereby the
foreign substances could result in an increase in through hole
resistance value. However, the present inventors could not clarify
the cause of their production and their composition.
[0050] The present inventors have repeatedly conducted experiments
even subsequently. The present inventors have found out a
remarkable result from an experiment shown next
[0051] Such an experiment is as follows: A semiconductor device
wherein a thickness dimension of an adhesion layer (titanium
nitride layer) deposited on a bottom surface of a through hole was
set to 0.75 nm, and a semiconductor device wherein it was set to 3
nm, were respectively produced using a testing wiring pattern shown
in FIG. 11. The values of through hole resistances employed in the
respective semiconductor devices were measured. Results thereof
were summarized in a graph shown in FIG. 12.
[0052] That is, the testing wiring pattern structure shown in FIG.
11 includes a first wiring M1 in which a wiring lying within a
range surrounded by a broken line is configured as a lower wiring,
a second wiring M2 configured as an upper wiring, a through hole
Via in which a plug for electrically connecting the first wiring M1
and the second wiring M2 to each other is formed, and measuring
terminals Pad for electrically connecting the wirings and a
measuring device. A linear dimension of the lower wiring M1 is 100
mm and a width dimension thereof is 0.52 .mu.m. Further, a diameter
dimension of the through hole is 0.26 .mu.m.
[0053] Using the testing wiring pattern referred to above, a
semiconductor device wherein titanium nitride for an adhesion layer
was deposited on a bottom surface of a through hole Via in a
thickness dimension of 0.75 nm was produced. A semiconductor device
wherein it was deposited thereon in a thickness dimension of 3 nm
was produced. Then the values of through hole resistances employed
in the former and latter semiconductor devices were respectively
measured. Their measured results were summarized in the graph of
FIG. 12. The graph of FIG. 12 is a cumulative normal distribution
diagram in which a distribution of through hole resistance values
at the time that the thickness dimension of the deposited titanium
nitride is 0.75, is represented by "+", and a distribution of
through hole resistance values at the time that the thickness
dimension thereof is 3 nm, is represented by ".largecircle.". It
turned out that as the thickness dimension of the titanium nitride
at the bottom surface of the through hole became thin as shown in
the figure, the through hole resistance value became low.
[0054] It was found out by carrying out further repeated
experiments that a semiconductor device formed with no adhesion
layer at a bottom surface of a through hole was capable of reducing
a through hole resistance value.
[0055] Further, this invention includes the following the
aspects.
[0056] 1.A method of manufacturing a semiconductor device,
comprising the following step:
[0057] forming, by sputtering, an adhesion layer for causing a plug
for electrically connecting a lower wiring and an upper wiring
opposite to each other with an interlayer insulating film
interposed therebetween to adhere to the interlayer insulating
film, within a through hole for forming the plug, based on a
predetermined aspect ratio indicated by a ratio of a depth
dimension of the through hole to a diameter dimension of the
through hole.
[0058] 2. The method according to claim 1, wherein the adhesion
layer lying within the through hole is formed only on a sidewall of
the through hole.
[0059] 3. The method according to claim 2, wherein a thickness
dimension of the adhesion layer on the lower wiring is formed to a
thickness dimension which causes gas having corrosion behavior to
be penetrable.
[0060] 4. The method according to claim 1, wherein each of the
lower wiring and the upper wiring is formed to a laminated
structure wherein a cap metal layer is provided on an aluminum
alloy layer.
[0061] 5. The method according to claim 4, wherein a high
melting-point metal layer is formed to a position to form the
aluminum alloy layer prior to the formation of the aluminum alloy
layer.
[0062] 6. The method according to claim 4, wherein the aluminum
alloy layer is formed using an alloy made of aluminum and
copper.
[0063] 7. The method according to claim 4, wherein the cap metal
layer is formed of a laminated layer of titanium nitride and
titanium, or a layer made of titanium nitride alone.
[0064] 8. The method according to claim 5, wherein the high
melting-point metal layer is formed of a laminated layer of
titanium nitride and titanium, or a layer made of titanium nitride
alone.
[0065] 9. The method according to claim 1, wherein a linear
dimension of the lower wiring is formed long.
[0066] 10. The method according to claim 1, wherein the lower
wiring is formed as a first wiring on a semiconductor substrate
having a semiconductor element.
[0067] 11. The method according to claim 1, wherein the lower
wiring is formed in a floating state of being not directly
connected to the semiconductor substrate having the semiconductor
element.
[0068] 12. The method according to claim 1, wherein the plug is
formed using tungsten.
[0069] 13. The method according to claim 1, wherein the adhesion
layer is formed using titanium nitride.
[0070] 14. The method according to claim 1, wherein said sputtering
is performed in such a manner that the relationship between a
thickness dimension of a material deposited on the interlayer
insulating film by said sputtering and the aspect ratio results in
the fact that when the aspect ratio is over 2.5 and less than 3,
the thickness dimension of the deposited material ranges from over
7.5 nm to under 10 nm, when the aspect ratio is over 3 and less
than 3.5, the thickness dimension of the deposited material ranges
from over 7.5 nm to under 20 nm, and when the aspect ratio is over
3.5 and less than 4, the thickness dimension of the deposited
material ranges from over 7.5 nm to under 30 -nm.
[0071] 15. The method according to claim 1, wherein said sputtering
is performed from every direction at an incident angle of 5.degree.
or more with respect to a target to be sputtered.
[0072] 16. The method according to claim 15, wherein said
sputtering is performed in such a manner that the relationship
between the aspect ratio and the incident angle results in the fact
that the incident angle at the time that the aspect ratio is over 1
and less than 1.5, is 45.degree. or more, the incident angle at the
time that the aspect ratio is over 1.5 and less than 2, is
26.degree. or more, and the incident angle at the time that the
aspect ratio is over 2.5 and less than 3, is 18.degree. or
more.
BRIEF DESCRIPTION OF THE DRAWINGS
[0073] While the specification concludes with claims particularly
pointing out and distinctly claiming the subject matter which is
regarded as the invention, it is believed that the invention, the
objects and features of the invention and further objects, features
and advantages thereof will be better understood from the following
description taken in connection with the accompanying drawings in
which:
[0074] FIG. 1 is a cross-sectional view showing a semiconductor
device according to a specific embodiment 1;
[0075] FIG. 2 is a cross-sectional view illustrating an aspect
ratio and a through hole;
[0076] FIG. 3 is a cross-sectional view depicting a titanium
nitride layer for an adhesion layer;
[0077] FIG. 4 is a cross-sectional view showing a tungsten layer
for a plug;
[0078] FIG. 5 is a cross-sectional view illustrating a
semiconductor device according to a specific embodiment 2;
[0079] FIG. 6 is a cross-sectional view depicting a sputter system
used in the specific embodiment 2;
[0080] FIG. 7 is a view showing an interlayer insulating film and
titanium nitride particles applied to through holes;
[0081] FIG. 8 is a cross-sectional view illustrating a titanium
nitride layer employed in the specific embodiment 2;
[0082] FIG. 9 is a graph showing the relationship between a through
hole aspect ratio and bottom coverage of a through hole;
[0083] FIG. 10 is a cross-sectional view illustrating a
conventional semiconductor device;
[0084] FIG. 11 is a view showing a testing wiring pattern; and
[0085] FIG. 12 is a graph illustrating distributions of through
hole resistances.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0086] Preferred embodiments of the present invention will
hereinafter be explained using the accompanying drawings on the
basis of the above-described findings.
[0087] Specific Embodiment 1
[0088] FIG. 1 is a cross-sectional view showing a semiconductor
device 10 according to a specific embodiment 1.
[0089] The semiconductor device 10 includes a semiconductor
substrate 11 formed with an unillustrated semiconductor element, an
insulating film 12 formed on the substrate 11, a high melting-point
metal layer 13 produced at a predetermined position on the
insulating film 12, a lower wiring 16 made up of an aluminum alloy
layer 14 produced on the high melting-point metal layer 13 and a
cap metal layer 15 produced on the alloy layer 14, an interlayer
insulating film 17 formed for wiring lamination, a through hole 18
defined in the interlayer insulating film 17 located on the lower
wiring 16, an adhesion layer 19 formed within the through hole 18,
a plug 20 formed within the through hole in which the adhesion
layer 19 is provided, and an upper wiring 21 formed on the plug
20.
[0090] The lower wiring 16 is a first wiring on the semiconductor
substrate 11. The wiring is not directly electrically connected to
the semiconductor substrate. The linear dimension of the wiring is
long and has a linear dimension of a few tens of mm. Further, the
lower wiring 16 has a multilayer structure comprising the high
melting-point metal layer 13, aluminum alloy layer 14 and cap metal
layer 15 for the purpose of an improvement in performance and
prevention of reflection in a photolithography process.
[0091] A method of manufacturing the semiconductor device 10 will
next be explained using FIGS. 1 through 4.
[0092] As shown in FIG. 2, an insulating film 12 is first formed on
a semiconductor substrate 11 having an unillustrated semiconductor
element.
[0093] Next, a layer for a high melting-point metal layer 13, which
is formed with a 20-nm film made of titanium and a 20-nm film made
of titanium nitride, is formed on the insulating film 12 to form a
lower wiring 16 sequentially laminated using a sputtering method.
After the layer for the high melting-point metal layer 13 has been
formed, a layer for an aluminum alloy layer 14, which is made of
aluminum and copper, is formed 400 nm thick on the layer 13.
Further, a layer for a cap metal layer 15, which is formed with a
5-nm film made of titanium and a 50-nm film made of titanium
nitride, is formed on the layer for the aluminum alloy layer 14.
Next, an unillustrated resist film is disposed on the layer for the
cap metal layer 15 in a predetermined pattern. Afterwards, the
layer for the cap metal layer 15, the layer for the aluminum alloy
layer 14, and the layer for the high melting-point metal layer 13
are etched to form the lower wiring 16 having a predetermined
wiring pattern, which is made up of the high melting-point metal
layer 13, the aluminum alloy layer 14 and the cap metal layer
15.
[0094] After the formation of the lower wiring 16, a silicon oxide
film is formed on the insulating film 12 as an interlayer
insulating film 17 by a high-density plasma method, for example.
The interlayer insulating film 17 is formed in a predetermined
thickness dimension so as to cover the lower wiring 16. Next, an
unillustrated resist film is disposed on the interlayer insulating
film 17 in a predetermined pattern and thereafter the interlayer
insulating film uncovered by the resist film is etched to define a
through hole 18.
[0095] As shown in FIG. 2, an aspect ratio represented by a ratio
of a depth dimension b (b=3.5) of the through hole 18 to a diameter
dimension a (a=1) of the through hole 18 is given as 3.5. The
through hole 18 having such an aspect ratio is formed by suitably
adjusting the thickness dimension of the interlayer insulating film
17, the diameter dimension of the through hole 18 and the height
dimension of the lower wiring 16.
[0096] After the formation of the through hole 18, a bottom surface
22 of the through hole 18 is etched by a sputter etching method.
Consequently, the surface of the cap metal layer 15 of the lower
wiring 16, which is exposed at the bottom surface 22 of the through
hole 18, is cut or chipped away 5 nm thick.
[0097] Afterward, as shown in FIG. 3, a layer 23 of titanium
nitride for an adhesion layer 19 is formed on the interlayer
insulating film 17 and within the through hole by a sputter
method.
[0098] While the titanium nitride layer 23 is deposited even on the
lower wiring 16 exposed at the bottom surface 22 of the through
hole, its linear dimension is set thinner than the thickness
dimension of the layer deposited on the interlayer insulating film
17. Assuming that a titanium nitride layer 23 having a thickness
dimension of 10 nm is formed on the interlayer insulating film by
the sputter method under the above aspect ratio 3.5, for example, a
titanium nitride layer having a thickness dimension of about 0.6 nm
is formed at the bottom surface 22 of the through hole. This
relationship is shown in FIG. 9. FIG. 9 shows the relationship
between aspect ratios and bottom coverage at the bottom surface 22
of the through hole, which are obtained by three types of sputter
methods different from one another. In the case of these sputter
methods; particles applied from a target to an objective one or
object are high in rectilinearity in order of a normal sputter, a
long-range sputter B and a long-range sputter A.
[0099] On the other hand, it turned out that though the thickness
dimension of the titanium nitride layer 23 deposited on the
interlayer insulating film 17 was set thin in order to make thin
the thickness dimension of the titanium nitride layer 23 deposited
at the bottom surface 22 of the through hole, peeling occurred in
the inner wall of the adhesion layer 19 with respect to the plug 20
or the inner wall of the through hole 18 with respect to the
adhesion layer 19 or both inner walls after the formation of the
adhesion layer 19 and the plug 20 to be described later in the case
where the thickness dimension of the titanium nitride layer 23
deposited on the interlayer insulating film 17 was 7.5 nm or less,
whereby sufficient adhesion was not ensured.
[0100] After the formation of the titanium nitride layer 23, as
shown in FIG. 4, a tungsten (W) portion for the plug 20 and a
tungsten layer 24 (having a thickness dimension ranging from 300 nm
to 500 nm) are next formed within the through hole 18 and on the
titanium nitride layer 23 by a CVD (Chemical Vapor Deposition)
method using tungsten hexafluoride gas (WF.sub.6) . After the
formation of the tungsten layer 24, the extra titanium nitride
layer 23 and tungsten layer 24 other than within the through hole
are removed by CMP (Chemical Mechanical Polishing) or an etchback
method as shown in FIG. 1. Afterwards, an upper wiring 21 having a
structure identical to that of the lower wiring 16 is formed in the
same manner as the lower wiring 16.
[0101] Owing to the formation of the adhesion layer 19 based on the
predetermined aspect ratio as mentioned above, the thickness
dimension of the adhesion layer at the bottom surface 22 of the
through hole 18 can be made thin. It is therefore possible to
manufacture a semiconductor device low in through hole resistance
value. Accordingly, a failure in operation developed due to an
increase in through hole resistance value can be prevented and
hence a satisfactory semiconductor device can be obtained.
[0102] Further, since the semiconductor device of the present
invention can be fabricated without using a special manufacturing
apparatus, a capital investment can be suppressed and hence the
semiconductor device of the present invention can be economically
fabricated.
[0103] Incidentally, as the cause of a reduction in through hole
resistance value, it is conceivable that when the thickness
dimension of the adhesion layer formed at the bottom surface of the
through hole is made thin, the tungsten hexafluoride gas having
corrosion behavior is penetrated from the adhesion layer and
foreign substances are eroded by the penetrated tungsten
hexafluoride gas, followed by being removed.
Specific Embodiment 2
[0104] While the adhesion layer 19 employed in the specific
embodiment 1 has been substantially uniformly formed in the
predetermined thickness dimension from the upper portion of the
inner wall of the through hole 18 to the lower portion thereof, the
specific embodiment 2 will explain a method of forming an adhesion
layer 31 whose thickness dimension gradually decreases as it
extends from an upper portion of a through hole to a lower portion
thereof.
[0105] FIG. 5 is a cross-sectional view showing a semiconductor
device 30 according to the specific embodiment 2.
[0106] The semiconductor device 30 includes a semiconductor
substrate 11 formed with an unillustrated semiconductor element, an
insulating film 12 formed on the substrate 11, a high melting-point
metal layer 13 produced at a predetermined position on the
insulating film 12, a lower wiring 16 made up of an aluminum alloy
layer 14 formed on the high melting-point metal layer 13 and a cap
metal layer 15 produced on the alloy layer 14, an interlayer
insulating film 17 formed to laminate a wiring over the lower
wiring 16, a through hole 18 defined in the interlayer insulating
film 17 located on the lower wiring 16, an adhesion layer 31 whose
thickness dimension gradually decreases as it extends from an upper
portion of an inner wall of the through hole 18 to a lower portion
thereof, a plug 20 formed within the through hole in which the
adhesion layer 31 is provided, and an upper wiring 21 formed on the
plug 20.
[0107] A method of manufacturing the semiconductor device 30 will
next be described using FIGS. 6 through 8.
[0108] In a manner similar to the specific embodiment 1, an
insulating film 12 is first formed to a predetermined position on a
semiconductor substrate 11. Afterwards, a lower wiring 16 is formed
which consists of a high melting-point metal layer 13, an aluminum
alloy layer 14 and a cap metal layer 15.
[0109] Next, an interlayer insulating film 17 made up of a silicon
oxide film is formed on the insulating film 12 so as to cover the
lower wiring 16. Afterwards, photolitho etching is effected thereon
to define a through hole 18 which exposes the surface of the lower
wiring 16 at its bottom surface. After the formation of the through
hole 18, the lower wiring exposed at the bottom surface 22 of the
through hole 18 is etched by a sputter etching method so that the
surface of the cap metal layer 15 of the lower wiring 16 is cut or
chipped away 5 nm thick.
[0110] A titanium nitride layer used for the adhesion layer 31,
which shows the feature of the specific embodiment 2, is next
formed by using a sputter system 50 shown in FIG. 6. The sputter
system 50 is provided with a target 51 which applies particles of
titanium nitride vertically from the surface of the ceiling thereof
to its floor, and a susceptor 53 on which a wafer 52 comprising a
plurality of semiconductor substrates 11 subjected to the
processing up to the above-described manufacturing process is
placed. The susceptor 53 has a predetermined angle with respect to
the target 51. When the titanium nitride is sputtered from the
target 51 to the wafer 52, the susceptor 53 is rotated
counterclockwise while maintaining a predetermined speed.
[0111] The predetermined angle has been found out by repeating
experiments and is determined depending on an aspect ratio of the
through hole. When the aspect ratio is more than or equal to 1 and
less than 1.5, the angle of incidence of the titanium nitride from
the target 51 may preferably be 45.degree. or more. When the aspect
ratio is greater than or equal to 1.5 and less than 2, the angle of
incidence of the titanium nitride from the target 51 may preferably
be 26.degree. or more. When the aspect ratio is greater than or
equal to 2.5 and less than 3, the angle of incidence angle of the
titanium nitride from the target 51 may preferably be 18.degree. or
more.
[0112] With the use of the sputter system 50, the titanium nitride
particles applied from the target 51 are applied to the interlayer
insulating film 17 and the through holes 18 at a predetermined
incident angle as shown in FIG. 7. With the rotation of the
susceptor 53 counterclockwise while the predetermined speed is
being maintained, a titanium nitride layer 32 is uniformly formed
on its corresponding interlayer insulating film 17 as shown in FIG.
8. Thus, the titanium nitride layer 32 for an adhesion layer, whose
thickness dimension gradually decreases from an upper portion of an
inner wall of each through hole 18 defined in the interlayer
insulating film 17 to a lower portion thereof, is formed on the
inner wall of each through hole 18.
[0113] The titanium nitride layer 32 for the adhesion layer is not
substantially formed at the bottom surface of each through hole
18.
[0114] After the formation of the titanium nitride layer 32, a
tungsten layer for plugs 20 is formed in the through holes 18 in a
manner similar to the specific embodiment 1. The tungsten layer is
formed by a W-CVD method using tungsten hexafluoride gas
WF.sub.6.
[0115] After the formation of the tungsten layer, the extra
titanium nitride layer 32 and tungsten layer other than within the
through holes are removed. Thereafter, an upper layer wiring 21
having a structure identical to that mentioned above is formed in a
manner similar to the specific embodiment 1.
[0116] As described above, the through holes 18 each having a
predetermined aspect ratio are defined in the interlayer insulating
film 17 and sputtered at a predetermined angle from all directions,
whereby adhesion layers 31 each having a predetermined thickness
dimension are formed on the inner walls of the through holes 18
without being deposited on the bottom surfaces 22 of the through
holes. Therefore, adhesion is provided between the plug 20 and the
interlayer insulating film 17, and a semiconductor device 30 low in
through hole resistance value can be fabricated. It is thus
possible to obtain a satisfactory semiconductor device 30 free of
the occurrence of a failure in operation.
[0117] Further, the adhesion layer 31 can be formed even when the
aspect ratio of the through hole 18 is less than 2.5. The adhesion
layer 31 can be adapted for use in the manufacture of a
miniaturized semiconductor device low in aspect ratio.
[0118] Since the adhesion layer 19 employed in the specific
embodiment 1 and the adhesion layer 31 employed in the specific
embodiment 2 can respectively be formed without effecting etching
processing on the titanium nitride layers (23 and 32) for the
adhesion layers, the manufacturing process can be shortened and
made efficient.
[0119] Although the specific embodiment 1 has shown an example in
which the through hole 18 whose aspect ratio is 3.5, is formed and
the thickness dimension of the titanium nitride layer 23 deposited
on the interlayer insulating film 17 is formed 10 nm, the present
invention is not limited to it. It has been found out by
experiments that a semiconductor device low in through hole
resistance value can be manufactured even in terms of the
relationship between each aspect ratio shown below and the
thickness dimension of the titanium nitride layer 23 deposited on
the interlayer insulating film 17 by sputtering.
[0120] That is, the relationship between the aspect ratio and the
thickness dimension of the titanium nitride layer 23 deposited on
the interlayer insulating film 17 is as follows. When the aspect
ratio is over 2.5 and less than 3, the thickness dimension of the
titanium nitride layer 23 deposited on the interlayer insulating
film 17 may preferably be formed so as to range from over 7.5 nm to
under 10 nm. When the aspect ratio is over 3 and less than 3.5, the
thickness dimension of the titanium nitride layer 23 deposited on
the interlayer insulating film 17 may preferably be formed so as to
range from over 7.5 nm to under 20 nm. When the aspect ratio is
over 3.5 and less than 4, the thickness dimension of the titanium
nitride layer 23 deposited on the interlayer insulating film 17 may
preferably be formed so as to range from over 7.5 nm to under 30
nm.
[0121] In the specific embodiment 2 described above, the titanium
nitride layer 32 may be formed by a collimator sputter method, a
long-range sputter method, an ion sputter method or the like. Any
of the sputter methods is a sputter method having directivity.
[0122] According to the present invention, as described above,
since the adhesion layer is formed based on the aspect ratio, the
adhesion layer is not formed at the bottom surface of the through
hole or the thickness dimension of the adhesion layer at the bottom
surface of the through hole can be formed thin, thus making it
possible to fabricate a semiconductor device low in through hole
resistance value. Accordingly, a satisfactory semiconductor device
can be obtained which does not incur a failure in operation
developed due to a high through hole resistance value.
[0123] While the present invention has been described with
reference to the illustrative embodiments, this description is not
intended to be construed in a limiting sense. Various modifications
of the illustrative embodiments, as well as other embodiments of
the invention, will be apparent to those skilled in the art on
reference to this description. It is therefore contemplated that
the appended claims will cover any such modifications or
embodiments as fall within the true scope of the invention.
* * * * *