U.S. patent application number 10/248030 was filed with the patent office on 2004-06-17 for robust field emitter array design.
This patent application is currently assigned to GENERAL ELECTRIC COMPANY. Invention is credited to WILSON, Colin.
Application Number | 20040113140 10/248030 |
Document ID | / |
Family ID | 32392316 |
Filed Date | 2004-06-17 |
United States Patent
Application |
20040113140 |
Kind Code |
A1 |
WILSON, Colin |
June 17, 2004 |
ROBUST FIELD EMITTER ARRAY DESIGN
Abstract
There is provided a field emitter device formed over a
semiconductor substrate. The field emitter device includes at least
one field emitter tip disposed over the substrate, and a conducting
gate electrode layer disposed over the substrate. The field emitter
device also includes a protective electronic component disposed
over and integral to the substrate and electrically connecting the
conducting gate electrode layer to the substrate such that if the
conducting gate electrode layer experiences a voltage greater than
a breakdown voltage of the field emitter device, the protective
electronic component conducts current between the conducting gate
electrode layer and the substrate.
Inventors: |
WILSON, Colin; (Niskayuna,
NY) |
Correspondence
Address: |
FOLEY AND LARDNER
SUITE 500
3000 K STREET NW
WASHINGTON
DC
20007
US
|
Assignee: |
GENERAL ELECTRIC COMPANY
Building K1 P.O. Box 8
Schenectady
NY
12301
|
Family ID: |
32392316 |
Appl. No.: |
10/248030 |
Filed: |
December 12, 2002 |
Current U.S.
Class: |
257/10 |
Current CPC
Class: |
H01J 1/3044 20130101;
H01J 9/025 20130101 |
Class at
Publication: |
257/010 |
International
Class: |
H01L 029/12 |
Claims
What is claimed is:
1. A field emitter device disposed over a semiconductor substrate
comprising: at least one field emitter tip disposed over the
substrate; a conducting gate electrode layer disposed over the
substrate; a protective electronic component disposed over and
integral to the substrate and electrically connecting the
conducting gate electrode layer to the substrate such that if the
conducting gate electrode layer experiences a voltage greater than
a breakdown voltage of the field emitter device, the protective
electronic component conducts current between the conducting gate
electrode layer and the substrate.
2. The field emitter device of claim 1, wherein the protective
electronic component comprises at least one zener diode.
3. The field emitter device of claim 2, wherein the protective
electronic component comprises a back-to-back zener diode voltage
clamp.
4. The field emitter device of claim 1, wherein the protective
electronic component comprises a varistor.
5. The field emitter device of claim 1, further comprising: an
intervening layer between the conducting gate electrode layer and
the substrate, wherein the protective electronic component is
disposed within a first section of the intervening layer.
6. The field emitter device of claim 5, wherein the intervening
layer further comprises an insulating material in a second section
laterally adjacent the first section and to the at least one field
emitter tip.
7. The field emitter device of claim 6, wherein the insulating
material is one of silicon dioxide, silicon nitride, and silicon
oxynitride.
8. The field emitter device of claim 6, wherein the first section
comprises at least one doped semiconductor material.
9. The field emitter device of claim 8, the first section comprises
a third section and a fourth section laterally adjacent the third
section, the third section comprising a third section top portion
comprising p-type semiconductor material and a third section bottom
portion comprising n-type semiconductor material, the fourth
section comprising a fourth section top portion comprising n-type
semiconductor material and a fourth section bottom portion
comprising p-type semiconductor material.
10. The field emitter device of claim 1, wherein the protective
electronic component is formed remote from the conducting gate
electrode layer.
11. The field emitter device of claim 10, further comprising a
conducting line electrically connecting the protective electronic
component to the conducting gate electrode layer.
12. The field emitter device of claim 1, wherein the substrate
further comprises insulating material.
13. The field emitter device of claim 1, wherein the substrate
comprises at least one of silicon, germanium and III-V
semiconductor material.
14. The field emitter device of claim 1, wherein the at least one
field emitter tip comprises one of a refractory metal tip, a
nanotube and a nanowire.
15. The field emitter device of claim 1, wherein the at least one
field emitter tip comprises a nanowire comprising one of ZnO,
refractory metal, refractory metal carbide, and diamond.
16. The field emitter device of claim 14, wherein the at least one
field emitter tip comprises a refractory metal tip comprising one
of molybdenum, niobium and hafnium.
17. The field emitter device of claim 1, wherein the at least one
field emitter tip comprises a carbon nanotube.
18. A method of forming a field emitter device formed over a
semiconductor substrate comprising: forming at least one field
emitter tip over the substrate; forming a conducting gate electrode
layer over the substrate; forming a protective electronic component
over and integral to the substrate and electrically connecting the
conducting gate electrode layer to the substrate such that if the
conducting gate electrode layer experiences a voltage greater than
a breakdown voltage of the field emitter device, the protective
electronic component conducts current between the conducting gate
electrode layer and the substrate.
19. The method of claim 18, wherein the protective electronic
component is formed remote from the conducting gate electrode
layer.
20. The method of claim 18, further comprising forming an
intervening layer between the conducting gate electrode layer and
the substrate, wherein the protective electronic component is
disposed within a first section of the intervening layer.
21. The method of claim 20, wherein the forming an intervening
layer further comprises forming an insulating material in a second
section laterally adjacent the first section.
22. The method of claim 21, wherein the forming a first section
further comprises: forming a third section and a fourth section
laterally adjacent the third section, the third section comprising
a third section top portion comprising p-type semiconductor
material and a third section bottom portion comprising n-type
semiconductor material, the fourth section comprising a fourth
section top portion comprising n-type semiconductor material and a
fourth section bottom portion comprising p-type semiconductor
material.
23. The method of claim 22, wherein the forming a third section top
portion and a fourth section top portion further comprises:
depositing a semiconductor material and selectively implanting
n-type ions into the semiconductor material to form the fourth
section top portion.
24. The method of claim 22, wherein the forming a third section
bottom portion and a fourth section bottom portion further
comprises: depositing a semiconductor material and selectively
implanting p-type ions into the semiconductor material to form the
fourth section bottom portion.
Description
BACKGROUND OF THE INVENTION
[0001] This invention is related generally to field emitter
arrays.
[0002] Field emitter arrays (FEAs) generally include an array of
field emitter devices. Each emitter device, when properly driven,
can emit electrons from the tip of the device. Field emitter arrays
have many applications, one of which is in field emitter displays
(FEDs), which can be implemented as a flat panel display. In
addition to flat panel displays, FEAs have applications as electron
sources in microwave tubes, X-ray tubes, and other microelectronic
devices.
[0003] FIG. 1 illustrates a portion of a conventional FEA. The
field emitter device shown in FIG. 1 is often referred to as a
"Spindt-type" FEA. It includes a field emitter tip 12 formed on a
semiconductor substrate 10. Refractory metal, carbide, diamond and
silicon tips, silicon carbon nanotubes and metallic nanowires are
some of the structures known to be used as field emitter tips 12.
The field emitter tip 12 is adjacent to an insulating layer 14 and
a conducting gate layer 16. By applying an appropriate voltage to
the conducting gate layer 16, the current to the field emitter tip
12 passing through semiconductor substrate 10 is controlled.
[0004] FEAs in many prior art designs are susceptible to failure
due to gate-to-substrate short circuiting and gate to tip arcing.
Typically, failure occurs from (i) an overvoltage on the gate and
bulk breakdown of the insulating layer 14 that allows current to
punch through or flash over the insulating layer 14 of the gate and
creates a high current arc that destroys the entire device or (ii)
an overvoltage on the gate that causes an arc to develop between
the grid and tip.
[0005] A large number of field emitter tips are typically supplied
current by a single conducting gate layer. Thus, when short circuit
failure occurs, all the emitter tips corresponding to a particular
gate layer are affected, and failure is catastrophic.
SUMMARY OF THE INVENTION
[0006] In accordance with one aspect of the present invention,
there is provided a field emitter device disposed over a
semiconductor substrate. The field emitter device comprises: at
least one field emitter tip disposed over the substrate; a
conducting gate electrode layer disposed over the substrate; a
protective electronic component disposed over and integral to the
substrate and electrically connecting the conducting gate electrode
layer to the substrate such that if the conducting gate electrode
layer experiences a voltage greater than a breakdown voltage of the
field emitter device, the protective electronic component conducts
current between the conducting gate electrode layer and the
substrate.
[0007] In accordance with another aspect of the present invention,
there is provided a method of forming a field emitter device formed
over a semiconductor substrate. The method comprises: forming at
least one field emitter tip over the substrate; forming a
conducting gate electrode layer over the substrate; forming a
protective electronic component over and integral to the substrate
and electrically connecting the conducting gate electrode layer to
the substrate such that if the conducting gate electrode layer
experiences a voltage greater than a breakdown voltage of the field
emitter device, the protective electronic component conducts
current between the conducting gate electrode layer and the
substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIG. 1 is a side cross sectional view of a prior art field
emitter device.
[0009] FIG. 2 is a schematic of a portion of a field emitter device
according to a preferred embodiment of the invention.
[0010] FIG. 3 illustrates a side view of a field emitting device
according to a preferred embodiment.
[0011] FIG. 4 is a top view of the field emitter device of FIG. 3
and further regions of the field emitter device.
[0012] FIG. 5 is a top view of a field emitter device according to
another preferred embodiment of the invention.
[0013] FIG. 6 is a side view of the field emitter device of FIG. 5
along the line B-B in FIG. 5.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0014] Reference will now be made in detail to presently preferred
embodiments of the present invention. Wherever possible, the same
reference numbers will be used throughout the drawings to refer to
the same or like parts.
[0015] The present inventor has realized that the problem of
catastrophic failure from gate to substrate arcing and gate-to-tip
arcing can be avoided by incorporating a protective electronic
component integral to the FEA. The protective electronic component
acts to channel current to the substrate as soon as a safe gate
voltage level is exceeded. In this manner when the voltage to the
gate begins to exceed a safe level, i.e., the breakdown voltage of
the device, the protective electronic component starts to draw
current and the gate voltage is prevented from further
increase.
[0016] Beneficially, the protective electronic component is
integral to the substrate on which the FEA is formed, and thus can
be formed using standard electronic bulk manufacturing processes.
In one embodiment of the invention, the protective electronic
component can be fabricated adjacent the insulating layer of the
gate and under a conducting gate electrode layer of the gate. In
another embodiment, the protective electronic component is formed
remote from the gate electrode layer.
[0017] FIG. 2 is a schematic of a portion of a field emitter device
according to a preferred embodiment of the invention. The field
emitter device includes a substrate 10, which may comprise a
semiconductor material. A field emitter tip 12 is disposed over the
substrate 10. A conducting gate electrode layer 16 is disposed over
the substrate. In general the conducting gate electrode layer 16
does not contact the substrate 10 directly, but is separated from
the substrate by an insulating layer which insulates the gate
electrode layer 16 from the substrate 10. The field emitter device
also includes a protective electronic component 20 disposed over
and integral to the substrate 10. The protective electronic
component 20 electrically connects the conducting gate electrode
layer 16 to the substrate 10 such that when the gate electrode
layer 16 experiences a voltage greater than a breakdown voltage,
the protective electronic component 20 conducts current between the
conducting gate electrode layer 16 and the substrate 10.
[0018] FIG. 2 (and FIGS. 3 and 6 discussed below) illustrate a
single field emitter tip for ease of illustration. In
implementation, the FEA has an array of field emitter tips where
the current to each tip is controlled by the conducting gate
electrode layer 16. In any event, the field emitter device has at
least one field emitter tip 12.
[0019] The protective electronic component 20 may comprise, for
example, at least one zener diode that allows current to pass from
the gate electrode layer 16 to the substrate 10 when the gate
electrode layer 16 voltage exceeds a breakdown voltage. The
protective electronic component 20 may comprise, for example, a
back-to-back zener diode voltage clamp.
[0020] The protective electronic component 20 may alternatively
comprise a varistor, or any other electronic component that
functions to allows current to pass from the gate electrode layer
16 to the substrate 10, when the gate electrode layer 16 voltage
exceeds a breakdown voltage.
[0021] Preferably the protective electronic component 20 is formed
as part of an intervening layer (not shown in FIG. 1), which is
disposed between the gate electrode layer 16 and the substrate 10.
In this case the protective electronic component 20 is formed
proximate the gate electrode layer 16. Arranging the protective
electronic component 20 proximate the gate electrode layer 16
prevents any high voltage transients formed in leads or cables
connected to the device from destroying the device. Assembly is
also easier when the protective electronic component 20 is arranged
proximate the gate electrode layer 16. Alternatively, the
protective electronic component 20 may be formed remote from the
gate electrode layer 16.
[0022] FIG. 3 illustrates a side view of a field emitting device
according to a preferred embodiment. The field emitting device of
FIG. 3 in a similar fashion to the schematic of FIG. 2 includes a
substrate 10, which may comprise a semiconductor material. At least
one field emitter tip 12 is disposed over the substrate 10. A
conducting gate electrode layer 16 is disposed over the substrate.
The conducting gate electrode layer 16 is separated from the
substrate 10 by an intervening layer 34. The field emitter device
also includes a protective electronic component 20 disposed over
and integral to the substrate 10. The protective electronic
component 20 electrically connects the conducting gate electrode
layer 16 to the substrate 10 such that when the gate electrode
layer 16 experiences a voltage greater than a breakdown voltage the
protective electronic component 20 conducts current between the
conducting gate electrode layer 16 and the substrate 10.
[0023] The substrate 10, may comprise a semiconductor material.
Exemplary semiconductor materials include silicon, germanium and
III-V semiconductor materials such as GaAs, but others may be used.
The substrate, may also comprise an insulating material, such as
glass or plastic for example, with a semiconductor layer formed on
the insulating material. In this case the substrate will comprise a
semiconductor material, but will also comprise an underlying
insulating (or conducting) material. Preferably, the substrate 10
is doped such that the gate 16, when an appropriate voltage is
applied, will allow current to flow to the at least one emitter tip
12 through the substrate. Thus, the gate 16 controls the flow of
current to the emitter tip.
[0024] In this embodiment, the protective electronic component 20
is formed as part of the intervening layer 34 located between the
conducting gate layer 16 and the substrate 10. Specifically, the
protective electronic component 20 is disposed within a first
section of the intervening layer 34 laterally adjacent a second
section 22, comprising insulating material. The insulating material
may comprise, for example, silicon dioxide, silicon nitride, or
silicon oxynitride.
[0025] The second section 22 insulating material may be formed by
blanket depositing an insulating material, by any suitable
technique, such as CVD or sputtering, followed by patterning the
insulating material. Patterning the first insulating material may
be performed using photolithographic techniques, which are well
known in the art. Alternatively, the second section 22 insulating
material may be formed by growing an insulating material directly
on the substrate 10, followed by patterning the insulating
material, or by selectively growing the insulating material on the
substrate.
[0026] If the second section 22 is formed by growing a material on
the substrate, the second section 22 may be formed by exposing the
substrate 10 to an oxidizing atmosphere. For example, if the
substrate 10 is silicon, the second section 22 may be formed by
exposing the substrate to oxygen gas or water vapor.
[0027] The second section 22 may be formed to a thickness of
between about 0.5 .mu.m and 5 .mu.m, and more preferably between
about 0.5 .mu.m and 1.5 .mu.m. The thickness of the second section
22 will depend upon the particular device formed, and it should be
thick enough to support an appropriate gate voltage. The thickness
of the second section 22 may be, for example, about 2.5 .mu.m. The
second section 22 may be formed prior to the protective electronic
component 20 of the first section or afterwards or at the same
time.
[0028] The protective electronic component 20 of the first section
may be, for example, a back-to-back zener voltage clamp comprising
doped semiconductor material. In this case, the first section may
comprise a third section 24 and a fourth section 26 forming the
respective zener diodes of the back to-back zener voltage clamp.
The third section 24 comprises a third section top portion 24a and
a third section bottom portion 24b, which are oppositely doped. For
example, the top portion 24a may comprise p-type semiconductor
material, while the bottom portion 24b comprises n-type
semiconductor material. The zener diode of the fourth portion 26
has opposite polarity to that of the third portion 24. The fourth
portion 26 may thus have a fourth portion top portion 26a
comprising n-type semiconductor material, while the fourth portion
bottom portion 26b comprises p-type semiconductor material.
[0029] The protective electronic component 20 of the first section
may be formed as follows. Semiconductor material for forming the
bottom portions 24b and 26b is deposited, and patterned if
necessary, for example as n-doped material. The bottom portion 24b
is masked with an ion implant mask, such as photoresist, and the
bottom portion 26b is implanted with appropriate ions to make the
bottom portion 26b p-type. Alternatively, the semiconductor
material is deposited undoped, and a p-type and n-type implants are
performed with appropriate masking. As another alternative, p-doped
material is deposited and the bottom portion 26b is masked with an
ion implant mask, such as photoresist, and the bottom portion 24b
is implanted with appropriate ions to make the bottom portion 24b
n-type.
[0030] Top portions 24a and 26a are then formed in a similar
fashion to the bottom portions, except that 24a and 26a are formed
to be p-type and n-type, respectively.
[0031] The conducting gate layer 16 may be formed by depositing a
conducting material on the intervening layer 34. The conducting
material may be a metal, such as a refractory metal, for example.
The conducting material may be one of molybdenum, niobium, chromium
and hafnium, or combinations of these materials, for example.
[0032] Other conducting materials may be used as are known in the
art. The conducting material may be deposited by physical vapor
deposition techniques, such as evaporation or sputtering, or by
chemical vapor deposition (CVD) techniques. The conducting material
may be deposited in the region between the intervening layer 34, in
addition to on the intervening layer 34 especially if the
conducting gate layer 16 is much thinner than the intervening layer
34. The conducting gate layer 16 may be formed to a thickness of
between about 0.1 .mu.m and 1 .mu.m, for example. The thickness of
the conducting gate layer 16 may be, for example, about 0.4 .mu.m.
The thickness of the conducting gate layer 16 will be dependent
upon the particular device formed, and should be thick enough to
allow conduction of the gate current, as is known in the art.
[0033] The conducting gate layer 16 and intervening layer 34 may be
formed by forming the intervening layer 34 and then the conducting
gate layer 16 on the intervening layer 34, followed by
photolithographically patterning both layers. Alternatively, the
intervening layer 34 may be patterned first followed by patterning
the conducting gate layer 16.
[0034] The voltage to the conducting gate layer 16 may be
controlled by other circuitry (not shown) on the substrate 10 as
known in the art.
[0035] The field emitter tip 12 may be formed as a refractory metal
tip, a nanotube, a nanowire or other types of emitter tips. If the
field emitter tip 12 is formed as a refractory metal tip, the tip
12 may be formed by the so-called "Spindt process". An example of a
Spindt process for depositing a refractory metal tip, for example,
is provided in U.S. Pat. No. 5,731,597 to Lee et al, which is
incorporated by reference. If the emitter tip 12 comprises a
refractory metal, the emitter tip 12 may be formed of molybdenum,
niobium, or hafnium, or combinations of these materials, for
example.
[0036] The field emitter tip 12 may also be formed as a nanotube or
nanowire. For example, the emitter tip 12 may be formed as a carbon
nanotube or a nanowire. The nanowire may be ZnO, refractory metal,
refractory metal carbide, or diamond, for example. Carbon nanotubes
may be formed using electric discharge, pulsed laser ablation or
chemical vapor deposition, for example. Nanowires can be grown by
several known methods, but preferably using electro-deposition.
[0037] FIG. 4 is a top view of the field emitter device of FIG. 3
and further regions of the field emitter device. FIG. 3 shows a
portion of FIG. 4 along the line A-A. The dashed lines in FIG. 4
denote the regions of the protective electronic component 20 of the
first section which includes the third section 24 and fourth
section 26. In FIG. 4, each of the field emitter tips 12 is
adjacent to a section of the protective electronic component 20
proximate the tip 12. Alternatively, only one or some of the field
emitter tips 12 may be adjacent to a section of the protective
electronic component 20.
[0038] FIG. 5 is a top view of a field emitter device according to
another preferred embodiment. In the embodiment of FIG. 5, the
protective electronic component 20 is remote from the conducting
gate electrode layer 16. The conducting gate electrode layer 16 is
electrically connected to the protective electronic component 20
via a conducting line 30.
[0039] FIG. 6 is a side view of the field emitter device of FIG. 5
along the line B-B in FIG. 5. In this case, the third and fourth
sections 24 and 26 of the protective electronic component 20 are
located remote from the conducting gate electrode layer 16. The
third and fourth sections 24 and 26 are all covered by a protective
electronic component conducting layer 32 which may be formed at the
same time as the conducting electrode layer 16, and the conducting
line 30 (not shown in FIG. 6).
[0040] FIGS. 5 and 6 illustrate a single protective electronic
component remote from the gate conducting electrode layer 16.
Alternatively, the gate conducting electrode layer 16 may be
connected to several protective electronic component located
remotely.
[0041] While the invention has been described in detail and with
reference to specific embodiments thereof, it will be apparent to
one skilled in the art that various changes and modifications can
be made therein without departing from the spirit and scope of the
invention. Thus, the breadth and scope of the present invention
should not be limited by any of the above-described exemplary
embodiments, but should be defined only in accordance with the
following claims and their equivalents.
* * * * *