U.S. patent application number 10/622484 was filed with the patent office on 2004-05-06 for ulsi mos with high dielectric constant gate insulator.
This patent application is currently assigned to Lam Research Corporation. Invention is credited to Setton, Michael.
Application Number | 20040087091 10/622484 |
Document ID | / |
Family ID | 22330688 |
Filed Date | 2004-05-06 |
United States Patent
Application |
20040087091 |
Kind Code |
A1 |
Setton, Michael |
May 6, 2004 |
ULSI MOS with high dielectric constant gate insulator
Abstract
MOS transistor formed on a semiconductor substrate of a first
conductivity type and method of fabrication are provided. The
device includes (a) an interfacial layer formed on the substrate;
(b) a high dielectric constant layer covering the interfacial layer
that comprises a material that is selected from the group
consisting of Ta.sub.2O.sub.5, Ta.sub.2(O.sub.1-xN.sub.x).sub.5
wherein x ranges from greater than 0 to 0.6, a solid solution of
(Ta.sub.2O.sub.5).sub.r--(TiO.sub.2).sub.1-r wherein r ranges from
about 0.9 to 1, a solid solution
(Ta.sub.2O.sub.5).sub.s--(Al.sub.2O.sub.3).sub.1-s wherein s ranges
from 0.9 to 1, a solid solution of
(Ta.sub.2O.sub.5).sub.t--(ZrO.sub.2).sub.1-- t wherein t ranges
from about 0.9 to 1, a solid solution of
(Ta.sub.2O.sub.5).sub.u--(HfO.sub.2).sub.1-u wherein u ranges from
about 0.9 to 1, and mixtures thereof wherein the interfacial layer
separates the high dielectric constant layer from the substrate;
(b) a gate electrode having a width of less than 0.3 micron
covering the high dielectric constant layer; (d) first and second
lightly doped regions of a second conductivity type disposed on
respective areas of the substrate surface; (e) a source and drain
regions of the second conductivity type; and (f) a pair of spacers
formed adjacent to the gate electrode and formed on the high
dielectric constant layer. The high dielectric layer can be subject
to densification. The gate oxide material will significantly
improve the performance of an MOS device by reducing or eliminating
the current leakage associated with prior art devices.
Inventors: |
Setton, Michael; (Iserc,
FR) |
Correspondence
Address: |
Peter K. Skiff
BURNS, DOANE, SWECKER & MATHIS, L.L.P.
P.O. Box 1404
Alexandria
VA
22313-1404
US
|
Assignee: |
Lam Research Corporation
|
Family ID: |
22330688 |
Appl. No.: |
10/622484 |
Filed: |
July 21, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10622484 |
Jul 21, 2003 |
|
|
|
09109992 |
Jun 30, 1998 |
|
|
|
Current U.S.
Class: |
438/287 ;
257/E29.152; 438/591 |
Current CPC
Class: |
H01L 29/517 20130101;
H01L 29/4983 20130101; H01L 29/513 20130101; H01L 21/28194
20130101; H01L 29/6659 20130101; H01L 29/6656 20130101; H01L
21/28185 20130101; H01L 29/518 20130101; H01L 21/28202
20130101 |
Class at
Publication: |
438/287 ;
438/591 |
International
Class: |
H01L 021/3205; H01L
021/336; H01L 021/4763 |
Claims
what is claimed is:
1. A method for fabricating a MOS device having a gate width of
less than 0.3 micron that comprises the steps of: (a) forming an
interfacial layer on a semiconductor substrate of a first
conductivity type; (b) forming a high dielectric constant layer on
the interfacial layer that comprises a material that is selected
from the group consisting of Ta.sub.2O.sub.5,
Ta.sub.2(O.sub.1-xN.sub.x).sub.5 wherein x ranges from greater 0 to
0.6, a solid solution of
(Ta.sub.2O.sub.5).sub.r--(TiO.sub.2).sub.1-r wherein r ranges from
about 0.9 to 1, a solid solution (Ta.sub.2O.sub.5).sub.s--(-
Al.sub.2O.sub.3).sub.1-s wherein s ranges from 0.9 to 1, a solid
solution of (Ta.sub.2O .sub.5).sub.t--(ZrO.sub.2).sub.1-t wherein t
ranges from about 0.9 to 1, a solid solution of
(Ta.sub.2O.sub.5).sub.u--(HfO.sub.2).- sub.1-u wherein u ranges
from about 0.9 to 1, and mixtures thereof wherein the interfacial
layer separates the high dielectric constant layer from the
substrate; (c) depositing a layer of electrically conductive
material on the high dielectric constant layer; (d) selectively
removing portions of the layer of electrically conductive material
to form a gate electrode and to expose portions of the high
dielectric constant layer; (e) implanting impurity ions through the
exposed portions of the high dielectric constant layer into the
substrate to form source and drain regions of a second conductivity
type; (f) forming first spacers that are adjacent the gate
electrode and cover portions of the source and drain regions of the
second conductivity type; (g) removing the exposed portions of the
high dielectric constant layer; (h) implanting a second dose of
impurity ions into the source and drain regions; (i) depositing a
layer of insulator material over the surface of the device; (j)
optionally, planarizing the surface of the insulator material; (k)
removing portions of the insulator material to form contact holes
in the insulator material that are in communication with the source
and drain regions; and (l) filling the contact holes with contact
material.
2. The method of claim 1 comprising the step of densifying the high
dielectric constant layer.
3. The method of claim 1 wherein the electrically conductive
material comprises metal that is selected from the group consisting
of TiN, W, Ta, Mo and multilayers thereof.
4. The method of claim 1 wherein the electrically conductive
material comprises doped polysilicon.
5. The method of claim 4 further comprising the step of forming a
barrier layer between the electrically conductive material and the
high dielectric constant layer.
6. The method of claim 1 further comprising the step of forming
second spacers that are adjacent the first spacers and cover
portions of the source and drain regions following step (g) and
before step (h).
7. The method of claim 1 further comprising the step of forming a
silicide layer on the source and drain regions following step
(h).
8. The method of claim 7 wherein forming the silicide layer
comprises the steps of: depositing a layer of metal over the at
least the source and drain regions; heating the layer of metal to
cause the metal to react with the silicon on the surface of the
source and drain regions to form metal silicide layers in the
source and drain regions; and removing unreacted metal from the
layer of metal.
9. The method of claim 7 wherein forming the silicide layer
comprises selectively depositing silicide over the source and drain
regions.
10. The method of claim 1 wherein the high dielectric constant
material layer has a thickness that ranges from about 4 nm to 12
nm.
11. The method of claim 1 wherein the interfacial layer comprises
silicon oxide, silicon nitride, or silicon oxynitride.
12. The method of claim 1 wherein step (h) comprises introducing a
light dosage of impurities to form lightly doped source and drain
regions.
13. The method of claim 1 wherein the high dielectric constant
material is Ta.sub.2O.sub.5.
14. The method of claim 1 wherein the high dielectric constant
material is Ta.sub.2(O.sub.1-xN.sub.x).sub.5 wherein x ranges from
greater than 0 to 0.6.
15. The method of claim 1 wherein the high dielectric constant
material is a solid solution
(Ta.sub.2O.sub.5).sub.r--(TiO.sub.2).sub.1-r wherein r preferably
ranges from about 0.9 to 1.
16. The method of claim 1 wherein the high dielectric constant
material is a solid solution
(Ta.sub.2O.sub.5).sub.s--(Al.sub.2O.sub.3).sub.1-s wherein s ranges
from 0.9 to 1.
17. The method of claim 1 wherein the high dielectric constant
material is a solid solution
(Ta.sub.2O.sub.5).sub.t--(ZrO.sub.2).sub.1-t wherein t ranges from
about 0.9 to 1.
18. The method of claim 1 wherein the high dielectric constant
material is a solid solution of
(Ta.sub.2O.sub.5).sub.u--(HfO.sub.2).sub.1-u wherein u ranges from
about 0.9 to 1.
19. The method of claim 1 wherein the substrate comprises
silicon.
20. The method of claim 1 wherein the first spacers comprise an
oxide or nitride material.
21. The method of claim 1 wherein step (i) comprises depositing a
conformal layer of insulator material and (j) planarizes the
surface of the insulator material by chemical mechanical
planarization.
22. An MOS transistor formed on a semiconductor substrate of a
first conductivity type comprising: (a) an interfacial layer formed
on the substrate; (b) a high dielectric constant layer covering the
interfacial layer that comprises a material that is selected from
the group consisting of Ta.sub.2O.sub.5,
Ta.sub.2(O.sub.1-xN.sub.x).sub.5 wherein x ranges from greater than
0 to 0.6, a solid solution of
(Ta.sub.2O.sub.5).sub.r--(TiO.sub.2).sub.1-r wherein r ranges from
about 0.9 to 1, a solid solution (Ta.sub.2O
.sub.5).sub.s--(Al.sub.2O.sub.3).su- b.1-s wherein s ranges from
0.9 to 1, a solid solution of
(Ta.sub.2O.sub.5).sub.t--(ZrO.sub.2).sub.1-t wherein t ranges from
about 0.9 to 1, a solid solution of
(Ta.sub.2O.sub.5).sub.u--(HfO.sub.2).sub.1-- u wherein u ranges
from about 0.9 to 1, and mixtures thereof wherein the interfacial
layer separates the high dielectric constant layer from the
substrate; (c) a gate electrode having a width of less than 0.3
micron covering the high dielectric constant layer; (d) first and
second lightly doped regions of a second conductivity type disposed
on respective areas of the substrate surface; (e) a source and
drain regions of a second conductivity type; and (f) a pair of
spacers formed adjacent to the gate electrode and formed on the
high dielectric constant layer.
23. The MOS transistor of claim 22 comprising: (g) an insulator
layer covering the device and defining a first contact hole that is
filled with a first contact material and a second contact hole that
are filled with a second contact material, wherein the insulator
layer has a substantially planar surface.
24. The MOS transistor of claim 22 wherein the gate electrode is
formed from a metal that is selected from the group consisting of
TiN; W, Ta, MO and multilayers thereof.
25. The MOS transistor claim 22 wherein the gate electrode
comprises doped polysilicon.
26. The MOS transistor of claim 25 comprising a barrier layer
between the gate electrode and the high dielectric constant
layer.
27. The MOS transistor of claim 22 comprising a pair of second
spacers that are adjacent to the first spacers and formed on the
lightly doped regions.
28. The MOS transistor of claim 22 comprising a silicide layer on
the source and drain regions.
29. The MOS transistor of claim 22 wherein the high dielectric
constant material layer has a thickness that ranges from about 4 nm
to 12 nm.
30. The MOS transistor of claim 22 wherein the high dielectric
constant material is Ta.sub.2O.sub.5.
31. The MOS transistor of claim 22 wherein the high dielectric
constant material is Ta.sub.2(O.sub.1-xN.sub.x).sub.5 wherein x
ranges from 0 to 0.6.
32. The MOS transistor of claim 22 herein the high dielectric
constant material is a solid solution of
(Ta.sub.2O.sub.5).sub.r--(TiO.sub.2).sub.- 1-r wherein r preferably
ranges from about 0.9 to 1.
33. The MOS transistor of claim 22 wherein the high dielectric
constant material is a solid solution
(Ta.sub.2O.sub.5).sub.s--(Al.sub.2O.sub.3).s- ub.1-s wherein s
ranges from 0.9 to 1.
34. The MOS transistor of claim 22 wherein the high dielectric
constant material is a solid solution
(Ta.sub.2O.sub.5).sub.t--(ZrO.sub.2).sub.1-t wherein t ranges from
about 0.9 to 1.
35. The MOS transistor of claim 22 wherein the high dielectric
constant material is a solid solution of
(Ta.sub.2O.sub.5).sub.u--(HfO.sub.2).sub.- 1-u wherein u ranges
from about 0.9 to 1.
36. The MOS transistor of claim 22 wherein the substrate comprises
silicon.
37. The MOS transistor of claim 22 wherein the first spacers
comprise an oxide or nitride material.
Description
FIELD OF THE INVENTION
[0001] The present invention relates generally to methods for
fabricating integrated circuits using metal oxide semiconductor
(MOS) technology. More particularly, the present invention relates
to MOS devices with a gate width of less than 0.3 micron.
BACKGROUND OF THE INVENTION
[0002] Metal oxide semiconductors are well known in the art. With
the rapid integration of elements in the device, the thickness of
the silicon oxide gate dielectric layer has approached the 2 nm
thickness level. Such thin gate oxide layers require stringent
protocols during fabrication especially in the gate etching
process. In addition, concomitant with this reduction in the
thickness of the gate oxide layer is the device's high leakage
current caused by direct tunneling effects.
[0003] Shinriki et. al., U.S. Pat. No. 5,292,673 describes a MOSFET
that contains a tantalum pentoxide gate insulating film. Although
the patent asserts that the device exhibits improved electrical
characteristics, nevertheless, it is believed that the device
suffers from, among other things, high leakage currents because of
the silicon oxide layer, which is formed by reoxidation between the
tantalum pentoxide gate insulating film and the silicon substrate,
has defects including non-uniformity.
SUMMARY OF THE INVENTION
[0004] The present invention is based in part on the recognition
that employing a gate dielectric layer formed at least in part from
a high dielectric constant material comprising Ta.sub.2O.sub.5 will
significantly improve the performance of the MOS device by, among
other things, reducing or eliminating the current leakage
associated with prior art devices.
[0005] Accordingly, in one aspect the invention is directed to a
method for fabricating an MOS device having a gate width of less
than 0.3 micron that includes the steps of:
[0006] (a) forming an interfacial layer on a semiconductor
substrate of a first conductive type wherein the interfacial is
preferably sufficiently thin to limit parasitic capacitance of the
device;
[0007] (b) forming a high dielectric constant layer on the
interfacial layer that comprises a material that is selected from
the group consisting of Ta.sub.2O.sub.5,
Ta.sub.2(O.sub.1-xN.sub.x).sub.5 wherein x ranges from greater than
0 to 0.6, a solid solution of
(Ta.sub.2O.sub.5).sub.r--(TiO.sub.2).sub.1-r wherein r ranges from
about 0.9 to 1, a solid solution
(Ta.sub.2O.sub.5).sub.s--(Al.sub.2O.sub.3).sub- .1-s wherein s
ranges from 0.9 to 1, a solid solution of
(Ta.sub.2O.sub.5).sub.t--(ZrO.sub.2).sub.1-t wherein t ranges from
about 0.9 to 1, a solid solution of
(Ta.sub.2O.sub.5).sub.u--(HfO.sub.2).sub.1-- u wherein u ranges
from about 0.9 to 1, and mixtures thereof wherein the interfacial
layer separates the high dielectric constant layer from the
substrate;
[0008] (c) depositing a layer of electrically conductive material
on the high dielectric constant layer;
[0009] (d) selectively removing portions of the layer of
electrically conductive material to form a gate electrode and to
expose portions of the high dielectric constant layer;
[0010] (e) implanting impurity ions through the exposed portions of
the high dielectric constant layer into the substrate to form
source and drain regions of a second conductive type;
[0011] (f) forming first spacers that are adjacent the gate
electrode and cover portions of the source and drain regions of the
second conductive type;
[0012] (g) removing the exposed portions of the high dielectric
constant layer;
[0013] (h) implanting a second dose of impurity ions into the
source and drain regions;
[0014] (i) depositing a layer of insulator material over the
surface of the device, wherein the layer of insulator material may
have an irregular surface;
[0015] (j) optionally, planarizing the surface of the insulator
material;
[0016] (k) removing portions of the insulator material to form
contact holes in the insulator material that are in communication
with the source and drain regions; and
[0017] (l) filling the contact holes with contact material.
[0018] In preferred embodiments, the electrically conductive
material comprises metal that is selected from the group consisting
of TiN, W, Ta, Mo and mixtures thereof. Alternatively, the
electrically conductive material comprises doped polysilicon.
[0019] In another embodiment the method includes the step of
forming second spacers that are adjacent the first spacers and
cover portions of the source and drain regions following step (g)
and before step (h) and/or the step of forming a silicide layer on
the source and drain regions following step (h).
[0020] In another aspect, the invention is directed to an MOS
transistor formed on a semiconductor substrate of a first
conductivity type that includes:
[0021] (a) an interfacial layer formed on the substrate;
[0022] (b) a high dielectric constant layer covering the
interfacial layer that comprises a material that is selected from
the group consisting of Ta.sub.2O.sub.5,
Ta.sub.2(O.sub.1-xN.sub.x).sub.5 wherein x ranges from greater than
0 to 0.6, a solid solution of (Ta.sub.2O.sub.5).sub.r--(TiO.-
sub.2).sub.1-r wherein r ranges from about 0.9 to 1, a solid
solution (Ta.sub.2O.sub.5).sub.s--(Al.sub.2O.sub.3).sub.1-s wherein
s ranges from 0.9 to 1, a solid solution of
(Ta.sub.2O.sub.5).sub.t--(ZrO.sub.2).sub.1-- t wherein t ranges
from about 0.9 to 1, a solid solution of
(Ta.sub.2O.sub.5).sub.u--(HfO.sub.2).sub.1-u wherein u ranges from
about 0.9 to 1, and mixtures thereof wherein the interfacial layer
separates the high dielectric constant layer from the
substrate;
[0023] (c) a gate electrode having a width of less than 0.3 micron
covering the high dielectric constant layer;
[0024] (d) first and second lightly doped regions of a second
conductivity type disposed on respective areas of the substrate
surface;
[0025] (e) a source and drain regions of the second conductivity
type; and
[0026] (f) a pair of spacers formed adjacent to the gate electrode
and formed on the high dielectric constant layer.
[0027] In a preferred embodiment, the MOS transistor also includes
an insulator layer covering the device and defining a first contact
hole that is filled with a first contact material and a second
contact hole that are filled with a second contact material,
wherein the insulator layer has a substantially planar surface.
BRIEF DESCRIPTION OF THE DRAWINGS
[0028] FIGS. 1A through 1H illustrate the steps in fabricating an
MOS device according to the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0029] It is to be noted that "n+" and "n-" are used throughout the
present disclosure. The short hand notation specifies the electron
concentration of various regions of a metal-oxide-semiconductor
device. For instance, "n-" specifies a region of light electron
concentration (on the order of 1.times.10.sup.18 cm.sup.-3) while
"n+" specifies a region of high electron concentration (on the
order of 1.times.10.sup.20 cm.sup.-3).
[0030] FIGS. 1A-1H illustrate an exemplary method for fabricating
an integrated circuit device with the inventive process. A p type
semiconductor substrate will be employed for illustrative purposes.
Therefore, n- source and n- drain regions and n+ source and n+
drain regions are formed in the substrate. Referring to FIG. 1A,
silicon substrate 100 has an interfacial layer 105 preferably
comprising SiO.sub.2, Si.sub.3N.sub.4, or silicon oxynitride formed
on an upper surface of the substrate. The interfacial layer is
formed by conventional processes, such as, for example, rapid
thermal processing (RTP), thermal annealing, CVD, plasma
nitridation or oxidation, or wet chemical treatment, such as
immersion into boiling nitric acid. A preferred method of forming
the interfacial layer comprises exposing the silicon substrate in
an RF or microwave plasma in an atmosphere containing ozone,
oxygen, N.sub.2O, nitrogen, or mixtures thereof. The interfacial
layer serves to prevent reaction of Ta.sub.2O.sub.5 in layer 110
with the silicon substrate. The interfacial layer will have a
thickness that is sufficient to prevent reaction between the high
dielectric constant layer and the silicon substrate and the
thickness typically ranges from about 1 nm to 5 nm and preferably
about 1 nm to 2 nm.
[0031] Subsequently, high dielectric constant layer 110 and
electrically conductive layer 120 are formed on interfacial layer
105. The high dielectric constant layer 110 preferably comprises
material that is selected from Ta.sub.2O.sub.5,
Ta.sub.2(O.sub.1-xN.sub.x).sub.5 wherein x preferably ranges from
greater than 0 to 0.6, a solid solution of
(Ta.sub.2O.sub.5).sub.r--(TiO.sub.2).sub.1-r wherein r preferably
ranges from about 0.9 to 1, a solid solution of
(Ta.sub.2O.sub.5).sub.s--(Al.sub- .2O.sub.3).sub.1-s wherein s
preferably ranges from 0.9 to 1, a solid solution of
(Ta.sub.2O.sub.5).sub.t--(ZrO.sub.2).sub.1-t wherein t preferably
ranges from about 0.9 to 1, a solid solution of
(Ta.sub.2O.sub.5).sub.u--(HfO.sub.2).sub.1-31 u wherein u ranges
from about 0.9 to 1, and mixtures thereof. Typically, the high
dielectric constant layer will have a thickness that ranges from
about 4 nm to 12 nm and preferably from about 5 nm to 10 nm. The
high dielectric constant layer will form the gate oxide layer. The
particular high dielectric constant materials employed with the
present invention allows for a thicker gate oxide layer to be
formed, resulting in less stringent requirements on gate etching
selectivity during the fabrication process. In addition, it is
believed that during operation of the MOS transistors, the devices
will exhibit a higher transconductance parameter. Further, since Ta
has already been used in MOS fabrication, Ta.sub.2O.sub.5
containing gate oxides are expected to be compatible with the
materials in the other MOS materials. The high dielectric constant
film can be fabricated by conventional means including, for
example, LPCVD, PECVD, ECR CVD, UVCVD, and reactive sputtering.
[0032] In particular Ta.sub.2O.sub.5 films can be prepared by
chemical vapor deposition (CVD) and physical vapor deposition (PVD)
as described in Alers et al., "Nitrogen Plasma Annealing for Low
Temperature Ta.sub.2O.sub.5 Films", Appl. Phys. Lett., Vol. 72,
(11), March 1998, pages 1308-1310. Ta.sub.2(O.sub.1-xN.sub.x).sub.5
films can be prepared by thermal CVD or plasma-assisted CVD as
described in U.S. Pat. No. 5,677,015.
(Ta.sub.2O.sub.5).sub.r--(TiO.sub.2).sub.1-r films can be prepared
by RF magnetron sputtering deposition as described in Gan et al.
"Dielectric property of
(TiO.sub.2).sub.x--(Ta.sub.2O.sub.5).sub.1-x Thin Films", Appl.
Phys. Lett. Vol. 72, (3), January 1998, pages 332-334 or by
chemical CVD as described in U.S. Pat. No. 4,734,340.
(Ta.sub.2O.sub.5).sub.s--(Al.sub.2O.sub.3).sub.1-s films can be
prepared by metalorganic solution deposition as described in Joshi
et al., "Structural and electrical properties of crystalline
(1-x)Ta.sub.2O.sub.5--xAl.sub.2O.sub.3 thin films fabricated by
metalorganic solution deposition technique", Appl. Phys. Lett. Vol.
71, (10), September 1997. Each of the above cited references is
incorporated herein. Finally, the
(Ta.sub.2O.sub.5).sub.t--(ZrO.sub.2).sub.1-t and
(Ta.sub.2O.sub.5).sub.u--(HfO.sub.2).sub.1-u thin films can be
fabricated by techniques used in fabricating the other solid
solution materials. Prior to formation of the electrically
conductive layer 120, the high dielectric constant material is
preferably subjected to a densification process comprising, for
example, exposing the silicon substrate to a RTP or an RF or
microwave plasma in an atmosphere containing ozone, oxygen,
N.sub.2O, nitrogen, or mixtures thereof. Densification is further
described in Alers et. al. cited above. Densification improves the
high dielectric constant material with respect to the leakage
current of the MOS device made.
[0033] Electrically conductive layer 120 preferably comprises one
or more layers of a high melting metal such as, for example, TiN,
W, Ta, Mo which can be deposited by sputtering. This layer
typically has a thickness that ranges from about 100 nm to 300 nm,
and preferably from about 150 nm to 250 nm. As will be described
herein, this electrically conductive layer will form the gate
electrode in this embodiment.
[0034] An optional oxide layer can be deposited and patterned over
the electrically conductive layer 120. Subsequently, a layer of
photoresist material 160 is applied onto electrically conductive
layer 120 before the photoresist is masked and patterned using
conventional photoresist techniques to form a gate pattern. After
etching, the line width (L) of the gate 121 is typically less than
0.3 micron, and preferably equal to or less than about 0.18 micron.
Etching down to the top high dielectric constant layer 110 removes
the exposed electrically conductive material as shown in FIG. 1B.
Source 190 and drain 180 regions are formed by self aligned ion
implantation before the remaining photoresist material 160A is
removed to form the device shown in FIG. 1C. As is apparent,
interfacial layer 105 shown in FIGS. 1A and 1B is not shown in FIG.
1C or subsequent figures although the layer is present in the
structures illustrated.
[0035] Referring to FIG. 1D, spacers 122 are formed by depositing a
phosphosilicate glass (PSG) film 124 over the entire surface of the
device of FIG. 1C and then anisotropic etching the glass. The
spacers can also be made from oxides or nitrides. Subsequently, the
exposed high dielectric constant material is removed by plasma
etching using fluorine or chlorine containing etchant gases to
yield the structure of FIG. 1E. The remaining layer of high
dielectric material 115 serves as the gate oxide. Second spacers
126 are formed by the same procedure as for spacers 122. Lightly
doped source (n-) 129 and drain (n-) 128 regions are then formed by
ion implantation as shown in FIG. 1F with the concomitant formation
of source (n+) 290 and drain (n+) 280 regions.
[0036] Silicide layers 133 and 132 are then formed on the source
and drain. regions. One method comprises the steps of (1)
depositing a layer of suitable metal preferably titanium, cobalt,
or multiple layers of these metals, over the surface of the device
of FIG. 1F, (2) allowing the metal and silicon in the substrate to
react, and thereafter (3) removing unreacted metal. Another method
comprises depositing silicide, e.g., metal.sub.xSi.sub.y, directly
onto source and drain regions using conventional selective
deposition techniques, e.g., CVD.
[0037] Following formation of the silicide regions, a conformal
layer of PSG film 40 is deposited on the structure of FIG. 1G,
thereafter, the top surface of the PSG film is planarized by
conventional techniques such as chemical-mechanical polishing
(CMP). CMP is particularly advantageous when small contact holes
(less than 0.3 micron) are required. Subsequently, contact holes
are etched in the PSG and they then filled with an electrically
conductive, e.g., metal, material 42 and 43 as shown in FIG.
1H.
[0038] As is apparent, the above structure has a metal gate
electrode 121. In an alternative embodiment, instead of a metal
gate electrode, a doped polysilicon gate electrode can be employed.
In this case, a doped polysilicon layer would be deposited in place
of the electrically conductive 120 layer as shown in FIG. 1A.
Optionally, a diffusion barrier layer made from a suitable material
such as, for example, TiN, WN, and TaN, can be deposited between
layers 110 and 120. This barrier layer, which is typically 5 nm to
15 nm thick, prevents polysilicon gate material from reacting with
the tantalum pentoxide in the gate dielectric. In this scenario,
the rest of the process would be essentially the same as above,
however, the preferred silicidation procedure entails depositing a
metal film over the structure so that a polycide layer on the
surface of the doped polysilicon layer is formed as well.
[0039] It is to be emphasized that although n channel transistors
have been described in detail herein, the present invention may
also be practiced as a p channel transistor. In fabricating the p
channel device, the doping conductives of the p channel device are
simply opposite to those of the n channel device.
[0040] Although only preferred embodiments of the invention are
specifically disclosed and described above, it will be appreciated
that many modifications and variations of the present invention are
possible in light of the above teachings and within the purview of
the appended claims without departing from the spirit and intended
scope of the invention.
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