U.S. patent application number 10/695262 was filed with the patent office on 2004-05-06 for oscillator with tunable capacitor.
This patent application is currently assigned to Intel Corporation, a Delaware Corporation. Invention is credited to Fulton, Robert, Lee, Tea, Senthilkumar, Chinnugounder.
Application Number | 20040085141 10/695262 |
Document ID | / |
Family ID | 21990495 |
Filed Date | 2004-05-06 |
United States Patent
Application |
20040085141 |
Kind Code |
A1 |
Senthilkumar, Chinnugounder ;
et al. |
May 6, 2004 |
Oscillator with tunable capacitor
Abstract
Circuitry for controlling the oscillation frequency of an
oscillator by using a digitally tunable on-chip capacitor bank. The
capacitor bank includes a plurality of on-chip capacitors, each of
which is independently selectable by a control signal for providing
a selectable amount of capacitance to the oscillator to control the
oscillator's oscillation frequency.
Inventors: |
Senthilkumar, Chinnugounder;
(Folsom, CA) ; Fulton, Robert; (Folsom, CA)
; Lee, Tea; (Sacramento-Rancho Cordova, CA) |
Correspondence
Address: |
FISH & RICHARDSON, PC
12390 EL CAMINO REAL
SAN DIEGO
CA
92130-2081
US
|
Assignee: |
Intel Corporation, a Delaware
Corporation
|
Family ID: |
21990495 |
Appl. No.: |
10/695262 |
Filed: |
October 27, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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10695262 |
Oct 27, 2003 |
|
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|
10054358 |
Jan 17, 2002 |
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Current U.S.
Class: |
331/36C |
Current CPC
Class: |
H03B 5/368 20130101 |
Class at
Publication: |
331/036.00C |
International
Class: |
H03L 007/00 |
Claims
What is claimed is:
1. Circuitry for controlling the oscillating frequency of an
oscillator, the circuitry comprising: a plurality of capacitors,
each of which is independently selectable by a control signal, and
each of which provides a controllable amount of capacitance to the
oscillator to control the oscillating frequency of the
oscillator.
2. The circuitry of claim 1, wherein each of the plurality of
capacitors has a different capacitance than the other capacitors,
and a predefined amount of capacitance is provided by a
predetermined combination of capacitors.
3. The circuitry of claim 2, wherein the capacitors are
drain-source connected MOSFETs.
4. The circuitry of claim 3, wherein the MOSFETs are P-type
enhancement mode MOSFETs.
5. The circuitry of claim 3, wherein the MOSFETs are N-type
depletion mode MOSFETs.
6. The circuitry of claim 1 wherein the capacitors are selected
from the group consisting of on-chip metal capacitors, on-chip poly
capacitors, and discrete capacitors.
7. The circuitry of claim 1, wherein each of the capacitors
corresponds to a transmission gate switch.
8. The circuitry of claim 7, further comprising a set of memory
registers to provide the control signals for selecting the
individual capacitors
9. The circuitry of claim 8, wherein the transmission gate switches
are decoupled from the set of memory registers by a set of buffer
circuitry.
10. The circuitry of claim 9, wherein the set of buffer circuitry
is powered by a filtered power signal.
11. The circuitry of claim 1, wherein the oscillator includes a
resonator and an inverting amplifier.
12. The circuitry of claim 11, wherein a first subset of the
plurality of capacitors is selectively electrically coupled to a
first terminal of the resonator, and a second subset of the
plurality of capacitors is selectively electrically coupled to a
second terminal of the resonator
13. An electronic device comprising: a real time clock for
generating a system time signal, the real time clock having a
digitally tunable oscillator for digitally adjusting an operating
frequency of the real time clock to speed up or slow down the
system time signal; and a memory device for storing data
representing a configuration of the digitally adjusted tunable
oscillator.
14. The electronic device of claim 13, further comprising a
communication port for receiving a reference time signal, wherein
the digitally tunable oscillator is digitally adjusted according to
the reference time signal to minimize the difference between the
system time signal and the reference time signal.
15. The electronic device of claim 13, wherein the digitally
tunable oscillator includes a capacitor bank having a set of
capacitors with capacitance values in a binary-weighted
relationship, the capacitors selectable through a set of control
signals.
16. A method comprising: generating a set of control signals to
select a subset of capacitors from a set of capacitors; connecting
the selected subset of capacitors to an oscillator; generating an
oscillating signal using the oscillator and the selected subset of
capacitors in combination; and generating a system time signal
using the oscillating signal.
17. The method of claim 16, further comprising receiving a
reference time signal, comparing the reference time signal with the
system time signal, and modifying the set of control signals in
response to the difference between the reference time signal and
the system time signal to select a different subset of
capacitors.
18. The method of claim 17, further comprising saving data
representing the setting of the control signals in a memory.
19. A method of generating a time signal comprising: generating a
system time signal using a real time clock circuit that has a
tunable oscillator for adjusting an operation frequency of the real
time clock circuit; receiving a reference time signal over a
network; adjusting the tunable oscillator to increase or decrease
the operating frequency of the real time clock circuit in response
to a difference between the system time signal and the reference
time signal.
20. The method of claim 19 wherein adjusting the tunable oscillator
comprises adjusting a set of control signals to modify a selection
of a set of capacitors within a capacitor bank, the selection of
the set of capacitors correlating to the operating frequency of the
real time clock circuit.
21. Apparatus for providing a variable level of capacitance,
comprising: a plurality of capacitors, each capacitor selectable
through an independent control signal generated by a logic circuit,
the selected capacitors providing an amount of capacitance that is
the sum of the individual capacitances of the selected capacitors;
and buffer circuitry for decoupling the plurality of capacitors
from the logic circuit to prevent noise in the logic circuit from
affecting the plurality of capacitors.
22. The apparatus of claim 21, further comprising a filter circuit
connected to a power supply to generate a filtered power supply
signal that is used to power the buffer circuitry.
23. The circuit of claim 21, further comprising transmission gates,
each of which corresponds to one of the plurality of capacitors and
can be turned on by the independent control signal when the
corresponding capacitor is selected.
24. Apparatus comprising: a control unit configured to generate a
set of control signals, each of which independently selects a
capacitor from a plurality of capacitors, the selected capacitors
being coupled to an oscillator, the selected capacitors in
combination proving a controllable amount of capacitance to the
oscillator to control the oscillating frequency of the
oscillator.
25. The apparatus of claim 24 in which the control unit is disposed
within a computer chipset.
26. The apparatus of claim 24, further comprising circuitry for
generating a system time signal based on the oscillating frequency
of the oscillator.
27. The apparatus of claim 26, further comprising a memory for
storing the configuration of the set of control signals, and a data
processing unit that processes data based on the system time
signal.
Description
TECHNICAL FIELD
[0001] This invention relates to oscillator circuits, and more
particularly to tunable oscillator circuits.
BACKGROUND
[0002] Oscillator circuits can be used to provide timing
signals.
[0003] For example, a personal computer motherboard typically has a
Real Time Clock (RTC) circuit that provides an accurate 32.768 KHz
oscillating signal that is further processed to obtain the second,
minute, and hour values used by the computer system to keep
time.
[0004] The RTC circuit is typically part of an I/O controller hub
chip (sometimes referred to as the south-bridge chipset), and is
connected to an external crystal resonator that resonates within a
narrow range of operating frequencies. Depending on the crystal
oscillator topology, one or more discrete external load capacitors
may be connected to the RTC circuit to tune the oscillating
frequency. The values of the load capacitors are selected according
to an initial circuit layout design so that the RTC circuit in
conjunction with the external components will oscillate at a
predetermined frequency.
[0005] However, variation between different motherboard designs may
result in placement of the load capacitors at slightly different
locations on the motherboard, resulting in the addition of a
certain amount of parasitic capacitance associated with the wiring
connections. Other factors, such as tolerances in circuit
components and minute routing differences, will also affect the
oscillating frequency. Because a small variance in the oscillating
frequency may significantly affect the accuracy of the system time
signal over time, individual tuning of the capacitance value
tailored to a specific motherboard design is required to obtain
accurate system timing signals.
[0006] The details of one or more embodiments of the invention are
set forth in the accompanying drawings and the description below.
Other features, objects, and advantages of the invention will be
apparent from the description and drawings, and from the
claims.
DESCRIPTION OF DRAWINGS
[0007] FIG. 1 is a schematic diagram of a computer chipset with
external components that form a digitally tunable oscillator.
[0008] FIG. 2 is a schematic diagram of an on-chip capacitor bank
of the oscillator circuit of FIG. 1.
[0009] FIG. 3 is a schematic diagram of a buffer circuit connected
to a transmission gate switch.
[0010] FIG. 4 is a schematic diagram of an alternative embodiment
of an on-chip capacitor bank.
[0011] FIG. 5 is a block diagram of an electronic device.
[0012] Like reference symbols in the various drawings indicate like
elements.
DETAILED DESCRIPTION
[0013] As will be described in more detail below, the invention is
directed towards circuitry for controlling oscillating frequency of
an oscillator. In addition to the external load capacitors, the
circuitry includes on-chip capacitors, each of which is
independently selectable by a control signal, and each of which
provides a controllable amount of capacitance to the oscillator to
control the oscillating frequency of the oscillator. The term
"on-chip capacitor" means that the capacitor is manufactured on a
semiconductor chip.
[0014] Referring to FIG. 1, a tunable clock oscillator circuit 100
(enclosed in dotted lines) includes two digitally selectable
on-chip capacitor banks 106 and 108 connected to a terminal X.sub.1
and a terminal X.sub.2, respectively, of a crystal resonator 102.
Terminals X.sub.1 and X.sub.2 are connected to an input terminal
110 and an output terminal 112, respectively, of an inverting
amplifier 104. A feedback resistor R.sub.f is connected in parallel
to resonator 102 to bias amplifier 104 into a linear mode.
Capacitor banks 106 and 108 are used to fine-tune the oscillating
frequency of oscillator circuit 100. By selecting different
combinations of capacitors in the on-chip capacitor banks, a
different amount of capacitance can be connected to resonator 102,
thereby controlling the oscillating frequency of oscillator circuit
100.
[0015] Two external load capacitors C.sub.L1 and C.sub.L2 are
connected to terminals X.sub.1 and X.sub.2, respectively. The
capacitance values of load capacitors C.sub.L1 and C.sub.L2 are
selected according to specifications given by the manufacturer of
resonator 102. The impedance of load capacitors, combined with the
crystal's calibrated impedance, tunes the circuit to operate in a
particular frequency in the "parallel or series resonance" area
(depending on oscillator topology). For example, resonator 102
resonates at approximately 32.77 KHz, capacitors C.sub.L1 and
C.sub.L2 have capacitances of about 15 pF, and resistor R.sub.f has
a value of about 10 MegOhms.
[0016] Capacitor banks 106 and 108 each include an array of
capacitors that are individually selectable by a set of externally
provided control signals to provide a variable amount of
capacitance. For example, capacitor banks 106 and 108 each provide
a selectable amount of capacitance in the range of 0 to 4 pF.
[0017] Amplifier 104 and capacitor banks 106, 108 are located
within an RTC circuit 122 (enclosed in dotted lines), which is part
of a chipset 114 of a computer system. RTC circuit 122 has a set of
latches 120 that latches a set of control signals S.sub.0 to
S.sub.9 that is generated by programmable registers 118 of chipset
114. Control signals S.sub.0 to S.sub.9 are used to select the
individual capacitors in capacitor banks 106 and 108.
[0018] RTC circuit 122 is powered by a system power supply, as well
as a separate battery supply when the computer system is turned
off. When the battery supply is first connected to RTC circuit 122,
default values are loaded into the latches to select a default set
of capacitors. When the computer is initially booted up after RTC
circuit 122 is connected to the battery supply, a predefined
register setting is read from a BIOS memory 116 and passed through
chipset registers 118 to latches 120. The latches store the
register setting for the life of the battery, or until the setting
is changed by chipset registers 118.
[0019] The load capacitors C.sub.L1 and C.sub.L2 are shown as being
connected outside of chipset 114. However, it is understood that
the load capacitors C.sub.L1 and C.sub.L2 may also be integrated
within chipset 114. It is also possible to integrate the resonator,
load capacitors, resistor, and the RTC circuitry within the same
package.
[0020] Referring to FIG. 2, capacitor bank 106 has a capacitor
array 202 that includes five capacitors, C.sub.0 to C.sub.4. Each
capacitor is selectable by one of the control signals S.sub.0 to
S.sub.4 through control gate switches G.sub.0 to G.sub.4. The
capacitance values of the capacitors have a binary-weighted
relationship, such that C.sub.4 has twice the amount of capacitance
as C.sub.3, C.sub.3 has twice the amount of capacitance of C.sub.2,
and so forth. For example, C.sub.4=2 pF, C.sub.3=1 pF, C.sub.2=0.5
pF, C.sub.1=0.25 pF, C.sub.0=0.125 pF.
[0021] Chipset registers 118 provide control signals S.sub.0 to
S.sub.4, which are latched by latches 120. A control signal selects
a capacitor by turning on the corresponding control gate switch so
that one terminal of the capacitor is connected to terminal 110 of
crystal resonator 102. To obtain a certain value of capacitance,
chipset registers 118 select a number of capacitors so that the sum
of the capacitances of the selected capacitors most closely
approximate the desired capacitance value. Capacitor bank 108
operates similarly to capacitor bank 106.
[0022] Capacitors C.sub.0 to C.sub.4 are enhancement mode P-type
MOSFETs (PMOS) with the drain nodes connected to the source nodes.
The gate of the MOSFET functions as one terminal of the capacitor,
and the drain/source node functions as the other terminal. A
V.sub.cc.sub..sub.--FILTER signal is derived from the power supply
signal V.sub.cc to bias the PMOS capacitors into saturation. Most
of the high frequency noise contained in the V.sub.cc signal is
filtered by a low pass filter composed of resistor R.sub.bias and
capacitor C.sub.bias. The V.sub.cc.sub..sub.--FILTER signal also
provides a filtered power supply signal to a buffer circuit that
drives transmission gate switches (FIG. 3). Use of the low pass
filter also enables low power operation because capacitor
C.sub.bias blocks direct current from flowing.
[0023] Referring to FIG. 3, a control gate switch G.sub.0 includes
a buffer circuit 302 and a transmission gate T.sub.0. Buffer
circuit 302 is used to decouple transmission gate switch T.sub.0
from logic circuit that produces signal S.sub.0. This is to prevent
noise generated in the chipset logic circuit from reaching
oscillator circuit 100 through transmission gate switch T.sub.0.
Buffer circuit 302 is powered by the V.sub.cc.sub..sub.--FILTER
signal. Use of V.sub.cc.sub..sub.--FILTER signal is required to
prevent unwanted noise in the RTC power supply signal from
interfering with the operation of oscillator circuit 100.
Additional buffer circuits (having the same configuration as buffer
circuit 302) are provided to decouple transmission gate switches
T.sub.1 to T.sub.9 from the logic circuits that produce signals
S.sub.1 to S.sub.9.
[0024] FIG. 4 shows an example of an on-chip capacitor bank
constructed from "depletion mode" NMOS transistors. An on-chip
capacitor bank 402 includes an on-chip capacitor array 404 and
control gates G.sub.10 to G.sub.14. Capacitor array 404 includes
depletion mode NMOS capacitors C.sub.10 to C.sub.14, each of which
is made of an N-type MOSFET, with one terminal of the capacitor
being the gate node of the MOSFET, and the other terminal of the
capacitor being the source-drain connected node of the MOSFET.
[0025] When NMOS capacitors are used, it is not necessary to use
V.sub.cc.sub..sub.--FILTER signal to bias the capacitors into
saturation. This is because a depletion mode transistor has a
negative threshold voltage, so a channel is formed for all
non-negative oscillation voltage levels, and thus provides a
greater capacitance. Because V.sub.cc.sub..sub.--FILTER is used
only to power the logic gates of buffer circuit 302, smaller values
for resistor R.sub.bias and capacitor C.sub.bias can be used. This
allows for reduction of the size of the capacitor bank 402 because
the "series effect" of the capacitor bank and the capacitor
C.sub.bias is eliminated.
[0026] An advantage of using tunable capacitor banks 106, 108 is
that the computer system can dynamically adjust the oscillating
frequency of oscillator circuit 100 based on a reference time
signal. The computer may log on to the Internet at regular time
intervals, and compare the system time signal with a reference time
signal, such as that provided by the NIST Internet Time Service.
Based on the difference between the system time and reference time,
chipset 114 may change the setting of registers 118 to select a
different arrangement of capacitors in capacitor banks 106 and 108.
By selecting a slightly higher or lower amount of capacitance to be
connected to crystal resonator 102, chipset 114 can fine-tune the
oscillating frequency of oscillator circuit 100. After each
adjustment, the chipset register setting are latched by latches 120
so that oscillator circuit 100 can provide accurate time signals
even after system is powered down or off.
[0027] Another advantage of using tunable capacitor banks in an
oscillator circuit is that adjustment of the oscillation frequency
can be performed after the hardware connections of the electronic
components and circuit boards are fixed. Due to tolerances in the
components and boards, the actual capacitance connected to the
crystal resonator is often slightly different from the capacitance
values in the original design. By adjusting the amount of
capacitance provided by the tunable capacitor banks, oscillation
frequency can be tuned without altering any hardware component or
connection. The adjustment can be done manually or automatically
through appropriate software.
[0028] Use of tunable capacitor banks is not limited to the RTC
circuit of computer systems. All circuits that require fine-tuning
of an accurate amount of capacitance may use a tunable capacitor
bank. All electronic devices that require an accurate oscillating
signal may use tunable capacitor banks to fine-tune the oscillation
frequency. The fine-tuning of the oscillation frequency may be used
to compensate changes in temperature and humidity, or to compensate
manufacturing tolerances. Such fine-tuning of the oscillation
frequency after hardware connections are fixed allows more
flexibility in the selection of electronic components and circuit
board layout designs.
[0029] Referring to FIG. 5, an electronic device 500 includes a
chipset 508 that has a RTC circuit 514 that provides a stable clock
signal. RTC circuit 514 includes two tunable on-chip capacitor
banks connected to each of the two terminals of a resonator 102.
The RTC circuit 514 is powered by both a main power supply and a
battery supply so that it can keep the oscillation even when the
main power supply is shut off.
[0030] Chipset 508 includes a set of latches that store a set of
register bit values used to control the selection of on-chip
capacitors in the capacitor banks. When chipset 508 is delivered to
a manufacturer of device 500, the latches store default values.
When the manufacturer designs a circuit board using the chipset
508, the manufacturer may decide to modify the values stored in the
latches by writing new register bit values into a BIOS 116.
[0031] When the battery is first inserted to provide power to RTC
circuit 514, the register bit values are read from BIOS 116 and
passed to the latches. Chipset 508 includes a register that stores
a "capacitor-set flag" which is used to track whether the register
bit values need to be updated. Initially, the capacitor-set flag is
set to "0". Every time electronic device 500 boots, the
capacitor-set flag is checked. If the flag is set to "1", the latch
values are not changed. If the flag equals "0", the register bit
values stored in BIOS 116 are read and used to overwrite the values
previously stored in the latches. The capacitor-set flag is then
set to "1".
[0032] A user can overwrite the register bit values stored in BIOS
116. The user then sets the capacitor-set flag to "1" to prevent
BIOS 116 from overwriting the user-defined settings when device 500
boots the next time. The latch settings may also be modified by an
operating system (OS) running on device 500. For example, the OS
may perform an adjustment to the clock signal. An accurate
reference time signal is received from an input/output device 510.
The OS controls chipset 508 to adjust the latch settings according
to the reference time signal so that RTC circuit 514 provides an
accurate time signal. The OS then sets the capacitor-set flag to
"1" to prevent BIOS 116 from overwriting the latch settings. The
register bit values defined by the user or operating system are
maintained in the latches as long as the battery continues to
provide power to the latches and the RTC circuit.
[0033] Device 500 further includes a processor 502 that processes
data and a memory device 504 that stores data. The electronic
device 500 may be a computer, a handheld device, a consumer
electronics device, or any other device that requires an accurate
time signal.
[0034] A number of embodiments of the invention have been
described. Nevertheless, it will be understood that various
modifications may be made without departing from the spirit and
scope of the invention. For example, the capacitor bank may
incorporate a greater number of capacitors to provide a greater
range of capacitance selection. The capacitance values of the
capacitors in the capacitor bank may have some relationship other
than a binary-weighted relationship so as to provide different
capacitance combinations. The capacitors in the capacitor bank may
be on-chip poly-capacitors or on-chip metal capacitors. The
capacitors in the capacitor bank may even include discrete
capacitors that are not made on a semiconductor chip. The external
capacitors C.sub.L1 and C.sub.L2 may be connected in series to
resonator 102 such that resonator 102 operate in a series resonance
mode. For the capacitor bank of FIG. 2, a series connection with
resistor R.sub.bias and capacitor C.sub.bias is not required if the
oscillator signals remain above the threshold voltage of the
capacitors in the capacitor bank. Device 500 may save the latch
settings in a file in a hard drive 512. The file is loaded each
time after device 500 is booted and used to set the chipset
registers to select appropriate capacitors in the capacitor banks.
This prevents the loss of latch settings in the event that the
battery power is lost. Accordingly, other embodiments are within
the scope of the following claims.
* * * * *