U.S. patent application number 10/664783 was filed with the patent office on 2004-04-29 for electropolishing metal layers on wafers having trenches or vias with dummy structures.
Invention is credited to Wang, Hui, Yih, Peihaur.
Application Number | 20040080053 10/664783 |
Document ID | / |
Family ID | 26806086 |
Filed Date | 2004-04-29 |
United States Patent
Application |
20040080053 |
Kind Code |
A1 |
Wang, Hui ; et al. |
April 29, 2004 |
Electropolishing metal layers on wafers having trenches or vias
with dummy structures
Abstract
A structure is formed on a semiconductor wafer by forming a
dielectric layer with a recessed area and a non-recessed area. A
plurality of dummy structures are formed within the recessed area,
where the dummy structures are inactive areas configured to
increase the planarity of a metal layer subsequently formed on the
dielectric layer. A metal layer is then formed to fill the recessed
area and cover the non-recessed area and the plurality of dummy
structures. The metal layer is then electropolished to expose the
non-recessed area.
Inventors: |
Wang, Hui; (Fremont, CA)
; Yih, Peihaur; (Newark, CA) |
Correspondence
Address: |
Peter J. Yim
Morrison & Foerster LLP
425 Market Street
San Francisco
CA
94105-2482
US
|
Family ID: |
26806086 |
Appl. No.: |
10/664783 |
Filed: |
September 16, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10664783 |
Sep 16, 2003 |
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10108614 |
Mar 27, 2002 |
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6638863 |
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60286273 |
Apr 24, 2001 |
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Current U.S.
Class: |
257/774 ;
257/773; 257/786; 257/E21.583 |
Current CPC
Class: |
C25D 5/48 20130101; C25D
7/123 20130101; H01L 21/32125 20130101; C25D 5/02 20130101; H01L
21/7684 20130101 |
Class at
Publication: |
257/774 ;
257/786; 257/773 |
International
Class: |
H01L 023/48 |
Claims
We claim:
1. A pad structure for providing electrical contact for
interconnections in a semiconductor wafer comprising: a metal
layer; and a dielectric layer having: a plurality of vias, wherein
the metal layer fills the vias to form plugs, and a plurality of
dummy structures disposed within the pad structure, wherein the
dummy structures are inactive areas configured to increase the
planarity of the metal layer.
2. The pad structure of claim 1, further comprising a barrier layer
disposed between the dielectric layer and the metal layer.
3. The pad structure of claim 1, further comprising a seed layer
disposed between the dielectric layer and the metal layer.
4. The pad structure of claim 1, further comprising a cover layer
disposed on the surface of the metal layer and dielectric
layer.
5. The pad structure of claim 1, wherein the metal layer is
copper.
6. The pad structure of claim 1, wherein the plurality of dummy
structures includes the same material as the dielectric layer.
7. The pad structure of claim 1, wherein the plurality of dummy
structures includes a metal.
8. The pad structure of claim 1, wherein the dielectric layer is
formed with a recessed area and a non-recessed area, wherein the
plurality of dummy structures are disposed within the recessed
area, wherein the metal layer is deposited to fill the recessed
area and cover the non-recessed area and the plurality of dummy
structures, and wherein the metal layer is electropolished to
expose the non-recessed area.
9. The pad structure of claim 8, wherein the recessed area has a
depth corresponding to a thickness of the metal layer to remain
within the recessed area after electropolishing and an offset
height corresponding to a distance between a surface of the
non-recessed area to be exposed after electropolishing and a
surface of the metal layer to remain within the recessed area after
electropolishing.
10. The pad structure of claim 9, wherein the exposed non-recessed
area is removed to a depth equal to the offset height.
11. A structure formed on a semiconductor wafer comprising: a
dielectric layer formed on the semiconductor wafer having a
recessed area and a non-recessed area; a plurality of dummy
structures formed within the recessed area, wherein the dummy
structures are inactive areas configured to increase the planarity
of a metal layer subsequently formed on the dielectric layer; a
metal layer formed to fill the recessed area and cover the
non-recessed area and the plurality of dummy structures, wherein
the metal layer is electropolished to expose the non-recessed
area.
12. The structure of claim 11, wherein the recessed area has a
depth corresponding to a thickness of the metal layer to remain
within the recessed area after electropolishing and an offset
height corresponding to a distance between a surface of the
non-recessed area to be exposed after electropolishing and a
surface of the metal layer to remain within the recessed area after
electropolishing.
13. The structure of claim 12, further comprising removing the
exposed non-recessed area to a depth equal to the offset
height.
14. The structure of claim 13, wherein the offset height is between
about 5 nanometers to about 100 nanometers.
15. The structure of claim 11, wherein the metal layer is formed by
depositing the metal layer.
16. The structure of claim 11, wherein the metal layer is formed by
electroplating the metal layer.
17. The structure of claim 11, wherein each dummy structure in the
plurality has a width, wherein the metal layer has a thickness,
wherein the thickness is based on the metal layer formed on the
non-recessed area, and wherein a ratio of the width to the
thickness is between about 0.1 to about 1.
18. The structure of claim 17, wherein the ratio is 0.3.
19. The structure of claim 11, wherein dummy structures in the
plurality are spaced apart from each other by a distance, wherein
the metal layer has a thickness, wherein the thickness is based on
the metal layer formed on the non-recessed area, and wherein a
ratio of the distance to the thickness is between about 1 to about
5.
20. The stucture of claim 19, wherein the ratio is less than 2.
21. The structure of claim 11, further comprising: a barrier layer
formed on the dielectric layer before forming the metal layer.
22. The structure of claim 11, further comprising: a seed layer
formed on the dielectric layer before forming the metal layer.
23. The structure of claim 11, further comprising: a cover layer
formed on the semiconductor wafer after electropolishing the metal
layer.
24. The structure of claim 11, wherein the recessed area is a wide
trench configured to form an interconnection when filled with the
metal layer.
25. The structure of claim 11, wherein the recessed area is a large
rectangular structure configured to form a pad when filled with the
metal layer.
26. The structure of claim 25, wherein the exposed non-recessed
area is removed beyond a surface of the electropolished metal layer
to form a pad that protrudes beyond the dielectric layer to
facilitate contact between the pad and a probe used for electrical
testing.
27. The structure of claim 25, wherein the large rectangular
structure has rounded corners.
28. The structure of claim 11, wherein the metal layer is
copper.
29. The structure of claim 11, wherein the plurality of dummy
structures includes the same material as the dielectric layer.
30. The structure of claim 11, wherein the plurality of dummy
structures includes a metal.
31. A structure formed on a semiconductor wafer comprising: a
dielectric layer formed on the semiconductor wafer, wherein the
dielectric layer is formed with a recessed area and a non-recessed
area; a plurality of dummy structures formed within the recessed
area; a barrier layer formed to cover the recessed area, the
non-recessed area, and the plurality of dummy structures; and a
metal layer formed to fill the recessed area and cover the
non-recessed area and the plurality of dummy structures, wherein
the metal layer is electropolished to expose the barrier layer
deposited on the non-recessed area, and wherein the exposed barrier
layer is removed at a first rate and the non-recessed area of the
dielectric layer is removed at a second rate.
32. The structure of claim 31, wherein the exposed barrier layer
and the non-recessed area of the dielectric layer have even
surfaces after the exposed barrier layer is removed at a first rate
and the non-recessed area of the dielectric layer is removed at a
second rate.
33. The structure of claim 31, wherein the exposed barrier layer
protrudes beyond the non-recessed area after the exposed barrier
layer is removed at a first rate and the non-recessed area is
removed at a second rate.
34. The structure of claim 31, wherein the first rate is equal to
the second rate.
35. The structure of claim 31, wherein the first rate is lower than
the second rate.
36. The structure of claim 31, wherein the exposed barrier layer is
removed at a third rate and wherein the non-recessed area of the
dielectric is removed at a fourth rate.
37. The structure of claim 36, wherein the third rate is higher
than the fourth rate.
38. The structure of claim 37, wherein the fourth rate is zero.
39. The structure of claim 36, wherein the fourth rate is higher
than the third rate.
40. The structure of claim 39, wherein the third rate is zero.
41. The structure of claim 36, wherein the first rate is higher
than the second rate.
42. The structure of claim 36, wherein the exposed barrier layer
and the non-recessed area have even surfaces after the exposed
barrier layer is removed at a third rate and the non-recessed area
is removed at a fourth rate.
43. The structure of claim 36, wherein the exposed barrier layer
protrudes beyond the non-recessed area after the exposed barrier
layer is removed at a third rate and the non-recessed area is
removed at a fourth rate.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application is a divisional of patent
application U.S. Ser. No. 10/108,614, filed Mar. 27, 2002, which
claims priority of an earlier filed provisional application U.S.
Ser. No. 60/286,273, entitled ELECTROPOLISHING METAL LAYERS ON
WAFERS HAVING TRENCHES OR VIAS WITH DUMMY STRUCTURES, filed on Apr.
24, 2001, the entire content of which is incorporated herein by
reference.
BACKGROUND
[0002] 1. Field of the Invention
[0003] The present invention generally relates to semiconductor
wafers. More particularly, the present invention relates to dummy
structures in trenches or vias of semiconductor wafers.
[0004] 2. Description of the Related Art
[0005] In general, semiconductor devices are manufactured or
fabricated on disks of semiconducting materials called wafers or
slices. More particularly, wafers are initially sliced from a
silicon ingot. The wafers then undergo multiple masking, etching,
and deposition processes to form the electronic circuitry of
semiconductor devices.
[0006] In particular, multiple masking and etching processes can be
used to form recessed areas in a wafer, such as trenches, vias, and
the like. In some applications, these recessed areas can form wide
trenches. Deposition processes can be used to deposit metal onto
both the wide trenches and non-recessed areas of the wafer. After
deposition, the metal can be removed from the non-recessed areas of
the wafer, such that the metal left in the wide trenches can form
interconnections. However, because of the width of the wide
trenches, when the metal is removed from the non-recessed areas, a
portion of the metal deposited in the wide trenches can also be
removed beyond a desirable depth. This over-removal, called
dishing, can reduce the cross-sectional area of the
interconnections, thereby increasing the resistance of the
interconnections. This increased resistance can cause reliability
problems in the semiconductor device.
[0007] Accordingly, forming dummy structures within the wide
trenches has been used to reduce dishing when chemical mechanical
polishing (CMP) is used to remove the metal from the non-recessed
areas of the wafer. In particular, the dummy structures can prevent
a CMP polishing pad from moving past the dummy structures and
overpolishing metal in the wide trenches. However, dishing can
still occur if electropolishing is used to remove metal from the
non-recessed areas, even when the wide trenches include dummy
structures.
SUMMARY
[0008] The present invention relates to electropolishing a metal
layer on a semiconductor wafer. In one embodiment of the present
invention, a dielectric layer is formed on the semiconductor wafer.
The dielectric layer is formed with a recessed area and a
non-recessed area. A plurality of dummy structures are formed
within the recessed area, where the dummy structures are inactive
areas configured to increase the planarity of a metal layer
subsequently formed on the dielectric layer. A metal layer is then
formed to fill the recessed area and cover the non-recessed area
and the plurality of dummy structures. The metal layer is then
electropolished to expose the non-recessed area. In one embodiment,
a portion of the non-recessed area is then removed.
DESCRIPTION OF THE DRAWING FIGURES
[0009] The present invention can be best understood by reference to
the following detailed description taken in conjunction with the
accompanying drawing figures, in which like parts may be referred
to by like numerals:
[0010] FIGS. 1A to 1D illustrate, in cross-sectional view, an
exemplary damascene process;
[0011] FIGS. 2A to 2D illustrate, in cross-sectional view, another
exemplary damascene process;
[0012] FIGS. 3A to 3E illustrate, in cross-sectional view, another
exemplary damascene process;
[0013] FIG. 4 illustrates an exemplary wide trench structure;
[0014] FIG. 5 is a flow chart illustrating the steps of an
exemplary damascene process, in accordance with the present
invention;
[0015] FIGS. 6A to 6E illustrate an exemplary process for forming a
metal pad in a semiconductor device;
[0016] FIGS. 7A to 7E illustrate another exemplary process for
forming a metal pad in a semiconductor device;
[0017] FIGS. 8A to 8D illustrate another exemplary process for
forming a metal pad in a semiconductor device;
[0018] FIGS. 9A and 9B illustrate an exemplary semiconductor device
that can be used with various exemplary processes of the present
invention;
[0019] FIGS. 10A and 10B illustrate another exemplary semiconductor
device that can be used with various exemplary processes of the
present invention;
[0020] FIGS. 11A and 11B illustrate another exemplary semiconductor
device that can be used with various exemplary processes of the
present invention;
[0021] FIGS. 12A and 12B illustrates another exemplary
semiconductor device that can be used with various exemplary
processes of the present invention;
[0022] FIG. 13 illustrates an exemplary layout of a large
rectangular structure;
[0023] FIG. 14 illustrates another exemplary layout of a large
rectangular structure;
[0024] FIG. 15 illustrates another exemplary layout of a large
rectangular structure;
[0025] FIG. 16 illustrates another exemplary layout of a large
rectangular structure;
[0026] FIGS. 17A to 17AA illustrate various exemplary shapes that
can be used to form dummy structures;
[0027] FIGS. 18A to 18E illustrate, in cross-sectional view, an
exemplary damascene process;
[0028] FIGS. 19A to 19C illustrate, in cross-sectional view,
another exemplary damascene process;
[0029] FIGS. 20A to 20C illustrate, in cross-sectional view,
another exemplary damascene process;
[0030] FIGS. 21A to 21D illustrate, in cross-sectional view,
another exemplary damascene process;
[0031] FIGS. 22A to 22D illustrate, in cross-sectional view,
another exemplary damascene process;
[0032] FIGS. 23A to 23D illustrate, in cross-sectional view,
another exemplary damascene process;
[0033] FIGS. 24A to 24D illustrate, in cross-sectional view,
another exemplary damascene process;
[0034] FIGS. 25A to 25D illustrate, in cross-sectional view,
another exemplary damascene process;
[0035] FIGS. 26A to 26D illustrate, in cross-sectional view,
another exemplary damascene process; and
[0036] FIGS. 27A to 27D illustrates, in cross-sectional view,
another exemplary damascene process.
DETAILED DESCRIPTION
[0037] In order to provide a more thorough understanding of the
present invention, the following description sets forth numerous
specific details, such as specific configurations, parameters,
examples, and the like. It should be recognized, however, that such
description is not intended as a limitation on the scope of the
present invention, but is intended to provide a better description
of the exemplary embodiments.
[0038] FIG. 1 depicts an exemplary damascene process that can be
used to form interconnections in a semiconductor device that
includes a recessed area having a large width, area, and the like.
In particular, with reference to FIG. 1A, the semiconductor device
can include dielectric 100 having recessed area 102 and
non-recessed area 103, where recessed area 102 can be a structure
such as a wide trench, a large rectangular structure, and the like.
In addition, dielectric 100 can include materials such as silicon
dioxide, and the like, or materials having dielectric constants
lower than silicon dioxide, such as fluorinated silicate glass,
polyimides, fluorinated polyimides, hybrid/composites, siloxanes,
organic polymers, [alpha]-C:F, Si--O--C, parylenes/fluorinated
parylenes, polyterafluoroethylene, nanoporous silica, nanoporous
organic, and the like. Materials having dielectric constants lower
than silicon dioxide can be used to lower the capacitance between
metal interconnections in the semiconductor device.
[0039] In the present exemplary process, a barrier layer 104 can be
deposited on dielectric 100 by any convenient deposition method,
such as chemical vapor deposition (CVD), physical vapor deposition
(PVD), atomic layer deposition (ALD), and the like, such that
barrier layer 104 covers both recessed area 102 and non-recessed
area 103. Because dielectric 100 can have a porous microstructure,
barrier layer 104 can include materials that can prevent the
diffusion or leaching of a subsequently deposited metal layer 106
(FIG. 1B) into dielectric 100, as described below. Furthermore,
barrier layer 104 can be formed from a conductive material, which
adheres to both dielectric 100 and metal layer 106 (FIG. 1B). For
instance, barrier layer 104 can include materials such as titanium,
tantalum, tungsten, titanium nitride, tantalum nitride, tungsten
nitride, tantalum silicon nitride, tungsten silicon nitride, and
the like. However, it should be recognized that barrier layer 104
can be omitted in some applications. For example, when dielectric
100 is formed from a material that is resistant to the diffusion of
a subsequently formed metal layer 106, or when the diffusion of a
subsequently formed metal layer 106 will not adversely affect the
performance of the semiconductor device, barrier layer 104 can be
omitted.
[0040] Next, with reference to FIG. 1B, metal layer 106 can be
deposited onto barrier layer 104 by any convenient method, such as
PVD, CVD, ALD, electroplating, electroless plating, and the like.
Furthermore, in some applications, such as when plating is used to
deposit metal layer 106, a seed layer can be deposited onto barrier
layer 104 before depositing metal layer 106. The seed layer can be
deposited by any convenient method, such as CVD, PVD, ALD, and the
like. The seed layer can include the same material as metal layer
106 in order to facilitate the deposition and bonding of metal
layer 106 onto barrier layer 104 or dielectric 100 if no barrier
layer 104 is used. As shown, metal layer 106 can fill recessed area
102 and cover non-recessed area 103. Additionally, metal layer 106
can include various electrically conductive materials, such as
copper, aluminum, nickel, chromium, zinc, cadmium, silver, gold,
rhodium, palladium, platinum, tin, lead, iron, indium,
super-conductor materials, and the like. Preferably, metal layer
106 can include copper. Furthermore, it should be recognized that
metal layer 106 can include an alloy of any of the various
electrically conductive materials, or compound of
superconductor.
[0041] Now with reference to FIG. 1C, after metal layer 106 is
deposited, metal layer 106 can then be removed from non-recessed
area 103 by any convenient method, such as CMP, electropolishing,
and the like. It should be recognized that polishing metal layer
106 from non-recessed area 103 can include removing metal layer 106
from the non-recessed area of any intermediate layer, such as
barrier layer 104 and the like, that is deposited onto dielectric
100. For a description of electropolishing, see U.S. patent
application Ser. No. 09/497,894, entitled METHODS AND APPARATUS FOR
ELECTROPOLISHING METAL INTERCONNECTIONS ON SEMICONDUCTOR DEVICES,
filed on Feb. 4, 2000, which is incorporated in its entirety herein
by reference.
[0042] With reference to FIG. 1D, after removing metal layer 106
from non-recessed area 103, barrier layer 104 can be removed from
non-recessed area 103 by any convenient method such as wet etching,
dry chemical etching, dry plasma etching, CMP, and the like.
Specifically, if plasma etching is used, either anisotropic etching
or isotropic etching can be used. Furthermore, the etching gas used
for plasma etching can include a single gas or a combination of
gases such as CF.sub.4, SF.sub.6, C.sub.4F.sub.8, O.sub.2, Ar, CO,
and the like. If dry chemical etching is used, vapor gases such as
HF, H.sub.2O, NH.sub.4F, N.sub.2, and the like, can be used, where
N.sub.2 can be used to bubble HF liquid (49% concentration) in
order to generate HF and H.sub.2O vapor. If wet etching is used,
etching liquids such as HF, NH.sub.4F, and the like, can be
used.
[0043] As shown in the present exemplary process, when metal layer
106 is removed from non-recessed area 103, a portion of metal layer
106 can be removed, or overpolished, from recessed area 102,
thereby causing the surface of metal layer 106 within recessed area
102 to be uneven with non-recessed area 103. This overpolishing of
metal layer 106 within recessed area 102, or dishing, can occur
because of the large width of recessed area 102. This dishing can
reduce the cross-sectional area of the metal layer 106 within
recessed area 102, and can therefore increase the resistance of the
interconnection formed by metal layer 106. This increased
resistance can cause the semiconductor device to malfunction.
[0044] Accordingly, as shown in FIGS. 2A-2D, dummy structures 200
can be included in recessed area 102 to reduce the unevenness of
metal layer 106 with non-recessed area 103. However, as described
below, dishing within the recessed area between each dummy
structure 200 can still occur if metal layer 106 is overpolished
when using an electropolishing method.
[0045] The process shown in FIGS. 2A-2D is similar in many respects
to the process shown in FIGS. 1A-1D, except that dummy structures
200 are included in recessed area 102. In particular, with
reference to FIG. 2A, dummy structures 200 can be included in
recessed area 102 of dielectric 100. Dummy structures 200 can form
a part of non-recessed area 103 and can include the same material
as dielectric 100 or can include any other material, depending on
the application. For instance, dummy structures can include
materials such as silicon dioxide, and the like, materials having
dielectric constants lower than silicon dioxide, such as
fluorinated silicate glass, polyimides, fluorinated polyimides,
hybrid/composites, siloxanes, organic polymers, [alpha]-C:F,
Si--O--C, parylenes/fluorinated parylenes, polyterafluoroethylene,
nanoporous silica, nanoporous organic, and the like, and metals
such as copper, aluminum, nickel, chromium, zinc, cadmium, silver,
gold, rhodium, palladium, platinum, tin, lead, iron, indium, and
the like.
[0046] If dummy structures 200 are formed of the same material as
dielectric 100, then dummy structures 200 can be formed at the same
time that recessed area 102 is formed. However, it should be
recognized that even if dummy structures 200 are formed of the same
material as dielectric 100, dummy structures can also be formed
after recessed area is formed. Alternatively, if dummy structures
200 are formed of a different material than dielectric 100, then
dummy structures 200 can be formed after recessed area 102 is
formed. For instance, after recessed area 102 is formed, a metal,
such as aluminum, and the like, can be deposited in the recessed
area. This metal can then be masked and etched to form dummy
structures 200, which are made of metal.
[0047] The number of dummy structures 200 included in recessed area
102 and the distance W.sub.1 between dummy structures 200 can
affect the planarity of the metal layer deposited onto the
semiconductor device, as shown in FIG. 2C. Accordingly, the ratio
of the distance W.sub.1 between dummy structures 200 to the
thickness T of the metal layer deposited on non-recessed area 103
(W.sub.1/T) can be chosen in the range of about 1 to about 5, and
preferably less than about 2. It should be recognized, however,
that this ratio can fall outside of this range depending on the
particular application. Furthermore, it should be recognized that
any number of dummy structures can be used depending on the
application.
[0048] Although W.sub.1 can affect the planarity of the metal layer
deposited, the width W.sub.2 of the dummy structures 200 typically
does not affect the planarity of the metal layer deposited.
However, W.sub.2 can affect the effective cross-sectional area of
the interconnection formed by the metal layer 106 deposited in
recessed area 102. Accordingly, W.sub.2 can be reduced in order to
increase the effective cross-sectional area of the interconnection.
In particular, the ratio of the width W.sub.2 of the dummy
structures 200 to the thickness T of the metal layer deposited on
non-recessed area 103 (W.sub.2/T) can be chosen in the range of
about 0.1 to about 1, and preferably about 0.3. It should be
recognized, however, that this ratio can fall outside of this range
depending on the particular application.
[0049] In the present exemplary process, after dummy structures 200
are included in recessed area 102, barrier layer 104 can be
deposited, such that barrier layer 104 covers both recessed area
102 and non-recessed area 103, including dummy structures 200. As
described above, it should be recognized that barrier layer 104 can
be omitted in some applications.
[0050] Next, with reference to FIGS. 2B and 2C, metal layer 106 can
be deposited onto barrier layer 104, such that metal layer 106
fills recessed area 102 and covers non-recessed area 103. As shown
in FIG. 2C, the surface of the metal layer 106 deposited over a
recessed area 102 having dummy structures 200 can be more planar
than a metal layer 106 deposited over a recessed area 102 without
dummy structures (FIG. 1B).
[0051] Now with reference to FIG. 2D, after metal layer 106 is
deposited, metal layer 106 can then be electropolished from
non-recessed area 103. However, dishing in recessed area 102 can
occur if electropolishing is allowed to continue after metal layer
106 is removed from non-recessed area 103. Although a certain
amount of overpolishing can be desirable in order to reduce the
risk of causing shortages in adjacent interconnections, dishing can
affect the planarity of the next layer deposited, such as a
dielectric layer, passivation layer, cover layer, and the like. In
turn, the planarity of the next layer deposited can affect
subsequent processes, such as lithography and the like, used to
form interconnections in subsequent layers. It should be recognized
that the occurrence of dishing when dummy structures are used is
specific to electropolishing. In contrast, when using only CMP to
remove metal layer 106, dummy structures 200 can prevent the CMP
polishing pad from moving past the dummy structures 200. Thus, the
dummy structures 200 can prevent the CMP polishing pad from
overpolishing metal layer 106 from recessed area 102.
[0052] Accordingly, as shown in FIG. 3, a portion of non-recessed
area 103 that is uneven with metal layer 106 can be removed in
order to increase the planarity of metal layer 106 with
non-recessed area 103. The exemplary process depicted in FIG. 3 is
similar in many respects to the process depicted in FIG. 2, except
that the process depicted in FIG. 3 includes overpolishing metal
layer 106 from recessed area 102 and then removing a portion of
non-recessed area 103 in order to increase the planarity of the
surface formed by metal layer 106 and non-recessed area 103.
[0053] In particular, with reference to FIG. 3A, dummy structures
200 can be included in recessed area 102 of dielectric 100, and can
form part of non-recessed area 103. Recessed area 102 can have a
depth of h+.delta.h, where h is the desired height of the final
metal interconnection formed in recessed area 102 and .delta.h is
the offset height, as described below. After dummy structures 200
are included in recessed area 102, barrier layer 104 can be
deposited, such that barrier layer 104 covers both recessed area
102 and non-recessed area 103, including dummy structures 200. As
described above, it should be recognized that barrier layer 104 can
be omitted in some applications.
[0054] Next, with reference to FIGS. 3B and 3C, metal layer 106 can
be deposited onto barrier layer 104, such that metal layer 106
fills recessed area 102 and covers non-recessed area 103. After
metal layer 106 is deposited, with reference to FIG. 3D, metal
layer 106 can then be electropolished from non-recessed area 103.
Electropolishing metal layer 106 from non-recessed area 103 can
include removing metal layer 106 from the non-recessed area of any
intermediate layer, such as barrier layer 104 and the like, that is
deposited onto dielectric 100. Furthermore, electropolishing can be
continued until metal layer 106 is overpolished from recessed area
102 an amount .delta.h, the offset height. According to one
embodiment of of the present invention, the offset height can be
chosen in the range of about 5 nm to about 100 nm. However, it
should be recognized that the offset height can be any height
depending on the particular application.
[0055] With reference now to FIG. 3E, after metal layer 106 is
overpolished from recessed area 102, a portion of non-recessed area
103 that is uneven with metal layer 106 can be removed. More
particularly, barrier layer 104, dielectric 100, and dummy
structures 200 can be removed by any convenient method such as wet
etching, dry chemical etching, dry plasma etching, and the like.
Specifically, if plasma etching is used, either anisotropic etching
or isotropic etching can be used. Furthermore, the etching gas used
for plasma etching can include a single gas or a combination of
gases such as CF.sub.4, SF.sub.6, C.sub.4F.sub.8, O.sub.2, Ar, CO,
and the like. If dry chemical etching is used, vapor gases such as
HF, H.sub.2O, NH.sub.4F, N.sub.2, and the like, can be used, where
N.sub.2 can be used to bubble HF liquid (49% concentration) in
order to generate HF and H.sub.2O vapor. If wet etching is used,
etching liquids such as HF, NH.sub.4F, and the like, can be used.
Furthermore, if barrier layer 104 is not deposited on dielectric
100 and dummy structures 200, dielectric 100 and dummy structures
200 can be removed by using a planarization process, such as CMP,
and the like. However, it should be recognized that dielectric 100
and dummy structures 200 can be removed by etching or any other
convenient process.
[0056] With reference to FIG. 4, an exemplary type of recessed area
100 (FIGS. 1-3) is shown. This recessed area is a wide trench
structure that includes dummy structures 200, which are spaced
apart at distances of L and W. As shown, dummy structures 200 can
be discontinuous, such that a metal layer deposited in wide trench
structure 102 can conduct current throughout the metal layer.
Furthermore, dummy structures 200 can be positioned such that
current can flow more uniformly across the metal layer, and thereby
enhance the reliability of the interconnection formed by the metal
layer. In particular, the ratio of distance L between dummy
structures 402 to the thickness T of the metal layer deposited on
the non-recessed area of the wide trench structure 400 (LIT) can be
chosen in the range of about 1 to about 5, and preferably less than
about 2. However, it should be recognized that this ratio can fall
outside of this range depending on the particular application.
[0057] With reference to FIG. 5, shown is a flow chart illustrating
an exemplary damascene process according to the present invention.
In step 500, a wafer having recessed and non-recessed areas can be
provided. In step 502, a dummy structure can be included in the
recessed area to form part of the non-recessed area. In step 504, a
metal layer can be deposited, such that the metal layer fills the
recessed area and covers the non-recessed area. In step 506, the
metal layer can be electropolished from the non-recessed area and
overpolished from the recessed area. In step 508, a portion of the
non-recessed area that is uneven with the metal layer in the
recessed area can be removed.
[0058] It should be recognized, however, that various modifications
can be made to the process depicted in the present flow chart. For
example, the step of depositing a barrier layer can be added
between steps 502 and 504. Additionally, it should be recognized
that each of the steps depicted in FIG. 5 can include numerous
steps. For example, step 504 can include depositing a seed layer
before depositing a metal layer. Moreover, it should be recognized
that the steps depicted in FIG. 5 can be used for any damascene
process, including a single-damascene process or a dual-damascene
process.
[0059] In FIG. 6, an exemplary process for forming a metal pad in a
semiconductor device is shown. The process shown in FIG. 6 is
similar in many respects to the process shown in FIG. 1, except
that vias 602 and large rectangular structure 600 are included in
the semiconductor device.
[0060] With reference now to FIGS. 6A and 6B, dielectric 100 can
include a non-recessed area 103 and a recessed area that forms a
large rectangular structure 600. Large rectangular structure 600
can connect with vias 602. When filled with metal layer 106, as
described below, large rectangular structure 600 can form a pad.
Additionally, when vias 602 are filled with metal layer 106, as
also described below, vias 602 can form plugs that can conduct
current from the pad to other pads or interconnections in the
semiconductor device. As shown in FIG. 6A, a barrier layer 104 can
be deposited on large rectangular structure 600, vias 602, and
non-recessed area 103. However, as described above, barrier layer
104 can be omitted in some applications.
[0061] Next, with reference to FIG. 6C, metal layer 106 can be
deposited onto barrier layer 104, such that metal layer 106 fills
large rectangular structure 600, vias 602, and covers non-recessed
area 103.
[0062] With reference to FIG. 6D, after metal layer 106 is
deposited, metal layer 106 can then be removed from non-recessed
area 103. Removing metal layer 106 from non-recessed area 103 can
include removing metal layer 106 from the non-recessed area of any
intermediate layer, such as barrier layer 104 and the like, that
are deposited onto dielectric 100. After removing metal layer 106
from non-recessed area 103, with reference to FIG. 6E, barrier
layer 104 can be removed from non-recessed area 103.
[0063] As shown in the present exemplary process, when metal layer
106 is removed from non-recessed area 103, a portion of metal layer
106 can be removed, or overpolished, from large rectangular
structure 600, thereby causing the surface of metal layer 106
within large rectangular structure 600 to be uneven with
non-recessed area 103. This overpolishing of metal layer 106 within
large rectangular structure 600, or dishing, can occur because of
the large size of large rectangular structure 600. This dishing can
reduce the cross-sectional area of the metal layer 106 within large
rectangular structure 600, and can therefore increase the
resistance in the pad formed by metal layer 106. This increased
resistance can cause the semiconductor device to malfunction.
[0064] Accordingly, as shown in FIG. 7, dummy structures 700 can be
included in large rectangular structure 600 to reduce the
unevenness of metal layer 106 with non-recessed area 103. The
exemplary process depicted in FIG. 7 is similar in many respects to
the process depicted in FIG. 6, except that the process depicted in
FIG. 7 includes overpolishing metal layer 106 from large
rectangular structure 600 and then removing a portion of
non-recessed area 103 in order to increase the planarity of the
surface formed by metal layer 106 and non-recessed area 103.
[0065] In particular, with reference to FIGS. 7A and 7B, dummy
structures 700 can be included in large rectangular structure 600
of dielectric 100, and can form part of non-recessed area 103.
Large rectangular structure 600 can have a depth of h+.delta.h,
where h is the desired height of the final metal interconnection
and .delta.h is the offset height, as described below. After dummy
structures 700 are included in large rectangular structure 600,
barrier layer 104 can be deposited, such that barrier layer 104
covers large rectangular structure 600, vias 602, and non-recessed
area 103, including dummy structures 700. As described above, it
should be recognized that barrier layer 104 can be omitted in some
applications. Furthermore, as also described above, any number of
dummy structures 700 can be used.
[0066] Next, with reference to FIG. 7C, metal layer 106 can be
deposited onto barrier layer 104, such that metal layer 106 fills
large rectangular structure 600 and vias 602 and covers
non-recessed area 103. After metal layer 106 is deposited, with
reference to FIG. 7D, metal layer 106 can then be electropolished
from non-recessed area 103. Electropolishing metal layer 106 from
non-recessed area 103 can include removing metal layer 106 from the
non-recessed area of any intermediate layer, such as barrier layer
104 and the like, that is deposited onto dielectric 100.
Furthermore, electropolishing can be continued until metal layer
106 is overpolished from large rectangular structure 600 an amount
.delta.h, the offset height. According to one embodiment of of the
present invention, the offset height can be chosen in the range of
about 5 nm to about 100 nm. However, it should be recognized that
the offset height can be any height depending on the particular
application.
[0067] With reference now to FIG. 7E, after metal layer 106 is
overpolished from large rectangular structure 600, a portion of
non-recessed area 103 that is uneven with metal layer 106 can be
removed. More particularly, barrier layer 104, dielectric 100, and
dummy structures 700 can be removed by any convenient method such
as wet etching, dry chemical etching, dry plasma etching, and the
like. Specifically, if plasma etching is used, either anisotropic
etching or isotropic etching can be used. Furthermore, the etching
gas used for plasma etching can include a single gas or a
combination of gases such as CF.sub.4, SF.sub.6, C.sub.4F.sub.8,
O.sub.2, Ar, CO, and the like. If dry chemical etching is used,
vapor gases such as HF, H.sub.2O, NH.sub.4F, N.sub.2, and the like,
can be used, where N.sub.2 can be used to bubble HF liquid (49%
concentration) in order to generate HF and H.sub.2O vapor. If wet
etching is used, etching liquids such as HF, NH.sub.4F, and the
like, can be used. Furthermore, if barrier layer 104 is not
deposited on dielectric 100 and dummy structures 700, dielectric
100 and dummy structures 700 can be removed by using a
planarization process, such as CMP, and the like. However, it
should be recognized that dielectric 100 and dummy structures 700
can be removed by etching or any other convenient process.
[0068] In FIG. 8, another exemplary process is shown. The exemplary
process shown in FIG. 8 is similar in many respects to the process
shown in FIG. 7, except that after metal layer 106 is overpolished
from large rectangular structure 600, the exposed portions of
non-recessed area 103 can be etched below the surface of metal
layer 106.
[0069] In particular, with reference to FIG. 8C, after metal layer
106 is deposited on the semiconductor device, such that metal layer
106 fills recessed area 600 and covers non-recessed area 103, metal
layer 106 can then be electropolished from non-recessed area 103
until metal layer 106 is overpolished from large rectangular
structure 600.
[0070] With reference now to FIG. 8D, after metal layer 106 is
overpolished from large rectangular structure 600, non-recessed
area 103 can be etched below the surface of metal layer 106. More
particularly, barrier layer 104, dielectric 100, and dummy
structures 700 can be removed by any convenient method such as wet
etching, dry chemical etching, dry plasma etching, and the like. As
shown in FIG. 8D, a portion of metal layer 106 can then protrude
from the surface of the semiconductor device.
[0071] Although the present exemplary process is not typically
useful for normal wafer production, this process can be useful for
producing a wafer suitable for performing electrical testing for
quality control purposes or research and development. In
particular, a probe used for electrical testing can more securely
and easily contact the surface of metal layer 106, thereby
increasing the conductivity between the pad of the semiconductor
device and the probe of the electrical testing device. This
increased conductivity can produce more accurate testing
results.
[0072] With reference to FIG. 9, another exemplary embodiment of a
semiconductor device that can be used with the process shown in
FIG. 7 is shown. The exemplary semiconductor device shown in FIG. 9
is similar in many respects to the exemplary semiconductor device
shown in FIG. 7B, except that additional dummy structures 900 have
been added. These additional dummy structures 900 can increase the
planarity of the metal layer 106 deposited on the semiconductor
device, and thereby reduce the amount of dishing of the metal layer
106 deposited in large rectangular structure 600. As discussed
before, it should be recognized that any number of dummy structures
can be included depending on the application. Furthermore, it
should be recognized that any configuration of dummy structures can
be used depending on the application.
[0073] With reference to FIG. 10, another exemplary embodiment of a
semiconductor device that can be used with the process shown in
FIG. 7 is shown. The exemplary semiconductor device shown in FIG.
10 is similar in many respects to the exemplary semiconductor
device shown in FIG. 9B, except that large rectangular structure
600 has rounded corners. These rounded corners can reduce stress in
the semiconductor device.
[0074] With reference to FIG. 11, another exemplary embodiment of a
semiconductor device that can be used with the process shown in
FIG. 7 is shown. The exemplary semiconductor device shown in FIG.
11 is similar in many respects to the exemplary semiconductor
device shown in FIG. 10, except that additional dummy structures
1100 have been added. These additional dummy structures 1100 can
increase the planarity of the metal layer 106 deposited on the
semiconductor device, and thereby reduce the amount of dishing of
the metal layer 106 deposited in large rectangular structure 600.
As discussed before, it should be recognized that any number of
dummy structures can be included depending on the application.
Furthermore, it should be recognized that any configuration of
dummy structures can be used depending on the application.
[0075] With reference to FIG. 12, another exemplary embodiment of a
semiconductor device that can be used with the process shown in
FIG. 7 is shown. The exemplary semiconductor device shown in FIG.
12 is similar in many respects to the exemplary semiconductor
device shown in FIG. 11B, except that additional vias 1200 have
been added. When filled with metal layer 106, these additional vias
1200 can form plugs. These plugs can increase the conductivity
between adjacent pads, and can enhance the mechanical strength of
the bond pad in the semiconductor device. Enhancing the mechanical
strength of the bond pad is particularly advantageous during
bonding process when dielectrics having low dielectric constants,
and consequently, lower mechanical strength, are used in the
semiconductor device. Some examples of materials having a low
dielectric constant include hydrogen-silsesquioxane (HSQ), Xerogel,
polymer, aerogel, and the like. A material having a lower
dielectric constant can be used to increase the speed of signals
passing through interconnections formed within the material, and
can be used to reduce the power consumption needed to send signals
through the interconnections. For instance, SiO.sub.2 has a
dielectric constant of about 4.0, HSQ has a lower dielectric
constant of about 3.0 to 2.5, and Xerogel has an even lower
dielectric constant of about 2.0.
[0076] With reference to FIG. 13, an exemplary layout of a large
rectangular structure that can be used with the process depicted in
FIG. 7 is shown. In particular, large rectangular structure 600 can
include dummy structures 900 and 700. Dummy structures 700 can be
placed apart at distances a.sub.1 and b.sub.2 from each other, and
dummy structures 900 can be placed at distances a.sub.2 and b.sub.1
from each other. Furthermore, dummy structures 700 can be placed at
a distance b.sub.3 from the edge of large rectangular structure 600
and dummy structures 900 can be placed at a distance a.sub.3 from
the edge of large rectangular structure 600.
[0077] In the present exemplary layout, the distance between dummy
structures 700 and 900 can affect the planarity of metal layer 106
deposited with a thickness T on the non-recessed area 103 of the
semiconductor device according to the process depicted in FIG. 7.
In particular, the planarity of metal layer 106 deposited on the
semiconductor device can be increased by choosing the distances
between dummy structures, such that the ratio of the distance
between dummy structures to thickness, a.sub.1/T, a.sub.b/T,
a.sub.1/T, b.sub.2/T, and the ratio of the distance between a dummy
structure and the edge of large rectangular structure 600 to
thickness, a.sub.3/T and b.sub.3/T, is in the range of about 1 to
about 5, and preferably less than about 2. However, it should be
recognized that other ratios outside of this range can be chosen
depending on the particular application.
[0078] Although the distance between dummy structures can affect
the planarity of the metal layer deposited in a large rectangular
structure, the width W of dummy structures 700 and 900 typically
does not affect the planarity of the metal layer deposited.
However, W can affect the effective cross-sectional area of the pad
formed by the metal layer deposited in large rectangular structure
600. Accordingly, W can be reduced in order to increase the
effective cross-sectional area of the pad. In particular, the ratio
of the width W of the dummy structures 700 and 900 to the thickness
T of the metal layer deposited on non-recessed area 103 (W/T) can
be chosen in the range of about 0.1 to about 1, and preferably
about 0.3. It should be recognized, however, that this ratio can
fall outside of this range depending on the particular
application.
[0079] With reference to FIG. 14, another exemplary layout of a
large rectangular structure that can be used with the process
depicted in FIG. 7 is shown. The exemplary layout in FIG. 14 is
similar in many respects to the exemplary layout shown in FIG. 13,
except that that additional vias 1200 have been added. As described
above, when filled with metal layer 106, these additional vias 1200
can form plugs that can increase the conductivity between adjacent
pads, and can enhance the mechanical strength of the bond pad in
the semiconductor device. As also described above, enhancing the
mechanical strength of the bond pad is particularly advantageous
during bonding process when dielectrics having low dielectric
constants, and consequently, lower mechanical strength, are used in
the semiconductor device.
[0080] With reference to FIG. 15, another exemplary layout of a
large rectangular structure that can be used with the process
depicted in FIG. 7 is shown. The exemplary layout in FIG. 15 is
similar in many respects to the exemplary layout shown in FIG. 14,
except that additional vias 1500 have been added. As generally
described above, when filled with metal layer 106, these additional
vias 1500 can form plugs that can increase the conductivity between
adjacent pads, and can enhance the mechanical strength of the bond
pad in the semiconductor device. As also described above, enhancing
the mechanical strength of the bond pad is particularly
advantageous during ponding process when dielectrics having low
dielectric constants, and consequently, lower mechanical strength,
are used in the semiconductor device.
[0081] With reference to FIG. 16, yet another exemplary layout of a
large rectangular structure that can be used with the process
depicted in FIG. 7 is shown. The exemplary layout in FIG. 16 is
similar in many respects to the exemplary layout depicted in FIG.
13, except that the entire pattern of dummy structures 700 and 900
has been rotated an angle .alpha., where .alpha. can be chosen at
any angle, such as between 0.degree. and 360.degree..
[0082] With reference to FIGS. 17A-17AA, various exemplary shapes
that can be used to form dummy structures are shown. In particular,
shapes such as a rectangle, circle, ellipse, triangle, trapezoid,
octagon, hexagon, pentagon, and the like can be used. It should be
recognized that although particular exemplary shapes are depicted
in FIGS. 17A-17AA, any shape can be used to form dummy structures
depending on the particular application. Dummy structures can be
formed from various materials such as silicon dioxide, and the
like, materials having dielectric constants lower than silicon
dioxide, such as fluorinated silicate glass, polyimides,
fluorinated polyimides, hybrid/composites, siloxanes, organic
polymers, [alpha]-C:F, Si--O--C, parylenes/fluorinated parylenes,
polyterafluoroethylene, nanoporous silica, nanoporous organic, and
the like, and metals such as copper, aluminum, nickel, chromium,
zinc, cadmium, silver, gold, rhodium, palladium, platinum, tin,
lead, iron, indium, and the like. As described above, in some
applications, dummy structures can be formed of the same material
as the dielectric used.
[0083] As shown in FIG. 18, a problem can arise when using dummy
structures according to the processes described above. The process
shown in FIG. 18 is similar to the process depicted in FIG. 3,
except that barrier layer 104 can become over-removed when a
portion of non-recessed area 103 is removed. In particular, with
reference to FIGS. 18C and 18D, after metal layer 106 is
overpolished from recessed area 102, a portion of non-recessed area
103 that is uneven with metal layer 106 can be removed.
Specifically, the exposed portions of barrier layer 104 can be
removed by etching, CMP, or any other convenient process.
[0084] With reference to FIG. 18E, after the exposed portions of
barrier layer 104 are removed, a cover layer or passivation layer
1802 can be deposited on the semiconductor device. The cover layer
or passivation layer 1802 can include an insulating material, such
as SiN, diamond, and the like. However, if barrier layer 104 is
over-removed in the previous step, a gap 1800 can form between
metal layer 106 and dielectric 100, especially if cover layer 1802
does not fill the space caused by the over-removal of barrier layer
104. Gap 1800 can allow metal layer 106 to diffuse into dielectric
100 when particular metals and dielectric materials are used, such
as when metal layer 106 is formed from copper and dielectric 100 is
a material having a low dielectric constant. Such diffusion of
metal layer 106 into dielectric 100 can cause reliability problems
in the semiconductor device.
[0085] Accordingly, FIGS. 19-27 depict various embodiments of
solutions to the problem presented in FIG. 18. In some of these
exemplary embodiments, non-recessed area 103 can be removed such
that barrier layer 104 is at the same or similar level as
dielectric 100. In other of these exemplary embodiments,
non-recessed area 103 can be removed such that barrier layer 104
protrudes beyond the surface of dielectric 100.
[0086] FIG. 19 shows an exemplary process of removing non-recessed
area 103, such that barrier layer 104, metal layer 106, and
dielectric 100 each have surfaces at the same or a similar level.
In particular, with reference to FIG. 19A, after metal layer 106 is
overpolished from recessed area 102 (FIG. 18), barrier layer 104
and dielectric 100 can be removed at the same rate in order to
allow barrier layer 104 and dielectric 100 to form surfaces at the
same or a similar level. In particular, with reference to FIG. 19B,
barrier layer 104 and dielectric 100 can be removed by any
convenient method such as wet etching, dry chemical etching, dry
plasma etching, CMP, and the like. For example, if plasma etching
is used, the plasma etching can include low density plasma
(reactive ion etching), high-density plasma (inductive couple
plasma (ICP), Helicon plasma (HP), electron cyclotron resonance
(ECR)), atmospheric pressure plasma (silent discharge plasma), and
the like, and the plasma power can be chosen between about 500 W
and about 2000 W, preferably about 1000 W. Furthermore, in the
present example, vacuum pressure can be chosen between about 30
mTorr and about 100 mTorr, preferably about 50 mTorr, the
temperature of the semiconductor device can be chosen to be about
20.degree. C., and the gas and flow rate of C.sub.4F.sub.8,
O.sub.2, and Ar, if used, can be about 8 sccm, about 2 sccm, and
about 100 sccm, respectively. In addition, TaN, which can be used
as barrier layer 104, can be removed at a rate of about 150 nm/min,
and SiO.sub.2, which can be used as dielectric 100, can be removed
at a rate of about 150 nm/min.
[0087] In the present exemplary embodiment, with reference to FIG.
19C, after a desired portion of barrier layer 104 and dielectric
100 is removed, cover layer 1802 can be deposited on the
semiconductor device. As shown, when barrier layer 104, dielectric
100, and metal layer 106 have surfaces at the same or a similar
level, gap 1800 (FIG. 18) can be eliminated, and the diffusion of
metal layer 106 into dielectric 100 can be reduced.
[0088] FIG. 20 shows an exemplary process of removing non-recessed
area 103, such that barrier layer 104 protrudes beyond the surface
of metal layer 106 and dielectric 100. In particular, with
reference to FIG. 20A, after metal layer 106 is overpolished from
recessed area 102 (FIG. 18), barrier layer 104 can be removed at a
lower rate than dielectric 100 in order to allow barrier layer 104
to protrude beyond the surface of dielectric 100 and metal layer
106. In particular, barrier layer 104 and dielectric 100 can be
removed by any convenient method such as wet etching, dry chemical
etching, dry plasma etching, CMP, and the like. For example, if
plasma etching is used, the plasma power can be chosen between
about 500 W and about 2000 W, preferably about 1000 W. Furthermore,
in the present example, vacuum pressure can be chosen between about
50 mTorr and about 120 mTorr, preferably about 90 mTorr, the
temperature of the semiconductor device can be chosen to be about
20.degree. C., and the gas and flow rate of C.sub.4F.sub.8,
O.sub.2, and Ar, if used, can be about 8.5 sccm, about 6.7 sccm,
and about 115 sccm, respectively. In addition, barrier layer 104
can be removed at a rate of about 70 nm/min if TaN is used, and at
a rate of about 90 nm/min if TiN is used. Furthermore, SiO.sub.2,
which can be used as dielectric 100, can be removed at a rate of
about 300 nm/min.
[0089] In the present exemplary embodiment, with reference to FIG.
20C, after a desired portion of barrier layer 104 and dielectric
100 is removed, cover layer 1802 can be deposited on the
semiconductor device. As shown, when barrier layer 104 protrudes
beyond the surface of dielectric 100 and metal layer 106, gap 1800
(FIG. 18) can be eliminated, and diffusion of metal layer 106 into
dielectric 100 can be reduced. In addition, allowing barrier layer
104 to protrude in this manner can better prevent diffusion than
forming barrier layer 104 at the same or a similar level as
dielectric 100 and metal layer 106. However, some planarity of
cover layer 1802 can be lost when barrier layer 104 protrudes in
this manner. As described, this loss of planarity can cause
problems when forming subsequent layers of the semiconductor
device. However, depending on the application, this loss of
planarity can be acceptable.
[0090] FIG. 21 shows another exemplary process of removing
non-recessed area 103, such that barrier layer 104 protrudes beyond
the surface of metal layer 106 and dielectric 100. In particular,
with reference to FIG. 21A, after metal layer 106 is overpolished
from recessed area 102 (FIG. 18), barrier layer 104 and dielectric
100 can be removed in two steps. With reference to FIG. 21B, in the
first step, barrier layer 104 and dielectric 100 can be removed at
the same rate. With reference to FIG. 21C, in the second step,
dielectric 100 can be removed at a higher rate than barrier layer
104 in order to allow barrier layer 104 to protrude beyond the
level of dielectric 100 and metal layer 106. In some applications,
removal of barrier layer 104 can be halted in the second step, such
that the rate is zero. Furthermore, barrier layer 104 and
dielectric 100 can be removed by any convenient method such as wet
etching, dry chemical etching, dry plasma etching, CMP, and the
like. For example, in the first step, plasma etching can be used,
and the plasma power can be chosen between about 500 W and about
2000 W, preferably about 1000 W. Furthermore, in the present
example, vacuum pressure can be chosen between about 30 mTorr and
about 100 mTorr, preferably about 50 mTorr, the temperature of the
semiconductor device can be chosen to be about 20.degree. C., and
the gas and flow rate of C.sub.4F8, 02, and Ar, if used, can be
about 8 sccm, about 2 sccm, and about 100 sccm, respectively. In
addition, both barrier layer 104, which includes TaN, and
dielectric 100, which includes SiO.sub.2, can be removed at a rate
of about 150 nm/min.
[0091] In the second step of the present example, plasma etching
can be used, and the plasma power can be chosen between about 500 W
and about 2000 W, preferably about 1000 W. Furthermore, in the
present example, vacuum pressure can be chosen between about 30
mTorr and about 100 mTorr, preferably about 80 mTorr, the
temperature of the semiconductor device can be chosen to be about
20.degree. C., and the gas and flow rate of SF.sub.6, if used, can
be about 50 sccm. In addition, barrier layer 104 can be removed at
a rate of about 250 nm/min if TaN is used, and at a rate of about
300 nm/min if TiN is used. Furthermore, SiO.sub.2, which can be
used as dielectric 100, can be removed at a rate of about 20
nm/min.
[0092] In the present exemplary embodiment, with reference to FIG.
21D, after a desired portion of barrier layer 104 and dielectric
100 is removed, cover layer 1802 can be deposited on the
semiconductor device. As shown, when barrier layer 104 protrudes
beyond the level of dielectric 100 and metal layer 106, gap 1800
(FIG. 18) can be eliminated, and diffusion of metal layer 106 into
dielectric 100 can be reduced. As described above, allowing barrier
layer 104 to protrude in this manner can result in some loss of
planarity of cover layer 1802. However, depending on the
application, this loss of planarity can be acceptable.
[0093] FIG. 22 shows yet another exemplary process of removing
non-recessed area 103, such that barrier layer 104 protrudes beyond
the surface of metal layer 106. In particular, with reference to
FIG. 22A, after metal layer 106 is overpolished from recessed area
102 (FIG. 18), barrier layer 104 and dielectric 100 can be removed
in two steps. With reference to FIG. 22B, in the first step,
barrier layer 104 can be removed at a higher rate than dielectric
100. With reference to FIG. 22C, in the second step, dielectric 100
can be removed at a higher rate while barrier layer 104 can be
removed at a rate of zero, in order to allow barrier layer 104 to
protrude beyond the surface of dielectric 100 and metal layer 106.
In particular, barrier layer 104 and dielectric 100 can be removed
by any convenient method such as wet etching, dry chemical etching,
dry plasma etching, CMP, and the like.
[0094] For example, in the first step, plasma etching can be used,
and the plasma power can be chosen between about 500 W and about
2000 W, preferably about 1000 W. Furthermore, in the present
example, vacuum pressure can be chosen between about 30 mTorr and
about 100 mTorr, preferably about 80 mTorr, the temperature of the
semiconductor device can be chosen to be about 20.degree. C., and
the gas and flow rate of SF.sub.6, if used, can be about 50 sccm.
In addition, barrier layer 104 can be removed at a rate of about
250 nm/min if TaN is used, and at a rate of about 300 nm/min if TiN
is used. Furthermore, dielectric 100, which includes SiO.sub.2, can
be removed at a rate of about 20 nm/min. In the second step of the
present example, the settings for the first step can be the same,
except that removal of barrier layer 104 can be halted and set to a
rate of zero.
[0095] In the present exemplary embodiment, with reference to FIG.
22D, after a desired portion of barrier layer 104 and dielectric
100 is removed, cover layer 1802 can be deposited on the
semiconductor device. As shown, when barrier layer 104 protrudes
beyond the surface of dielectric 100 and metal layer 106, gap 1800
(FIG. 18) can be eliminated, and diffusion of metal layer 106 into
dielectric 100 can be reduced. As described above, allowing barrier
layer 104 to protrude in this manner can result in some loss of
planarity of cover layer 1802. However, depending on the
application, this loss of planarity can be acceptable.
[0096] FIG. 23 shows another exemplary process of removing
non-recessed area 103, such that barrier layer 104, metal layer
106, and dielectric. 100 each have surfaces at the same or a
similar level. In particular, with reference to FIG. 23A, after
metal layer 106 is overpolished from recessed area 102 (FIG. 18),
barrier layer 104 and dielectric 100 can be removed in two steps.
With reference to FIG. 23B, in the first step, barrier layer 104
can be removed at a higher rate than dielectric 100. With reference
to FIG. 23C, in the second step, dielectric 100 can be removed at a
higher rate than barrier layer 104, in order allow barrier layer
104 and dielectric 100 to form surfaces at the same or a similar
level. In particular, barrier layer 104 and dielectric 100 can be
removed by any convenient method such as wet etching, dry chemical
etching, dry plasma etching, CMP, and the like.
[0097] For example, in the first step, plasma etching can be used,
and the plasma power can be chosen between about 500 W and about
2000 W, preferably about 1000 W. Furthermore, in the present
example, vacuum pressure can be chosen between about 30 mTorr and
about 100 mTorr, preferably about 80 mTorr, the temperature of the
semiconductor device can be chosen to be about 20.degree. C., and
the gas and flow rate of SF.sub.6, if used, can be about 50 sccm.
In addition, barrier layer 104 can be removed at a rate of about
250 nm/min if TaN is used, and at a rate of about 300 nm/min if TiN
is used. Furthermore, dielectric 100, which includes SiO.sub.2, can
be removed at a rate of about 20 nm/min.
[0098] In the second step of the present example, plasma etching
can be used, and the plasma power can be chosen between about 500 W
and about 2000 W, preferably about 1000 W. Furthermore, in the
present example, vacuum pressure can be chosen between about 50
mTorr and about 120 mTorr, preferably about 90 mTorr, the
temperature of the semiconductor device can be chosen to be about
20.degree. C., and the gas and flow rate of C.sub.4F.sub.8,
O.sub.2, and Ar, if used, can be about 8.5 sccm, about 6.7 sccm,
and about 115 sccm, respectively. In addition, barrier layer 104
can be removed at a rate of about 70 nm/min if TaN is used, and at
a rate of about 90 nm/min if TiN is used. Furthermore, dielectric
100, which includes SiO.sub.2, can be removed at a rate of about
300 nm/min.
[0099] In the present exemplary embodiment, with reference to FIG.
23D, after a desired portion of barrier layer 104 and dielectric
100 is removed, cover layer 1802 can be deposited on the
semiconductor device. As shown, when barrier layer 104, dielectric
100, and metal layer 106 have surfaces at the same or a similar
level, gap 1800 (FIG. 18) can be eliminated, and diffusion of metal
layer 106 into dielectric 100 can be reduced. Although the
planarity of the semiconductor device produced by this exemplary
process can be better than semiconductor devices including a
barrier layer 104 that protrudes beyond dielectric 100 and metal
layer 106, the semiconductor device produced by the present
exemplary process poses an increased risk that metal layer 106 can
diffuse into dielectric 100, as compared to semiconductor devices
including a barrier layer 104 that protrudes beyond dielectric 100
and metal layer 106.
[0100] FIG. 24 shows yet another exemplary process of removing
non-recessed area 103, such that barrier layer 104, dielectric 100,
and metal layer 106 have surfaces at the same or a similar level.
In particular, with reference to FIG. 24A, after metal layer 106 is
overpolished from recessed area 102 (FIG. 18), barrier layer 104
and dielectric 100 can be removed in two steps. With reference to
FIG. 24B, in the first step, barrier layer 104 can be removed at a
higher rate while dielectric 100 can be removed at a rate of zero.
With reference to FIG. 24C, in the second step, dielectric 100 can
be removed at a higher rate while barrier layer 104 can be removed
at a rate of zero, in order to allow barrier layer 104 and
dielectric 100 to form surfaces at the same or a similar level. In
particular, barrier layer 104 and dielectric 100 can be removed by
any convenient method such as wet etching, dry chemical etching,
dry plasma etching, CMP, and the like.
[0101] In the present exemplary embodiment, with reference to FIG.
24D, after a desired portion of barrier layer 104 and dielectric
100 is removed, cover layer 1802 can be deposited on the
semiconductor device. As shown, when barrier layer 104, dielectric
100 and metal layer 106 have surfaces at the same or a similar
level, gap 1800 (FIG. 18) can be eliminated, and diffusion of metal
layer 106 into dielectric 100 can be reduced. Although the
planarity of the semiconductor device can be better than
semiconductor devices including a barrier layer 104 that protrudes
beyond dielectric 100 and metal layer 106, the semiconductor device
produced by the present exemplary process poses an increased risk
that metal layer 106 can diffuse into dielectric 100, as compared
to semiconductor devices that include a barrier layer 104 that
protrudes beyond dielectric 100 and metal layer 106.
[0102] FIG. 25 shows another exemplary process of removing
non-recessed area 103, such that barrier layer 104, dielectric 100,
and metal layer 106 have surfaces at the same or a similar level.
In particular, with reference to FIG. 25A, after metal layer 106 is
overpolished from recessed area 102 (FIG. 18), barrier layer 104
and dielectric 100 can be removed in two steps. With reference to
FIG. 25B, in the first step, barrier layer 104 can be removed at a
lower rate than dielectric 100. With reference to FIG. 25C, in the
second step, barrier layer 104 can be removed at a higher rate
while dielectric 100 can be removed at a rate of zero, in order to
allow barrier layer 104 and dielectric 100 to form surfaces at the
same or a similar level. In particular, barrier layer 104 and
dielectric 100 can be removed by any convenient method such as wet
etching, dry chemical etching, dry plasma etching, CMP, and the
like. For example, in the first step, plasma etching can be used,
and the plasma power can be chosen between about 500 W and about
2000 W, preferably about 1000 W. Furthermore, in the present
example, vacuum pressure can be chosen between about 50 mTorr and
about 120 mTorr, preferably about 90 mTorr, the temperature of the
semiconductor device can be chosen to be about 20.degree. C., and
the gas and flow rate of C.sub.4F.sub.8, O.sub.2, and Ar, if used,
can be about 8.5 sccm, about 6.7 sccm, and about 115 sccm,
respectively. In addition, barrier layer 104 can be removed at a
rate of about 70 nm/min if TaN is used, and at a rate of about 90
nm/min if TiN is used. Furthermore, dielectric 100, which includes
SiO.sub.2, can be removed at a rate of about 300 nm/min. In the
second step of the present example, the settings for the first step
can be the same, except that removal of dielectric 100 can be
halted and set to a rate of zero.
[0103] In the present exemplary embodiment, with reference to FIG.
25D, after a desired portion of barrier layer 104 and dielectric
100 is removed, cover layer 1802 can be deposited on the
semiconductor device. As shown, when barrier layer 104, dielectric
100, and metal layer 106 have surfaces at the same or a similar
level, gap 1800 (FIG. 18) can be eliminated, and diffusion of metal
layer 106 into dielectric 100 can be reduced. Although the
planarity of the semiconductor device can be better than
semiconductor devices including a barrier layer 104 that protrudes
beyond dielectric 100 and metal layer 106, the semiconductor device
produced by the present exemplary process poses an increased risk
that metal layer 106 can diffuse into dielectric 100, as compared
to semiconductor devices including a barrier layer 104 that
protrudes beyond dielectric 100 and metal layer 106.
[0104] FIG. 26 shows an exemplary process of removing non-recessed
area 103, such that metal layer 106 protrudes beyond the level of
dielectric 100 and barrier layer 104. Although the present
exemplary process is not typically useful for normal wafer
production, this process can be useful for producing a wafer
suitable for performing electrical testing for quality control
purposes or research and development. In particular, a probe used
for electrical testing can more securely and easily contact the
surface of metal layer 106, thereby increasing the conductivity
between the pad of the semiconductor device and the probe of the
electrical testing device. This increased conductivity can produce
more accurate testing results.
[0105] With reference to FIG. 26A, after metal layer 106 is
overpolished from recessed area 102 (FIG. 18), barrier layer 104
and dielectric 100 can be removed in two steps. With reference to
FIG. 26B, in the first step, barrier layer 104 can be removed at a
higher rate than dielectric 100. With reference to FIG. 26C, in the
second step, dielectric 100 can be removed at a higher rate while
barrier layer 104 can be removed at a rate of zero. In particular,
barrier layer 104 and dielectric 100 can be removed by any
convenient method such as wet etching, dry chemical etching, dry
plasma etching, CMP, and the like.
[0106] In the present exemplary process, with reference to FIG.
26D, after a desired portion of barrier layer 104 and dielectric
100 is removed, cover layer 1802 can be deposited on the
semiconductor device. Cover layer 1802 can be used to protect the
present layers from diffusing into subsequently formed layers.
[0107] FIG. 27 shows another exemplary process of removing
non-recessed area 103, such that metal layer 106 protrudes beyond
the level of dielectric 100 and barrier layer 104. Like the process
depicted in FIG. 26, the present exemplary process is not typically
useful for normal wafer production, but this process can be useful
for producing a wafer suitable for performing electrical testing
for quality control purposes or research and development. In
particular, a probe used for electrical testing can more securely
and easily contact the surface of metal layer 106, thereby
increasing the conductivity between the pad of the semiconductor
device and the probe of the electrical testing device. This
increased conductivity can produce more accurate testing
results.
[0108] With reference to FIG. 27A, after metal layer 106 is
overpolished from recessed area 102 (FIG. 18), barrier layer 104
and dielectric 100 can be removed in two steps. With reference to
FIG. 27B, in the first step, barrier layer 104 can be removed at a
higher rate and dielectric 100 can be removed at a rate of zero.
With reference to FIG. 26C, in the second step, dielectric 100 can
be removed at a higher rate while barrier layer 104 can be removed
at a rate of zero. In particular, barrier layer 104 and dielectric
100 can be removed by any convenient method such as wet etching,
dry chemical etching, dry plasma etching, CMP, and the like.
[0109] In the present exemplary embodiment, with reference to FIG.
27D, after a desired portion of barrier layer 104 and dielectric
100 is removed, cover layer 1802 can be deposited on the
semiconductor device. Cover layer 1802 can be used to protect the
present layers from diffusing into subsequently formed layers.
[0110] Table 1 provides a summary of the various exemplary
embodiments described with regard to FIGS. 19-27. In particular,
each column includes a different combination of removal rates for
barrier layer 104 and dielectric 100 in the first step, and each
row includes a different combination of removal rates for barrier
layer 104 and dielectric 100 in the second step.
1 TABLE 1 Step 1: Step 1: Step 1: Removal of Removal of Removal of
barrier layer and barrier layer at dielectric at dielectric at same
higher rate than higher rate than rate dielectric barrier layer No
Step 2 N/A Step 2: N/A N/A N/A Removal of barrier layer and
dielectric at same rate Step 2: N/A N/A Removal of barrier layer at
higher rate than dielectric Step 2: FIG. 22, FIG. 23, N/A Removal
of FIG. 24, FIG. 26, dielectric at higher rate than barrier
layer
[0111] Table 1 depicts particular combinations of removal rates for
dielectric 100 and barrier layer 104, however, it should be
recognized that other combinations of removal rates can be used
depending on the application.
[0112] Although the present invention has been described with
respect to certain embodiments, examples, and applications, it will
be apparent to those skilled in the art that various modifications
and changes may be made without departing from the invention.
* * * * *