U.S. patent application number 10/685623 was filed with the patent office on 2004-04-29 for methods and configuration to simplify connections between polysilicon layer and diffusion area.
Invention is credited to Shau, Jeng-Jye.
Application Number | 20040080017 10/685623 |
Document ID | / |
Family ID | 32110302 |
Filed Date | 2004-04-29 |
United States Patent
Application |
20040080017 |
Kind Code |
A1 |
Shau, Jeng-Jye |
April 29, 2004 |
Methods and configuration to simplify connections between
polysilicon layer and diffusion area
Abstract
An electronic device supported on a semiconductor substrate. The
semiconductor device includes a diffusion area in the substrate and
a polysilicon layer extending over the substrate and contacting the
diffusion area. The electronic device further includes a conductive
contact covering and contacting both the polysilicon layer and the
diffusion area. Therefore, the semiconductor device disclosed in
this invention includes poly-to-diffusion connection for a
semiconductor device that has a diffusion are and a polysilicon
area. The semiconductor device further includes a contact that
covers both the diffusion area and the polysilicon area with a
contact filling material forming the connection between these two
areas.
Inventors: |
Shau, Jeng-Jye; (Palo Alto,
CA) |
Correspondence
Address: |
Bo-In Lin
13445 Mandoli Drive
Los Altos Hills
CA
94022
US
|
Family ID: |
32110302 |
Appl. No.: |
10/685623 |
Filed: |
October 14, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60420884 |
Oct 23, 2002 |
|
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Current U.S.
Class: |
257/509 ;
257/377; 257/E21.59; 257/E21.627; 438/225 |
Current CPC
Class: |
H01L 21/823475 20130101;
H01L 21/76895 20130101 |
Class at
Publication: |
257/509 ;
438/225; 257/377 |
International
Class: |
H01L 029/76; H01L
021/8238 |
Claims
What is claimed is:
1. An electronic device supported on a semiconductor substrate
comprising: a diffusion area in said substrate and a polysilicon
area comprising a polysilicon layer extending over said substrate
for contacting said diffusion area; and a single contact disposed
on top of said substrate contacting both said polysilicon layer and
said diffusion area.
2. The electronic device of claim 1 further comprising: a field
oxide disposed next to said diffusion area wherein said polysilicon
layer disposed on top of said field oxide and extending therefrom
to contact said diffusion area.
3. The electronic device of claim 1 further comprising: a metal
layer disposed on top of said single contact for connecting to
another circuit element of said electronic device.
4. The electronic device of claim 1 wherein: said single contact
further comprising a conductive material filling a contact opening
etched in an insulating layer overlying said diffusion area and
said polysilicon area.
5. The electronic device of claim 1 wherein: said electronic device
further comprising a transistor and said diffusion area further
comprising a source/drain of said transistor.
6. A ploy-to diffusion connection (PDC) disposed on a substrate
comprising: a diffusion area in said substrate and a polysilicon
area comprising a polysilicon layer extending over said substrate
for contacting said diffusion area.
7. The PDC of claim 6 further comprising: a single contact disposed
on top of said substrate contacting both said polysilicon layer and
said diffusion area.
8. The PDC of claim 6 further comprising: a field oxide disposed on
said substrate next to said diffusion area wherein said polysilicon
layer disposed on top of said field oxide and extending therefrom
to contact said diffusion area.
9. The PDC of claim 7 wherein: said single contact further
comprising a conductive material filling a contact opening etched
in an insulating layer overlying said diffusion area and said
polysilicon area.
10. The PDC of claim 7 further comprising: a metal layer disposed
on top of said single contact for connecting to another circuit
element disposed on said substrate.
11. A method for configuring an electronic device on a
semiconductor substrate comprising: forming a diffusion area in
said substrate; configuring a polysilicon area by forming a
polysilicon layer extending over said substrate for contacting said
diffusion area; and forming a single contact on top of said
substrate contacting both said polysilicon layer and said diffusion
area.
12. The method of claim 11 further comprising: forming a field
oxide next to said diffusion area and forming said polysilicon
layer on top of said field oxide and extending therefrom to contact
said diffusion area.
13. The method of claim 11 further comprising: forming a metal
layer on top of said single contact for connecting to another
circuit element of said electronic device.
14. The method of claim 1 wherein said step of forming said single
contact further comprising: etching a contact opening in an
insulating layer that overlying said diffusion area and said
polysilicon layer; and filling said contact opening with a
conductive material.
15. The method of claim 11 wherein: said method of configuring said
electronic device further comprising a step of forming a transistor
by employing said diffusion area as a source/drain of said
transistor.
16. A method for forming a ploy-to diffusion connection (PDC) on a
substrate comprising: forming a diffusion area in said substrate
and forming a polysilicon area by extending a polysilicon layer
from said polysilicon area over said substrate to said diffusion
area for contacting said diffusion area.
17. The method of claim 16 further comprising: forming a single
contact on top of said substrate contacting both said polysilicon
layer and said diffusion area.
18. The method of claim 16 further comprising: forming a field
oxide on said substrate next to said diffusion area and forming
said polysilicon layer on top of said field oxide and extending
therefrom to contact said diffusion area.
19. The method of claim 17 wherein said step of forming said single
contact further comprising: etching a contact opening in an
insulting layer overlying said diffusion area and said polysilicon
area; and filling said contact opening with a conductive
material.
20. The method of claim 17 further comprising: forming a metal
layer on top of said single contact for connecting to another
circuit element disposed on said substrate.
Description
[0001] This application claims priority to a pending U.S.
provisional patent application entitled METHODS AND CONFIGURATION
TO SIMPLIFY CONNECTIONS BETWEEN POLYSILICON LAYER AND DIFFUSION
AREA, filed Oct. 23, 2002 by Jeng-Jye Shau as the sole inventor of
this Application and accorded a Ser. No. 60/420,884, the benefit of
its filing date being hereby claimed under Title 35 of the United
States Code.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to integrated circuit (IC)
manufacture procedures, and more particularly to methods for
connecting poly-crystal silicon (poly) layer and diffusion
area.
[0004] 2. Descriptions of Related Arts
[0005] FIG. 1(a) shows the top view for an example of current art
poly-to-diffusion connection (PDC). A diffusion contact (108) is
placed on top of diffusion area (103). A poly contact (109) is
placed on top of poly (105) area. These two contacts (108, 109)
connected by a metal layer (107). The cross section view of the
structure in FIG. 1(a) is shown in FIG. 1(b). The poly layer (115)
on field oxide (110) is connected to the diffusion area (113)
through a poly contact (119), a metal layer (117), and a diffusion
contact (118).
[0006] The dimension of such PDC is limited by many design rules.
There is a design rule limiting the poly-to-diffusion distance
(Dd-p), a design rule limiting the poly contact to diffusion
distance (Dd-c), and a design rule limiting the contact to contact
(Dc-c) distance as shown in FIG. 1(a). In the conventional
techniques of integrated circuit designs, these design rules are
originally required for the purpose of preventing accidental shorts
between the poly and the diffusion areas. However, these design
rules are still imposed and employed for designing IC circuits even
under the circumstances that the circuit design is intended to
connect the poly and diffusion areas. In the conventional
techniques of IC design, these rules are still used even that those
design rules are not meaningful as exemplified by a circuit as that
shown in FIGS. 1A and 1B. In order to meet those design rules that
are required for other purposes, current art PDC is highly
inefficient. For many integrated circuits, especially for tightly
pitched layout circuits, such limitations caused increase in
overall layout area. It is therefore desirable to develop an
efficient PDC structure to remove those constraints.
SUMMARY OF THE INVENTION
[0007] The primary objective of this invention is, therefore, to
reduce the areas of poly-to-diffusion connections. The other
primary objective of this invention is to reduce the resistance of
PDC. Another objective is to achieve said simplification without
changing current art IC manufacture procedures.
[0008] These and other objects are accomplished by novel structure
that using a single contact to form PDC.
[0009] While the novel features of the invention are set forth with
particularly in the appended claims, the invention, both as to
organization and content, will be better understood and
appreciated, along with other objects and features thereof, from
the following detailed description taken in conjunction with the
drawing.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1(a) is the top view of a prior art PDC;
[0011] FIG. 1(b) shows the cross-section structures of the prior
art PDC in FIG. 1(a);
[0012] FIG. 2(a) is the top view for a PDC of the present
invention;
[0013] FIG. 2(b) shows the cross-section structures of the PDC in
FIG. 2(a) after contact etching procedure;
[0014] FIG. 2(c) shows the final cross-section structures of the
PDC in FIG. 2(a);
[0015] FIG. 2(d) is the top view for a PDC of the present invention
that does not use metal layer;
[0016] FIG. 2(e) shows the cross-section structures of the PDC in
FIG. 2(d) after contact etching procedure;
[0017] FIG. 2(f) shows the final cross-section structures of the
PDC in FIG. 2(d);
[0018] FIG . 3(a) is the top view for a PDC of the present
invention that has a rectangular contact; and
[0019] FIG. 3(b) shows the cross-section structures of the PDC in
FIG. 3(a).
DETAILED DESCRIPTION OF THE INVENTION
[0020] FIG. 2(a) shows the top view for one example of a PDC of the
present invention. In this example, the poly area (205) is extended
into the depletion area (203). A contact (208) is placed covering
both the poly (205) and depletion (203) areas. The connection is
therefore formed by a single contact (208). FIG. 2(b) shows the
cross section structures of the PDC in FIG. 2(a) after contact
etching procedures have been done. A contact opening (210) is
opened covering both the poly area (215) and the diffusion area
(213). The contact etching procedure will remove the insulating
layers while stopping on silicon. Since both the poly and the
diffusion areas are made of silicon, both areas will be exposed
after the contact etching procedures as shown in FIG. 2(b). The
following contact forming procedures will fill the contact opening
(210) in FIG. 2(b) and form a direct connection between diffusion
and poly as shown in the cross section diagram in FIG. 2(c).
[0021] The PDC of the present invention uses only one contact. Its
area is therefore much smaller than prior art PDC in FIG. 1(a). No
changes in IC manufacture procedures are needed to support the
structure in FIG. 2(a). Therefore, there is no additional cost to
support such connection structures.
[0022] While specific embodiments of the invention have been
illustrated and described herein, it is realized that other
modifications and changes will occur to those skilled in the art.
For example, different contact filling materials can be used to
assure better connections. Different contact etching procedures
also can have similar effects. In the above example, the shared
contact (208, 218) is connected to metal layer (207, 217) so that
other structures also can be connected to this PDC using metal
connections. When there is no need to connect this PDC to other
structures, there would be no need for such metal connection. FIG.
2(d) shows the top view of a PDC of the present invention that uses
a contact without metal connection. FIG. 2(e) and FIG. 2(f) are
cross section views of the structures in FIG. 2(d). Such PDC that
does not use metal layer further optimize the area efficiency of
PDC.
[0023] One potential problem for the above PDC structure is the
possibility for the contact to miss diffusion or poly layer due to
misalignment of the contact. A simple solution is to elongate the
contact area as shown in FIG. 3(a). In this example, the contact
(308) is elongated vertical to the poly/diffusion edge to assure
sufficient connections. The cross section view of such contact
(318) is shown in FIG. 3(b).
[0024] The above examples assume that the PDC contacts of the
present invention are formed in the same time as other metal
contacts for cost-saving reasons. It is certainly an option to use
separated contact etching procedures specifically to form PDC
contacts of the present invention. Using separated contact forming
procedures will increase manufacture costs, but in will allow other
options. One example is to use poly silicon as the contact filling
materials (218, 258, 358). It is also possible to further optimize
the area of PDC contacts using separated manufacture
procedures.
[0025] The present invention provides novel contact structures to
achieve significant area reduction for PDC. While specific
embodiments of the invention have been illustrated and described
herein, it is realized that other modifications and changes will
occur to those skilled in the art. It is therefore to be understood
that the appended claims are intended to cover all modifications
and changes as fall within the true spirit and scope of the
invention.
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