U.S. patent application number 10/277854 was filed with the patent office on 2004-04-22 for surfactants for chemical mechanical polishing.
This patent application is currently assigned to Texas Instruments Incorporated. Invention is credited to Eissa, Mona M., Korthuis, Vincent C., Shinn, Gregory B..
Application Number | 20040074517 10/277854 |
Document ID | / |
Family ID | 32093363 |
Filed Date | 2004-04-22 |
United States Patent
Application |
20040074517 |
Kind Code |
A1 |
Korthuis, Vincent C. ; et
al. |
April 22, 2004 |
Surfactants for chemical mechanical polishing
Abstract
Methods and compositions are disclosed for chemical mechanical
polishing (CMP) of semiconductor substrates, post-CMP storage of
semiconductor substrates and post-CMP cleaning of semiconductor
substrates. The methods and compositions feature the use of
surfactants and, in some cases, passivation agents. The methods and
compositions are particularly suited to polishing, storing and
cleaning semiconductor substrates comprising hydrophobic
surfaces.
Inventors: |
Korthuis, Vincent C.;
(Plano, TX) ; Eissa, Mona M.; (Plano, TX) ;
Shinn, Gregory B.; (Dallas, TX) |
Correspondence
Address: |
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, M/S 3999
DALLAS
TX
75265
|
Assignee: |
Texas Instruments
Incorporated
Dallas
TX
|
Family ID: |
32093363 |
Appl. No.: |
10/277854 |
Filed: |
October 22, 2002 |
Current U.S.
Class: |
134/1.3 ; 134/3;
134/6; 257/E21.304; 510/175 |
Current CPC
Class: |
H01L 21/02074 20130101;
B24B 37/042 20130101; H01L 21/3212 20130101 |
Class at
Publication: |
134/001.3 ;
134/003; 134/006; 510/175 |
International
Class: |
C25F 001/00 |
Claims
What is claimed is:
1. A method for the chemical-mechanical polishing of a surface
material on a semiconductor substrate comprising: a. applying a
liquid comprising a surfactant to the surface material; and b.
polishing the surface material to create a newly-exposed surface
material.
2. The method of claim 1 wherein the surface material comprises
copper.
3. The method of claim 2 wherein the newly-exposed surface material
comprises copper.
4. The method of claim 3 further comprising applying a passivation
agent to the newly-exposed surface material.
5. The method of claim 4 wherein the passivation agent is selected
from the group consisting of benzotriazole, hydroquinone,
pyrogallol, gallic acid and combinations thereof.
6. The method of claim 4 wherein the passivation agent comprises
benzotriazole.
7. The method of claim 1 wherein the surfactant is an anionic
surfactant.
8. The method of claim 1 wherein the surfactant is an cationic
surfactant.
9. The method of claim 1 wherein the surfactant is an nonionic
surfactant.
10. The method of claim 1 wherein the surfactant is Coppeready.RTM.
Post Clean Surfactant.
11. The method of claim 1 wherein the concentration of surfactant
in the liquid is between about 0.01 and about 10 weight
percent.
12. The method of claim 2 wherein the newly-exposed surface
material comprises tantalum.
13. The method of claim 1 wherein at least part of the
newly-exposed surface material is hydrophobic.
14. The method of claim 1 wherein the newly-exposed surface
material comprises a low-k dielectric material.
15. The method of claim 1 wherein the newly-exposed surface
material comprises an organosilica glass.
16. A method for the chemical-mechanical polishing of a surface
material on a semiconductor substrate comprising: a. polishing the
surface material; b. applying a liquid comprising a surfactant to a
newly-exposed surface material; and c. polishing the newly-exposed
surface material.
17. The method of claim 21 wherein the surface material comprises
copper.
18. The method of claim 22 wherein the newly-exposed surface
material comprises copper.
19. The method of claim 23 further comprising applying a
passivation agent to the newly-exposed surface material.
20. The method of claim 24 wherein the passivation agent is
selected from the group consisting of benzotriazole, hydroquinone,
pyrogallol, gallic acid and combinations thereof.
21. The method of claim 24 wherein the passivation agent comprises
benzotriazole.
22. The method of claim 16 wherein the surfactant is an anionic
surfactant.
23. The method of claim 16 wherein the surfactant is an cationic
surfactant.
24. The method of claim 16 wherein the surfactant is an nonionic
surfactant.
25. The method of claim 16 wherein the surfactant is
Coppeready.RTM. Post Clean Surfactant.
26. The method of claim 16 wherein the concentration of surfactant
in the liquid is between about 0.01 and about 10 weight
percent.
27. The method of claim 22 wherein the newly-exposed surface
material comprises tantalum.
28. The method of claim 21 wherein at least part of the
newly-exposed surface material is hydrophobic.
29. The method of claim 21 wherein the newly-exposed surface
material comprises an organosilica glass.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
[0002] Not applicable.
BACKGROUND OF THE INVENTION
[0003] 1. Technical Field of the Invention
[0004] The present invention relates generally to the preparation
of integrated circuits on semiconductor substrates such as silicon
wafers and more particularly to improved methods for
chemical-mechanical polishing (CMP), post-CMP storage prior to
cleaning, and post-CMP cleaning.
[0005] 2. Description of Related Art
[0006] The semiconductor technology central to the modern
integrated circuit has been developing for over a century. In the
late nineteenth century, the special properties of the
semiconductor selenium were first observed and recognized. The
field of semiconductor physics advanced rapidly and the first
transistor was proposed in the 1930s. However, not until the late
1940s was a functional point contact transistor constructed. The
integrated circuit, which employs a plurality of circuit elements
in a monolithic semiconductor substrate rather than using discrete
components, was first developed in the late 1950s by Jack Kilby at
Texas Instruments, Inc.
[0007] Since the late 1950s, integrated circuit technology has
evolved rapidly and has revolutionized virtually every industry and
capacity in which integrated circuits are used. Today's integrated
circuits frequently employ hundreds of thousands or even millions
of transistors and highly complex, multi-layered architectures. The
proliferation of electronics in general, and integrated circuits in
particular, has resulted in large part from the ability to increase
circuit functionality while simultaneously reducing device cost and
size. An important catalyst for these improvements has been
advances in semiconductor processing technologies, the various
techniques used to construct circuit elements-e.g., transistors,
resistors and capacitors-on the semiconductor substrate, as well as
the necessary conducting interconnects between individual circuit
elements. Improved materials, equipment and processes have allowed
increasingly complex circuits having improved speed, reduced power
requirements and a smaller footprint.
[0008] Integrated circuits are typically constructed at the surface
of a crystalline silicon wafer, although other semiconductors such
as gallium arsenide and germanium are also used. The individual
circuit elements are formed in and on the wafer surface. The
electrical conduction between appropriate circuit elements, and
electrical isolation between other circuit elements, is then
established using alternating layers of appropriately patterned
conductors and insulators. The circuit elements and their
interconnections are formed using a series of processing steps
including photolithography, thin film deposition, selective etching
and ion implantation, as well as various cleaning processes.
[0009] Increasingly complex integrated circuits utilize an
increasing number of circuit elements, which in turn requires both
more electrical conduction paths between circuit elements and a
greater number of conductor-insulator layers to achieve these
paths. This has proved problematic for several reasons. First,
longer interconnect paths means increasing resistance and
capacitance, which not only decreases circuit speed by increasing
RC-delay times but also increases resistive power loss. Second, an
increasing number of layers makes successive layer-to-layer
alignment more difficult. This latter problem is compounded by
layers that lack global and local planarity. Historically, the
techniques available to improve layer planarity in the
semiconductor industry have been quite limited.
[0010] Until recently, aluminum was the interconnect conductor of
choice in integrated circuit processing. Techniques for depositing
thin aluminum films are well established and, because aluminum
trichloride is somewhat volatile, aluminum can be etched
effectively in chlorine plasmas to form patterned aluminum films
following appropriate photolithography steps. At the same time,
aluminum interconnects have several undesirable properties. First,
aluminum is not a particularly good conductor: its resistivity is
considerably higher than many other metals. Second, aluminum is
particularly susceptible to electromigration, the physical movement
of a conductor due to electron flow. Electromigration at grain
boundaries results in conductor discontinuities and reduced circuit
reliability.
[0011] The semiconductor industry is transitioning from aluminum to
copper as the electrical conductor of choice for establishing
interconnections between circuit elements. Copper has a
significantly higher conductivity than aluminum and is inherently
more resistant to electromigration. Although these properties of
copper have been known for a long time, the absence of acceptable
methods for selectively etching or otherwise removing copper have
limited its use: unlike aluminum, copper is not amenable to plasma
etch. Thus, a key limitation in moving to copper metallization is
the ability to etch or otherwise remove copper at the wafer
surface.
[0012] The shift to copper metallization is being driven by the
development of chemical mechanical polishing (CMP), a relatively
new technique in semiconductor processing. CMP not only provides a
method for copper removal and for forming patterned copper films
but also addresses the increased need for local and global
planarity in complex integrated circuit architectures.
[0013] Today, CMP is an essential step in the manufacture of almost
every modern integrated circuit. According to the 1997 National
Technology Roadmap for Semiconductors, the typical logic device in
2004 will include seven inner-layer dielectric (ILD) CMP steps,
seven metal CMP steps and one shallow trench isolation (STI) CMP
step. Put simply, CMP is quickly becoming a central aspect of
semiconductor processing in the formation of integrated
circuits.
[0014] CMP is a method of fabricating planar structures by the
selective removal of topography-generating features. The CMP
process involves the controlled removal of material on the wafer
surface through the combined chemical and mechanical action of a
slurry of abrasive particles and a polishing pad on the
semiconductor wafer. The slurries used in CMP are best classified
by the types of films they are intended to planarize. In
semiconductor manufacturing, CMP processes are most commonly used
for films comprised of silicon oxide, tungsten, copper, tantalum
and titanium. CMP of copper films, for example, often employs
slurries based with a complexing agent which offer high copper ion
solubility.
[0015] In addition to polishing of metallization layers, CMP
processing generally also involves barrier layer and dielectric
layer polishing. The dielectric layer is frequently comprised of an
oxide material such as silica that forms the electrically
insulating layer between conducting metal layers. A barrier layer
is a layer disposed between two layers that prevent one layer from
contaminating the other layer and vice versa. Copper metallization
schemes often employ barrier metals such as tantalum or
tantalum-rich alloys between the copper and dielectric layers to
minimize cross-contamination between those layers. A integrated CMP
processing technique should allow the polishing and planarization
of alternating layers such as those described e.g., a layer
comprising copper on a layer comprising tantalum or Ta alloy, on a
layer comprising oxide.
[0016] Following the CMP process, wafers are typically subjected to
a post-CMP cleaning process to remove particulate and molecular
contaminants before continuing the construction of the integrated
circuit. For wafers processed in batches rather than individually,
storage techniques are used following the CMP process and prior to
the post-CMP cleaning process. Storing the wafers frequently
consists of placing them in a cassette filled with an appropriate
liquid such as water.
[0017] For a variety of reasons, currently available CMP techniques
are less than optimal. First, the CMP process involves the use of
small, abrasive particles that can prove difficult to remove from
the wafer surface. Although the slurry particles serve a valuable
role during CMP, they constitute particulate defects following the
CMP process. Consequently, techniques for improving the removal
efficiency of slurry particles are desirable. In addition,
molecular contaminants can be introduced during the CMP process
that are not always effectively removed during post-CMP cleaning.
For wafers processed in lots, the wafer storage process can
introduce additional problems. It has been noted that wafers
removed from storage solutions can evidence streaking wherein
contaminants appear preconcentrated in certain areas on the wafer
surface. Furthermore, exposed copper surfaces are susceptible to
corrosion, resulting in undesirable etching during the post-CMP
storage and cleaning processes.
BRIEF SUMMARY OF THE PREFERRED EMBODIMENTS
[0018] The preferred embodiments of the present invention include
improved methods and compositions for chemical mechanical polishing
(CMP) of semiconductor substrates, storage of semiconductor
substrates following CMP prior to cleaning processes ("post-CMP
storage") and subsequent cleaning processes ("post-CMP
cleaning").
[0019] One preferred embodiment of the present invention involves a
method for CMP that utilizes a surfactant during the CMP process,
preferably when a hydrophobic surface is exposed. Optionally, the
method includes the use of a passivation agent during the CMP
process.
[0020] Another preferred embodiment of the present invention
involves a method for storing semiconductor substrates that
utilizes a surfactant in a post-CMP storage liquid. Optionally, a
passivation agent is also present in the post-CMP storage liquid.
Yet another preferred embodiment of the present invention involves
a composition of a post-CMP storage liquid comprising water, a
surfactant and a passivation agent.
[0021] Yet another preferred embodiment of the present invention
involves a method for post-CMP cleaning of semiconductor substrates
that uses a surfactant, preferably in a liquid and with the
application of a mechanical force. Yet another preferred embodiment
of the present invention involves a composition of a post-CMP
cleaning liquid comprising water, a surfactant and a passivation
agent.
BRIEF DESCRIPTION OF THE DRAWINGS
[0022] For a more detailed description of the present invention,
reference will now be made to the accompanying drawings,
wherein:
[0023] FIG. 1 depicts a wafer in a CMP apparatus comprising a
platen and a wafer carrier;
[0024] FIG. 2 depicts the chemical structure of benzotriazole;
and
[0025] FIGS. 3A-3D depicts the cross-section of a wafer during
various stages of a multi-step CMP process.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0026] In the manufacture of integrated circuits, wafer surface
planarity and quality are of extreme importance. In order to
achieve the degree of planarity required to produce ultra-high
density integrated circuits, CMP processes are being employed. In
general, CMP involves pressing a semiconductor wafer against a
moving polishing surface that is wetted with a chemically reactive,
abrasive slurry. Conventional slurries are either acidic or basic,
and generally contain either fumed or colloidal alumina, silica,
zirconium oxide, magnesium oxide, or cerium oxide abrasive
particles. The polishing surface usually is a planar pad made of a
relatively soft, porous material such as polyurethane.
[0027] The term "semiconductor substrate" as used herein refers to
a substrate comprised of a semiconductor material upon which an
integrated circuit is being, will be or has been constructed.
Typically, the substrate is in the form of a thin, circular wafer.
A variety of semiconductor materials are used in semiconductor
processing such as silicon and gallium arsenide. Furthermore, other
semiconductor materials exist and may be amenable to the methods
and compositions disclosed herein. Therefore, without limiting the
scope of the present invention, the preferred embodiments of the
present invention involve a semiconductor substrate comprised of
silicon. More preferably, the semiconductor substrate is a
single-crystal silicon wafer. Furthermore, the term "semiconductor
substrate" also encompasses a substrate comprised of a
semiconductor upon which other materials have been deposited.
[0028] The term "surface material" as used herein refers to a
material located at the surface of a semiconductor substrate.
Because integrated circuits processing involves the deposition of
patterned thin films on the semiconductor substrate, there will
frequently be two or more surface materials on a semiconductor
substrate. Consequently, references herein to "surface material"
are not intended to imply a single surface material and instead
refer to one or more particular surface materials.
[0029] The semiconductor processing industry has generally
determined that barrier materials facilitate the construction of
high-yield, high-reliability copper interconnects. As used herein,
the term "barrier layer" is a layer disposed between two layers
that prevent one layer from contaminating the other layer and vice
versa. Barrier layers may be deposited by any manner over the
surface of the semiconductor substrate and may be any other region
that functions to protect one layer from an otherwise adjacent
layer or vice versa. Barrier layers generally used in the
semiconductor industry include, for example, tantalum nitride,
titanium nitride, titanium/tungsten, tungsten, tantalum, composites
thereof, and the like. Preferably, barrier layers are comprised of
tantalum nitride when copper metallization is used. The barrier
layer may be of any appropriate thickness. Preferably, the barrier
layer is a few tens of angstroms to several hundred angstroms in
thickness.
[0030] During the course of integrated circuit processing-e.g.,
during CMP processing both copper surfaces and barrier metal
surfaces may be exposed. Differences in the galvanic potentials of
the exposed metals can give rise to a type of corrosion in which
the more easily oxidized metal is etched from the wafer surface.
This phenomenon is frequently referred to as galvanic corrosion.
Because of its galvanic potential, copper is particularly
susceptible to galvanic corrosion.
[0031] Some of the preferred embodiments of the present invention
apply to processes involving hydrophobic surfaces exposed on
semiconductor substrates. Hydrophobic surfaces are typically
non-polar surfaces that do not interact favorably with polar
solvents such as water. Because hydrophobic surfaces are not wet
effectively by these polar solvents, hydrophobic surfaces are
cleaned less effectively than are hydrophilic surfaces when polar
solvents are used. Furthermore, hydrophobic surfaces exposed to
polar solvents are susceptible to beading, meaning that the polar
solvent forms beads on the surface rather than wetting the surface.
As the bead evaporates, the residual contaminants become
preconcentrated in small spots on the hydrophobic surface,
resulting in localized stains or spots with high contaminant
levels.
[0032] Hydrophobic surfaces are frequently generated during the
processing of integrated circuits on semiconductor substrates. For
example, some low-k dielectrics films such as organosilica glasses
(OSGs) are hydrophobic. Similarly, some passivation agents applied
to otherwise hydrophilic surfaces result in hydrophobic surface.
For example, a copper surface passivated with benzotriazole results
in a hydrophobic surface. Hydrophobic surfaces may be characterized
based upon their contact angle with an appropriate liquid material.
Without limiting the scope of the present invention, a hydrophobic
material or surface as used herein refers to a material or surface
having a contact angle with water of greater than five degrees.
[0033] Various dielectric materials are used during semiconductor
processing. Commonly, such dielectric materials are comprised of a
silica-containing material. As used herein, the term "silica"
encompasses pure silica, any type of modified silica such as OSGs
or doped silica and other materials comprising silica.
[0034] The preferred embodiments of the present invention employ
one or more surfactants. Surfactants are typically molecules having
both a polar moiety and a non-polar moiety that assist in the
wetting of hydrophobic surfaces by polar solvents. Surfactants may
be characterized as ionic or nonionic. Ionic surfactants may be
further characterized as cationic or anionic. As will be evident to
a person of ordinary skill, a variety of surfactants may be
suitable in the embodiments of the present invention. Therefore,
without limiting the scope of the invention, the preferred
embodiments of the present invention employ anionic surfactants.
More preferably, the anionic surfactant is Coppeready.RTM. Post
Clean Surfactant (Ashland Chemical). Depending upon its
characteristics, the surfactant employed in the present invention
may be employed neat or as a component in a liquid. The preferred
embodiments of the present invention employ the surfactant as a
component of an aqueous liquid used during a CMP process, a
post-CMP storage process, or a post-CMP cleaning process.
[0035] Some of the preferred embodiments of the present invention
employ a passivation agent to coat an exposed surface material.
Numerous passivation agents may prove adequate in the present
invention. Therefore, without limiting the scope of the present
invention, suitable passivation agents include benzotriazole (BTA),
hydroquinone, pyrogallol, gallic acid and combinations thereof. The
passivation agent may be provided neat or in an appropriate liquid.
Preferably, the passivation agent is BTA alone or in an aqueous
liquid and the exposed surface material comprises a copper surface
exposed following a CMP process.
[0036] CMP Processes
[0037] FIG. 1 depicts single-platen CMP apparatus 10 for polishing
semiconductor wafer 20. Single-platen CMP apparatus 10 comprises
wafer carrier 30 and platen 40 supporting polishing pad 50.
Preferably, single-platen CMP apparatus 10 includes a controller
that allows a variable down force to be applied to wafer carrier
30, allows wafer carrier 30 and platen 40 to be rotated at variable
and independent rates, and allows slurry and/or other materials to
be applied between the surface of semiconductor wafer 20 and
polishing pad 50. During operation, a preselected down force is
preferably applied to wafer carrier 30 to achieve a desired polish
pressure. Also during operation, wafer carrier 30 is preferably
rotated at a desired rate while platen 40 is preferably rotated in
an opposing direction at a desired rate. Preferably, a slurry
having a pH between about 3 and about 11 and comprised of slurry
particles having an average diameter of between about 20 and about
200 nanometers (nm) is present during polishing. More preferably,
the slurry particles are comprised of alumina. The combined action
of the down force of wafer carrier 30, the rotation of wafer
carrier 30 and platen 40 and polishing pad 50, and the chemical and
mechanical effects of the slurry combine to polish the surface of
semiconductor wafer 20.
[0038] According to the preferred embodiments of the present
invention, the CMP apparatus is a multi-platen CMP apparatus. A
multi-platen CMP apparatus comprises a plurality of individual
platens and their associated wafer carriers and polishing pads.
Multi-platen CMP apparatuses allow for the processing of multiple
wafers in parallel or in series. For example, a three-platen CMP
apparatus could be used to process three wafers in parallel at
three times the throughput of a single-platen CMP apparatus. Such
an arrangement would typically use the same slurry, down force and
rotation rates on each of the three platens. Alternatively, where
multiple CMP processes must be performed on each wafer, a
multi-platen apparatus may be used to process wafers in series. For
example, a three-platen CMP apparatus could be used to process
three wafers in series wherein the wafer on the first platen is
subjected to a first CMP process, the wafer on the second platen is
subjected to a second CMP process, and the wafer on the third
platen is subjected to a third CMP process. Such an arrangement
would frequently use different slurries, down forces and/or
rotation rates on each of the three platens depending on the nature
of the individual CMP processes. The preferred embodiments of the
present invention employ a three-platen CMP process.
[0039] The duration of each CMP process may be determined by any
suitable method. For example, the duration of each CMP process may
be calculated by reference to the removal rate and the layer
thickness. Alternatively, the duration of each CMP process may be
determined using any suitable endpoint detection technique. For
example, endpoint detection may involve Eddy current where the film
thickness is monitored or an optical measurement in which an energy
source impinges upon the wafer and the reflectivity of the wafer is
measured. As the surface layer is removed from the wafer over time
to expose the underlying layer, Eddy current or reflectivity of the
wafer will change measurably. Upon the detection of this change in
Eddy current or surface reflectivity, the polishing process can be
terminated. The preferred embodiments of the present invention
employ monitoring film thickness on first platen and stopping prior
to exposing the barrier. The second platen uses a low down force
polishing process where the barrier is exposed and monitoring of
the reflectivity of the wafer signals endpoint, after which a timed
polish to remove residual copper is employed. The third platen
removes the barrier material off the surface of the dielectric by a
timed polish.
[0040] To accomplish planarization, CMP must etch and polish high
film areas at a substantially faster rate than low areas. Copper
CMP involves the creation of a thin passivating layer that is
susceptible to abrasion in high areas but that is resistant to
etching in low areas. The passivating layer may either be a native
oxide film--e.g., Cu.sub.2O--or a normative film formed from the
addition of a separate reagent such as benzotriazole (BTA), as
depicted in FIG. 2. Heterocyclic-nitrogen-based compounds such as
BTA form organometallic complexes at the copper surface. The
ability of the nitrogen atom in these chemicals to bond at the
copper surface facilitates the formation of a hydrophobic
passivating film.
[0041] In one preferred embodiment, the present invention is
directed to methods of using surfactants in CMP processes. CMP
processes can be characterized, in part, based on both the surface
material being removed and the underlying layer. The identities of
both the surface and underlying layer are important in defining the
CMP process because ideally CMP processes offer high etch
selectivities for the surface layer material relative to the
underlying layer material. In other words, CMP processes desirably
have much higher etch rates for the surface layer material than for
the underlying layer material so that a given CMP step essentially
terminates once the underlying layer material is reached. Clearly,
because CMP process strategies should be formulated with an eye
towards not only the surface layer material but also the underlying
layer material, a large number of CMP processes exist. The methods
of the present invention are applicable to a wide variety of CMP
applications. Therefore, without limiting the scope of the present
invention, the preferred embodiments disclosed herein include a
three-platen CMP process for polishing a common design structure in
modern integrated circuits: namely a threelevel stack having a
surface material comprising copper on a barrier material comprising
tantalum on an insulator material comprising silica.
[0042] FIGS. 3A, 3B, 3C and 3D depict a cross-section of a
semiconductor substrate during various stages of a multi-step CMP
process. FIG. 3A depicts the surface topography of semiconductor
substrate 100 prior to CMP comprising surface layer 110, barrier
layer 120, and dielectric layer 130. Preferably, surface layer 110
comprises copper, barrier layer 120 comprises tantalum and
dielectric layer 130 comprises an organosilica glass (OSG). Such
architectures can be formed on semiconductor substrates through a
series of processing steps. For example, dielectric layer 130 can
be formed as a unpatterned layer by blanket deposition on
semiconductor substrate 100. Dielectric layer 130 may be, for
example, silica formed by the decomposition of
tetraethylorthosilicate (TEOS) on semiconductor substrate 100 or by
a spin on glass process. Preferably, dielectric layer 130 is a
low-k dielectric such as an organosilica glass (OSG). Dielectric
layer 130 may then be patterned and etched to form contact holes
exposing selected areas of semiconductor substrate 100 using
standard photolithographic techniques. Following deposition and
patterning of dielectric layer 130, barrier layer 120 may then be
conformally deposited over dielectric layer 130, including in the
contact holes to contact the layer underneath dielectric layer 130
on semiconductor substrate 100. The material deposited to form
barrier layer 120 generally depends on the material comprising
surface layer 110. For example, when surface layer 110 comprises
tungsten (W), barrier layer 120 typically comprises titanium
(Ti)--e.g., Ti, titanium nitride (TiN), or a Ti/TiN stack. However,
when surface layer 110 comprises copper (Cu), barrier layer 120
typically comprises tantalum (Ta) e.g., Ta, tantalum nitride (TaN)
or a Ta/TaN stack. According to one preferred embodiment, surface
layer 110 comprises copper and barrier layer 120 comprises Ta or
TaN or Ta/TaN bilayer.
[0043] FIGS. 3B, 3C and 3D depict a cross-sectional view of the
surface of semiconductor substrate 100 of FIG. 3A at various stages
of the process of the preferred embodiments of the present
invention. Silicon wafers having a surface topography of copper on
a tantalum-rich barrier on an organosilica glass (OSG) as depicted
in FIG. 3A were subjected to a three-platen CMP process for removal
of copper and barrier metal. FIG. 3B depicts a cross-section of
semiconductor substrate 100 of FIG. 3A following CMP on the first
platen in which a bulk copper removal is performed. FIG. 3C depicts
a cross-section of semiconductor substrate 100 of FIG. 3B following
CMP on the second platen in which a residual copper removal is
performed. FIG. 3D depicts a cross-section of semiconductor
substrate 100 of FIG. 3C following CMP on the third platen in which
barrier layer 120 was removed.
[0044] As depicted in FIG. 3B, the first CMP process of the
three-step CMP process comprises the bulk removal of surface layer
110 on the first platen. In the first CMP process, semiconductor
substrate 100 is loaded on a first wafer carrier associated with
the first platen in a three-platen CMP apparatus. A controller
initially causes a high pressure water spray and a surfactant to be
sprayed on a polishing pad located on the platen to clean the
surface of the pad prior to polish. The controller then causes a
dispenser to dispense a first slurry to the surface of the
polishing pad. Preferably, the first slurry is dispensed at a flow
rate between about 50 and about 500 milliliters per minute
(ml/min). More preferably, the slurry is dispensed at a flowrate of
about 200 ml/min for 200 mm wafers. The first slurry is any slurry
suitable for polishing a surface layer comprising copper on a
barrier layer comprising tantalum. Preferably, the first slurry has
a selectivity ratio of greater than ten-to-one for copper to
tantalum. Typical slurries appropriate for a copper CMP process
include an alumina abrasive having an average particle size of
between 20 and 200 nm, an oxidizer and a corrosion inhibitor.
Preferably, the oxidizer is hydrogen peroxide (H.sub.2O.sub.2) and
the corrosion inhibitor is benzotriazole.
[0045] During the first CMP step, the controller also causes the
first wafer carrier to rotate. Preferably, the first wafer carrier
rotates at a rate of between about 18 and about 150 rotations per
minute (rpm). At the same time, the controller also causes the
first platen to orbit relative to the first wafer carrier.
Preferably, the first platen orbits at a rate of between about 20
and about 150 rpm. The controller also causes a polishing pressure
to be exerted between the platen and the wafer carrier. Preferably,
the polishing pressure is between about 1 and about 6 pounds per
square inch (psi).
[0046] The combined chemical etching effect of the slurry and the
mechanical abrasion effect of the pressure and rotation cause the
removal of surface material from semiconductor substrate 100.
Because the first CMP polishing process is used to remove the bulk
of surface layer 110 without polishing barrier layer 120, the first
CMP step may be optimized for a high removal rate. Preferably, the
removal rate is between about 1,000 and about 10,000 A/min. The
first CMP process continues until the bulk of surface layer 110 is
removed and stops slightly before barrier layer 120 is exposed.
Consequently, as illustrated in FIG. 3B, a relatively thin surface
layer 110 remains above barrier layer 120.
[0047] Following the first CMP process, the wafer is rinsed with
Coppeready.RTM. Post Clean Surfactant (Ashland) before being
transferred to a second wafer carrier. Without limiting the scope
of the invention, such rinses serve several important purposes.
First, these rinses eliminate contaminants and particles introduced
or created during the prior CMP process. Furthermore, the CMP
slurries used to polish copper are radically different and may even
be chemically incompatible with the CMP slurries used to polish the
underlying barrier material. Thus, a rinsing process reduces the
deposition of contamination from one polishing pad on another
polishing pad. In addition to rinsing the wafer, one or more
various adjacent platens (especially the second platen and/or the
third platen), may also be rinsed along with the wafer. This
rinsing of the wafer, the second platen, and/or the third platen,
significantly reduces cross contamination between platens.
[0048] Referring to FIG. 2C, the next step is a second CMP process
in which surface layer 110 remaining above barrier layer 120 is
removed. In the second CMP process, semiconductor substrate 100 is
loaded on a second wafer carrier associated with a second platen in
the conventional three-platen CMP apparatus. During the second CMP
process, the down force pressure and rotation rates for the second
wafer carrier and platen are reduced relative to the first wafer
carrier and first platen to reduce the removal rate. The controller
initially causes a high pressure water spray and a surfactant to be
sprayed on a polishing pad located on the platen. To clean the
surface of the pad prior to the polish. Preferably, the surfactant
flow is between 10 and 100 ml/min and the deionized water high
pressure spray is 1-10 L per minute. Preferably, the first slurry
is again dispensed at a flow rate between about 50 and about 500
milliliters per minute (ml/min). During the second CMP process, the
controller causes the second wafer carrier to rotate. Preferably,
the second wafer carrier rotates at a rate of between about 20 and
about 120 rpm and provides a polishing pressure of about 1 to about
3 psi. At the same time, the controller also causes the second
platen to orbit relative to the first wafer carrier. Preferably,
the second platen orbits at a rate of between about 20 and about
150 rpm. The second CMP process continues until barrier layer 120
is exposed.
[0049] As depicted in FIG. 3C, the CMP process on the second platen
removes the remaining copper down to barrier layer 120. Because of
the recessed surface material from surface layer 100 in FIG. 3B, as
depicted in FIG. 3C, following the polishing on the second platen,
material from both surface layer 110 and barrier layer 120 are
exposed. After the optical endpoint signal is received, BTA is then
applied while the surface wafer is being polished for a fixed time
period. The force applied to the wafer to polish is then reduced
and BTA saturates the surface of the pad and wafer.
[0050] Referring to FIG. 3D, the next step is a third CMP process
in which newly-exposed barrier layer 120 is removed. In the third
CMP process, semiconductor substrate 100 is loaded on a third wafer
carrier associated with a third platen in the three-platen CMP
apparatus. During the third CMP process, barrier layer 120 is
removed to expose dielectric layer 130 underneath. The controller
initially causes a high pressure water spray and a surfactant to be
sprayed on a polishing pad located on the platen to clean the
surface of the pad. Preferably, the surfactant flow is between 10
and 100 ml/min and the deionized water high pressure spray is 1-10
L per minute. The controller then causes a dispenser to dispense a
second slurry to the surface of the polishing pad. Preferably, the
second slurry is dispensed at a flow rate between about 50 and
about 500 milliliters per minute (ml/min). Preferably, the second
slurry is any slurry suitable for polishing a barrier layer
comprising tantalum tantalum nitride on silica. Preferably, the
second slurry has a selectivity ratio of greater than ten-to-one
for tantalum to silica.
[0051] During the third CMP process, the controller also causes the
third wafer carrier to rotate. Preferably, the third wafer carrier
rotates at a rate of between about 18 and about 36 rotations per
minute (rpm) and provides a polishing pressure of about 3 to about
6 psi. At the same time, the controller also causes the third
platen to orbit relative to the first wafer carrier. Preferably,
the third platen orbits at a rate of between about 20 and about 150
rpm. The third CMP process continues until the barrier layer 120 is
removed and dielectric layer 130 is exposed, as illustrated in FIG.
3D.
[0052] Following the third CMP process, the wafer is rinsed with
BTA at flow between 50-200 ml/min while the wafer is in contact
with the surface of the pad for a time period between 1 and 30 s.
The wafer is then rinsed with a high pressure spray of deionized
water and surfactant where the flow of the water is between 1 L/min
and 10 L/min and the surfactant flow between 10 ml/min and 100
ml/min before being transferred for storage prior to a post-CMP
cleaning process. Post-CMP Storage Processes and Compositions
[0053] Frequently, semiconductor substrates such as silicon wafers
are processed using batch techniques in which lots comprising
multiple wafers are subjected to identical processing steps in
serial fashion. For example, in the case of CMP processing, a lot
or batch of wafers may be processed one by one until the CMP
process has been completed for all wafers before subjecting the lot
to post-CMP cleaning processes. This type of batch processing
results in the need to store wafers between processes.
[0054] Although BTA and related chemicals are useful during the CMP
processing step, they introduce difficulties during the post-CMP
cleaning step. BTA, like organic chemicals in general, is
hydrophobic and the passivating layer formed using BTA is
hydrophobic. Consequently, the aqueous liquids used to clean the
wafer surface following copper CMP processing are not entirely
effective at wetting the wafer surface and the result is an
undesirably high number of defects following the post-CMP storage
and post-CMP cleaning processes.
[0055] The storage liquid described in the preferred embodiments of
the present invention may find application in any storage operation
employed during semiconductor processing. Therefore, without
limiting the scope of the invention, the preferred embodiments of
the present invention employ the storage liquid during post-CMP
storage. Preferably, the storage solution is employed during
post-CMP storage when a hydrophobic surface is exposed on the
semiconductor substrate. According to one preferred embodiment, the
hydrophobic surface is a low-k dielectric comprised of an OSG.
According to another preferred embodiment, the hydrophobic surface
is a passivated copper surface.
[0056] According to one preferred embodiment of the present
invention, semiconductor substrates such as wafers that have
completed one processing step and are awaiting another process step
are placed in an aqueous liquid comprising one or more surfactants.
Preferably, the concentration of the surfactant is between
approximately 0.01 percent by weight and approximately 10 percent
by weight. This storage may further comprise one or more
passivation agents when the exposed surface includes a material
susceptible to degradation such as by galvanic corrosion.
Preferably, if the surface includes a copper surface material, the
passivation agent is BTA and is present at a concentration of
between about 0.002 weight percent and about 1 weight percent. It
may also in conjunction with the BTA solution contain a surfactant
solution to be at a concentration of between 10 ppm to 500 ppm.
[0057] Post-CMP Cleaning Processes and Compositions
[0058] The cleaning liquids described in the preferred embodiments
of the present invention may find application in any cleaning
operation employed during semiconductor processing. Therefore,
without limiting the scope of the invention, the preferred
embodiments of the present invention employ the cleaning liquid
during post-CMP cleaning. Preferably, the cleaning liquid is
employed during post-CMP cleaning when a hydrophobic surface is
exposed on the semiconductor substrate. According to one preferred
embodiment, the hydrophobic surface comprises a low-k dielectric
comprised of an OSG. According to another preferred embodiment, the
hydrophobic surface comprises a passivated copper surface.
[0059] The constituents of the cleaning liquid may be mixed
together in any order. Preferably, though, surfactant is added to
an aqueous liquid comprising the other components of the cleaning
liquid. Ideally, the resulting solution is filtered before use
using a 0.1 .mu.m or better filter. The cleaning liquids employed
in the preferred embodiments of the present invention are aqueous
liquids. Such aqueous liquids may be low pH solutions having a pH
less than 7 (the pH of pure water) and comprising one or more
acidic components such as hydrochloric acid, acetic acid or citric
acid. Alternatively, such aqueous liquids may also be high pH
solutions having a pH greater than 7 and comprising one or more
basic components such as tetramethylammonium hydroxide. Such
aqueous liquids may also be neutral pH solutions having a pH of
approximately 7 and comprising either no acidic or basic components
or alternatively, comprising both acidic and basic components whose
combined effect is to retain a pH of approximately 7. The preferred
embodiments of the present invention employ low pH cleaning
liquids.
[0060] The cleaning processes of the present invention may employ
low pH cleaning liquids, high pH cleaning liquids and/or neutral pH
cleaning liquids. Preferably, though, the cleaning processes
employed herein comprise sequential cleaning processes in which two
or more distinct cleaning liquids are employed. Preferably, one or
more of these cleaning liquids comprises a surfactant. More
preferably, a cleaning process comprises cleaning a surface
material on a semiconductor substrate in a low pH cleaning
solution, followed by cleaning in a high pH cleaning solution,
followed by an approximately neutral pH cleaning solution,
preferably purified water.
[0061] The cleaning processes of the present invention can be
performed at any stage of integrated circuit processing. However,
the preferred embodiments of the present invention employ post-CMP
cleaning processes that follow a CMP process. Preferably, these
cleaning processes are performed under conditions that facilitate
the removal of both particulate and molecular contaminants on the
semiconductor substrate surface. Preferably, the cleaning processes
of the present invention include the application of mechanical
force to assist in the removal of contaminants from the wafer
surface. This type of mechanical force includes any type of
mechanical agitation. Therefore, without limiting the scope of the
present invention, representative examples of mechanical agitation
include buffing, rubbing, brushing or vibrating the surface of the
semiconductor substrate. Preferably, the mechanical agitation
comprises sonic or ultrasonic energy during cleaning. The term
"ultrasonic" as used herein includes megasonic cleaning, which
generally comprises not only of high-frequency mechanical
vibrations, but also the application of a shearing force caused by
directed beams that run parallel to the silicon surface.
[0062] During a cleaning process, the temperature may be maintained
so as to facilitate contaminant removal from the surface material
on the semiconductor substrate. Preferably, the temperature in the
cleaning liquid is maintained between approximately ambient
temperature and approximately 50.degree. C. Most preferably,
cleaning processes employing low pH cleaning liquids are performed
at approximately ambient temperatures and cleaning processes
employing high pH and neutral pH cleaning liquids are performed at
between 20 and 45.degree. C.
[0063] Following cleaning processes, semiconductor substrates such
as wafers may be subjected to an appropriate drying step to remove
residual liquids from the substrate surface. The preferred
embodiments of the present invention include an isopropyl alcohol
(IPA) drying step in which one or more surfactants are present on
the surface of the wafer.
[0064] While the preferred embodiments of the present invention
have been shown and described, modifications thereof can be made by
one skilled in the art without departing from the spirit and
teachings of the invention. The embodiments described herein are
exemplary only, and are not intended to be limiting. Many
variations and modifications of the invention disclosed herein are
possible and are within the scope of the invention.
[0065] Accordingly, the scope of protection is not limited by the
description set out above, but is only limited by the claims which
follow, that scope including all equivalents of the subject matter
of the claims. Each and every claim is incorporated into the
specification as an embodiment of the present invention. Thus the
claims are a further description and are an addition to the
preferred embodiments of the present invention. Use of the term
"optional" with respect to any element of a claim is intended to
mean that the subject element is required, or alternatively, is not
required. Both alternatives are intended to be within the scope of
the claim. The discussion of a reference in the Description of
Related Art, if any, is not an admission that it is prior art to
the present invention, especially any reference that may have a
publication date after the priority date of this application. The
disclosures of all patents, patent applications and publications
cited herein are hereby incorporated herein by reference, to the
extent that they provide exemplary, procedural or other details
supplementary to those set forth herein.
* * * * *