U.S. patent application number 10/626272 was filed with the patent office on 2004-04-15 for chip carrier, semiconductor package and fabricating method thereof.
This patent application is currently assigned to Siliconware Precision Industries Co., Ltd.. Invention is credited to Chen, Chien-Chih, Lai, Chin-Wen, Lai, Yu-Ting.
Application Number | 20040072389 10/626272 |
Document ID | / |
Family ID | 25466908 |
Filed Date | 2004-04-15 |
United States Patent
Application |
20040072389 |
Kind Code |
A1 |
Chen, Chien-Chih ; et
al. |
April 15, 2004 |
Chip carrier, semiconductor package and fabricating method
thereof
Abstract
A chip carrier, a semiconductor package and a fabricating method
thereof are proposed, in which on one side of the chip carrier
finally removed from an engaged surface of a mold in a de-molding
process there is formed at least one grounding means corresponding
in position to an eject pin of the mold, so as to allow a gear
amount of electrical static generated on a surface of the
semiconductor package during molding and de-molding to be
discharged to the outside, instead of being retained on a
semiconductor chip, conductive elements and conductive traces of
the semiconductor package. This therefore can prevent electrical
leakage and damage to the semiconductor chip from occurrence, and
improve the quality and production efficiency for the semiconductor
package.
Inventors: |
Chen, Chien-Chih;
(Kaohsiung, TW) ; Lai, Yu-Ting; (Taichung, TW)
; Lai, Chin-Wen; (Taichung, TW) |
Correspondence
Address: |
EDWARDS & ANGELL, LLP
P.O. BOX 55874
BOSTON
MA
02205
US
|
Assignee: |
Siliconware Precision Industries
Co., Ltd.
|
Family ID: |
25466908 |
Appl. No.: |
10/626272 |
Filed: |
July 24, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10626272 |
Jul 24, 2003 |
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09935312 |
Aug 22, 2001 |
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6617680 |
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Current U.S.
Class: |
438/127 ;
257/E21.504; 257/E23.069 |
Current CPC
Class: |
H01L 2224/451 20130101;
H01L 2924/00014 20130101; H01L 2224/48091 20130101; H01L 2224/73265
20130101; H01L 23/49816 20130101; H01L 2224/73265 20130101; H01L
2924/15311 20130101; H01L 2924/00014 20130101; H01L 2924/01079
20130101; H01L 2924/15311 20130101; H01L 24/48 20130101; H01L 24/45
20130101; H01L 2224/48091 20130101; H01L 21/565 20130101; H01L
2924/01078 20130101; H01L 2224/48227 20130101; H01L 2224/48227
20130101; H01L 2924/00 20130101; H01L 2924/00014 20130101; H01L
2224/73265 20130101; H01L 2924/00012 20130101; H01L 2224/32225
20130101; H01L 2924/00015 20130101; H01L 2924/00014 20130101; H01L
2224/32225 20130101; H01L 2224/451 20130101; H01L 2924/181
20130101; H01L 2224/32225 20130101; H01L 2224/451 20130101; H01L
2924/181 20130101; H01L 2224/48227 20130101; H01L 2224/05599
20130101 |
Class at
Publication: |
438/127 |
International
Class: |
H01L 021/44; H01L
021/48; H01L 021/50 |
Claims
What is claimed is:
1. A chip carrier, comprising: a first side; a second side opposing
the first side and removed finally from an engaged surface of a
mold in a de-molding proess; and at least one grounding means
formed on the second side corresponding in position to an eject pin
of the mold.
2. The chip carrier of claim 1, further comprising: a base layer
having a first and a second surface opposing the first surface; a
plurality of conductive traces disposed on the first surface of the
base layer and elecically connected to a semiconductor chip; a
plurality of ball pads formed on the second surface of the base
layer for implanting a plurality of solder balls thereon; a
plurality of vias for electrically connecting the conductive traces
to the ball pads respectively; a die pad formed on the first
surface of the base layer for mounting the semicondutor chip
thereon; and a solder mask layer deposited on each of the first and
second surfaces of the base layer in a manner that part of the
conductive traces electrically connected to the semiconductor chip
on the first surface and the ball pads on the second surface are
respectively exposed to outside of the solder mask layer.
3. The chip carrier of claim 1, wherein the grounding means is
formed by plating a conductive material.
4. The chip carrier of claim 3, wherein the conductive material is
gold.
5. The chip carrier of claim 2, wherein the grounding means is
exposed to the outside of the solder mask layer.
6. The chip carrier of claim 2, wherein the grounding means is
electrically connected to a grounding trace disposed on the first
side of the chip carrier by a grounding via formed through the base
layer.
7. A semiconductor package, comprising: a chip carrier having a
first side and a second side opposing the first side; at least one
semiconductor chip mounted on the first side of the chip carrier; a
plurality of conductive elements for electrically connecting the
semiconductor chip to the chip carrier: an encapsulant formed of a
molding compound for encapsulating the semiconductor chip and the
conductive elements on the first side of the chip carrier: and a
plurality of solder balls implanted on the second side of the chip
carrier; wherein on one of the sides of the chip carrier finally
removed from an engaged surface of a mold in a de-molding process
there is formed at least one grounding means corresponding in
position to an eject pin of the mold.
8. The semiconductor package of claim 7, wherein the chip carrier
further comprises: a base layer having a first surface and a second
surface opposing the first surface; a plurality of conductive
traces disposed on the first surface of the base layer and
electrically connected to the semiconductor chip; a plurality of
ball pads formed on the second surface of the base layer for
implanting the solder balls thereon; a plurality of vias for
electrically connecting the conductive traces to the ball pads
respectively; a die pad formed on the first surface of the base
layer for mounting the semiconductor chip thereon; and a solder
mask layer deposited on each of the first and second surfaces of
the base layer in a manner that part of the conductive traces
electrically connected to the semiconductor chip on the first
surface and the ball pads on the second surface are respectively
exposed to outside of the solder mask layer.
9. The semiconductor package of claim 7, wherein the grounding
means is formed by plating a conductive material.
10. The semiconductor package of claim 9, wherein the conductive
material is gold.
11. The semiconductor package of claim 8, wherein the grounding
means is exposed to the outside of the solder mask layer.
12. The semiconductor package of claim 8, wherein the grounding
means is electrically connected to a grounding trace disposed on
the first side of the chip carrier by a grounding via formed
through the base layer.
13. A fabricating method of a semiconductor package, comprising:
preparing a chip carrier having a first side, and a second side
opposing the first side and finally removed from an engaged surface
of a mold in a de-molding process, wherein at least one grounding
means is formed on the second side corresponding in position to an
eject pin of the mold; performing a die bonding process for
mounting at least one semiconductor chip on the first side of the
chip carrier; providing a plurality of conductive elements for
electrically connecting the semiconductor chip to the chip carrier;
performing a molding process for forming an encapsulant for
encapsulating the semiconductor chip and the conductive elements on
the first side of the chip carrier; performing a de-molding process
for ejecting the semi-fabricated semiconductor package from the
mold by using the eject pins on the mold; performing a ball
implanting process for implanting a plurality of solder balls on
the second side of the chip carrier; and performing a singulating
process for forming individual fabricated semiconductor
packages.
14. The fabricating method of claim 13, wherein the chip carrier
further comprises: a base layer having a first surface and a second
surface opposing the first surface; a plurality of conductive
traces disposed on the first surface of the base layer and
electrically connected to the semiconductor chip; a plurality of
ball pads formed on the second surface of the base layer for
implanting the solder balls thereon; a plurality of vias for
electrically connecting the conductive traces to the ball pads
respectively; a die pad formed on the first surface of the base
layer for mounting the semiconductor chip thereon; and a solder
mask layer deposited on each of the first and second surfaces of
the base layer in a manner that part of the conductive traces
electrically connected to the semiconductor chip on the first
surface and the ball pads on the second surface are respectively
exposed to outside of the solder mask layer.
15. The fabricating method of claim 13, wherein the grounding means
is formed by plating a conductive material.
16. The fabricating method of claim 15, wherein the conductive
material is gold.
17. The fabricating method of claim 14, wherein the grounding means
is exposed to the outside of the solder mask layer.
18. The fabricating method of claim 14, wherein the grounding means
is electrically connected to a grounding trace disposed on the
first side of the chip carrier by a grounding via formed through
the base layer.
19. The chip carrier of claim 1, further comprising: at least one
grounding means formed on the first side of the chip carrier
corresponding in position to the eject pin of the mold.
20. The semiconductor package of claim 7, wherein on one of the
sides of the chip carrier not finally removed from the engaged
surface of the mold in the de-molding process there is further
formed at least one grounding means corresponding in position to
the eject pin of the mold.
21. The fabricating method of claim 13, wherein the chip carrier
further comprises: at least one grounding means formed on the first
side of the chip carrier corresponding in position to the eject
pins of the mold.
Description
FIELD OF THE INVENTION
[0001] This invention relates to chip carriers, semiconductor
packages and fabricating methods of the semiconductor packages, and
more particularly, to a chip carrier, a semiconductor package and a
fabricating method of the semiconductor package, in which
electrical static produced on a surface of the semiconductor
package is discharged to outside of the semiconductor package.
BACKGROUND OF THE INVENTION
[0002] It is desired for semiconductor packages to be provided with
I/O connections in higher density, in an effort to improve
electrical and operational performance for electronic products.
Therefore, a BGA semiconductor package employs a plurality of
array-arranged solder balls for electrically connecting a
semiconductor chip to external devices, so as to desirably increase
the I/O connections for allowing the BGA semiconductor package to
be a mainstream product.
[0003] Generally, as shown in FIG. 8, a BGA semiconductor package 1
substantially comprises a chip carrier 10 having a first side and a
second side opposing the first side; a semiconductor chip 40
mounted on the first side of the chip carrier 10; a plurality of
conductive elements 50 such as metallic bonding wires for
electrically connecting the semiconductor chip 40 to the chip
carrier 10; an encapsulant 70 formed of a molding compound such as
epoxy resin for encapsulating the semiconductor chip 40 and the
conductive elements 50 on the first side of the chip carrier 10;
and a plurality of solder balls 80 implanted on the second side of
the chip carrier 10 for electrically connecting the semiconductor
chip 40 to external devices.
[0004] The chip carrier 10 is commonly made of a material such as
BT (bismaleimide triazine) resin, and includes a base layer 11
having a first surface and a second surface opposing the first
surface. On the first surface of the base layer 11 there are formed
a die pad 16 for mounting the semiconductor chip 40 thereon and a
plurality of conductive traces 12 electrically connected to the
semiconductor chip 40. On the second surface of the base layer 11
there are disposed a plurality of ball pads 14 for implanting
solder balls 80 thereon, while the ball pads 14 are electrically
connected to the conductive traces 12 by a plurality of vias 13
formed through the base layer 11. A solder mask layer 15 is formed
on each of the first and second surfaces of the base layer 11, in a
manner that part of the conductive traces 12 electrically connected
to the semiconductor chip 40 on the first surface and the ball pads
14 on the second surface are respectively exposed to outside of the
solder mask layer 15, so as to prevent the conductive traces 12
from coming into contact with one another for eliminating the
occurrence of short circuit, and protect the conductive traces 12
against external detrimental factors.
[0005] The BGA semiconductor package 1 is fabricated by the steps
as follows: preparing a chip carrier as the one described above;
performing a die bonding process for mounting at least one
semiconductor chip on a die pad formed on a first side of the chip
carrier; providing a plurality of conductive elements for
electrically connecting the semiconductor chip to the chip carrier;
performing a molding process for forming an encapsulant, which
encapsulated the semiconductor chip and the conductive elements on
the first side of the chip carrier; performing a de-molding process
for ejecting the semi-fabricated semiconductor package from a mold
used in the molding process by eject pins formed on the mold;
performing a ball implanting process for implanting a plurality of
solder balls on ball pads formed on a second side of the chip
carrier; and performing a singulating process for forming
individual fabricated semiconductor packages.
[0006] U.S. Pat. No. 5,450,283 discloses a mold 100, which can be
used in the foregoing molding and de-molding processes, as shown in
FIG. 4. The mold 100 includes a top mold 110 and a bottom mold 120
engaged with the top mold 110, wherein plurality of eject pins 111,
121 respectively having bias means 112, 122 such as spiral springs
are formed on the top and bottom molds 110, 120. Further, on an
engaged surface of the top mold 110 there is formed a molding
cavity 113, while on an engaged surface of the bottom mold 120
there is formed a plurality of pilot pins 123 for positioning a
chip carrier.
[0007] FIGS. 4A-4D illustrate the steps involved in using the
conventional mold 100 in the foregoing molding and de-molding
processes. After completing the die bonding and electrically
connecting processes, the semi-fabricated semiconductor package 1A
is horizontally placed on the engaged surface of the bottom mold
120, in a manner that a plurality of pilot holes 18 preformed on
the chip carrier 10 are coupled to the pilot pins 123 of the bottom
mold 120, for positioning the chip carrier 10 on the engaged
surface of the bottom mold 120. Then, the top mold 110 is engaged
with the bottom mold 120 for performing the molding process,so as
to form the encapsulant 70 for encapsulating the semiconductor chip
and the conductive elements on the first side of the chip carrier
10, as shown in FIG. 4B.
[0008] Then, the de-molding process is performed for ejecting the
semiconductor package 1A from the mold 100. As shown in FIG. 4C,
first, the top mold 110 is moved upwardly, so as to eject the
semi-fabricated semiconductor package 1A after molding from the
molding cavity 113 of the top bottom 110 by resilient force of the
bias means 112, while the eject pins 111 of the top mold 110 are
maintained in position, and the semi-fabricated semiconductor
package 1A are retained on the engaged surface of the bottom mold
120
[0009] Moreover, as shown in FIG. 4D, the bottom mold 120 is moved
downwardly to an end position, where the eject pins 121 counteract
bias force of the bias means 122 and protrude from the engaged
surface of the bottom mold 120, so as to eject the semi-fabricated
semiconductor package 1A from the engaged surface of the bottom
mold 120, and remove the semi-fabricated semiconductor package 1A
from the mold 100.
[0010] In the molding process, a molding compound used for forming
the encapsulant 70 is injected to the molding cavity 113 of the
mold 100, and a large amount of electrical static is produced due
to friction between mold flow of the molding compound and a solder
mask layer 15 on the chip carrier 10 disposed on the engaged
surface of the bottom mold 120. Similarly, in the de-molding
process, electrical static is also generated at a great amount
during ejecting the semi-fabricated semiconductor package 1A from
the mold 100. However, as the solder mask layer 15 on the chip
carrier 10 and the encapsulant 70 are both made of electrical
insulative materials, the electrical static can not be transmitted
therethrough to the mold 100 to be discharged to outside of the
mold 100. Therefore, the electrical static is retained on the
semiconductor chip, the conductive elements or the conductive
traces of the semi-fabricated semiconductor package 1A. This
seriously damages the package, and tends to cause electrical
leakage, as well as deteriorates the quality of the package.
[0011] Accordingly, U.S. Pat. No. 6,214,645 discloses a mold and a
chip carrier for preventing electrical static from being retained
therein, as shown in FIGS. 5-7. In a first embodiment of the chip
carrier, besides a solder mask layer 15, on a second side of the
chip carrier 10 disposed on an engaged surface of a bottom mold 120
there is formed a metallic protrusion 20 to be used as a grounding
means, for being electrically connected to the engaged surface of
the bottom mold 120, so as to allow the electrical static to be
discharged through the metallic protrusion 20 and the bottom mold
120 to the outside in a molding process, as shown in FIG. 5.
[0012] In a second embodiment of the chip carrier, as shown in FIG.
6, on an inside wall of a pilot hole 18 disposed in the chip
carrier 10 there is formed by a conventional technique, such as
electrically plating, a metal layer 23 to be used as a grounding
means. In the molding process, the metal layer 23 is electrically
connected to a pilot pin 123 on the engaged surface of the bottom
mold 120, for allowing the electrical static to be discharged to
the outside through the metal layer 23 and the bottom mold 120.
[0013] In a third embodiment of the mold, as shown in FIG. 7, on a
runner 32 of a top mold 110 there proudes a protrusion 35 to be
used as a grounding means. In the molding process, the protrusion
35 is electrically connected to a metallic runner 17 on the chip
carrier 10, so as to allow the electrical static to be discharged
to the outside through the protrusion 35 and the top mold 110.
[0014] In practice, by determining a value of the electrical static
produced in the semiconductor package 1A during molding and
de-molding, it is observed that the electrical static, generated
due to the friction between the mold flow of the molding compound
and the solder mask layer 15 on the chip carrier 10, is discharged
through the grounding means such as the metallic protrusion 20, the
metal layer 23 and the protrusion 35 and then through the mold 100
to the outside.
[0015] However, during de-molding as shown in FIG. 4C, as the top
mold 110 is moved upwardly for ejecting the semiconductor package
1A from the molding cavity 113 of the top mold, the protrusion 35
protruding from the top mold 110 in the foregoing embodiment of the
mold is disconnected from the metallic runner 17 of the chip
carrier 10, and thus can not function as the grounding means.
Accordingly, the electrically static subsequently produced during
ejecting the semiconductor package 1A from the bottom mold 120 can
not be transmitted to the mold 100 and discharged through the mold
100 to the outside, whereas the electrically static is retained on
the semiconductor chip, the conductive elements or the conductive
traces in the semiconductor package 1A. Moreover, the chip carrier
various in dimension and type has the metallic runner variably
formed in shape and position, and accordingly the top mold having
the corresponding protrusion is needed, which increases the
fabrication cost for the semiconductor package. Further, the
correspondinglyimensioned mold has to be employed during molding,
which increases the fabrication time and reduces the production
efficiency.
[0016] In addition, in the foregoing first embodiment of the chip
carrier, the metallic protrusion 20 keeps in electrical connection
with the engaged surface of the bottom mold 120 during ejecting the
semiconductor package 1A from the top mold 110, however, the
metallic protrusion 20 is disconnected from the bottom mold 120 and
can not act as the grounding means when the bottom mold 120 is
moved downwardly for ejecting the semiconductor package 1A from the
engaged surface of the bottom mold 120 by using the eject pins 121
on the bottom mold 120, as shown in FIG. 4D. Therefore, the
electrically static generated during ejecting the semiconductor
package 1A from the bottom mold 120 can not be transmitted and
discharged through the mold 100 to the outside, nevertheless, the
electrically static is retained on the semiconductor chip, the
conductive elements or the conductive traces in the semiconductor
package 1A. Furthermore, the formation of the metallic protrusion
20 as the grounding means on the chip carrier 10 also increases the
complexity and cost in fabrication in this embodiment of the chip
carrier.
[0017] Similarly, in the foregoing second embodiment of the chip
carrier, the metal layer 23 formed as the grounding means on the
inside wall of the pilot hole 18 keeps in electrical connection
with the pilot pin 123 of the bottom mold 120 during ejecting the
semiconductor package 1A from the top mold 110; however, the metal
layer 23 is disconnected from the pilot pin 123 and can not further
function as the grounding means when the bottom mold 120 is moved
downwardly for ejecting the semiconductor package 1A from the
engaged surface of the bottom mold 120 by using the eject pins 121
on the bottom mold 120 as shown in FIG. 4D. This makes the
electrically static generated during ejecting the semiconductor
package 1A from the bottom mold 120 retained on the semiconductor
chip, the conductive elements or the conductive in the
semiconductor package 1A, instead of being transmitted and
discharged to the outside through the mold 100. Moreover, the pilot
hole is generally constructed with positioning accuracy, for
example, around 1.5.+-.0.05 mm, so as to control deviation in
position for the encapsulant within 0.05 mm. However, the formation
of the metal layer 23 on the inside wall of the pilot hole 18 makes
the positioning accuracy for the pilot hole become 1.5.+-.0.1 mm,
which then increases the deviation for the encapsulant in position
and accordingly degrades the quality of the semiconductor
package.
SUMMARY OF TRE INVENTION
[0018] A primary objective of the present invention is to provide a
chip carrier, a semiconductor package and a fabricating method
thereof in which, in a molding and a de-molding processes,
electrical static generated on a surface of the semiconductor
package is not retained on a semiconductor chip, conductive
elements or conductive traces in the semiconductor package, without
constructing a metallic protrusion on the chip carrier, a metal
layer on an inside wall of a pilot hole of the chip carrier, or a
protrusion on a runner of a mold.
[0019] In accordance with the above and other objectives, the
present invention proposes a chip carrier, including: a first side;
a second side opposing the first side and removed finally from an
engaged surface of a mold in a de-molding process; and at least one
grounding means formed on the second side corresponding in position
to eject pins of the mold.
[0020] The invention proposes a semiconductor package, comprising:
a chip carrier having a first side and a second side opposing the
first side; a semiconductor chip deposited on the first side of the
chip; carrier a plurality of conductive elements such as metallic
wires for electrically connecting the semiconductor chip to the
chip carrier; an encapsulant formed of a molding compound such as
epoxy resin for encapslating the semiconductor chip and the
conductive elements on the first side of the chip carriers; and a
plurality of solder balls implanted on the second side of the chip
carrier for electrically connecting the semiconductor chip to
external devices, wherein on one of the sides of the chip carrier
finally removed from an engaged surface of a mold in a de-molding
process there is formed at least one grounding means corresponding
in position to object, pins of the mold.
[0021] A fabricating method of a semiconductor package proposed in
the invention comprises the steps of: preparing a chip carrier
having a first side and a second side opposing the first side,
wherein on one of the sides of the chip carrier finally removed
from an engaged surface of a mold in a de-molding process there is
formed at least one grounding means corresponding in position to
oeject pins of the mold; performing a die bonding process for
mounting at least one semiconductor chip on the first side of the
chip carrier, providing a plurality of conductive elements for
electrically connecting the semiconductor chip to the chip carrier;
performing a molding process for forming an encapsulant for
encapsulating the semiconductor chip and the conductive elements on
the first side of the chip carrier; performing a de-molding process
for ejecting the semi-fabricated semiconductor package from the
mold by using the eject pins on the mold; performing a ball
implanting process for implanting a plurality of solder balls at
ball pads on the second side of the chip carrier; and performing a
singulating process for forming individual fabricated semiconductor
packages.
[0022] In this case, in the molding and de-molding processes, the
grounding means formed on the chip carrier allows electrical static
produced on a surface of the semi-fabricated semiconductor package
to be effectively discharged through the mold to outside of the
semiconductor package, instead of being retained on the
semiconductor chip, the conductive elements or the conductive
traces. This further prevents electrical leakage or damage to the
semiconductor chip from occurrence, and also greatly improves the
quality and production efficiency for the semiconductor
package.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] The invention can be more fully understood by reading the
following detailed description of the preferred embodiments, with
reference made to the accompanying drawings, wherein:
[0024] FIG. 1A is a bottom view of a preferred embodiment of the
chip carrier of the invention;
[0025] FIG. 1B is a sectional view of FIG. 1A cutting along the
line 1B-1B;
[0026] FIG. 2 is a sectional view of FIG. 1A cutting along the line
2-2 showing a preferred embodiment of the semiconductor package of
the invention prior to a singulating process;
[0027] FIG. 3 is a schematic diagram showing the use of eject pins
of a mold for ejecting the semiconductor package of the invention
in a demolding process;
[0028] FIGS. 4A-4D (PRIOR ART) are schematic diagrams showing the
steps involved using a conventional mold for performing a molding
and a de-molding process;
[0029] FIG. 5 (PRIOR ART) is a schematic diagram showing the
formation of a metal protusion exposed to outside of a solder mask
layer on a chip carrier for being used as a grounding means;
[0030] FIG. 6 (PRIOR ART) is a schematic diagram showing the
formation of a metal layer on an inside wall of a pilot hole of a
chip earner for being used as a grounding means;
[0031] FIG. 7 (PRIOR ART) is a schematic diagram showing the
formation of a profusion on a namer of a mold for being used as a
grounding means; and
[0032] FIG. 8 (PRIOR ART) is a schematic diagram of a BGA
conventional semiconductor package.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0033] As shown in FIGS. 1A and 1B, a chip carrier 10A proposed in
the invention includes: a first side 101; a second side 102
opposing the first side and removed finally from an engaged surface
of a mold in a de-molding process; and at least one grounding means
G formed on the second side 102 corresponding in position to eject
pins of the mold.
[0034] The chip carrier 10A can be constructed in a same manner as
a conventional chip carrier 10 shown in FIG. 8, comprising a base
layer 11 made of a material such as BT resin and having a first
surface and a second surface opposing the first since. On the first
surfing of the base layer 11 there are formed a die pad 16 for
mounting a semiconductor chip 40 thereon and a plurality of
conductive traces 12 electrical counted to the semicontor chip 40.
On the second surface the base layer 11 there are disposed a
plurality of ball pads 14 for implanting solder balls 80 thereon,
while the ball pads 14 are electrically connected to the
conductivities 12 by a plurality of vias 13 formed through the base
layer 11. Solder mask layers 15 are evenly formed on the first
surface and second surface of the base layer 11, in a manner that
part of the conductive traces 12 electrically connected to the
semiconductor chip 40 on the first surface and the ball pads 14 on
the second surface are end to outside of the solder mask layers 15,
so as to prevent the conductive traces 12 from coming into contact
with one another for elminaming the occurrence of short circuit,
and protect the conductive traces 12 against external detrimental
fators. In addition, cuting lines S are provided on the chip
carrier 10A for a cutting means to cut therehrough so as to form
individual semiconductor packages in a singulating process, as
shown in FIGS. 1A and 2.
[0035] Moreover, as shown in FIGS. 1A and 1B, the grounding means G
is commonly formed by plating a conductive material such as gold or
copper in a manner as to be exposed to the outside of solder mask
layer 15. Further, a grounding vias 13A is formed through the chip
earner 10A for electrically connecting the grounding means G to a
grounding trace 12A finned on the first side 101 of the chip
carrier 10A, while the grounding trace 12A is generally connected
to the die pad 16 on the first side 101 of the chip carrier
10A.
[0036] As shown in FIG. 2, a semiconductor package proposed in the
invention comprises: a chip carrier 10A as the one described above;
a semiconductor chip 40 mounted on a first side 101 of the chip
carrier 10A; a plurality of conductive elements 50 such as metallic
wires for electrically cuting the semiconductor chip 40 to the chip
carrier 10A; an encapsulant 70 formed of a molding compound such as
epoxy resin for encapsulating the semiconductor chip 40 and the
conductive elements 50 on the first side 101 of the cip carrier
10A; and a plurality of solder balls 80 implanted on a second side
102 of the chip crew 10A for electically coning the semiconductor
chip 40 to external devices.
[0037] A fabricatig metod of a semiconductor package proposed in
the invention comprises the steps of: preparng a chip carrier 10A
as the one descmned above; perfoming a die bonding proes for
mounting at least one semiconductor chip 40 on a first side 101 of
the chip earner 10A; providing a plurality of conductive elements
50 for elecrically connecting the semiconductor chip 40 to the chip
carrier 10A; performing a molding process for forming an
encapsulant 70 for encapsulating the semiconductor chip 40 and the
conductive elements 50 on the first side 101 of the chip carrier
10A; performing a de-molding process for ejecting the
semi-fabicated semiconducor package respectively from a top mold
110 and a bottom mold 120 of a mold 100 by using the eject pins 111
and 121 on the mold 100 in a manner illustrated in FIGS. 4C and
4D); performing a ball implanting process for implanting a
plurltity of solder balls 80 at corresponding ball pads 14 on a
second side 10 of the chip carrier 10A; and performing a
singulating process for forming individual fabricated semiconductor
packages.
[0038] Morever, in the de-molding proces, the semi-fabricated
semiconductor package is ejected from an engaged se of the bottom
mold 120 in a manner illustrated in FIG.3 that the eject pins 121
on the bottom mold 120 act on grounding means G formed on the chip
carrier 10A. In this case, during molding and demolding, the
grounding means G of the chip carrier 10A allow electrical static
produced at a great amount on a surfice of the semi-fabricated
semiconduor package to be effectively discharged throgh the mold
100 to outside of the semiconductor package, instad of being
retained on the semiconductor chip 40, the conductive elements 50
or the conduve traces. This further prevents electrical leakage or
damage to the semiconductor chip 40 from occurrence, and also
greatly improves the quality and production efficiency for the
semiconductor package.
[0039] The grounding means G can also be optionally fbrmed on the
first side 101 of the chip carrier 10A coresponding in position to
the eject pins 111 Iofthe top mold 110, so as to further elminate
the electrical static produced on the semiconductor package during
fabrication.
[0040] Further, beides a conventional BGA semiconductor package
shown in FIG. 8, the chip carrier, the semiconductor package and
the fabricating method of the semiconductor package of the
invention can also be applied to other types of semiconductor
package, in an effort to prevent the electrical static from being
retained in the semiconductor package during fabrication.
[0041] Moreover, due to no metallic protrusion necessarily formed
on the chip carrier 10A, the fabricahon accordingly can be
simplified in process, and reduced in time expense and cost.
[0042] Furthermore, as it is not to form a metal layer on an inside
wall of a pilot hole of the chip carrier 10A, the encaplant can be
prevented from being greatly deviated in position and the quality
of the semiconductor package cn be assured.
[0043] In addition, on a runner of the mold 100 there is formed no
profusion, and thus the mold 100 can be repetitively employed for
various types of semiconductor packages, so that the fabrication
cost can be reduced.
[0044] The invention has been described usag exemplary preferred
embodiments. However, it is to be understood that the scope of the
invention is not limited to the disclosed embodiments. On the
contrary, it is intended to covervarious modiications and similar
arrangemnets, for example, grounding means can be alternaively
constructed in other forms such as metallic protrusions, in place
of the foregoing plated grounding means G. The scope of the claims,
therefore, should be accorded the broadest interpretation so as to
encompass all such modifications and similar arrangements.
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