U.S. patent application number 10/267951 was filed with the patent office on 2004-04-15 for wide-range local bias generator for body bias grid.
Invention is credited to De, Vivek K., Somasekhar, Dinesh, Tang, Stephen H., Tschanz, James W..
Application Number | 20040070440 10/267951 |
Document ID | / |
Family ID | 32068465 |
Filed Date | 2004-04-15 |
United States Patent
Application |
20040070440 |
Kind Code |
A1 |
Tang, Stephen H. ; et
al. |
April 15, 2004 |
Wide-range local bias generator for body bias grid
Abstract
According to some embodiments, a wide-range local bias generator
provides a body bias voltage to transistors in an integrated
circuit.
Inventors: |
Tang, Stephen H.;
(Beaverton, OR) ; Somasekhar, Dinesh; (Portland,
OR) ; Tschanz, James W.; (Portland, OR) ; De,
Vivek K.; (Beaverton, OR) |
Correspondence
Address: |
BUCKLEY, MASCHOFF, TALWALKAR LLC
5 ELM STREET
NEW CANAAN
CT
06840
US
|
Family ID: |
32068465 |
Appl. No.: |
10/267951 |
Filed: |
October 9, 2002 |
Current U.S.
Class: |
327/534 |
Current CPC
Class: |
G05F 3/205 20130101;
H03K 2217/0018 20130101 |
Class at
Publication: |
327/534 |
International
Class: |
H03K 003/01 |
Claims
What is claimed is:
1. A circuit, comprising: first and second inputs to receive a
desired body bias signal, and a third input to receive a supply
voltage, the circuit to generate an output signal, said output
signal coupled to a fourth input, to cause said output signal to
reference to variations in said supply voltage.
2. The circuit of claim 1, further comprising: an output buffer,
coupled to receive said an intermediate output signal and to
generate said output signal having a desired gain.
3. The circuit of claim 1, wherein said desired body bias signal is
received from a body bias generation circuit.
4. The circuit of claim 3, wherein said body bias generation
circuit is variably adjustable to provide a range of said desired
body bias signal.
5. The circuit of claim 4, wherein said range includes negative and
positive values.
6. The circuit of claim 1, further comprising a plurality of
transistors coupled to a body bias grid, wherein said output signal
is distributed to said plurality of transistors using said body
bias grid to set a threshold voltage of each of said plurality of
transistors.
7. The circuit of claim 6, wherein said plurality of transistors
are at least one of a plurality of n-channel transistors and a
plurality of p-channel transistors.
8. A circuit, comprising: a differential difference amplifier (DDA)
generating an output signal, said DDA having inputs to receive a
body bias signal, a local supply voltage, and a desired body bias
signal referenced to said local supply voltage; and an output
buffer, to receive said output signal and to generate said desired
body bias signal.
9. The circuit of claim 8, further comprising a body bias grid
coupled to said output buffer and to a plurality of
transistors.
10. A circuit, comprising: a body bias circuit including first and
second inputs coupled to receive a desired body bias voltage and a
third input coupled to receive a supply voltage, said body bias
circuit to output a first output signal; and an output buffer, to
receive said first output signal and to output a second output
signal having a higher gain than said first output signal, said
second output signal input to a fourth input of said body bias
circuit to reference said second output signal to said supply
voltage, said second output signal further provided to a body bias
grid.
11. The circuit of claim 10, wherein said body bias circuit
comprises a differential difference amplifier.
12. The circuit of claim 10, wherein said body bias circuit has a
first gain (k) and said output buffer has a second gain (k1)
selected to provide said second output signal having an overall
gain to drive a plurality of transistors coupled to said body bias
grid.
13. The circuit of claim 10, wherein said body bias grid is coupled
to a plurality of transistors.
14. An integrated circuit, comprising: a bias generation circuit
selectively operable to generate a desired body bias voltage; and a
first and a second circuit region, each region comprising a local
supply voltage, a body bias circuit having a first and second input
to receive said desired body bias voltage, a third input coupled to
a local supply voltage, and a fourth input coupled to receive an
output signal from said body bias circuit, said output signal
referenced to said local supply voltage, and a body bias grid
coupled to provide said output signal to a plurality of
transistors.
15. The integrated circuit of claim 14, wherein each region further
comprising: an output buffer, coupled to increase a gain of said
output signal.
16. The integrated circuit of claim 14, wherein said body bias
circuit comprises a differential difference amplifier (DDA).
17. A method of operating an integrated circuit, comprising:
selecting a desired body bias voltage; supplying said desired body
bias voltage to a plurality of bias generation circuits distributed
on said integrated circuit; generating, in each of said plurality
of bias generation circuits, a local bias voltage referenced to a
local supply voltage associated with each of said plurality of bias
generation circuits; and distributing said local bias voltage to a
plurality of transistors associated with each of said plurality of
bias generation circuits.
18. The method of claim 17, wherein said desired body bias voltage
is at least one of a reverse bias, a zero bias, and a forward
bias.
19. A system comprising: a dynamic random access memory to store
data from a device, said device comprising: a local supply voltage
source, to generate a local supply voltage; a bias generation
circuit; and a body bias circuit, to receive a supply voltage and a
bias voltage from said bias generation circuit, said body bias
circuit to generate a bias voltage referenced to said local supply
voltage and to provide said bias voltage to at least a first
transistor.
20. A system according to claim 19, said device further comprising
an output buffer coupled to said body bias circuit to receive an
intermediate bias voltage and to generate said bias voltage having
a desired gain.
Description
BACKGROUND
[0001] A circuit may be used to apply a body bias to one or more
transistors in an integrated circuit. Through application of a body
bias, performance of a transistor may be improved and/or power
consumption may be reduced. In particular, a body bias circuit may
be used to set the threshold voltage (V.sub.th) of one or more
transistors in an integrated circuit by using the body effect of
the transistors.
[0002] Body bias circuits generally provide either a fixed forward
bias or a zero bias of transistors in integrated circuits.
Generally, body bias circuits provide body bias voltages to
relatively small areas of integrated circuits. Many integrated
circuits have local supply voltage variations. Body bias circuits
generally are unable to respond to local supply voltage variations
while providing a wide range of body bias voltages, including
forward, reverse and zero body biases.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] FIG. 1 is a block diagram of a circuit according to some
embodiments.
[0004] FIG. 2 is a block diagram of a differential difference
amplifier which may be utilized in the circuit of FIG. 1 in some
embodiments.
[0005] FIG. 3 is a block diagram of a further circuit according to
some embodiments.
[0006] FIG. 4 is a block diagram of an integrated circuit utilizing
features of some embodiments.
[0007] FIG. 5 illustrates a relationship between a desired bias
voltage for various supply voltages in the circuit of FIG. 1.
[0008] FIG. 6 is a block diagram of a system according to some
embodiments.
DETAILED DESCRIPTION
[0009] Some embodiments are associated with circuits that generate
a body bias voltage for application to one or more transistors.
Details of features of embodiments will be described by first
referring to FIG. 1 where a body bias circuit 100 is depicted. Body
bias circuit 100 includes a differential difference amplifier (DDA)
102 configured to receive a bias voltage (V.sub.bs), a local supply
voltage (V.sub.cc) and a feedback signal 106 from the output
(V.sub.out') of a buffer 104. Buffer 104 receives an output signal
(V.sub.out) from DDA 102. The signal (V.sub.out') output from
buffer 104 is a body bias voltage that is distributed to one or
more transistors 108. For example, in some embodiments V.sub.out'
is distributed to a plurality of transistors of an integrated
circuit. For clarity and ease of exposition, the transistor 108 of
the circuit of FIG. 1 will be referred to in the singular; however,
embodiments distribute Vout' to a plurality of transistors as will
be described further below in conjunction with FIGS. 3 and 4.
[0010] Bias voltage (V.sub.bs) is a differential signal (e.g.,
representing a difference between a body and a source voltage). The
signal may be fixed or it may be variable. In some embodiments,
body bias circuit 100 may be configured to supply a negative, or
reverse body bias voltage to transistor 108. In this manner,
V.sub.th of transistor 108 may be raised to reduce leakage power of
the transistor. In some embodiments, V.sub.th of a number of
transistors in an integrated circuit are adjusted to reduce the
overall leakage power of the circuit.
[0011] In some embodiments, body bias circuit 100 may be configured
to supply a positive, or forward body bias. In this manner,
V.sub.th of transistor 108 may be lowered to increase operating
speed. In some embodiments, V.sub.th of a number of transistors in
an integrated circuit are adjusted to increase an overall operating
speed of the integrated circuit. In some embodiments, a number of
body bias circuits 100 are provided throughout an integrated
circuit and the local supply voltage (V.sub.cc) applied to each
body bias circuit 100 is the supply voltage available at different
portions of the integrated circuit.
[0012] DDA 102 is a device that is configured to track local
variations in the supply voltage. Referring now to FIG. 2, a
representation of DDA 102 is shown which will be used to describe a
functional relationship between the output signal (Vout) and the
four input signals. In general, embodiments utilize a DDA or
similar circuitry that provides the following functional
relationship between the output signal (V.sub.out), a gain (k) of
the DDA, and the four input signals:
V.sub.out=k*[(V.sub.pp-V.sub.pn)-(V.sub.np-V.sub.nn)]
[0013] Assuming high gain, with feedback, DDA 104 generally
operates to ensure that V.sub.pp-V.sub.pn=V.sub.np-V.sub.nn, or
V.sub.pp-V.sub.np=V.sub.pn-V.sub.nn. Therefore, if the desired body
bias V.sub.bs is applied across V.sub.pp and V.sub.np and the local
supply rail is monitored at V.sub.pn, with feedback, V.sub.nn will
be forced to be the desired body bias, referenced to the local
supply voltage. Those skilled in the art will recognize that any
suitable circuit configured to provide the above-identified
functional relationship between the output and the inputs may be
used. Applicants have found that differential difference amplifiers
configured as depicted in the attached figures provide desirable
results. Further details of one suitable differential difference
amplifier are described in E. Sackinger and W. Guggenbuhl, "A
Versatile Building Block: The CMOS Differential Difference
Amplifier," IEEE Journal of Solid-State Circuits, Vol. 22, No. 2,
April 1987, pp. 287-294. Other devices configured to provide the
above-described functional relationship between the inputs and
V.sub.out may also be used.
[0014] Referring again to FIG. 1, in the embodiment depicted, the
body bias voltage signal V.sub.out' is configured to apply a body
bias voltage to one or more p-channel transistors by applying the
local supply voltage (V.sub.cc) to a negative input line of DDA 102
(referenced as input line V.sub.pn of FIG. 2). Those skilled in the
art will recognize, upon reading this disclosure, that body bias
circuit 100 may be configured to deliver a body bias voltage to
n-channel transistors as well (e.g., by applying a local ground
signal, or V.sub.ss, to a negative input line of DDA 102, or input
line V.sub.pn of FIG. 2).
[0015] DDA 102, in some embodiments, provides relatively low
current drive. Buffer 104 is selected to provide an output gain
sufficient to drive one or more transistors 108. In some
embodiments, for example, where few transistors are coupled to an
output of body bias circuit 100, there may be no need for buffer
104 (i.e., DDA 102 may provide sufficient output drive to deliver a
body bias voltage to each of the transistors). In some embodiments,
e.g., where a number of transistors will receive the body bias
voltage provided by body bias circuit 100, buffer 104 is utilized
to provide sufficient gain to supply the body bias voltage to each
of the transistors. In addition, embodiments utilize buffer 104 to
provide a desired total gain which reduces fluctuations or errors
in the generated body bias voltage.
[0016] As a particular example, where body bias circuit 100 is
utilized in a large-scale integrated circuit having a local
V.sub.cc of approximately 1.1 V, and where the desired body bias
voltage is approximately 0.3 V, a total gain of body bias circuit
100 is selected to be approximately 100 (e.g., where a gain of DDA
102 is approximately 10 and a gain of buffer 104 is selected to
also be approximately 10). In such a configuration, the body bias
voltage produced at the output (V.sub.out') of buffer 104 is
provided with sufficient gain to drive a number of transistors.
Further, a total gain of approximately 100 provides a relatively
stable output with low error (e.g., with variations in the bias
voltage of no more than approximately 10 mV). Use of an output
buffer having a higher gain will provide greater current drive and
lower variations in the bias voltage.
[0017] An example graphical depiction of simulation results for a
particular device is shown in FIG. 5. FIG. 5 depicts simulation
results for a particular device having particular design
characteristics which are provided for illustrative purposes only.
As shown, V.sub.out' (labled on FIG. 5 as "LBG Output [V]") is
compared to a desired V.sub.bs for various local supply voltages.
As depicted in FIG. 5, the top curve is for a local supply voltage
(V.sub.cc) of 1.3V, the middle curve is for a V.sub.cc of 1.2V, and
the lower curve is for a V.sub.cc of 1.1 V. As shown, V.sub.out' is
generally equal to the desired V.sub.bs referenced to the local
supply voltage.
[0018] Embodiments allow the application of a desired body bias to
a number of transistors in a large-scale integrated circuit. In
many large-scale integrated circuits, transistor sources are
typically tied to local supply rails. These local supply rails can
suffer from noise due to fluctuating current demands. This can
result in local variations in supply voltage. Embodiments allow the
application of a desired body bias, which tracks local variations
in supply voltage. Reference is now made to FIG. 3, where an
embodiment is depicted which applies a desired body bias voltage to
a body bias grid 300. Body bias grid 300 is used to deliver a
desired body bias voltage to a number of transistors coupled to the
grid. In this manner, a desired body bias which tracks local
variations in supply voltage can be applied to large numbers of
transistors in an integrated circuit.
[0019] In the depicted embodiment, a bias generation circuit 200 is
used to set a desired body bias voltage (V.sub.bs). This body bias
voltage is delivered to one or more body bias circuits (100) (which
also may be referred to as "local bias generators" or "LBGs")
distributed throughout the integrated circuit. Each body bias
circuit 100 is tied to a local supply rail (identified in FIG. 3 as
the "local V.sub.cc") to track local variations in supply voltage.
In the embodiment depicted, body bias circuit 100 is configured to
provide a body bias voltage to a number of p-channel transistors
(e.g., because the local V.sub.cc is tied to a negative input of
DDA 102). A similar body bias circuit 100 may be configured to
provide a body bias voltage to a number of n-channel transistors.
Body bias circuit 100 is configured to receive a desired body bias
voltage (V.sub.bs) from bias generation circuit 200 and also
receives a feedback signal 106 from an output of a buffer 104. A
body bias signal, referenced to the local V.sub.cc, is output from
buffer 104 and supplied to a body bias grid 300. Transistors to be
biased are coupled to receive the body bias signal distributed by
body bias grid 300.
[0020] Bias generation circuit 200 may be configured to variably
select a desired body bias voltage (V.sub.bs). Embodiments allow
the selective application of different body biases, including
reverse or forward body biases of different magnitudes. Further,
bias generation circuit 200 may be configured to select a zero body
bias voltage as well. In this manner, operation characteristics of
an integrated circuit may be tuned as desired. Bias generation
circuit 200 may be a circuit such as, for example, a scaled bandgap
circuit or other circuit configured to provide a desired V.sub.bs
to one or more body bias circuits 100.
[0021] In this manner, embodiments allow the application of a
desired body bias to change the threshold voltage (V.sub.th) of a
large number of transistors in a large-scale integrated circuit.
Further, embodiments allow the consistent application of a desired
body bias despite the existence of noise or other fluctuations in
local supply voltage (e.g., due to fluctuating current demands
across portions of a large-scale integrated circuit). Embodiments
track local variations in supply voltage and maintain a desired
body bias voltage using a network of local bias generators (LBGs)
distributed throughout a large-scale integrated circuit. Each LBG
may be coupled to a body bias grid to distribute a desired body
bias voltage to a number of transistors coupled to the grid.
[0022] Further details of embodiments will now be described by
reference to FIG. 4, where an integrated circuit 400 is depicted.
Integrated circuit 400 may include digital and/or analog components
including a number of transistors whose performance may be adjusted
by application of a body bias voltage to the transistors.
Integrated circuit 400 includes a number of regions 120a-n, each
having a body bias circuit 100a-n and a body bias grid 300a-n. Each
body bias grid 300 is coupled to a number of transistors (not
shown) to receive a body bias voltage. The number of body bias
circuits 100 utilized in integrated circuit 400 may be selected
based on several considerations. For example, embodiments may
provide a desired number of body bias circuts 100 based on the
total capacitance of transistors in a particular area of integrated
circuit 400. The number of body bias circuts 100 may be selected to
balance considerations such as noise tolerance, device size, and
circuit power requirements.
[0023] In general, the circuits of each region 120 are configured
to reference a desired body bias voltage to a local supply voltage
to maintain a desired body to source voltage for transistors in
each region. Each body bias circuit 100 receives an input body bias
signal (V.sub.bs) from a bias generation circuit 200. Each body
bias circuit 100 includes a local supply input tied to a local
supply rail associated with the region 120 in which body bias
circuit 100 is located. In this manner, a desired body bias
voltage, referenced to the local supply voltage, can be delivered
to a number of transistors in each region using body bias grid 300.
Use of bias generation circuit 200 in conjunction with body bias
circuits 100 allows application of an entire range of body biases
which are tracked to local supply rails. In some embodiments, a
single bias generation circuit 200 may be utilized to apply a
variety of body bias voltages referenced to local supply voltages,
thereby allowing the use of adaptive body bias schemes to reduce
power consumed by integrated circuit 400 and/or to improve
performance of integrated circuit 400. Further, peformance
variation of integrated circuits may also be reduced. Reduction of
performance variation may provide increased die yield and other
desirable manufacturing improvements.
[0024] FIG. 6 is a block diagram of a system according to some
embodiments. Computer system 200 includes microprocessor 210, which
includes an instance of body bias circuit 100 of FIG. 1. Computer
system 200 also includes memory controller/chipset 220 coupled to
one or more I/O pins of microprocessor 200 and to memory 300. As
shown, memory controller 220 and memory 200 each include at least
one instance of body bias circuit 100. Each of the illustrated
instances of body bias circuit 100 is adapted to apply a body bias
to one or more transistors (not shown). Embodiments may provide a
computer system 200 in which body bias circuit 100 is provided in
one or more components of the computer system.
[0025] Memory 300 may include any memory adapted to store data.
Examples of such a memory include, but are not limited to, a hard
drive, Dynamic Random Access Memory, Static Random Access Memory,
Read-Only Memory, and Non-Volatile Random Access Memory. Moreover,
microprocessor 210 may comprise any chip or processor including but
not limited to a graphics processor, a digital signal processor,
and a sound processor.
[0026] The several embodiments described herein are solely for the
purpose of illustration. Persons skilled in the art will recognize
from this description other embodiments may be practiced with
modifications and alterations limited only by the claims.
* * * * *