U.S. patent application number 10/690350 was filed with the patent office on 2004-04-01 for thin film semiconductor package and method of fabrication.
This patent application is currently assigned to MEGIC CORPORATION. Invention is credited to Huang, Ching-Cheng, Lee, Jin-Yuan, Lin, Mou-Shiung.
Application Number | 20040063249 10/690350 |
Document ID | / |
Family ID | 29731542 |
Filed Date | 2004-04-01 |
United States Patent
Application |
20040063249 |
Kind Code |
A1 |
Lin, Mou-Shiung ; et
al. |
April 1, 2004 |
Thin film semiconductor package and method of fabrication
Abstract
A thin film semiconductor die circuit package is provided
utilizing low dielectric constant (k) polymer material for the
insulating layers of the metal interconnect structure. Five
embodiments include utilizing glass, glass-metal composite, and
glass/glass sandwiched substrates. The substrates form the base for
mounting semiconductor dies and fabricating the thin film
interconnect structure.
Inventors: |
Lin, Mou-Shiung; (Hsinchu,
TW) ; Lee, Jin-Yuan; (Hsin-Chu City, TW) ;
Huang, Ching-Cheng; (Hsin-Chu City, TW) |
Correspondence
Address: |
George O. Saile
28 Davis Avenue
Poughkeepsie
NY
12603
US
|
Assignee: |
MEGIC CORPORATION
|
Family ID: |
29731542 |
Appl. No.: |
10/690350 |
Filed: |
October 21, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10690350 |
Oct 21, 2003 |
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10054001 |
Jan 19, 2002 |
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6673698 |
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Current U.S.
Class: |
438/110 ;
257/E23.178; 438/113; 438/125; 438/129; 438/599; 438/613 |
Current CPC
Class: |
H01L 2924/00 20130101;
H01L 2224/0401 20130101; H01L 2224/73267 20130101; H01L 2924/09701
20130101; H01L 2924/15788 20130101; H01L 2224/32225 20130101; H01L
2224/97 20130101; H01L 2924/14 20130101; H01L 24/97 20130101; H01L
2924/1461 20130101; H01L 2924/19041 20130101; H01L 2224/97
20130101; H01L 2224/97 20130101; H01L 2924/01033 20130101; H01L
2924/01079 20130101; H01L 2924/01005 20130101; H01L 2924/15311
20130101; H01L 2924/15788 20130101; H01L 2924/01029 20130101; H01L
2224/211 20130101; H01L 2224/97 20130101; H01L 2924/15153 20130101;
H01L 23/3114 20130101; H01L 21/6835 20130101; H01L 2924/01019
20130101; H01L 23/5389 20130101; H01L 2924/01013 20130101; H01L
2924/014 20130101; H01L 2224/12105 20130101; H01L 2924/01006
20130101; H01L 2224/20 20130101; H01L 2221/68377 20130101; H01L
2224/04105 20130101; H01L 2924/1461 20130101; H01L 2924/12044
20130101; H01L 2924/3011 20130101; H01L 24/19 20130101; H01L
2924/19043 20130101; H01L 2924/19042 20130101; H01L 2224/82
20130101; H01L 2924/00 20130101; H01L 2224/83 20130101; H01L
2924/15311 20130101 |
Class at
Publication: |
438/110 ;
438/125; 438/113; 438/129; 438/613; 438/599 |
International
Class: |
H01L 021/82 |
Claims
What is claimed is:
1. A thin film semiconductor die package structure comprising: one
or more semiconductor dies backside bonded on planar glass
substrate; one or more layers of interconnect metal connected to
and above said semiconductor dies; and one or more insulating
layers of polymer with contact holes, formed around said
interconnect metal.
2. The thin film semiconductor package structure of claim 1 wherein
the substrate is diced into single chip semiconductor packages.
3. The thin film semiconductor package structure of claim 1 wherein
the substrate is diced into multi-chip semiconductor packages.
4. The thin film semiconductor package of claim 3 wherein said
semiconductor dies mounted within said multi-chip semiconductor
packages comprise the same type of integrated circuit chips.
5. The thin semiconductor package of claim 3 wherein said
semiconductor dies mounted within said multi-chip semiconductor
packages comprise different types of integrated circuit chips.
6. The thin film semiconductor package structure of claim 1 wherein
solder bumps are connected to said interconnect metal and
incorporated as interconnects to the next level of assembly.
7. The thin film semiconductor package structure of claim 1
incorporating connector pins connected to said interconnect metal
and for assembly to the next level of packaging.
8. The thin film semiconductor package structure of claim 1 wherein
said one or more layers of interconnect metal and said one or more
insulating layers comprise an interconnect system, and wherein one
of more devices are incorporated within said interconnect
system.
9. The thin film semiconductor package structure of claim 8 where n
said one or more devices are selected from the group comprising
inductors, resistors, capacitors, waveguides, filters and MEMS
devices.
10. A thin film semiconductor die packaging structure comprising:
one or more semiconductor dies backside bonded on a planar glass
substrate, wherein the glass substrate has cavities on the top
surface for containing and bonding the semiconductor dies; one or
more layers of interconnect metal connected to and above said
semiconductor dies; and one or more insulating layers of polymer
with contact holes, formed around said interconnect metal.
11. The thin film semiconductor package structure of claim 1
further comprising epoxy on said glass substrate and adjacent to
said one or more semiconductor dies.
12. The thin film semiconductor package structure of claim 10
wherein the substrate is diced into single semiconductor die
packages.
13. The thin film semiconductor package structure of claim 10
wherein the substrate is diced into multi-chip semiconductor
packages.
14. The thin film semiconductor package of claim 10 wherein said
semiconductor dies mounted within said multi-chip semiconductor
packages comprise the same type of integrated circuit chips.
15. The thin semiconductor package of claim 10 wherein said
semiconductor dies mounted within said multi-chip semiconductor
packages comprise different types of integrated circuit chips.
16. The thin film semiconductor package structure of claim 10
wherein one or more solder bumps are incorporated for interconnect
to the next level of assembly.
17. The thin film semiconductor package structure of claim 10
wherein one or more connector pins are incorporated for
interconnect to the next level of assembly.
18. The thin film semiconductor package structure of claim 10
wherein said one or more layers of interconnect metal and said one
or more insulating layers comprise an interconnect system, and
wherein one or more devices are incorporated within said
interconnect system.
19. The thin film semiconductor package structure of claim 17
wherein said one or more devices are selected from the group
comprising inductors, resistors, capacitors, waveguides, filters
and MEMS devices.
20. A thin film semiconductor die packaging structure comprising:
one or more semiconductor dies backside bonded on a metal-glass
composite substrate, wherein the glass has cavities for containing
and bonding the semiconductor dies; one or more layers of
interconnect metal connected to and above said semiconductor dies;
and one or more insulating layers of polymer with contact holes,
formed around said interconnect metal.
21. The thin film semiconductor package structure of claim 20
wherein the substrate is diced into single semiconductor die
packages.
22. The thin film semiconductor package structure of claim 20
wherein the substrate is diced into multi-chip semiconductor die
packages.
23. The thin film semiconductor package of claim 22 wherein said
semiconductor dies mounted within said multi-chip semiconductor
packages comprise the same type of integrated circuit chips.
24. The thin semiconductor package of claim 22 wherein said
semiconductor dies mounted within said multi-chip semiconductor
packages comprise different types of integrated circuit chips.
25. The thin film semiconductor package structure of claim 20
wherein one or more solder bumps are incorporated for
interconnection to the next level of assembly.
26. The thin film semiconductor package structure of claim 20
wherein one or more connector pins are incorporated for
interconnecting to the next level of assembly.
27. The thin film semiconductor package structure of claim 20
wherein said one or more layers of interconnect metal and said one
or more insulating layers comprise an interconnect system, and
wherein one or more devices are incorporated within said
interconnect system.
28. The thin film semiconductor package structure of claim 20
wherein said one or more devices are selected from the group
comprising inductors, resistors, capacitors, waveguides, filters
and MEMS devices.
29. A thin film semiconductor die packaging structure comprising:
one or more semiconductor dies backside bonded on a glass
substrate; one or more layers of interconnect metal connected to
and above said semiconductor dies; a glass layer between said
semiconductor dies and the first of said one or more layers of
interconnect metal; and one or more insulating layers of polymer
with contact holes, formed around said interconnect metal.
30. The thin film semiconductor package structure of claim 29
wherein the substrate is diced into single semiconductor die
packages.
31. The thin film semiconductor package structure of claim 29
wherein the substrate is diced into multi-chip semiconductor die
packages.
32. The thin film semiconductor package of claim 31 wherein said
semiconductor dies mounted within said multi-chip semiconductor
packages comprise the same type of integrated circuit chips.
33. The thin semiconductor package of claim 31 wherein said
semiconductor dies mounted within said multi-chip semiconductor
packages comprise different types of integrated circuit chips
34. The thin film semiconductor package structure of claim 29
wherein one or more solder bumps are incorporated for
interconnection to the next level of assembly.
35. The thin film semiconductor package structure of claim 29
wherein one or more corrector pins are incorporated for
interconnecting to the next level of assembly.
36. The thin film semiconductor package structure of claim 29
wherein said one or more layers of interconnect metal and said one
or more insulating layers comprise an interconnect system, and
wherein one or more devices are incorporated within said
interconnect system.
37. The thin film semiconductor package structure of claim 29
wherein said one or more devices are selected from the group
comprising inductors, resistors, capacitors, waveguides, filters
and MEMS devices.
38. The thin film semiconductor package structure of claim 29
further comprising epoxy formed on said glass substrate and between
said semiconductor dies.
39. A method for fabricating a thin film semiconductor die package,
comprising the steps of: providing a planar glass substrate;
attaching semiconductor dies to said planar glass substrate;
sequentially depositing one or more polymer layers and one or more
metal interconnect layers over said substrate; forming a layer of
solder over and connected to said one or more metal interconnect
layers; and reflowing the solder to form solder bumps.
40. A method of fabricating a thin film semiconductor die package
structure comprising the steps of: providing a glass substrate with
cavities having semiconductor dies mounted therein; sequentially
forming polymer insulating layers and metal interconnect layers;
forming a layer of solder; and reflowing the solder to form solder
bumps.
41. A method of fabricating the thin film semiconductor die package
structure comprising: providing a metal substrate; forming a glass
layer with cavities for mounting semiconductor dies on said metal
substrate; sequentially forming polymer insulating layers and metal
interconnect layers; forming a layer of solder; and reflowing the
solder to form solder bumps
42. A method of fabricating a thin film semiconductor die package
structure comprising: providing a glass substrate with
semiconductor dies mounted on the active surface; filling polymer
or epoxy between and over the backside of said semiconductor dies,
to obtain a planarized surface; grinding the planarized surface,
and said backside of said semiconductor dies, to a desired
thickness of said semiconductor dies; mounting a second glass
substrate on the backside of the semiconductor dies; grinding the
first glass substrate to a desired glass thickness; etching holes
in said first glass substrate to expose said semiconductor dies;
sequentially forming polymer insulating layers and metal
interconnect layers over said first glass substrate; depositing a
layer of solder; and reflowing the solder to form solder bumps.
43. The method of claim 42 wherein said desired thickness of said
semiconductor dies is between about 2 and 500 um.
44. The method of claim 42 wherein said desired glass thickness is
between about 2 and 150 um.
45. The method of claim 42 further comprising dicing said thin film
semiconductor die package structure into single chip semiconductor
packages.
46. The method of claim 42 further comprising dicing said thin film
semiconductor die package structure into multi-chip semiconductor
packages.
47 The method of claim 46 wherein said semiconductor dies mounted
within said multi-chip semiconductor packages comprise the same
type of integrated circuit chips.
48. The method of claim 46 wherein said semiconductor dies mounted
within said multi-chip semiconductor packages comprise different
types of integrated circuit chips
49. The method of claim 42 wherein solder bumps are connected to
said interconnect metal and incorporated as interconnects to the
next level of assembly.
50. The method of claim 42 wherein connector pins are connected to
said interconnect metal and for assembly to the next level of
packaging.
51. The method of claim 42 wherein said one or more layers of
interconnect metal and said one or more insulating layers comprise
an interconnect system, and further comprising incorporating one or
more devices within said interconnect system.
52. The method of claim 51 wherein said one or more devices are
selected from the group comprising inductors, resistors,
capacitors, waveguides, filters and MEMS devices.
53. A method of fabricating a thin film semiconductor die package
structure comprising: providing a glass substrate with
semiconductor dies mounted on the active surface; filling polymer
or epoxy between and over the backside of said semiconductor dies,
to obtain a planarized surface; grinding the planarized surface,
and said backside of said semiconductor dies, to a desired
thickness of said semiconductor dies; mounting a second glass
substrate on the backside of the semiconductor dies; removing said
first glass substrate; sequentially forming polymer insulating
layers and metal interconnect layers over said semiconductor dies;
depositing a layer of solder; and reflowing the solder to form
solder bumps.
54. The thin film semiconductor die package structure of claim 1
wherein said one or more layers of interconnect metal are used as
interconnections between one or more points of electrical contact
on each of said semiconductor dies.
55. The thin film semiconductor die package structure of claim 10
wherein said one or more layers of interconnect metal are used as
interconnections between one or more points of electrical contact
on each of said semiconductor dies.
56. The thin film semiconductor die package structure of claim 20
wherein said one or more layers of interconnect metal are used as
interconnections between one or more points of electrical contact
on each of said semiconductor dies.
57. The method of claim 42 further comprising using said one or
more layers of interconnect metal for interconnections between one
or more points of electrical contact on each of said semiconductor
dies.
58. The method of claim 53 further comprising using said one or
more layers of interconnect metal for interconnections between one
or more points of electrical contact on each of said semiconductor
dies.
Description
BACKGROUND OF INVENTION
[0001] (1) Technical Field
[0002] This invention relates in general to the interconnection and
packaging of semiconductor dies and discrete components.
[0003] (2) Description of Prior Art The following publications
relate to the use of thin films in the interconnection and
packaging of semiconductor dies.
[0004] Microelectronic Packaging Handbook Chapter 9. R. R. Tummala,
E. J. Rymaszewski. Van Nostrand Reinhold 1989.
[0005] Novel Microelectronic Packaging Method For Reduced
Thermomechanical Stresses on Low Dielectric Constant Materials R.
M. Emery, S. Towle, H. Braunisch, C. Hu, G. Raiser, G. J.
Vandentop. Intel Corp. Chandler, Ariz.
[0006] The requirements for packaging of semiconductor circuit
devices are that the package provides physical protection, thermal
control, powering capability, and desirable electrical properties
of the interconnections. Semiconductor packages also provide the
physical translation of interconnecting wiring structures from the
fine wiring and wire spacing, and small area, of the semiconductor
chip to the bigger interconnection spacing and larger area of the
next level of assembly. This capability is usually referred to as
"fan-out". In addition the packages need to provide the ability to
integrate passive components, such as capacitors, inductors,
resistors, waveguides, filters, MEMS (MicroElectroMechanical)
devices, and the like, into the wiring structure.
[0007] These demands have been and are currently met by numerous
package designs. In general these designs tend to degrade the
signals that communicate between devices. Usually this degradation
is due to the high dielectric constant materials and high
resistance metal used as insulators in the interconnection design.
The materials used as insulators; silicon oxides, glass, glass
ceramics, or ceramics are chosen for their mechanical properties
and the method of fabrication. An important mechanical property is
the material's thermal coefficient of expansion, or TCE. The TCE in
many package designs needs to match that of the silicon
semiconductor die in order to have low mechanical stresses in the
package structure.
[0008] Materials with low TCE also have high dielectric constants
(k). The high dielectric constants result in unwanted electrical
properties of the interconnections; i.e., high impedances. Examples
of such designs are semiconductor packages that utilize ceramic
substrates to mount and interconnect the semiconductor
circuits.
[0009] In order to take advantage of the high switching speeds of
today's digital circuits the interconnection technology both on and
off the semiconductor chips or dies requires novel approaches
utilizing low dielectric constant (k) materials such as polyimide
or BCB (benzocyclobutene) to provide the necessary electrical
parameters of the interconnects that do not degrade circuit
performance.
[0010] The use of low dielectric materials used as insulating
layers for interconnects also requires novel mechanical design
approaches to minimize the deleterious effects of TCE
mismatches.
SUMMARY OF THE INVENTION
[0011] The objective of the present invention is to provide a
semiconductor interconnecting package design and method of
fabrication utilizing polymer thin film techniques.
[0012] It is a further objective of the invention that the
semiconductor package provide the interconnect density required by
the semiconductor design.
[0013] It is also the objective of the present invention to provide
a semiconductor package that allows for input and output
interconnections on a pitch compatible both with the semiconductor
and the next level of package.
[0014] The capability to place discrete components close to the
semiconductor circuit's input and output connections is an
additional objective of the present invention.
[0015] In addition an objective of the present invention is to
utilize current fabrication techniques and existing fabrication
infrastructure.
[0016] The above objectives are achieved by the present invention
by utilizing a glass or glass-metal composite substrate as the
basic structure of the package. Semiconductor dies are bonded to
the substrates and a thin film structure is fabricated utilizing
metal and polymer films to interconnect the semiconductor dies. The
glass or glass-metal composite substrate provides the necessary
mechanical protection and support to the semiconductor dies. It
also provides the planarity necessary for the fabrication of the
interconnect polymer layers that interconnect the
semiconductors.
DESCRIPTION OF THE DRAWINGS
[0017] FIGS. 1a-1j show a first embodiment of the invention and the
major fabrication steps.
[0018] FIGS. 2a-2j show a second embodiment of the invention and
the major fabrication steps.
[0019] FIGS. 3a-3j show a third embodiment of the invention and the
major fabrication steps.
[0020] FIGS. 4a-4j show a fourth embodiment of the invention and
the major fabrication steps.
[0021] FIGS. 5a-5j show a fifth embodiment of the invention and the
major fabrication steps.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0022] Semiconductor packages provide mechanical protection to the
semiconductor dies as well as providing the ability to interconnect
the circuits and the circuits to the next level of package. The
semiconductor packages also provide the necessary interconnection
paths between semiconductor dies when used in multi-chip
designs.
[0023] One approach to providing interconnection capabilities and
connectivity to the next level package, is described in U.S. patent
application Ser. No. 09/251,183, filed on Feb. 17, 1999, and herein
incorporated by reference. After typical semiconductor processing
is completed, including a top passivation layer and exposed metal
pads, this application describes a "post passivation process" using
thick layers of organic dielectric films, and thick metal layers
for signal paths and power/ground busses. Post passivation
technology offers low impedance interconnection, passive components
and metal bumps (usually solder) based on a wafer level process.
However, the wafer level process limits the capability of fan out
of pad location to a larger pitch, and limits the capability to
integrate more passive components requiring a large area. The
invention relies on a separate substrate for the pad fan out and
accomodation of more and bigger passive components.
[0024] The interconnect technology used needs the ability to
provide the necessary fine pitch as required by the semiconductor
circuits. Also, the interconnect technology has to provide low
impedance interconnects utilizing low dielectric constant (k)
insulating layers. The present invention discloses five different
embodiments for the thin film semiconductor package structure.
[0025] The first embodiment of the present invention as shown in
FIGS. 1a-1j utilizes a glass substrate 10. Semiconductor dies 12
are attached by conventional means; i.e., die bonding to the glass
substrates face up, at the desired locations. A polymer 14 is
optionally used to fill the gaps between the dies and provide a
planar surface. This material may also be epoxy, deposited by
spin-on, dispense, or screen printing. The first layer of
dielectric 16, a polymer such as polyimide, BCB, elastomer and the
like, is deposited by spin coating to a thickness of between about
5 and 100 um. If the polymer or epoxy 14 is not used to fill the
gaps between dies, the dielectric 16 is used to fill the gaps.
Contact holes to the semiconductor dies are exposed by lithographic
and etching techniques to expose the metal contacts on the
semiconductor dies. The polymer 16 can be photosensitive
material.
[0026] The first metal layer 18 is deposited by sputtering or
electroplating and is patterned by photographic techniques. This
layer contains the interconnects or fan-out lines and may contain
passive components such as capacitors, inductors, resistors,
waveguides, filters, MEMS devices, and the like, that are required
by the electrical design. The metal used is preferably copper but
may be gold, aluminum or other conducting elements, and is
deposited to a thickness of between about 1 and 150 um.
[0027] The second layer of dielectric polymer 20 is formed by
spin-on coating, screen printing or laminating, to a thickness of
between about 1 and 150 um, and patterned by photolithographic
techniques. Chemical etching is used to open contact holes 22 to
the first layer of metal 18. The polymer 20 can also be
photosensitive material
[0028] A second layer of metal 24 is then deposited, to a similar
thickness as metal layer 18, by sputtering or electroplating to
provide the necessary interconnects or fan-out to the terminals of
the package or a third layer of metal if required.
[0029] Multiple alternating layers of dielectric and metal (not
shown) may be deposited and patterned until the final layer of
dielectric 26 is then deposited, on the last layer of metal 24, and
holes opened to the contact points of metal layer 24.
[0030] A layer of solder is deposited by electroplating, screen
printing or ball mounting and contacts are made through the etched
holes in the insulating layer to the final metal layer. The solder
is then reflowed to form the solder bumps 28. Alternately, gold
bumps, or pins may be used, as is known in the art.
[0031] At this stage the panel is segmented. If the product is a
single chip package, it is segmented into individual single chip
modules 30, as shown in FIGS. 1i and 1j. If the product application
is a multi-chip package, it would include interconnections (not
shown) between the dies, and segmenting would be performed so that
the interconnected dies were not segmented from one another. In the
case of multi-chip packages, each chip within the multi-chip
package can be the same type (e.g., memory, logic, etc.) or they
may be of different types.
[0032] The second embodiment of the present invention shown in
FIGS. 2a-2j also utilizes thin film polymer material for the
insulating layers of the interconnect structure. The major
fabrication steps are the same as the first embodiment shown in
FIG. 1 with the exception that the glass substrate 32 used has
cavities 34 to house the semiconductor dies, and that allow the
semiconductor dies 12 to have a common planar surface for the
application of the first dielectric layer 16. The cavities are
formed by etching to a depth of about the thickness of the die,
which is typically between about 30 and 750 um.
[0033] The third embodiment of the present invention shown in FIGS.
3a-3j utilizes a glass-metal composite as the substrate 36. The
glass layer is etched with cavities, using the underlying metal as
an etch stop, that allow the semiconductor dies 12 to be bonded and
to have a common planar surface for the application of the first
dielectric layer 16. Alternately, holes may be punched in the glass
sheet and the sheet laminated to the metal substrate. In addition
the thermal path from the chip is improved by bonding to the metal
substrate which acts as a thermal spreader. The thin film
interconnect structure is the same as in the previous
embodiments.
[0034] The fourth embodiment of the present invention as shown in
FIGS. 4a-4j utilizes a glass substrate with the semiconductor dies
mounted with the active surface on the glass substrate 38, or face
down. A polymer or epoxy is used to fill the gap between dies and
may cover dies also. The polymer or epoxy is used for planarization
purposes. The surface is then ground to the desired thickness. CMP
(Chemical Mechanical Planarization) may be used in the grinding.
The first glass is used for the leveling of the active surface of
the semiconductor dies A second glass substrate 10 is then bonded
to the back side of the semiconductor dies 12. The first glass
substrate 38 is thinned by backside grinding to a thickness of 2 um
to 150 um depending on the electrical design of the interconnect.
Vias are etched in the thin glass substrate layer 38 to contact the
semiconductor dies. The thin film interconnect layers are then
formed as in the previous embodiments.
[0035] The fifth embodiment of the present invention shown in FIGS.
5a-5j utilizes a glass substrate 38 with the semiconductor dies
mounted face down on the surface. A coating of a polymer or epoxy
is deposited and the surface including the back of the
semiconductor dies is ground to the desired thickness. Leveling of
the surface is important for the follow-on thin film process. A
second glass substrate is bonded to the back of the thinned
semiconductor dies and the first glass substrate is removed. The
thin film process is then completed as described above.
[0036] In each of the above embodiments, the interconnect metal may
be used to form interconnections between one or more points of
electrical contact on each of the semiconductor dies.
[0037] The present invention as described in the five embodiments
provides wiring structures and methods to obtain them, that have
the ability of greater fan-out from the semiconductor dies, with
wiring structures that are far superior to the post passivation
process described earlier and/or wafer level packages. The
structures described above also have the ability to provide for a
variety of passive components, e.g., capacitors, inductors, etc.,
internal to the wiring structure. These structures may be used in
single chip fan-out packages or as interconnections between chips
or multi-chip packages. Another advantage of the present invention
is the ability to utilize present manufacturing equipment such as
used in the manufacture of glass LCD panels
[0038] Although the invention has been described and illustrated
with reference to specific illustrative embodiments thereof, it is
not intended that the invention be limited to those illustrative
embodiments. Those skilled in the art will recognize that
variations and modifications can be made without departing from the
spirit of the invention. It is therefore intended to include within
the invention all such variations and modifications which fall
within the scope of the appended claims and equivalents
thereof.
* * * * *