U.S. patent application number 10/443950 was filed with the patent office on 2004-03-25 for gate with dual gate dielectric layer and method of fabricating the same.
This patent application is currently assigned to Nanya Technology Corporation. Invention is credited to Chuang, Ying-Cheng, Huang, Chung-Lin.
Application Number | 20040058498 10/443950 |
Document ID | / |
Family ID | 31989792 |
Filed Date | 2004-03-25 |
United States Patent
Application |
20040058498 |
Kind Code |
A1 |
Huang, Chung-Lin ; et
al. |
March 25, 2004 |
Gate with dual gate dielectric layer and method of fabricating the
same
Abstract
A gate with dual gate dielectric layer and fabrication method
thereof. A semiconductor substrate is provided, on which a
dielectric layer and a patterned hard mask layer with an opening
are sequentially formed. A spacer is formed on a sidewall of the
opening. The semiconductor substrate is ion implanted, the spacer
and the exposed dielectric layer are removed, and a gate oxide
layer is formed on the bottom of the opening.
Inventors: |
Huang, Chung-Lin; (Taichung
City, TW) ; Chuang, Ying-Cheng; (Taoyuan Hsien,
TW) |
Correspondence
Address: |
QUINTERO LAW OFFICE
1617 BROADWAY, 3RD FLOOR
SANTA MONICA
CA
90404
US
|
Assignee: |
Nanya Technology
Corporation
|
Family ID: |
31989792 |
Appl. No.: |
10/443950 |
Filed: |
May 22, 2003 |
Current U.S.
Class: |
438/287 ;
257/411; 257/E21.335; 257/E21.434; 257/E29.152; 438/216 |
Current CPC
Class: |
H01L 29/518 20130101;
H01L 29/6653 20130101; H01L 29/66583 20130101; H01L 29/512
20130101; H01L 21/28202 20130101; H01L 29/4983 20130101; H01L
21/2822 20130101; H01L 29/513 20130101; H01L 21/26506 20130101;
H01L 21/28194 20130101; H01L 29/66553 20130101 |
Class at
Publication: |
438/287 ;
438/216; 257/411 |
International
Class: |
H01L 021/336; H01L
021/8238; H01L 029/76; H01L 031/062 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 25, 2002 |
TW |
91121992 |
Claims
What is claimed is:
1. A method for fabricating a gate with dual gate dielectric layer,
comprising: providing a semiconductor substrate, with a dielectric
layer and a patterned hard mask layer with an opening sequentially
formed thereon; forming a spacer on a sidewall of the opening;
implanting nitrogen ions into the semiconductor substrate; removing
the spacer and the exposed dielectric layer; and forming a gate
oxide layer on a bottom of the opening.
2. The method for fabricating a gate with dual gate dielectric
layer as claimed in claim 1, further comprising: filling a
conducting layer in the opening; and removing the hard mask
layer.
3. The method for fabricating a gate with dual gate dielectric
layer as claimed in claim 1, wherein the dielectric layer is a pad
oxide layer.
4. The method for fabricating a gate with dual gate dielectric
layer as claimed in claim 1, wherein the patterned hard mask layer
comprises a nitride layer.
5. The method for fabricating a gate with dual gate dielectric
layer as claimed in claim 1, wherein a method for forming the gate
oxide layer comprises thermal oxidation.
6. The method for fabricating a gate with dual gate dielectric
layer as claimed in claim 1, wherein the conducting layer comprises
a polysilicon layer or an exi-silicon layer.
7. A method for fabricating a gate with dual gate dielectric layer,
comprising: providing a semiconductor substrate, with a dielectric
layer, a hard mask layer, and a patterned photoresist layer with a
first opening sequentially formed thereon, wherein the first
opening exposes the hard mask layer; etching the hard mask layer to
form a second opening using the patterned photoresist layer as a
mask; removing the patterned photoresist layer; conformally forming
an insulating layer over the hard mask layer and the second
opening; anisotropically etching the insulating layer to form a
spacer on a sidewall of the second opening; implanting nitrogen
ions into the exposed semiconductor substrate using the hard mask
layer and the spacer as masks; removing the spacer and the exposed
dielectric layer; and thermally oxidizing the semiconductor
substrate to form a gate oxide layer over a bottom of the second
opening using the hard mask layer as a mask.
8. The method for fabricating a gate with dual gate dielectric
layer as claimed in claim 7, further comprising: forming a
conducting layer over the hard mask layer, the second opening
filled with the conducting layer; planarizing the conducting layer
to expose the hard mask layer; and removing the hard mask
layer.
9. The method for fabricating a gate with dual gate dielectric
layer as claimed in claim 7, wherein the dielectric layer comprises
a pad oxide layer.
10. The method for fabricating a gate with dual gate dielectric
layer as claimed in claim 7, wherein the hard mask layer comprises
a nitride layer.
11. The method for fabricating a gate with dual gate dielectric
layer as claimed in claim 7, wherein the insulating layer comprises
an oxide layer.
12. The method for fabricating a gate with dual gate dielectric
layer as claimed in claim 7, wherein the method of anisotropic
etching comprises a reactive ion etching or a plasma etching.
13. The method for fabricating a gate with dual gate dielectric
layer as claimed in claim 7, wherein the conducting layer comprises
a polysilicon layer or an exi-silicon layer.
14. The method for fabricating a gate with dual gate dielectric
layer as claimed in claim 7, wherein the method of planarizing
comprises chemical mechanical polishing.
15. A gate with dual gate dielectric layer, comprising: a dual gate
dielectric layer, formed over a semiconductor substrate, comprising
an inner portion and a outer portion, wherein the inner portion is
thinner than the outer portion; and a conducting layer, formed on
the dual gate dielectric layer.
16. The gate with dual gate dielectric layer as claimed in claim
15, wherein the dual gate dielectric layer comprises a gate oxide
layer.
17. A gate with dual gate dielectric layer, comprising: a
semiconductor substrate; a dual gate dielectric layer, formed over
the semiconductor substrate, comprising a first gate dielectric
layer and a second gate dielectric layer, wherein the second gate
dielectric layer is formed in an inner portion of the first gate
dielectric layer, and the second gate dielectric layer is thinner
than the first gate dielectric layer; and a conducting layer,
formed on the dual gate dielectric layer.
18. The gate with dual gate dielectric layer as claimed in claim
17, wherein the first gate dielectric layer comprises a gate oxide
layer.
19. The gate with dual gate dielectric layer as claimed in claim
17, wherein the second gate dielectric layer comprises a gate oxide
layer.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The invention relates to a method for fabricating a gate
dielectric layer, and more particularly a dual gate dielectric
layer.
[0003] 2. Description of the Related Art
[0004] A gate dielectric layer, such as silicon oxide layer, is a
dielectric formed under a gate of a MOS. MOS evokes electric charge
in a channel through the gate dielectric layer, improving the
quality of the gate dielectric layer.
[0005] FIGS. 1a to 1e are cross-sections of a conventional method
for fabricating a gate with a gate dielectric layer;
[0006] In FIG. 1a, a semiconductor substrate 101, such as silicon
substrate, is provided. A dielectric layer 102, such as pad oxide
layer, a hard mask layer 103, such as LPCVD nitride layer, and a
patterned photoresist layer 104 with an opening 105 are
sequentially formed on the surface of the semiconductor substrate
101, wherein the position of the opening 105 is the position a gate
formed in the subsequent process.
[0007] In FIG. 1b, the hard mask layer 103 is etched to form an
opening 106 using the patterned photoresist layer 104 as a mask,
wherein the opening 106 exposes the surface of the semiconductor
substrate 101.
[0008] In FIG. 1c, the semiconductor substrate 101 is thermally
oxidized to form a gate dielectric layer 107, such as gate oxide
layer, on the bottom surface of the opening 106.
[0009] In FIG. 1d, a conducting layer 108, such as polysilicon or
exi-silicon, is formed on the hard mask layer 103, wherein the
opening 106 is filled with the conducting layer 108.
[0010] In FIG. 1e, the conducting layer 108 is planarized to expose
the surface of the hard mask layer 103. The hard mask layer 103 and
the dielectric layer 102 are sequentially removed to leave the
conducting layer 108a as a gate. S/D area is formed in the
semiconductor substrate 101 in the subsequent process, and a MOS
with gate with the gate dielectric layer 107 is complete.
[0011] The conventional method will fabricate a MOS with one gate
dielectric thickness. The thickness of the gate dielectric layer is
less when the size of the element is reduced. In order to reduce
the GIDL (gate induced gate leakage) effect and gate to S/D
leakage, after gate patterned, the gate is oxidized to gain a
thicker dielectric thickness at the gate edge. This traditional
gate re-oxidation method is hard to control the mini-bird-beak
length into the gate at the gate edge. In this invention, a dual
gate dielectric thickness to achieve thin dielectric thickness at
gate center and thick dielectric thickness at gate edge is
fabricated. The gate length of thick gate dielectric can be
precisely controlled with a spacer implant mask, which means the
device performance can be prcised controlled. Device fabrication
with more process window will be achieved with the two independent
gate dielectric thickness fabrication at the same time.
SUMMARY OF THE INVENTION
[0012] The present invention is directed to a gate with dual gate
dielectric layer and a method of fabricating the same.
[0013] Accordingly, the present invention provides a method for
forming a gate with dual gate dielectric layer. A semiconductor
substrate is provided. A dielectric layer and a patterned hard mask
layer with an opening are sequentially formed on the semiconductor
substrate. A spacer is formed on a sidewall of the opening.
Nitrogen ions are implanted into the semiconductor substrate. The
spacer and the exposed dielectric layer are removed. A gate oxide
layer is formed on a bottom of the opening. A conducting layer is
formed in the opening. The hard mask layer is removed.
[0014] Accordingly, the present invention also provides a method
for fabricating a gate with dual gate dielectric layer. A
semiconductor substrate is provided. A dielectric layer, a hard
mask layer, and a patterned photoresist layer with a first opening
are sequentially formed on the semiconductor substrate, wherein the
first opening exposes a partial surface of the hard mask layer. The
hard mask layer is etched to form a second opening using the
patterned photoresist layer as a mask, and the patterned
photoresist layer is removed. An insulating layer is conformally
formed on the surface of the hard mask layer and the second
opening. The insulating layer is anisotropically etched to form a
spacer on a sidewall of the second opening. Nitrogen ions are
implanted into the semiconductor substrate using the hard mask
layer and the spacer as masks. The spacer and the exposed
dielectric layer are removed. The semiconductor substrate is
thermally oxidized to form a gate oxide layer on the bottom of the
second opening using the hard mask layer as a mask. A conducting
layer is formed on the hard mask layer, and the second opening is
filled with the conducting layer. The conducting layer is
planarized to expose a surface of the hard mask layer, and the hard
mask layer is removed.
[0015] Accordingly, the present invention provides a gate with dual
gate dielectric layer, comprising a dual gate dielectric layer and
a conducting layer. The dual gate dielectric layer is formed on the
semiconductor substrate, comprising an inner portion and an outer
portion, where the inner portion is thinner than the outer portion.
The conducting layer is formed on the dual gate dielectric
layer.
[0016] Accordingly, the present invention also provides a gate with
dual gate dielectric layer, comprising a semiconductor substrate, a
dual gate dielectric layer, and a conducting layer. The dual gate
dielectric layer is formed on the semiconductor substrate. The dual
gate dielectric layer comprises a first gate dielectric layer and a
second gate dielectric layer, wherein the second gate dielectric
layer is formed closer to the center than the first gate dielectric
layer, and the thickness of the second gate dielectric layer is.
thinner than the first gate dielectric layer. The conducting layer
is formed on the dual gate dielectric layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] For a better understanding of the present invention,
reference is made to a detailed description to be read in
conjunction with the accompanying drawings, in which:
[0018] FIGS. 1a to 1e are cross-sections of a conventional method
for fabricating a gate with a gate dielectric layer;
[0019] FIGS. 2a to 2l are cross-sections of the method for
fabricating a MOS with dual gate dielectric layer of the present
invention.
DETAILED DESCRIPTION OF THE INVENTION
[0020] FIGS. 2a to 2l are cross-sections of the method for
fabricating a MOS with dual gate dielectric layer of the present
invention.
[0021] In FIG. 2a, a semiconductor substrate 201,such as silicon
substrate, is provided, on which a dielectric layer 202, such as
pad oxide layer, a hard mask layer 203, such as LPCVD nitride
layer, and a patterned photoresist layer 204 with an opening 205
are sequentially formed. The LPCVD nitride layer is deposited using
SiCl.sub.2H.sub.2 and NH.sub.3 as reactive gas at 250 to
400.degree. C. The position of the opening 205 is the position of a
dual gate dielectric layer in the subsequent process, and the
opening 205 exposes the surface of the hard mask layer 203.
[0022] In FIG. 2b, the hard mask layer 203 is etched using the
patterned photoresist layer 204 to form an opening in the hard mask
layer 203, wherein the opening exposes the surface of the
semiconductor substrate 201.
[0023] In FIG. 2c, a first insulating layer 207, such as LPCVD
oxide layer or PECVD oxide layer, is conformally formed on the
surface of the hard mask layer 203 and the opening 206, wherein the
LPCVD oxide layer or PECVD oxide layer is deposited at 350 to
850.degree. C.
[0024] In FIG. 2d, the insulating layer 207 is anisotropically
etched to form a first spacer 207a on a sidewall of the opening
206, wherein the anisotropic etching comprises reactive ion and
plasma etching.
[0025] In FIG. 2e, ions are implanted into the semiconductor
substrate 201 to form an ion implanting area 208 using the hard
mask 203 and the first spacer 207a as masks. The ion comprises
nitrogen ion.
[0026] In FIG. 2f, the first spacer 207a is removed in the opening
206. The semiconductor substrate 201 is thermally oxidized to form
a gate dielectric layer 209, such as gate oxide layer, on the
bottom of the opening 206 at 750 to 950.degree. C. using the hard
mask layer 203 as a mask.
[0027] In FIG. 2g, after a thermal oxidation, the second gate
dielectric layer 209b on the semiconductor substrate 201 formed in
the ion implanted area 208 is thinner than the first gate
dielectric layer 209a on the semiconductor substrate 201 outside
the ion implanted area 208 because the nitrogen ions in the ion
implanted area 208 retard the oxidation speed on the semiconductor
201. Thus, the gate dielectric layer 209 comprises the first gate
dielectric layer 209a and the second gate dielectric layer 209b,
wherein the second gate dielectric layer 209b is formed closer to
the center than the first gate dielectric layer 209a.
[0028] In FIG. 2h, with low pressure chemical vapor deposited to
form a conducting layer 210, such as a polysilicon layer or a
exi-silicon layer, on the hard mask layer 203 at 525 to 575.degree.
C., wherein the opening 206 is filled with the conducting layer
210.
[0029] In FIG. 2i, the conducting layer 210 is planarized to expose
the hard mask layer 203. The planarization comprises chemical
mechanical polishing.
[0030] In FIG. 2j, the hard mask layer 203 and the dielectric layer
202 are sequentially removed to leave the conducting layer 210a and
gate dielectric layer 209, wherein comprise the gate of a MOS
structure.
[0031] In FIG. 2k, a second insulating layer 211, such as LPCVD
oxide, LPCVD nitride, PECVD oxide, or PECVD nitride, is conformally
formed on the surface of the conducting layer 210a and the
semiconductor substrate 201 at 350 to 850.degree. C.
[0032] In FIG. 2l, the insulating layer 211 is anisotropically
etched to form a second spacer 211a on the sidewall of the
conducting layer 210a, wherein the anisotropic etching comprises
reactive ion etching or plasma etching. The semiconductor substrate
201 is ion implanted to form a doped SID area using the conducting
layer 210a and the second spacer 211a as masks. The doped S/D area
is rapidly thermally annealed to activate ions in the doped S/D
area. Thus, the gate with dual gate dielectric layer is
completed.
[0033] The present invention provides a method for fabricating a
dual gate dielectric layer using difference in oxidizing rate
between the doped area and non-doped area of the semiconductor
substrate. Integration of embodiments of the present invention is
relatively easy, and does not require additional masking operations
compared to conventional dual gate dielectric layer processes.
Additionally, it does not require the use of marginal processes or
unusual materials.
[0034] While the invention has been described by way of example and
in terms of the preferred embodiments, it is to be understood that
the invention is not limited to the disclosed embodiments. To the
contrary, it is intended to cover various modifications and similar
arrangements (as would be apparent to those skilled in the art).
Therefore, the scope of the appended claims should be accorded the
broadest interpretation so as to encompass all such modifications
and similar arrangements.
* * * * *