U.S. patent application number 10/246245 was filed with the patent office on 2004-03-18 for bridge-type magnetic random access memory (mram) latch.
This patent application is currently assigned to Micron Technology, Inc.. Invention is credited to Fulkerson, David E., Lu, Yong.
Application Number | 20040052105 10/246245 |
Document ID | / |
Family ID | 31992289 |
Filed Date | 2004-03-18 |
United States Patent
Application |
20040052105 |
Kind Code |
A1 |
Fulkerson, David E. ; et
al. |
March 18, 2004 |
BRIDGE-TYPE MAGNETIC RANDOM ACCESS MEMORY (MRAM) LATCH
Abstract
A technique to read a stored state in a magnetoresistive random
access memory (MRAM) device, such as a giant magneto-resistance
(GMR) MRAM device or a tunneling magneto-resistance (TMR) device
uses a bit line in an MRAM device that is segmented into a first
portion and a second portion. An interface circuit compares the
resistance of a first portion and a second portion of a first bit
line to the resistance of a first portion and a second portion of a
second bit line to determine the logical state of a cell in the
first bit line. The interface circuit includes a reset circuit that
selectively couples the outputs of the interface circuit together.
A subsequent decoupling of the outputs allows cross-coupling within
the interface circuit to latch the outputs to a logical state
corresponding to the stored magnetic state, thereby allowing the
stored state of a cell to be read.
Inventors: |
Fulkerson, David E.;
(Plymouth, MN) ; Lu, Yong; (Rosemount,
MN) |
Correspondence
Address: |
KNOBBLE, MARTENS, OLSON & BEAR, LLP
620 NEWPORT CENTER DRIVE
SIXTEENTH FLOOR
NEWPORT BEACH
CA
92660
US
|
Assignee: |
Micron Technology, Inc.
Boise
ID
|
Family ID: |
31992289 |
Appl. No.: |
10/246245 |
Filed: |
September 17, 2002 |
Current U.S.
Class: |
365/158 |
Current CPC
Class: |
G11C 11/15 20130101 |
Class at
Publication: |
365/158 |
International
Class: |
G11C 011/00 |
Goverment Interests
[0001] This invention was made with Government support under
Contract Number MDA972-98-C-0021 awarded by DARPA. The Government
has certain rights in the invention.
Claims
We claim:
1. A latching circuit that senses and latches the magnetic states
of a first bit line and a second bit line in a magnetoresistive
random access memory (MRAM), the latching circuit comprising: a
first output and a second output; a reset circuit having a first
terminal, a second terminal, and a third terminal, the reset
circuit responsive to a first state of an input signal applied to
the first terminal to couple the second terminal to the third
terminal, and responsive to a second state of the input signal
applied to the first terminal to decouple the second terminal from
the third terminal; a first n-type transistor having a source, a
drain and a gate, the source of the first n-type transistor coupled
to a first portion of the first bit line; a second n-type
transistor having a source, a drain and a gate, the source of the
second n-type transistor coupled to a first portion of the second
bit line; a first p-type transistor having a source, a drain and a
gate, the source of the first p-type transistor coupled to a second
portion of the second bit line; a second p-type transistor having a
source, a drain and a gate, wherein: the source of the second
p-type transistor is coupled to a second portion of the first bit
line; the drain of the second p-type transistor is coupled to the
drain of the second n-type transistor, to the gate of the first
n-type transistor, to the gate of the first p-type transistor, to
the second terminal of the reset circuit, and to the second output;
and the gate of the second p-type transistor is coupled to the gate
of the second n-type transistor, to the third terminal of the reset
circuit, to the drain of the first n-type transistor, to the drain
of the first p-type transistor, and to the first output.
2. The MRAM latching circuit as defined in claim 1, wherein the
first n-type transistor and the second n-type transistor comprise
n-channel metal-oxide semiconductor field-effect transistors
(MOSFETs), where the first p-type transistor and the second p-type
transistor comprise p-channel MOSFETs, and where the reset circuit
comprises an n-channel MOSFET with a gate, a drain, and a source as
the first, the second, and the third terminals of the reset
circuit.
3. The MRAM latching circuit as defined in claim 1, wherein the
first n-type transistor and the second n-type transistor comprise
n-channel metal-oxide semiconductor field-effect transistors
(MOSFETs), where the first p-type transistor and the second p-type
transistor comprise p-channel MOSFETs, and where the reset circuit
comprises a p-channel MOSFET with a gate, a drain, and a source as
the first, the second, and the third terminals of the reset
circuit.
4. A magnetoresistive random access memory (MRAM) latching circuit
comprising: a first terminal adapted to couple to a first portion
of a first bit line; a second terminal adapted to couple to a
second portion of the first bit line; a third terminal adapted to
couple to a first portion of a second bit line; a fourth terminal
adapted to couple to a second portion of the second bit line; a
first output; a second output; and an input terminal adapted to
receive a reset signal, where a first state of the reset signal
couples the first output to the second output, and where a second
state of the reset signal decouples the first output from the
second output so that the first output and the second output latch
in opposite directions in response to an imbalance in resistance
between the first bit line and the second bit line.
5. A bit line in a magnetoresistive random access memory (MRAM)
comprising: a first portion to which a first plurality of
magnetically sensitive resistors are coupled, where the first
portion is adapted to couple to a voltage source and to an
interface circuit; and a second portion to which a second plurality
of magnetically sensitive resistors are coupled, where the second
portion is adapted to couple to a reference voltage and to the
interface circuit, where the second portion is not electrically
connected to the first portion.
6. The bit line as defined in claim 5, wherein the MRAM is a giant
magneto-resistance (GMR) memory, and where the first plurality of
magnetically sensitive resistors are arranged in series and the
second plurality of magnetically sensitive resistors are arranged
in series.
7. The bit line as defined in claim 5, where the first plurality of
magnetically sensitive resistors and the second plurality of
magnetically sensitive resistors comprise about one-half each of
the resistors coupled to the bit line.
8. A magnetoresistive random access memory (MRAM) device
comprising: a plurality of word lines; and a plurality of bit
lines, wherein a bit line in the plurality of bit lines is coupled
to a first portion of magnetically sensitive resistors and is
coupled to a second portion of magnetically sensitive resistors,
and where a memory state of a cell in the MRAM device can be
determined by passing a first current through a corresponding word
line and a second current through at least one corresponding bit
line, where the resistance of the bit line is lower when a magnetic
field stored in a hard layer of the cell is aligned with a field
induced by the first current and the second current.
9. The MRAM device as defined in claim 8, wherein at least one pair
of bit lines is coupled to a different number of resistors in the
corresponding first portion and second portion than another pair of
bit lines.
10. A method of determining a magnetic state in a magnetoresistive
random access memory (MRAM) cell comprising: applying a reset
signal to an interface circuit such that at least one output of the
interface circuit is reset to a balanced state; removing the reset
signal; comparing an amount of resistance in a first portion of a
first bit line to an amount of resistance in a first portion of a
second bit line; comparing an amount of resistance in a second
portion of the first bit line to an amount of resistance in a
second portion of the second bit line; and generating an output
with a logic state corresponding to the magnetic state stored in
the cell based on the comparisons of the amount of resistance.
11. A method of latching a magnetic state in a magnetoresistive
random access memory (MRAM) cell comprising: applying current to a
word line corresponding to the MRAM cell; in a reset state,
neutralizing cross-coupled feedback of an interface circuit to
allow the interface circuit to balance in response to current
applied through first and second portions of a first bit line and
through first and second portions of a second bit line, where the
current applied to the first bit line and the current applied
through the second bit line are substantially equal, where the
first bit line corresponds to the MRAM cell; and in a latched
state, enabling cross-coupled feedback across the interface circuit
that allows an imbalance in resistance from a stored state of the
cell to latch the cell in a corresponding logical state.
Description
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The invention generally relates to memory technology. In
particular, the invention relates to non-volatile magnetic
memory.
[0004] 2. Description of the Related Art
[0005] Computers and other digital systems use memory to store
programs and data. A common form of memory is random access memory
(RAM). Many memory devices, such as dynamic random access memory
(DRAM) devices and static random access memory (SRAM) devices, are
volatile memories. A volatile memory loses its data when power is
removed. For example, after a conventional personal computer is
powered off, the volatile memory is reloaded upon a boot up. In
addition, certain volatile memories, such as DRAM devices, require
periodic refresh cycles to retain their data even when power is
continuously supplied.
[0006] In contrast to the potential loss of data encountered in
volatile memory devices, nonvolatile memory devices retain data for
long periods of time when power is removed. Examples of nonvolatile
memory devices include read only memory (ROM), programmable read
only memory (PROM), erasable PROM (EPROM), electrically erasable
PROM (EEPROM), flash memory, and the like. Disadvantageously,
conventional nonvolatile memories are relatively large, slow, and
expensive. Further, many types of conventional semiconductor
nonvolatile memories are relatively limited in write cycle
capability and typically can only be programmed to store data about
10,000 times in a particular memory location. This prevents a
conventional non-volatile memory device, such as a flash memory
device, from being used as general purpose memory.
[0007] An alternative memory device is known as magnetoresistive
random access memory (MRAM). An MRAM device uses magnetic states to
retain data in its memory cells. Advantageously, MRAM devices are
relatively fast, are nonvolatile, consume relatively little power,
and do not suffer from a write cycle limitation. There are at least
three different types of MRAM devices, including giant
magneto-resistance (GMR) MRAM devices, magnetic tunnel junction
(MTJ) or tunneling magneto-resistance (TMR) MRAM devices, and
pseudo spin valve (PSV) MRAM devices. GMR MRAM devices separate at
least two ferromagnetic layers with a metallic layer. In a MTJ MRAM
device, at least two ferromagnetic layers are separated by a thin
insulating tunnel barrier. A PSV MRAM device uses an asymmetric
sandwich of the ferromagnetic layers and metallic layer as a memory
cell, and the ferromagnetic layers are driven so that they do not
switch at the same time.
[0008] An interface circuit detects and latches the memory state of
a magnetic memory cell so that the contents of the cell can be
provided to another circuit, such as a central processing unit
(CPU). Disadvantageously, conventional circuits that latch the
state of the magnetic memory cell are relatively sensitive to
variations in transistor parameters, such as gate length. These
sensitivities can disadvantageously increase production costs and
can also cause data to be incorrectly read from the magnetic memory
cell. Embodiments of the invention solve these and other problems
by providing a latching circuit that is relatively less sensitive
to variations in transistor parameters.
SUMMARY OF THE INVENTION
[0009] The invention relates to techniques to read a stored state
in a magnetoresistive random access memory (MRAM) memory device.
Advantageously, an interface circuit or latching circuit according
to an embodiment of the invention is relatively insensitive to
transistor parameter variations, such as gate length. This
advantageously allows the interface circuit to be manufactured less
expensively and also allows the interface circuit to reliably
detect logic states with relatively small differences in
resistance.
[0010] A bit line in an MRAM device is segmented into a first
portion and a second portion. An interface circuit compares the
resistance associated with a first portion and a second portion of
a first bit line to the resistance associated with a first portion
and a second portion of a second bit line to determine the logical
state of a cell in the first bit line. The interface circuit
includes a reset circuit to allow the circuit to achieve a balanced
state by coupling outputs of the interface circuit to a relatively
low resistance. Decoupling of the outputs allows cross-coupling
within the interface circuit to latch the outputs to a logical
state corresponding to the stored magnetic state, thereby allowing
the stored state of a cell to be read.
[0011] One embodiment according to the invention includes an MRAM
memory latching circuit that includes a reset circuit, a first
n-type transistor, a second n-type transistor, a first p-type
transistor, and a second p-type transistor. The memory latching
circuit can be used to latch the stored state of a corresponding
memory cell and can also be used as an interface between the memory
cell and another device, such as a central processing unit (CPU).
The reset circuit includes a first terminal, a second terminal, and
a third terminal. The reset circuit couples the second terminal to
the third terminal in response to a first state of an input signal
applied to the first terminal, and the reset circuit decouples the
second terminal from the third terminal in response to a second
state of the input signal applied to the first terminal. Coupling
of the second terminal to the third terminal effectively disables
cross-coupled feedback across the memory latching circuit. The
first n-type transistor includes a source coupled to a first
portion of a first bit line. The second n-type transistor includes
a source coupled to a first portion of a second bit line. The first
p-type transistor includes a source coupled to a second portion of
the second bit line, where a drain of the first p-type transistor
is coupled to a drain of the first n-type transistor and to a first
output. A gate of the first p-type transistor is coupled to a gate
of the first n-type transistor, to a drain of a second n-type
transistor, to a drain of a second p-type transistor, and to the
second terminal of the reset circuit. The second p-type transistor
includes a source coupled to a second portion of the first bit
line, where the drain of the second p-type transistor is coupled to
the drain of the second n-type transistor and to a second output. A
gate of the second p-type transistor is coupled to a gate of the
second n-type transistor, to the drain of the first n-type
transistor, to the drain of the first p-type transistor, and to the
third terminal of the reset circuit. In one embodiment, the
transistors are metal-oxide semiconductor field-effect transistors
(MOSFETs).
[0012] Another embodiment according to the invention includes an
MRAM latching circuit. The latch includes a first terminal adapted
to couple to a first portion of a first bit line, a second terminal
adapted to couple to a second portion of the first bit line, a
third terminal adapted to couple to a first portion of a second bit
line, and a fourth terminal adapted to couple to a second portion
of the second bit line. The memory latching circuit further
includes an input terminal adapted to receive a reset signal, where
a first state of the reset signal couples a first output to a
second output, and where a second state of the reset signal
decouples the first output from the second output so that the first
output and the second output latch in opposite directions in
response to an imbalance in resistance between the first bit line
and the second bit line.
[0013] Another embodiment according to the invention includes a bit
line in an MRAM. The bit line includes a first portion and a second
portion coupled to magnetically sensitive resistors. The first
portion is adapted to couple to a voltage source and to an
interface circuit. The second portion is adapted to couple to a
voltage reference (e.g., ground) and to the interface circuit. The
first portion is electrically connected to the second portion
through the interface circuit. In one embodiment, the first portion
and the second portion contain about the same number of
magnetically sensitive resistors.
[0014] Another embodiment according to the invention includes an
MRAM device. The MRAM device includes a plurality of word lines and
a plurality of bit lines. A bit line in the plurality of bit lines
is coupled to a first portion of magnetically sensitive resistors
and is also coupled to a second portion of magnetically sensitive
resistors. A memory state of a cell in the MRAM device can be
determined by passing a first current through a corresponding word
line and a second current through at least one corresponding bit
line. Where the MRAM device is a GMR, a corresponding bit line is
lower in resistance when a magnetic field in a hard layer of the
cell is aligned with a field induced by the first current and the
second current than when the magnetic field is not aligned. The
number of resistors coupled to first portions and second portions
of bit lines can be the same. In one embodiment, at least one pair
of bit lines is coupled to a different number of resistors in the
corresponding first portion and second portion than another pair of
bit lines.
[0015] One embodiment according to the invention includes a method
of determining a magnetic state in an MRAM cell. The method
includes applying a reset signal to an interface circuit such that
at least one output of the interface circuit is reset to a balanced
state, removing the reset signal, comparing an amount of resistance
associated with a first portion of a first bit line to an amount of
resistance associated with a first portion of a second bit line,
comparing an amount of resistance associated with a second portion
of the first bit line to an amount of resistance associated with a
second portion of the second bit line, and generating an output
with a logic state corresponding to the magnetic state stored in
the cell based on the comparisons.
[0016] Another embodiment according to the invention includes a
method of latching a magnetic state in an MRAM cell, such as a GMR
cell. The method includes applying current to a word line
corresponding to the MRAM cell. In a reset state, the method
includes neutralizing cross-coupled feedback of an interface
circuit to allow the interface circuit to balance in response to
current applied through first and second portions of a first bit
line and through first and second portions of a second bit line,
where the current applied to the first bit line and the current
applied through the second bit line are substantially equal, and
where the first bit line corresponds to the MRAM cell. In a latched
state, the method includes enabling cross-coupled feedback across
the interface circuit that allows an imbalance in resistance from a
stored state of the cell to latch the cell in a corresponding
logical state.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] These and other features of the invention will now be
described with reference to the drawings summarized below. These
drawings and the associated description are provided to illustrate
preferred embodiments of the invention and are not intended to
limit the scope of the invention.
[0018] FIG. 1 is a perspective view illustrating a giant
magneto-resistance (GMR) cell in a spin valve mode.
[0019] FIG. 2 is a schematic top-down view illustrating an array of
GMR cells.
[0020] FIG. 3 illustrates a GMR cell in a pseudo spin valve (PSV)
mode.
[0021] FIG. 4 illustrates a conventional latching circuit.
[0022] FIG. 5 illustrates a latching circuit according to an
embodiment of the invention.
[0023] FIG. 6 is a schematic of a bit line of an array of
magnetoresistive random access (MRAM) cells according to an
embodiment of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0024] Although this invention will be described in terms of
certain preferred ents, other embodiments that are apparent to
those of ordinary skill in the art, g embodiments that do not
provide all of the benefits and features set forth herein, within
the scope of this invention. Accordingly, the scope of the
invention is defined reference to the appended claims.
[0025] A magnetoresistive random access memory (MRAM) stores data
in magnetic its memory cells. The electrical resistance of the cell
varies depending on the stored c state of the cell. The stored
state of the cell is detected by sensing the difference in e.
[0026] While illustrated in the context of giant magneto-resistance
(GMR) memories, the artisan will appreciate that the principles and
advantages described herein are le to other types of magnetic
memories, such as tunneling magneto-resistance (TMR)
[0027] FIG. 1 is a perspective view illustrating a GMR cell 100 in
a spin valve mode. R cell 100 includes a word line 102 and a bit
line 104. In a GMR cell, the bit line so known as a sense line. The
bit line 104 contains magnetic layers. Data is stored body portion
of the bit line 104 by simultaneously applying current through the
word and the bit line 104. The direction of the current in the bit
line 104 determines the ion of the magnetic field that stores the
logical state of the data. The polarization lockwise around the bit
line 104 for a first state, and counterclockwise around the bit for
a second state. Where the magnetic memory cell corresponds to a
tunneling resistance (TMR) configuration, a TMR cell is disposed
between the bit line 104 ord line 102.
[0028] To read data from the GMR cell 100, currents are again
applied to the word line 102 and the bit line 104 corresponding to
the GMR cell 100. The resistance encountered by the current applied
to the bit line 104 varies depending on the logical state stored in
the magnetic layers. A cell with a larger resistance exhibits a
larger voltage drop in response to the current than a cell with a
smaller resistance.
[0029] FIG. 2 is a schematic top-down view illustrating an array
200 of GMR cells. A plurality of cells are arranged into the array
200 in a memory device. The array 200 of cells includes a plurality
of word lines 202 and a plurality of bit lines 204. An individual
cell within the array 200 is selected by applying current through
the corresponding word line and the corresponding bit line. Data is
not stored or read in a cell where current flows through only one
of the cell's word line or bit line. Thus, data is only stored in a
cell where the applied word line current and the applied bit line
current intersect (i.e., both currents are present at the same
cell).
[0030] FIG. 3 illustrates a GMR cell 300 in a pseudo spin valve
(PSV) mode. The GMR cell 300 includes a word line 302 and a bit
line 304. The bit line 304 of the GMR cell 300, which is also known
as a sense line, further includes a first magnetic layer 306, a
conductive layer 308, and a second magnetic layer 310. The first
magnetic layer 306 and the second magnetic layer 310 are mismatched
so that the first magnetic layer 306 is magnetically "softer" than
the second magnetic layer 310. The mismatch in magnetic properties
can be obtained by making the first magnetic layer 306 relatively
thin as compared to the second magnetic layer 310, by selecting a
relatively soft magnetic material for the first magnetic layer 306
and a relatively hard magnetic material for the second magnetic
layer 310, or by making the first magnetic layer 306 thinner and
magnetically softer than the second magnetic layer 310.
[0031] The GMR cell 300 stores the logical state in the second
magnetic layer 310. A relatively high magnetic field is required to
switch the magnetization of the second magnetic layer 310. The
magnetization of the second magnetic layer 310 is read by switching
the magnetization of the first magnetic layer 306, which can be
switched with a relatively low magnetic field generated by applying
currents to the corresponding word line 302 and the corresponding
bit line 304. The resulting magnetization of the first magnetic
layer 306 is either parallel or anti-parallel to the magnetization
of the second magnetic layer 310, which stores the state. When the
magnetization in the first magnetic layer 306 is relatively aligned
with or in parallel with the magnetization of the second magnetic
layer 310, the electrical resistance of the GMR cell 300 is lower
than when the magnetization of the first magnetic layer 306 is
relatively not aligned with or is anti-parallel to the
magnetization of the second magnetic layer 310. In one embodiment,
current is applied in the word line 302 in both directions to
peruse the magnetization of the second magnetic layer 310. The
difference in electrical resistance of the bit line 304 is then
sensed, thereby allowing the stored logical state of the GMR cell
300 to be retrieved. In a TMR memory cell, a cell body is formed
between the bit line and the word line, and the conductive layer
308 is replaced by a relatively thin insulating layer, which is
thin enough to allow the tunneling of electrons from one magnetic
layer to the other magnetic layer to detect memory states.
[0032] FIG. 4 illustrates a conventional latching circuit 400. The
conventional latching circuit 400 is disadvantageously relatively
sensitive to transistor parameter variations, such as gate length.
The conventional latching circuit 400 detects a logic state by
comparing the resistance of a first magnetically sensitive resistor
R.sub.A 402, with the resistance of a second magnetically sensitive
resistor R.sub.B 404. Although the first magnetically sensitive
resistor RA 402 and the second magnetically sensitive resistor
R.sub.B 404 are schematically illustrated with a single resistor
symbol, the first magnetically sensitive resistor R.sub.A 402 and
the second magnetically sensitive resistor R.sub.B 404 correspond
to a combination of multiple resistances from a bit line or a sense
line that corresponds to multiple memory cells in an array.
[0033] The resistance of the first magnetically sensitive resistor
R.sub.A 402, the resistance of the second magnetically sensitive
resistor R.sub.B 404, or the resistances of both resistors can vary
depending on the stored state of the selected memory cell, which is
the cell corresponding to the cell at the intersection of the
applied word line current and the applied bit line current.
[0034] Initially, a reset transistor M.sub.5 406 is switched "on"
by providing a relatively high signal to the gate of the reset
transistor M.sub.5 406 from an input terminal 408. The "on" state
of the reset transistor M.sub.5 406 balances the conventional
latching circuit 400 by electrically tying the gate of a first
n-type transistor M.sub.1 410 to the gate of a second n-type
transistor M.sub.2 412. The first n-type transistor M.sub.1 410 and
the second n-type transistor M.sub.2 412 are matched. The "on"
state of the reset transistor M.sub.5 406 also electrically ties
the gate of a first p-type transistor M.sub.3 414 with the gate of
a second p-type transistor M.sub.4 416. The first p-type transistor
M.sub.3 414 and the second p-type transistor M.sub.4 416 are also
matched.
[0035] To illustrate the latching operation of the conventional
latching circuit 400, the operation of the conventional latching
circuit 400 will now be described with the first magnetically
sensitive resistor R.sub.A 402 at a lower resistance than the
second magnetically sensitive resistor R.sub.B 404. When the
resistance of the first magnetically sensitive resistor RA 402 is
lower than the resistance of the second magnetically sensitive
resistor R.sub.B 404, the source of the first n-type transistor
M.sub.1 410 should be at a lower voltage relative to voltage at the
source of the second n-type transistor M.sub.2 412. Since the gate
of the first n-type transistor M.sub.1 410 and the gate of the
second n-type transistor M.sub.2 412 are tied to the same
potential, the first n-type transistor M.sub.1 410 is relatively
more conductive from drain to source than the second n-type
transistor M.sub.2 412 because of the larger gate to source voltage
of the first n-type transistor M.sub.1 410.
[0036] To latch the conventional latching circuit 400, the reset
transistor M.sub.5 406 is turned "off" by deactivating the
relatively high input signal previously applied to the gate of the
reset transistor M.sub.5 406 via the input terminal 408. When
operating as intended, the conventional latching circuit 400
latches into an electrical state determined by the mismatch in
resistance between the first magnetically sensitive resistor
R.sub.A 402 and the second magnetically sensitive resistor R.sub.B
404. When the first magnetically sensitive resistor R.sub.A 402 has
a lower resistance than the second magnetically sensitive resistor
R.sub.B 404, the conventional latching circuit 400 should switch to
a state where a first output OUT, 418 is at a "low" state and a
second output OUT.sub.2 420 is at a "high" state.
[0037] When the reset transistor M.sub.5 406 is turned "off," the
gates of the first n-type transistor M.sub.1 410 and the first
p-type transistor M.sub.3 414 are decoupled from the gates of the
second n-type transistor M.sub.2 412 and the second p-type
transistor M.sub.4 416. Because the drain of the first n-type
transistor M.sub.1 410 is relatively more conductive than the
second n-type transistor M.sub.2 412, the voltage at the first
output OUT, 418 is relatively low as compared with the voltage at
the second output OUT.sub.2 420. The relatively low voltage at the
first output OUT.sub.1 418 is cross-coupled to the gate of the
second n-type transistor M.sub.2 412 and to the gate of the second
p-type transistor M.sub.4 416. A relatively low voltage on the gate
of the second n-type transistor M.sub.2 412 tends to turn the
second n-type transistor M.sub.2 412 "off" (i.e., less conductive).
A relatively low voltage on the gate of the second p-type
transistor M.sub.4 416 tends to turn the second p-type transistor
M.sub.4 416 "on" (i.e., more conductive). This causes the voltage
of the second output OUT.sub.2 420 to rise.
[0038] A relatively high voltage on the second output OUT.sub.2 420
is cross-coupled to the first n-type transistor M.sub.1 410 and to
the first p-type transistor M.sub.3 414. A relatively high voltage
on the gate of the first n-type transistor M.sub.1 410 turns the
first n-type transistor M.sub.1 410 more "on" (i.e., more
conductive). A relatively high voltage on the gate of the first
p-type transistor M.sub.3 414 causes the first p-type transistor
M.sub.3 414 to turn "off" (i.e., less conductive). This causes the
voltage of the first output OUT, 418 to go lower. The process
continues until the first output OUT.sub.1 418 is at a "low" state
and the second output OUT.sub.2 420 is at a "high" state.
[0039] The skilled artisan will appreciate that relatively closely
matched transistors are difficult and expensive to manufacture. In
addition, the magnitude of the difference in resistance between one
logic state and another logic state is relatively small, e.g., a
few percent. Where, for example, the drain currents of the first
p-type transistor M.sub.3 414 and the second p-type transistor
M.sub.4 416 are mismatched by more than the difference in
resistance between logic states, the final state of the latch will
be undesirably determined by the transistor mismatch rather than
the stored logic state, and the logic state may not be correctly
reported. The drain current in the first p-type transistor M.sub.3
414 or in the second p-type transistor M.sub.4 416 is approximately
inversely proportional to the gate length, L, of the transistor.
Thus, for the conventional latching circuit 400 to properly report
data, the gate lengths of the first p-type transistor M.sub.3 414
and the second p-type transistor M.sub.4 416 should be matched to
at least the difference in resistance between logic states.
[0040] FIG. 5 illustrates an improved latching circuit 500
according to an embodiment of the invention. The latching circuit
500 more reliably detects logical states of magnetically sensitive
resistors, such as those used in GMR and in TMR memory devices,
than the conventional latching circuit 400 described above in
connection with FIG. 4. The latching circuit 500 is advantageously
relatively insensitive to transistor parameter variations, such as
gate length. This advantageously allows the latching circuit 500 to
be manufactured less expensively and also allows the latching
circuit 500 to reliably detect logic states with relatively small
differences in resistance.
[0041] Although the latching circuit 500 is illustrated with
n-channel and p-channel metal-oxide semiconductor field-effect
transistors (MOSFETs) for the n-type and p-type transistors,
respectively, it will be understood by one of ordinary skill in the
art that the circuit can also be implemented with other
technologies. For example, silicon-germanium (Si--Ge) bipolar
transistors, silicon bipolar transistors, gallium arsenide metal
semiconductor field-effect transistors (GaAs FETs or MESFETs),
heterojunction bipolar transistors (HBTs), Si--Ge bipolar
complementary metal-oxide semiconductor (BiCMOS), and the like can
also be used.
[0042] The latching circuit 500 detects a logic state by comparing
the resistance of a first bit line with the resistance of a second
bit line. When the magnetic cells are GMR cells, the first bit line
and the second bit line include a plurality of magnetically
sensitive resistors for their respective cells that are connected
in series. When the magnetic cells are TMR cells, the first bit
line and the second bit line carry current coupled from word lines
through the TMR cells in addition to current applied to the bit
line. In the illustrated latching circuit 500, the first bit line
is segmented into two portions. The bit line can be segmented into
more than two portions. In one embodiment, the bit line is
segmented into two approximately equal portions.
[0043] A first portion of the first bit line is schematically
illustrated as a first magnetically sensitive resistor R.sub.1 502,
and a second portion of the first bit line is schematically
illustrated as a second magnetically sensitive resistor R.sub.2
504. A first portion of the second bit line is schematically
illustrated as a third magnetically sensitive resistor R.sub.3 506,
and a second portion of the second bit line is schematically
illustrated as a fourth magnetically sensitive resistor R.sub.4
508. It will be understood by one of ordinary skill in the art that
the portions of the first bit line and the second bit line
schematically illustrated by the first magnetically sensitive
resistor R.sub.1 502, the second magnetically sensitive resistor
R.sub.2 504, the third magnetically sensitive resistor R.sub.3 506,
and the fourth magnetically sensitive resistor R.sub.4 508 include
combinations of multiple magnetically sensitive resistors.
[0044] The combined resistance (i.e., the series resistance) of the
first magnetically sensitive resistor R.sub.1 502 and the second
magnetically sensitive resistor R.sub.2 504, the combined
resistance of the third magnetically sensitive resistor R.sub.3 506
and the fourth magnetically sensitive resistor R.sub.4 508, or both
combined resistances can vary depending on the stored state of the
selected memory cell, which is the cell corresponding to the cell
with the applied word line current and the applied bit line
current.
[0045] Initially, a reset transistor M.sub.5 510 is switched "on"
by providing a relatively high signal to the gate of the reset
transistor M.sub.5 510 from an input terminal 512. The illustrated
reset transistor M.sub.5 510 is an n-type transistor. However, the
skilled practitioner will appreciate that a p-type transistor can
also be used. The "on" state of the reset transistor M.sub.5 510
balances the latching circuit 500 by electrically tying the gate of
a first n-type transistor M.sub.1 514, the gate of a second n-type
transistor M.sub.2 516, the gate of a first p-type transistor
M.sub.3 518, and the gate of a second p-type transistor M.sub.4 520
together. The first n-type transistor M.sub.1 514 and the second
n-type transistor M.sub.2 516 are preferably matched to each other.
The first p-type transistor M.sub.3 518 and the second p-type
transistor M.sub.4 520 are also preferably matched to each
other.
[0046] To illustrate the latching operation of the latching circuit
500, the operation of the latching circuit 500 will now be
described with the reset transistor M.sub.5 510 switched "on" and
with the combined resistance of the first magnetically sensitive
resistor R.sub.1 502 and the second magnetically sensitive resistor
R.sub.2 504 (i.e., the resistance of the first bit line) at a lower
resistance than the combined resistance of the third magnetically
sensitive resistor R.sub.3 506 and the fourth magnetically
sensitive resistor R.sub.4 508 (i.e., the resistance of the second
bit line).
[0047] When the combined resistance of the first magnetically
sensitive resistor R.sub.1 502 and the second magnetically
sensitive resistor R.sub.2 504 is lower than the combined
resistance of the third magnetically sensitive resistor R.sub.3 506
and the fourth magnetically sensitive resistor R.sub.4 508, then
one of the first magnetically sensitive resistor R.sub.1 502 or the
second magnetically sensitive resistor R.sub.2 504 is lower in
resistance than the corresponding one of the third magnetically
sensitive resistor R.sub.3 506 or the fourth magnetically sensitive
resistor R.sub.4 508. The other resistor in each series resistance
should have about the same resistance (e.g., if the resistance of
the first resistor R.sub.1 502 is lower than the resistance of the
third resistor R.sub.3 506, then the resistance of the second
resistor R.sub.2 504 is approximately equal to the resistance of
the fourth resistor R.sub.4 508).
[0048] When the resistance of the first magnetically sensitive
resistor R.sub.1 502 is lower than the resistance of the third
magnetically sensitive resistor R.sub.3 506, the first n-type
transistor M.sub.1 514 is relatively more conductive from drain to
source than the second n-type transistor M.sub.2 516 is from drain
to source because the lower resistance of the first magnetically
sensitive resistor R.sub.1 502 results in a larger voltage from
gate to source in the first n-type transistor M.sub.1 514 than in
the second n-type transistor M.sub.2 516. When the resistance of
the second magnetically sensitive resistor R.sub.2 504 is lower
than the resistance of the fourth magnetically sensitive resistor
R.sub.4 508, then the source of the second p-type transistor
M.sub.4 520 is at a higher electrical potential than the source of
the gate of the first p-type transistor M.sub.3 518. Since the
gates of the second p-type transistor M.sub.4 520 and the gate of
the first p-type transistor M.sub.3 518 are tied to the same
potential when the reset transistor M.sub.5 510 is switched "on,"
the second p-type transistor M.sub.4 520 has a relatively larger
source to gate voltage than the gate of the first p-type transistor
M.sub.3 518. The relatively larger source to gate voltage of the
second p-type transistor M.sub.4 520 as compared to the source to
gate voltage of the first p-type transistor M.sub.3 518 causes the
second p-type transistor M.sub.4 520 to be relatively more
conductive from source to drain than the first p-type transistor
M.sub.3 518.
[0049] Following the foregoing process, a relatively low signal is
provided from the input terminal 512 to the gate of the reset
transistor M.sub.5 510 to switch the reset transistor M.sub.5 510
to an "off" state to thereby enable the latching action of the
latching circuit 500. When the reset transistor M.sub.5 510 is
switched "off," the gates of the first n-type transistor M.sub.1
514 and the first p-type transistor M.sub.3 518 are decoupled from
the gates of the second n-type transistor M.sub.2 516 and the
second p-type transistor M.sub.4 520.
[0050] When the first n-type transistor M.sub.1 514 is relatively
more conductive than the second n-type transistor M.sub.2 516, the
voltage at a first output OUT.sub.1 522 is relatively low as
compared with the voltage at a second output OUT.sub.2 524. The
relatively low voltage at the first output OUT.sub.1 522 is
cross-coupled to the gate of the second n-type transistor M.sub.2
516 and to the gate of the second p-type transistor M.sub.4 520. A
relatively low voltage on the gate of the second n-type transistor
M.sub.2 516 tends to turn the second n-type transistor M.sub.2 516
"off" (i.e., less conductive). A relatively low voltage on the gate
of the second p-type transistor M.sub.4 520 tends to turn the
second p-type transistor M.sub.4 520 "on" (i.e., more conductive).
This causes the voltage at the second output OUT.sub.2 524 to
rise.
[0051] A relatively high voltage on the second output OUT.sub.2 524
is cross-coupled to the first n-type transistor M.sub.1 514 and the
first p-type transistor M.sub.3 518. A relatively high voltage on
the gate of the first n-type transistor M.sub.1 514 turns the first
n-type transistor M.sub.1 514 more "on" (i.e., more conductive). A
relatively high voltage on the gate of the first p-type transistor
M.sub.3 518 causes the first p-type transistor M.sub.3 518 to turn
"off" (i.e., less conductive). This causes the voltage of the first
output OUT, 522 to go lower. The process continues until the first
output OUT, 522 is at a "low" state and the second output OUT.sub.2
524 is at a "high" state.
[0052] When the second p-type transistor M.sub.4 520 is relatively
more conductive than the first p-type transistor M.sub.3 518, the
voltage at the second output OUT.sub.2 524 is relatively high as
compared with the voltage at the first output OUT, 522. The
relatively high voltage at the second output OUT.sub.2 524 is
cross-coupled to the gate of the first n-type transistor M.sub.1
514 and to the gate of the first p-type transistor M.sub.3 518. A
relatively high voltage on the gate of the first n-type transistor
M.sub.1 514 tends to turn the first n-type transistor M.sub.1 514
"on" (i.e., more conductive). A relatively high voltage on the gate
of the first p-type transistor M.sub.3 518 tends to turn the first
p-type transistor M.sub.3 518 "off" (i.e., less conductive). This
causes the voltage at the first output OUT.sub.1 522 to
decrease.
[0053] A relatively low voltage on the first output OUT, 522 is
cross-coupled to the second n-type transistor M.sub.2 516 and to
the second p-type transistor M.sub.4 520. A relatively low voltage
on the gate of the second n-type transistor M.sub.2 516 turns the
second n-type transistor M.sub.2 516 further "off" (i.e., less
conductive). A relatively low voltage on the gate of the second
p-type transistor M.sub.4 520 causes the second p-type transistor
M.sub.4 520 to turn "on" (i.e., more conductive). This causes the
voltage of the second output OUT.sub.2 524 to increase. The process
continues until the first output OUT, 522 is at a "low" state, and
the second output OUT.sub.2 524 is at a "high" state.
[0054] As illustrated above, when the combined resistance of the
first magnetically sensitive resistor R.sub.1 502 and the second
magnetically sensitive resistor R.sub.2 504 is less than the
combined resistance of the third magnetically sensitive resistor
R.sub.3 506 and the fourth magnetically sensitive resistor R.sub.4
508, the latching circuit 500 switches to a state where the first
output OUT.sub.1 522 is at a "low" state, and the second output
OUT.sub.2 524 is at a "high" state.
[0055] Advantageously, the latching circuit 500 is relatively less
sensitive to variations in transistor parameters, such as channel
length. The conventional latching circuit 400 described in
connection with FIG. 4 is relatively sensitive to variations in the
first p-type transistor M.sub.3 414 and the second p-type
transistor M.sub.4 416. Equations 1 and 2 express a relationship of
the sensitivity of the conventional latching circuit 400 to
variations in channel length. 1 L L = R R ( Eq . 1 ) L L = ( 1 2 )
( R R ) ( Eq . 2 )
[0056] Equation 1 applies when the first n-type transistor M.sub.1
410 and the second n-type transistor M.sub.2 412 are relatively
large and the inverse of the transconductances, i.e.,
g.sub.m.sup.-1, of the first n-type transistor M.sub.1 410 and the
second n-type transistor M.sub.2 412 are relatively small as
compared to the amount of the resistance of the first magnetically
sensitive resistor R.sub.A 402 or the second magnetically sensitive
resistor R.sub.B 404. Equation 2 applies when the first n-type
transistor M.sub.1 410 and the second n-type transistor M.sub.2 412
are relatively small, and when the inverse of the transconductance
(1/gm) of the first n-type transistor M.sub.1 410 and the second
n-type transistor M.sub.2 412 are about the same as the resistance
of the first magnetically sensitive resistor R.sub.A 402 or the
resistance of the second magnetically sensitive resistor RB 404.
Equations 1 and 2 illustrate that in the conventional latching
circuit 400, the variability of the channel lengths of the first
p-type transistor M.sub.3 414 and the second p-type transistor
M.sub.4 416 should be relatively small to ensure proper detection
or translation of stored data.
[0057] In contrast to the conventional latch of FIG. 4, the
latching circuit 500 of FIG. 5 is relatively insensitive to
variations in channel lengths of the first p-type transistor
M.sub.3 518 and the second p-type transistor M.sub.4 520 because of
the inclusion of the second magnetically sensitive resistor R.sub.2
504 and the fourth magnetically sensitive resistor R.sub.4 508
between the voltage source V.sub.DD and the respective sources of
the transistors. Mismatches in transistor channel lengths are
relatively small as compared to the resistances of the second
magnetically sensitive resistor R.sub.2 504 and the fourth
magnetically sensitive resistor R.sub.4 508, thereby allowing the
latching circuit 500 to detect relatively small differences in
resistance and allowing the production of the latching circuit 500
with a relatively large amount of variability in transistor
parameters, such as channel lengths.
[0058] FIG. 6 is a schematic of a bit line 600 of an array of MRAM
cells according to an embodiment of the invention. The illustrated
bit line 600 includes a first portion 602 and a second portion 604,
and is shown in a GMR configuration. It will be understood by one
of ordinary skill in the art that in a TMR configuration, a bit
line can also be apportioned between a first portion and a second
portion, but that the TMR cells couple to the bit line in parallel
from corresponding word lines.
[0059] The first portion 602 and the second portion 604 each
include a plurality of magnetically sensitive resistors that store
data in magnetic states. The resistance of the first portion 602
and the resistance of the second portion 604 can vary over a broad
range. The amount of resistance of the first portion 602 and the
amount of resistance of the second portion 604 can be equal, but do
not have to be equal. For example, one portion can have 60% of the
resistance, and the other portion can have 40% of the resistance.
In addition, the proportion of allocated resistance in portions of
bit lines can vary within an array, although preferably not within
pairs of bit lines coupled to an interface circuit. In one
embodiment, the resistance of the first portion 602 and the
resistance of the second portion 604 are approximately equal.
[0060] In one embodiment, the first portion 602 and the second
portion 604 do not electrically connect within the array of GMR
cells. The resistance of the magnetically sensitive resistors vary
in accordance with the stored magnetic state and can be translated
to logical states with an interface circuit, such as the latching
circuit 500 described in connection with FIG. 5.
[0061] A first terminal 606 of the bit line 600 is provided to
connect, either directly or indirectly, the bit line 600 to the
voltage source V.sub.DD. A second terminal 608 of the bit line 600
is provided to interface with a corresponding interface circuit,
such as the latching circuit 500. A third terminal 610 of the bit
line 600 is also provided to interface with the interface circuit.
A fourth terminal 612 of the bit line 600 is provided to connect,
either directly or indirectly, the bit line 600 to a reference
voltage (e.g., ground). The illustrated configuration of the bit
line 600 advantageously allows an interface circuit to be produced
with a relatively large tolerance for transistor variations, such
as channel lengths.
[0062] Various embodiments of the invention have been described
above. Although this invention has been described with reference to
these specific embodiments, the descriptions are intended to be
illustrative of the invention and are not intended to be limiting.
Various modifications and applications may occur to those skilled
in the art without departing from the true spirit and scope of the
invention as defined in the appended claims.
* * * * *