U.S. patent application number 10/600524 was filed with the patent office on 2004-03-18 for devices without current crowding effect at the finger's ends.
Invention is credited to Hsu, Hsin-Chyh, Ker, Ming-Dou, Lin, Geeng-Lih.
Application Number | 20040052020 10/600524 |
Document ID | / |
Family ID | 31989753 |
Filed Date | 2004-03-18 |
United States Patent
Application |
20040052020 |
Kind Code |
A1 |
Ker, Ming-Dou ; et
al. |
March 18, 2004 |
Devices without current crowding effect at the finger's ends
Abstract
ESD protection devices without current crowding effect at the
finger's ends. It is applied under MM ESD stress in
sub-quarter-micron CMOS technology. The ESD discharging current
path in the NMOS or PMOS device structure is changed by the
proposed new structures, therefore the MM ESD level of the NMOS and
PMOS can be significantly improved. In this invention, 6 kinds of
new structures are provided. The current crowding problem can be
successfully solved, and have a higher MM ESD robustness. Moreover,
these novel devices will not degrade the HBM ESD level and are
widely used in ESD protection circuits.
Inventors: |
Ker, Ming-Dou; (Hsinchu,
TW) ; Lin, Geeng-Lih; (Hsinchu Hsien, TW) ;
Hsu, Hsin-Chyh; (Taoyuan, TW) |
Correspondence
Address: |
BIRCH STEWART KOLASCH & BIRCH
PO BOX 747
FALLS CHURCH
VA
22040-0747
US
|
Family ID: |
31989753 |
Appl. No.: |
10/600524 |
Filed: |
June 23, 2003 |
Current U.S.
Class: |
361/56 |
Current CPC
Class: |
H01L 2924/0002 20130101;
H01L 27/027 20130101; H01L 27/0277 20130101; H01L 2924/0002
20130101; H01L 2924/00 20130101 |
Class at
Publication: |
361/056 |
International
Class: |
H02H 009/00 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 18, 2002 |
TW |
91121370 |
Claims
What is claimed is:
1. An ESD protection device comprising: a substrate; an isolation
region on the substrate, enclosing an active region; a first gate
having a first and second end overlapping the isolation region to
stretch over the active region, and coupled to a first node; a
second gate disposed on a first side of the first gate and near the
first end of the first gate; and a first and second doping region
on the first and a second side of the first gate, and coupled to a
second and the first node respectively, wherein the first doping
region has a first gap under the second gate.
2. The ESD protection device as claimed in claim 1, wherein the
isolation region is a shallow trench isolation.
3. The ESD protection device as claimed in claim 1, wherein the
first node is ground while the second node is a pad.
4. The ESD protection device as claimed in claim 1 further
comprising: a third gate disposed on the first side of the first
gate and near the second end of the first gate, wherein the first
doping region has a second gap under the third gate.
5. The ESD protection device as claimed in claim 4 further
comprising: a fourth gate having a first and second end overlapping
the isolation region to stretch over the active region, and coupled
to the first node, wherein the first doping region is between the
first and fourth gate; a fifth and sixth gate both disposed on a
first side of the fourth gate, and respectively near a first and
second end of the fourth gate, wherein the first doping region has
a third and fourth gap respectively under the fifth and sixth gate;
and a third doping region on a second side of the fourth gate and
coupled to the second node.
6. The ESD protection device as claimed in claim 5, wherein each of
the second, third, fifth and sixth gate has one end overlapping the
isolation region.
7 The ESD protection device as claimed in claim 5, wherein each of
the first, second, third, fourth, fifth and sixth gate comprises: a
conducting layer; a gate oxide layer under the conducting layer;
and a first and second spacer respectively adjacent to two sides of
the conducting layer and gate oxide layer.
8. The ESD protection device as claimed in claim 7, wherein the
conducting layer is a polysilicon layer while the gate oxide layer,
and the first and second spacer are silicon oxide layers.
9. The ESD protection device as claimed in claim 1 further
comprising a fourth doping region enclosing the isolation
region.
10. The ESD protection device as claimed in claim 9, wherein the
substrate is a P substrate, the first, second and third doping
region are N doping regions, and the fourth doping region is a P
doping region.
11. An ESD protection device comprising: a substrate; an isolation
region on the substrate, enclosing an active region; a first gate
having a first and second end overlapping the isolation region to
stretch over the active region, and coupled to a first node; a
second gate disposed on a second side of the first gate and near
the first end of the first gate; and a first and second doping
region on a first and the second side of the first gate, and
coupled to a second and the first node respectively, wherein the
second doping region has a first gap under the second gate.
12. The ESD protection device as claimed in claim 11, wherein the
isolation region is a shallow trench isolation.
13. The ESD protection device as claimed in claim 11, wherein the
first node is ground while the second node is a pad.
14. The ESD protection device as claimed in claim 11 further
comprising: a third gate disposed on the second side of the first
gate and near the second end of the first gate, wherein the second
doping region has a second gap under the third gate.
15. The ESD protection device as claimed in claim 14 further
comprising: a fourth gate having a first and second end overlapping
the isolation region to stretch over the active region, and coupled
to the first node, wherein the first doping region is between the
first and fourth gate; a fifth and sixth gate both disposed on a
first side of the fourth gate, and respectively near a first and
second end of the fourth gate; and a third doping region on the
first side of the fourth gate, coupled to the second node, and
having a third and fourth gap respectively under the fifth and
sixth gate.
16. The ESD protection device as claimed in claim 15, wherein each
of the second, third, fifth and sixth gate has one end overlapping
the isolation region.
17 The ESD protection device as claimed in claim 15, wherein each
of the first, second, third, fourth, fifth and sixth gate
comprises: a conducting layer; a gate oxide layer under the
conducting layer; and a first and second spacer respectively
adjacent to two sides of the conducting layer and gate oxide
layer.
18. The ESD protection device as claimed in claim 17, wherein the
conducting layer is a polysilicon layer while the gate oxide layer,
and the first and second spacer are silicon oxide layers.
19. The ESD protection device as claimed in claim 11 further
comprising a fourth doping region enclosing the isolation
region.
20. The ESD protection device as claimed in claim 19, wherein the
substrate is a P substrate, the first, second and third doping
region are N doping regions, and the fourth doping region is a P
doping region.
21. An ESD protection device comprising: a substrate; an isolation
region on the substrate, enclosing an active region; a first gate
having a first and second end overlapping the isolation region to
stretch over the active region, and coupled to a first node; and a
first and second doping region on the first and a second side of
the first gate, and coupled to a second and the first node
respectively, wherein the first doping region has a first gap near
the first end of the first gate.
22. The ESD protection device as claimed in claim 21, wherein the
isolation region is a shallow trench isolation.
23. The ESD protection device as claimed in claim 21, wherein the
first node is ground while the second node is a pad.
24. The ESD protection device as claimed in claim 21, wherein the
first doping region further has a second gap near the second end of
the first gate.
25. The ESD protection device as claimed in claim 24 further
comprising: a second gate having a first and second end overlapping
the isolation region to stretch over the active region, and coupled
to the first node, wherein the first doping region is on a first
side of the second gate; and a third doping region on a second side
of the second gate, coupled to the second node; wherein the first
doping region has a third and fourth gap respectively near the
first and second end of the second gate.
26. The ESD protection device as claimed in claim 25, wherein each
of the first, second, third and fourth gap has one end connected to
the isolation region.
27 The ESD protection device as claimed in claim 26, wherein each
of the first and second gate comprises: a conducting layer; a gate
oxide layer under the conducting layer; and a first and second
spacer respectively adjacent to two sides of the conducting layer
and gate oxide layer.
28. The ESD protection device as claimed in claim 27, wherein the
conducting layer is a polysilicon layer while the gate oxide layer,
and the first and second spacer are silicon oxide layers.
29. The ESD protection device as claimed in claim 21 further
comprising a fourth doping region enclosing the isolation
region.
30. The ESD protection device as claimed in claim 29, wherein the
substrate is a P substrate, the first, second and third doping
region are N doping regions, and the fourth doping region is a P
doping region.
31. An ESD protection device comprising: a substrate; an isolation
region on the substrate, enclosing an active region; a first gate
having a first and second end overlapping the isolation region to
stretch over the active region, and coupled to a first node; and a
first and second doping region on the first and a second side of
the first gate, and coupled to a second and the first node
respectively, wherein the second doping region has a first gap near
the first end of the first gate.
32. The ESD protection device as claimed in claim 31, wherein the
isolation region is a shallow trench isolation.
33. The ESD protection device as claimed in claim 31, wherein the
first node is ground while the second node is a pad.
34. The ESD protection device as claimed in claim 31, wherein the
second doping region further has a second gap near the second end
of the first gate.
35. The ESD protection device as claimed in claim 34 further
comprising: a second gate having a first and second end overlapping
the isolation region to stretch over the active region, and coupled
to the first node, wherein the first doping region is on a first
side of the second gate; and a third doping region on a second side
of the second gate, coupled to the second node; wherein the second
doping region has a third and fourth gap respectively near the
first and second end of the second gate.
36. The ESD protection device as claimed in claim 35, wherein each
of the first, second, third and fourth gaps has one end connected
to the isolation region.
37 The ESD protection device as claimed in claim 36, wherein each
of the first and second gates comprises: a conducting layer; a gate
oxide layer under the conducting layer; and a first and second
spacer respectively adjacent to two sides of the conducting layer
and gate oxide layer.
38. The ESD protection device as claimed in claim 37, wherein the
conducting layer is a polysilicon layer while the gate oxide layer,
and the first and second spacer are silicon oxide layers.
39. The ESD protection device as claimed in claim 31 further
comprising a fourth doping region enclosing the isolation
region.
40. The ESD protection device as claimed in claim 39, wherein the
substrate is a P substrate, the first, second and third doping
region are N doping regions, and the fourth doping region is a P
doping region.
41. An ESD protection device comprising: a substrate; an isolation
region on the substrate, enclosing an active region; a first gate
having a first and second end overlapping the isolation region to
stretch over the active region, and coupled to a first node; and a
first and second doping region on the first and a second side of
the first gate, and coupled to a second and the first node
respectively; wherein the isolation region protruding into the
first doping region near the first end of the first gate.
42. The ESD protection device as claimed in claim 41, wherein the
isolation region is a shallow trench isolation.
43. The ESD protection device as claimed in claim 41, wherein the
first node is ground while the second node is a pad.
44. The ESD protection device as claimed in claim 41, wherein the
isolation region protruding into the first doping region near the
second end of the first gate.
45. The ESD protection device as claimed in claim 44 further
comprising: a second gate having a first and second end overlapping
the isolation region to stretch over the active region, and coupled
to the first node, wherein the first doping region is on a first
side of the second gate; and a third doping region on a second side
of the second gate, coupled to the second node; wherein the
isolation region protruding into the first doping region near the
first and second end of the second gate.
46. The ESD protection device as claimed in claim 45, wherein each
of the first and second gate comprises: a conducting layer; a gate
oxide layer under the conducting layer; and a first and second
spacer respectively adjacent to two sides of the conducting layer
and gate oxide layer.
47. The ESD protection device as claimed in claim 46, wherein the
conducting layer is a polysilicon layer while the gate oxide layer,
and the first and second spacer are silicon oxide layers.
48. The ESD protection device as claimed in claim 41 further
comprising a fourth doping region enclosing the isolation
region.
49. The ESD protection device as claimed in claim 48, wherein the
substrate is a P substrate, the first, second and third doping
regions are N doping regions, and the fourth doping region is a P
doping region.
50. An ESD protection device comprising: a substrate; an isolation
region on the substrate, enclosing an active region; a first gate
having a first and second end overlapping the isolation region to
stretch over the active region, and coupled to a first node; and a
first and second doping region on the first and a second side of
the first gate, and coupled to a second and the first node
respectively; wherein the isolation region protruding into the
second doping region near the first end of the first gate.
51. The ESD protection device as claimed in claim 50, wherein the
isolation region is a shallow trench isolation.
52. The ESD protection device as claimed in claim 50, wherein the
first node is ground while the second node is a pad.
53. The ESD protection device as claimed in claim 50, wherein the
isolation region protruding into the second doping region near the
second end of the first gate.
54. The ESD protection device as claimed in claim 53 further
comprising: a second gate having a first and second end overlapping
the isolation region to stretch over the active region, and coupled
to the first node, wherein the first doping region is on a first
side of the second gate; and a third doping region on a second side
of the second gate, coupled to the second node; wherein the
isolation region protruding into the second doping region near the
first and second end of the second gate.
55. The ESD protection device as claimed in claim 54, wherein each
of the first and second gate comprises: a conducting layer; a gate
oxide layer under the conducting layer; and a first and second
spacer respectively adjacent to two sides of the conducting layer
and gate oxide layer.
56. The ESD protection device as claimed in claim 55, wherein the
conducting layer is a polysilicon layer while the gate oxide layer,
and the first and second spacer are silicon oxide layers.
57. The ESD protection device as claimed in claim 50 further
comprising a fourth doping region enclosing the isolation
region.
58. The ESD protection device as claimed in claim 57, wherein the
substrate is a P substrate, the first, second and third doping
regions are N doping regions, and the fourth doping region is a P
doping region.
59. An ESD protection device comprising: a substrate; an isolation
region on the substrate, enclosing an active region; a first gate
having a first and second end overlapping the isolation region to
stretch over the active region, and coupled to a first node; and a
first and second doping region on the first and a second side of
the first gate, and coupled to a second and the first node
respectively; wherein the isolation region has a first portion
under the first end of the first gate protruding into both the
first and second doping region.
60. The ESD protection device as claimed in claim 59, wherein the
isolation region is a shallow trench isolation.
61. The ESD protection device as claimed in claim 59, wherein the
first node is ground while the second node is a pad.
62. The ESD protection device as claimed in claim 59, wherein the
isolation region further has a second portion under the second end
of the first gate protruding into both the first and second doping
regions.
63. The ESD protection device as claimed in claim 62 further
comprising: a second gate having a first and second end overlapping
the isolation region to stretch over the active region, and coupled
to the first node, wherein the first doping region is on a first
side of the second gate; and a third doping region on a second side
of the second gate, coupled to the second node; wherein the
isolation region has a third and fourth portion respectively under
the first and second protruding into both the first and second
doping region.
64. The ESD protection device as claimed in claim 63, wherein each
of the first and second gate comprises: a conducting layer; a gate
oxide layer under the conducting layer; and a first and second
spacer respectively adjacent to two sides of the conducting layer
and gate oxide layer.
65. The ESD protection device as claimed in claim 64, wherein the
conducting layer is a polysilicon layer while the gate oxide layer,
and the first and second spacer are silicon oxide layers.
66. The ESD protection device as claimed in claim 59 further
comprising a fourth doping region enclosing the isolation
region.
67. The ESD protection device as claimed in claim 66, wherein the
substrate is a P substrate, the first, second and third doping
region are N doping regions, and the fourth doping region is a P
doping region.
68. An ESD protection device comprising: a substrate; an isolation
region on the substrate, enclosing an active region; a first gate
having a first and second end overlapping the isolation region to
stretch over the active region, and coupled to a first node; a
first and second doping region on the first and a second side of
the first gate, and coupled to a second and the first node
respectively; and a third doping region disposed under the first
and second doping region and near the first end of the first gate,
having a doping concentration lower than that of the first and
second doping regions.
69. The ESD protection device as claimed in claim 68, wherein the
isolation region is a shallow trench isolation.
70. The ESD protection device as claimed in claim 68, wherein the
first node is ground while the second node is a pad.
71. The ESD protection device as claimed in claim 68 further
comprising a fourth doping region disposed under the first and
second doping regions and near the second end of the first gate,
having a doping concentration lower than that of the first and
second doping regions.
72. The ESD protection device as claimed in claim 71 further
comprising: a second gate having a first and second end overlapping
the isolation region to stretch over the active region, and coupled
to the first node, wherein the first doping region is on a first
side of the second gate; and a fifth doping region on a second side
of the second gate, coupled to the second node; wherein the third
doping region is disposed under the first, second and fifth doping
regions and near the first end of the first and second gate while
the fourth doping region is disposed under the first, second and
fifth doping regions and near the second end of the first and
second gates.
73. The ESD protection device as claimed in claim 72, wherein each
of the first and second gate comprises: a conducting layer; a gate
oxide layer under the conducting layer; and a first and second
spacer respectively adjacent to two sides of the conducting layer
and gate oxide layer.
74. The ESD protection device as claimed in claim 73, wherein the
conducting layer is a polysilicon layer while the gate oxide layer,
and the first and second spacer are silicon oxide layers.
75. The ESD protection device as claimed in claim 68 further
comprising a sixth doping region enclosing the isolation
region.
76. The ESD protection device as claimed in claim 75, wherein the
substrate is a P substrate, the first, second, third, fourth and
fifth doping region are N doping regions, and the sixth doping
region is a P doping region.
77. An ESD protection device comprising: a substrate; an isolation
region on the substrate, enclosing an active region; a first gate
having a first and second end overlapping the isolation region to
stretch over the active region, and coupled to a first node; a
first and second doping region on the first and a second side of
the first gate, and coupled to a second and the first node
respectively; and a first doping region well disposed under the
first doping region and near the first end of the first gate.
78. The ESD protection device as claimed in claim 77, wherein the
isolation region is a shallow trench isolation.
79. The ESD protection device as claimed in claim 77, wherein the
first node is ground while the second node is a pad.
80. The ESD protection device as claimed in claim 77 further
comprising a second doping region well disposed under the first
doping region and near the second end of the first gate.
81. The ESD protection device as claimed in claim 80 further
comprising: a second gate having a first and second end overlapping
the isolation region to stretch over the active region, and coupled
to the first node, wherein the first doping region is on a first
side of the second gate; and a third doping region on a second side
of the second gate, coupled to the second node.
82. The ESD protection device as claimed in claim 81, wherein each
of the first and second gates comprise: a conducting layer; a gate
oxide layer under the conducting layer; and a first and second
spacer respectively adjacent to two sides of the conducting layer
and gate oxide layer.
83. The ESD protection device as claimed in claim 82, wherein the
conducting layer is a polysilicon layer while the gate oxide layer,
and the first and second spacer are silicon oxide layers.
84. The ESD protection device as claimed in claim 77 further
comprising a fourth doping region enclosing the isolation
region.
85. The ESD protection device as claimed in claim 84, wherein the
substrate is a P substrate, the first, second and third doping
regions are N doping regions, and the first and second doping
regions are P doping regions.
86. An ESD protection device comprising: a substrate; an isolation
region on the substrate, enclosing an active region; a first gate
having a first and second end overlapping the isolation region to
stretch over the active region, and coupled to a first node; and a
first and second doping region on the first and a second side of
the first gate, and coupled to a second and the first node
respectively; and wherein the first gate protruding into the first
doping region so that, in the first doping region, a width of a
center portion is larger than those of portions near the first and
second end of the first gate.
87. The ESD protection device as claimed in claim 86, wherein the
isolation region is a shallow trench isolation.
88. The ESD protection device as claimed in claim 86, wherein the
first node is ground while the second node is a pad.
89. The ESD protection device as claimed in claim 86 further
comprising: a second gate having a first and second end overlapping
the isolation region to stretch over the active region, and coupled
to the first node, wherein the first doping region is on a first
side of the second gate; and a third doping region on a second side
of the second gate, coupled to the second node; wherein the second
gate protruding into the first doping region.
90. The ESD protection device as claimed in claim 89, wherein each
of the first and second gate comprises: a conducting layer; a gate
oxide layer under the conducting layer; and a first and second
spacer respectively adjacent to two sides of the conducting layer
and gate oxide layer.
91. The ESD protection device as claimed in claim 90, wherein the
conducting layer is a polysilicon layer while the gate oxide layer,
and the first and second spacer are silicon oxide layers.
92. The ESD protection device as claimed in claim 86 further
comprising a fourth doping region enclosing the isolation
region.
93. The ESD protection device as claimed in claim 92, wherein the
substrate is a P substrate, the first, second and third doping
region are N doping regions, and the fourth doping region is a P
doping region.
94. A device without current crowding effect at the finger's ends,
comprising: a substrate; an isolation region on the substrate,
enclosing an active region; a first gate having a first and second
end overlapping the isolation region to stretch over the active
region, and coupled to a first node; a second gate disposed on a
first side of the first gate and near the first end of the first
gate; and a first and second doping region on the first and a
second side of the first gate, and coupled to a second and the
first node respectively, wherein the first doping region has a
first gap under the second gate.
95. The device as claimed in claim 94, wherein the isolation region
is a shallow trench isolation.
96. The ESD protection device as claimed in claim 94, wherein the
first node is ground while the second node is a pad.
97. The ESD protection device as claimed in claim 94 further
comprising: a third gate disposed on the first side of the first
gate and near the second end of the first gate, wherein the first
doping region has a second gap under the third gate.
98. The ESD protection device as claimed in claim 97 further
comprising: a fourth gate having a first and second end overlapping
the isolation region to stretch over the active region, and coupled
to the first node, wherein the first doping region is between the
first and fourth gate; a fifth and sixth gate both disposed on a
first side of the fourth gate, and respectively near a first and
second end of the fourth gate, wherein the first doping region has
a third and fourth gap respectively under the fifth and sixth gate;
and a third doping region on a second side of the fourth gate and
coupled to the second node.
99. The ESD protection device as claimed in claim 98, wherein each
of the second, third, fifth and sixth gate has one end overlapping
the isolation region.
100. The ESD protection device as claimed in claim 98, wherein each
of the first, second, third, fourth, fifth and sixth gate
comprises: a conducting layer; a gate oxide layer under the
conducting layer; and a first and second spacer respectively
adjacent to two sides of the conducting layer and gate oxide
layer.
101. The ESD protection device as claimed in claim 100, wherein the
conducting layer is a polysilicon layer while the gate oxide layer,
and the first and second spacer are silicon oxide layers.
102. The ESD protection device as claimed in claim 94 further
comprising a fourth doping region enclosing the isolation
region.
103. The ESD protection device as claimed in claim 102, wherein the
substrate is a P substrate, the first, second and third doping
region are N doping regions, and the fourth doping region is a P
doping region.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to an ESD protection device
and particularly to an ESD protection device eliminating ESD
current crowding events, so that a higher ESD level may be achieved
under MM ESD testing.
[0003] 2. Description of the Prior Art
[0004] ESD damage has become one of the main reliability concerns
facing IC (integrated circuit) products. Particularly, when scaled
down to the deep sub-micron regime and the thinner gate oxide, the
MOS become more vulnerable to ESD stress. For general industrial
specifications, the input and output pins of IC products must
sustain HBM (Human-Body-Model) ESD stress of over 2000V and MM
(Machine-Model) ESD stress of over 200V. Therefore, ESD protection
circuits must be placed around the input and output (I/O) pads of
the IC to protect IC against the ESD stress.
[0005] ESD protection devices are frequently drawn with large
device dimensions and realized by finger-type layout to save total
layout area. The layout top views and cross-sectional views of the
prior arts to improve the ESD level of ESD protection devices by
layout method are shown in FIGS. 1A and 1B. It is formed on a P
silicon substrate 11 and includes a STI (shallow trench isolation)
13 enclosing an active region 12, a P guard ring 14 enclosing the
STI 13, two gates 15, each composed of polysilicon layer 151, gate
oxide 152 and spacers 153, and N drain and source region 161 and
162 placed in between and on the outer sides of the gates 15. The
gates, source region, and body are typically connected to the
ground while the drain region is connected to the input/output pad.
The fundamental theorem of ESD protection design is based on the
mechanisms of the MOS and the parasitic lateral n-p-n bipolar (BJT)
under high current, and high field conduction. FIGS. 2A and 2B are
sectional views and an equivalent circuit of a NMOS transistor,
with the drain 22 as the collector, substrate 21 as the body and
source 23 as the emitter. During ESD stress, high field at the
drain causes the N+ to P substrate junction to enter an avalanche
breakdown condition, generating excessive electron-hole pairs. The
current of the electron-hole pairs forward biases the
substrate-source (PN junction), and the voltage drop across the
substrate resistances increase the BE junction voltage of the
parasitic BJT which is triggered to generate the snapback region in
its I-V curves, as shown in FIG. 3. Thus, the parasitic BJT turns
on to and bypass the ESD current.
[0006] FIGS. 4A and 4B are top and sectional views of another
conventional ESD protection device, a gate grounded NMOS. With
comparison to the ESD protection device in FIGS. 1A and 1B, it is
noted that the bulk substrate resistance of the BB' region is much
larger than that of the AA' region. This allows the parasitic BJT
of the BB' region to turn on faster than that of the AA' region
with higher collector current to bypass the ESD current and spread
through the BB' region. The parasitic BJT of the BB' region can
provide larger effective area than the AA' region to discharge the
ESD current, therefore it may have a high HBM ESD robustness.
However, under MM ESD zapping, the drain node conductivity with
higher peak currents of 3.about.4 Amps (for 200V MM ESD stress)
often cause ESD damage at the corner or finger's end regions. The
cause of damage is MM ESD current 3 or 4 times higher through an
extremely small resistance than the HBM ESD current. Although the
resistance of the AA' region is smaller than that of the BB'
region, the breakdown current (due to ESD zapping at the drain) of
the drain to substrate junction at the AA' region is still high
enough to forward bias and to turn on the parasitic BJT at the AA'
region, before turning on the parasitic BJT at the BB' region.
Thus, an excess of current crowds around the AA' region and causes
device failure at this region. Such damage is commonly shown in
photographic training materials used in ESD protection design
training courses.
SUMMARY OF THE INVENTION
[0007] The object of the present invention is to provide an ESD
protection device eliminating ESD current crowding events to
achieve a higher ESD level under MM ESD testing.
[0008] The present invention provides a first ESD protection device
comprising a substrate, an isolation region on the substrate,
enclosing an active region, a first gate having a first and second
end overlapping the isolation region to stretch over the active
region, and coupled to a first node, a second gate disposed on a
first side of the first gate and near the first end of the first
gate, and a first and second doping region on the first and a
second side of the first gate, and coupled to a second and the
first node respectively, wherein the first doping region has a
first gap under the second gate.
[0009] The present invention provides a second ESD protection
device comprising a substrate, an isolation region on the
substrate, enclosing an active region, a first gate having a first
and second end overlapping the isolation region to stretch over the
active region, and coupled to a first node, a second gate disposed
on a second side of the first gate and near the first end of the
first gate, and a first and second doping region on a first and the
second side of the first gate, and coupled to a second and the
first node respectively, wherein the second doping region has a
first gap under the second gate.
[0010] The present invention provides a third ESD protection device
comprising a substrate, an isolation region on the substrate,
enclosing an active region, a first gate having a first and second
end overlapping the isolation region to stretch over the active
region, and coupled to a first node, and a first and second doping
region on the first and a second side of the first gate, and
coupled to a second and the first node respectively, wherein the
first doping region has a first gap near the first end of the first
gate.
[0011] The present invention provides a fourth ESD protection
device comprising a substrate, an isolation region on the
substrate, enclosing an active region, a first gate having a first
and second end overlapping the isolation region to stretch over the
active region, and coupled to a first node, and a first and second
doping region on the first and a second side of the first gate, and
coupled to a second and the first node respectively, wherein the
second doping region has a first gap near the first end of the
first gate.
[0012] The present invention provides a fifth ESD protection device
comprising a substrate, an isolation region on the substrate,
enclosing an active region, a first gate having a first and second
end overlapping the isolation region to stretch over the active
region, and coupled to a first node, and a first and second doping
region on the first and a second side of the first gate, and
coupled to a second and the first node respectively, wherein the
isolation region protruding into the first doping region near the
first end of the first gate.
[0013] The present invention provides a sixth ESD protection device
comprising a substrate, an isolation region on the substrate,
enclosing an active region, a first gate having a first and second
end overlapping the isolation region to stretch over the active
region, and coupled to a first node, and a first and second doping
region on the first and a second side of the first gate, and
coupled to a second and the first node respectively, wherein the
isolation region protruding into the second doping region near the
first end of the first gate.
[0014] The present invention provides a seventh ESD protection
device comprising a substrate, an isolation region on the
substrate, enclosing an active region, a first gate having a first
and second end overlapping the isolation region to stretch over the
active region, and coupled to a first node, and a first and second
doping region on the first and a second side of the first gate, and
coupled to a second and the first node respectively, wherein the
isolation region has a first portion under the first end of the
first gate protruding into both the first and second doping
region.
[0015] The present invention provides an eighth ESD protection
device comprising a substrate, an isolation region on the
substrate, enclosing an active region, a first gate having a first
and second end overlapping the isolation region to stretch over the
active region, and coupled to a first node, a first and second
doping region on the first and a second side of the first gate, and
coupled to a second and the first node respectively, and a third
doping region disposed under the first and second doping region and
near the first end of the first gate, having a doping concentration
lower than that of the first and second doping region.
[0016] The present invention provides a ninth ESD protection device
comprising a substrate, an isolation region on the substrate,
enclosing an active region, a first gate having a first and second
end overlapping the isolation region to stretch over the active
region, and coupled to a first node, a first and second doping
region on the first and a second side of the first gate, and
coupled to a second and the first node respectively, and a first
well disposed under the first doping region and near the first end
of the first gate.
[0017] The present invention provides a tenth ESD protection device
comprising a substrate, an isolation region on the substrate,
enclosing an active region, a first gate having a first and second
end overlapping the isolation region to stretch over the active
region, and coupled to a first node, and a first and second doping
region on the first and a second side of the first gate, and
coupled to a second and the first node respectively, and wherein
the first gate protruding into the first doping region so that, in
the first doping region, a width of a center portion is larger than
those of portions near the first and second end of the first
gate.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The present invention will become more fully understood from
the detailed description given hereinbelow and the accompanying
drawings, given by way of illustration only and thus not intended
to be limitative of the present invention.
[0019] FIGS. 1A and 1B are top and sectional views of a
conventional ESD protection device.
[0020] FIGS. 2A and 2B are sectional views and an equivalent
circuit of a NMOS transistor.
[0021] FIG. 3 is a diagram showing a relation between the current
and breakdown voltage of a NMOS transistor.
[0022] FIGS. 4A and 4B are top and sectional views of another
conventional ESD protection device.
[0023] FIGS. 5A and 5B are top and sectional views along a line AA'
of an ESD protection device according to a first embodiment of the
invention.
[0024] FIGS. 6A and 6B are top and sectional views along a line AA'
of an ESD protection device according to a second embodiment of the
invention.
[0025] FIGS. 7A and 7B are top and sectional views along a line AA'
of an ESD protection device according to a third embodiment of the
invention.
[0026] FIGS. 8A and 8B are top and sectional views along a line AA'
of an ESD protection device according to a fourth embodiment of the
invention.
[0027] FIGS. 9A and 9B are top and sectional views along a line AA'
of an ESD protection device according to a fifth embodiment of the
invention.
[0028] FIGS. 10A and 10B are top and sectional views along a line
AA' of an ESD protection device according to a sixth embodiment of
the invention.
[0029] FIGS. 11A and 11B are top and sectional views along a line
AA' of an ESD protection device according to a seventh embodiment
of the invention.
[0030] FIGS. 12A and 12B are top and sectional views along a line
AA' of an ESD protection device according to an eighth embodiment
of the invention.
[0031] FIGS. 13A and 13B are top and sectional views along a line
AA' of an ESD protection device according to a ninth embodiment of
the invention.
[0032] FIGS. 14A and 14B are top and sectional views along a line
AA' of an ESD protection device according to a tenth embodiment of
the invention.
DETAILED DESCRIPTION OF THE INVENTION
[0033] First Embodiment
[0034] FIGS. 5A and 5B are top and sectional views along a line AA'
of an ESD protection device according to a first embodiment of the
invention. It includes a P silicon substrate 51, STI (shallow
trench isolation) 52, a P guard ring 50 enclosing the STI 52, gates
531 and 532, dummy gates 541.about.544, and N drain and source
region 551 and 552. The STI 52 is on the substrate 51 and encloses
an active region 56. The gates 531 and 532 have two ends
overlapping the STI 52 to stretch over the active region 56, and
are coupled to ground or a pre-driver. The dummy gates
541.about.544 are disposed on a common side and near each end of
the gates 531 and 532. Each of the dummy gates 541.about.544 has
one end overlapping the STI 52. The drain and source region 551 and
552 are disposed in between and on outer sides of the gates 531 and
532, and coupled to a pad and ground, respectively. The drain
region 551 has gaps 571.about.574 under the dummy gates
541.about.544. Each of the gates 531 and 532, and dummy gates
541.about.544 includes a conducting layer 581 made of polysilicon,
an oxide layer 582 made of silicon oxide under the conducting layer
581 and spacers 583 made of silicon oxide adjacent to the
conducting layer 581 and oxide layer 582.
[0035] In the first embodiment, the base width of the parasitic BJT
is directly related to the gate length of the NMOS and the longer
channel transistor will have a lower turned-on efficiency because
of lower bipolar efficiency. The dummy gates 541.about.544 at the
AA' region are used to increase the base width of the parasitic BJT
at the AA' region and decrease its turned-on efficiency. While the
base width of the parasitic BJT at the BB' region is shorter than
it is at the AA' region, the turned-on efficiency of the BB' region
can be successfully balanced. Therefore, the parasitic BJT at the
BB' region will turn on sooner than it will at the AA' region,
providing a larger bypass ESD current area than the AA' region and
increasing the high MM ESD level. On the other hand, the HBM ESD
level will not decrease while dummy gates 541.about.544 are
inserted into the active region 56 under HBM ESD zapping because
the bypass ESD current area is almost the same as the devices of
the prior arts.
[0036] Second Embodiment
[0037] FIGS. 6A and 6B are top and sectional views along a line AA'
of an ESD protection device according to a second embodiment of the
invention. With comparison to the ESD protection device shown in
FIGS. 5A and 5B, it is noted that the dummy gates 541.about.544 are
disposed on the source region 552 so that the gaps 571.about.574
are located in the source region 552 in the ESD protection device
of FIGS. 6A and 6B. The ESD protection devices in FIGS. 5A and 5B,
and 6A and 6B have equal ESD performance.
[0038] Third Embodiment
[0039] FIGS. 7A and 7B are top and sectional views along a line AA'
of an ESD protection device according to a third embodiment of the
invention. It includes a P silicon substrate 71, STI (shallow
trench isolation) 72, a P guard ring 70 enclosing the STI 72, gates
731 and 732, and N drain and source region 751 and 752. The STI 72
is on the substrate 71 and encloses an active region 76. The gates
731 and 732 have two ends overlapping the STI 72 to stretch over
the active region 76, and are coupled to ground or a pre-driver.
The drain and source region 751 and 752 are disposed in between and
on outer sides of the gates 731 and 732, and coupled to a pad and
ground, respectively. The drain region 751 has gaps 741.about.744
near each end of the gates 731 and 732. The gaps 741.about.744 are
formed by an implantation step compatible with a CMOS process,
during which a mask blocks the gaps 741.about.744 from N+ ions.
Each of the gates 731 and 732 includes a conducting layer 781 made
of polysilicon, an oxide layer 782 made of silicon oxide under the
conducting layer 781 and spacers 783 made of silicon oxide adjacent
to the conducting layer 781 and oxide layer 782.
[0040] The layout method of the third embodiment, increases the AA'
region resistance and decreases parasitic BJT turning on
efficiency, making it possible for ESD current to go through the
BB' region under MM ESD zapping. Thus, the MM ESD current bypasses
bigger areas and has a higher MM ESD level than the device
structures of prior arts. On the other hand, the HBM ESD level will
not decrease as it will without N+ diffusion between the gates and
drain contact at the AA' region. Moreover, the proposed layout
method can also be applied to the PMOS to improve its ESD
robustness.
[0041] Fourth Embodiment
[0042] FIGS. 8A and 8B are top and sectional views along a line AA'
of an ESD protection device according to a fourth embodiment of the
invention. With comparison to the ESD protection device shown in
FIGS. 7A and 7B, it is noted that the gaps 741.about.744 are
located in the source region 752. The ESD protection devices in
FIGS. 7A and 7B, and 8A and 8B have equal ESD performance.
[0043] Fifth Embodiment
[0044] FIGS. 9A and 9B are top and sectional views along a line AA'
of an ESD protection device according to a fifth embodiment of the
invention. It includes a P silicon substrate 91, STI (shallow
trench isolation) 92, a P guard ring 90 enclosing the STI 92, gates
931 and 932, and N drain and source region 951 and 952. The STI 92
is on the substrate 91 and encloses an active region 96. The gates
931 and 932 have two ends overlapping the STI 92 to stretch over
the active region 96, and are coupled to ground or a pre-driver.
The drain and source region 951 and 952 are disposed in between and
on outer sides of the gates 931 and 932, and coupled to a pad and
ground, respectively. The STI 941.about.944 protrudes into the
drain region 951 near each end of the gates 931 and 932. Each of
the gates 931 and 932 includes a conducting layer 981 made of
polysilicon, an oxide layer 982 made of silicon oxide under the
conducting layer 981 and spacers 983 made of silicon oxide adjacent
to the conducting layer 981 and oxide layer 982.
[0045] The layout method of the fifth embodiment, increases the AA'
region resistances and decreases parasitic BJT turning on
efficiency, making it possible for ESD current to go through the
BB' region under MM ESD zapping. Thus, the MM ESD current bypasses
bigger areas and has a higher MM ESD level than the device
structures of prior arts. Conversely, the HBM ESD level will not
decrease as STI is inserted between the gate and drain contact or
below the gate at the AA' region. Moreover, the proposed layout
method can also be applied to the PMOS to improve ESD
robustness.
[0046] Sixth Embodiment
[0047] FIGS. 10A and 10B are top and sectional views along a line
AA' of an ESD protection device according to a sixth embodiment of
the invention. With comparison to the ESD protection device shown
in FIGS. 9A and 9B, it is noted that the STI 941.about.944
protrudes into the source region 952. The ESD protection devices in
FIGS. 9A and 9B, and 10A and 10B have equal ESD performance.
[0048] Seventh Embodiment
[0049] FIGS. 11A and 11B are top and sectional views along a line
AA' of an ESD protection device according to a seventh embodiment
of the invention. For the sake of clarity, the same elements in
FIGS. 11A and 11B, and 9A and 9B refer to the same symbols. The ESD
protection device includes a P silicon substrate 91, STI (shallow
trench isolation) 92, a P guard ring 90 enclosing the STI 92, gates
931 and 932, and N drain and source region 951 and 952. The STI 92
is on the substrate 91 and encloses an active region 96. The gates
931 and 932 have two ends overlapping the STI 92 to stretch over
the active region 96, and are coupled to ground or a pre-driver.
The drain and source region 951 and 952 are disposed in between and
on outer sides of the gates 931 and 932, and coupled to a pad and
ground, respectively. The STI 941.about.944 has portions under the
gates 931 and 932 and near each end of the gates 931 and 932
protruding into both the drain and source region 951 and 952. Each
of the gates 931 and 932 includes a conducting layer 981 made of
polysilicon, an oxide layer 982 made of silicon oxide under the
conducting layer 981 and spacers 983 made of silicon oxide adjacent
to the conducting layer 981 and oxide layer 982.
[0050] The layout method of the fifth embodiment, increases the AA'
region resistances and decreases parasitic BJT turning on
efficiency, making it possible for ESD current to go through the
BB' region under MM ESD zapping. Thus, the MM ESD current bypasses
bigger areas and has a higher MM ESD level than the device
structures of prior arts. Conversely, the HBM ESD level will not
decrease as STI is inserted between the gate and drain contact or
below the gate at the AA' region.
[0051] Eighth Embodiment
[0052] FIGS. 12A and 12B are top and sectional views along a line
AA' of an ESD protection device according to an eighth embodiment
of the invention. For the sake of clarity, the same elements in
FIGS. 12A and 12B, and 5A and 5B refer to the same symbols. The ESD
protection device includes a P silicon substrate 51, STI 52, a P
guard ring 50 enclosing the STI 52, gates 531 and 532, N drain and
source region 551 and 552, and ESD implantation regions 591 and
592. The STI 52 is on the substrate 51 and encloses an active
region 56. The gates 531 and 532 have two ends overlapping the STI
52 to stretch over the active region 56, and are coupled to ground
or a pre-driver. The drain and source region 551 and 552 are
disposed in between and on outer sides of the gates 531 and 532,
and coupled to a pad and ground, respectively. The ESD implantation
regions 591 and 592 are N lightly doped regions disposed under the
drain and source region 551 and 552, and near each end of the gates
531 and 532. The doping concentrations of the ESD implantation
regions 591 and 592 are lower than those of the drain and source
region 551 and 552. Each of the gates 531 and 532 includes a
conducting layer 581 made of polysilicon, an oxide layer 582 made
of silicon oxide under the conducting layer 581 and spacers 583
made of silicon oxide adjacent to the conducting layer 581 and
oxide layer 582.
[0053] In the eighth embodiment, the junction covered by the
proposed ESD implantation has an increased junction breakdown
voltage, because it has a lighter doping concentration across the
p-n junction. The BB' region without covering the ESD implantation,
however, has the original junction breakdown voltage, which is
lower than the junction breakdown of the ESD implantation region.
During the ESD stress, the junction the BB' region with the lowest
junction breakdown voltage will be broken first to discharge the
ESD current. As previously mentioned, the AA' region provides a
larger bypass area and path for ESD current and has a high MM ESD
level. On the other hand, the HBM ESD level will not decrease as
the ESD implanted between the gate and drain contact or below the
gate at the AA' region. This can also be applied to the PMOS to
improve its ESD robustness.
[0054] Ninth Embodiment
[0055] FIGS. 13A and 13B are top and sectional views along a line
AA' of an ESD protection device according to an eighth embodiment
of the invention. For the sake of clarity, the same elements in
FIGS. 13A and 13B, and 5A and 5B refer to the same symbols. The ESD
protection device includes a P silicon substrate 51, STI 52, a P
guard ring 50 enclosing the STI 52, gates 531 and 532, N drain and
source region 551 and 552, and N wells 593 and 594. The STI 52 is
on the substrate 51 and encloses an active region 56. The gates 531
and 532 have two ends overlapping the STI 52 to stretch over the
active region 56, and are coupled to ground or a pre-driver. The
drain and source region 551 and 552 are disposed in between and on
outer sides of the gates 531 and 532, and coupled to a pad and
ground, respectively. The N wells 593 and 594 are disposed under
the drain region 551, and near each end of the gates 531 and 532.
Each of the gates 531 and 532 includes a conducting layer 581 made
of polysilicon, an oxide layer 582 made of silicon oxide under the
conducting layer 581 and spacers 583 made of silicon oxide adjacent
to the conducting layer 581 and oxide layer 582.
[0056] In the ninth embodiment, the MOSFET at the AA' region has a
lighter doping concentration (N well) than that of the original
(N+) drain junction. Therefore, the junction covered by the
proposed N well has an increased junction breakdown voltage,
because it has a lighter doping concentration across the p-n
junction. However, the BB' region without inserting N well has the
original junction breakdown voltage, which is lower than the
junction breakdown of the AA' region with N well inserted. During
the ESD stress, the junction the BB' region with the lowest
junction breakdown voltage will be broken first to discharge the
ESD current. As previously mentioned, the AA' region provides a
larger bypass area and path for ESD current and has a higher MM ESD
level.
[0057] Tenth Embodiment
[0058] FIGS. 14A and 14B are top and sectional views along a line
AA' of an ESD protection device according to an eighth embodiment
of the invention. For the sake of clarity, the same elements in
FIGS. 14A and 14B, and 5A and 5B refer to the same symbols. The ESD
protection device includes a P silicon substrate 51, STI 52, a P
guard ring 50 enclosing the STI 52, gates 531 and 532, and N drain
and source region 551 and 552. The STI 52 is on the substrate 51
and encloses an active region 56. The gates 531 and 532 have two
ends overlapping the STI 52 to stretch over the active region 56,
and are coupled to ground or a pre-driver. The drain and source
region 551 and 552 are disposed in between and on outer sides of
the gates 531 and 532, and coupled to a pad and ground,
respectively. The gates 531 and 532 are bent at an angle so that
their center portions protrude into the drain region 551. Thus, the
widths of the drain region 551 near the center portions of the
gates 531 and 532 are smaller than those near each end of the gates
531 and 532. Each of the gates 531 and 532 includes a conducting
layer 581 made of polysilicon, an oxide layer 582 made of silicon
oxide under the conducting layer 581 and spacers 583 made of
silicon oxide adjacent to the conducting layer 581 and oxide layer
582.
[0059] In the tenth embodiment, at the AA' region, the drain
contact to the poly edge space (DGS) is larger than the space at
the BB' region, therefore the equivalent base spacing of the
parasitic BJT device at the AA' region can be increased. With a
wider base spacing, the BJT will have a lower turn-on speed and
lower current gain. In this structure, the turn-on efficiency of
the parasitic BJT at the AA' region decreases. ESD current will be
discharged through the parasitic BJT at the BB' region under MM ESD
zapping. Thus, the MM ESD current effectively bypasses bigger areas
and has a higher MM ESD level than the device structures of the
prior arts. Conversely, the HBM ESD level will not decrease and can
also be applied to the PMOS to improve its ESD robustness.
[0060] In all the previously described embodiments, the layouts are
also suitable for PMOS although NMOS is used as an example. They
are also suitable for stacked NMOS or PMOS in mixed voltage I/O
circuits.
[0061] In conclusion, novel ESD protection device structures are
proposed in this invention for application under MM ESD stress in
sub-quarter-micron CMOS technology. The ESD discharging current
path in the NMOS or PMOS device structure is changed by the
proposed new structures, therefore the MM ESD level of the NMOS and
PMOS can be significantly improved. In this invention, 6 kinds of
new structures protect the lateral BJT at the AA' region from
current crowding and to balance the turned on efficiency of the
lateral BJT at the BB' region. The MM ESD current bypasses through
the lateral BJT at the BB' region instead of the AA' region, and
has a larger bypass area than the prior structures. The current
crowding problem can be solved successfully, and have a higher MM
ESD robustness. Moreover, these novel devices will not degrade the
HBM ESD level and are widely used in ESD protection circuits.
[0062] The foregoing description of the preferred embodiments of
this invention has been presented for purposes of illustration and
description. Obvious modifications or variations are possible in
light of the above teaching. The embodiments were chosen and
described to provide the best illustration of the principles of
this invention and its practical application to thereby enable
those skilled in the art to utilize the invention in various
embodiments and with various modifications as are suited to the
particular use contemplated. All such modifications and variations
are within the scope of the present invention as determined by the
appended claims when interpreted in accordance with the breadth to
which they are fairly, legally, and equitably entitled.
* * * * *