U.S. patent application number 09/772559 was filed with the patent office on 2004-01-29 for high peak current density resonant tunneling diode.
This patent application is currently assigned to Wisconsin Alumni Research Foundation. Invention is credited to Botez, Dan, Mawst, Luke J., Mirabedini, Ali R..
Application Number | 20040016921 09/772559 |
Document ID | / |
Family ID | 26693083 |
Filed Date | 2004-01-29 |
United States Patent
Application |
20040016921 |
Kind Code |
A1 |
Botez, Dan ; et al. |
January 29, 2004 |
High peak current density resonant tunneling diode
Abstract
A resonant tunneling diode is produced in a gallium arsenide
material system formed with barrier layers of AlGaAs with a quantum
well layer of low band-gap material between them. The material of
the well is selected to adjust the second energy level to the edge
of the conduction band in GaAs, with a preferred quantum well layer
formed of InGaAs. The resonant tunneling diode structure is grown
by a metal organic chemical vapor deposition process on the surface
of the nominally exact (100) GaAs substrate. Layers of doped GaAs
may be formed on either side of the multilayer resonant tunneling
diode structure, and spacer layers of GaAs may also be provided on
either side of the barrier layers to reduce the intrinsic
capacitance of the structure.
Inventors: |
Botez, Dan; (Madison,
WI) ; Mawst, Luke J.; (Sun Prairie, WI) ;
Mirabedini, Ali R.; (Madison, WI) |
Correspondence
Address: |
Harry C. Engstrom
Foley & Lardner
150 E. Gilman Street
P. O. Box 1497
Madison
WI
53701-1497
US
|
Assignee: |
Wisconsin Alumni Research
Foundation
|
Family ID: |
26693083 |
Appl. No.: |
09/772559 |
Filed: |
January 30, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09772559 |
Jan 30, 2001 |
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08879161 |
Jun 19, 1997 |
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6229153 |
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60020141 |
Jun 21, 1996 |
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Current U.S.
Class: |
257/25 ;
257/E29.34 |
Current CPC
Class: |
H01L 29/882 20130101;
B82Y 10/00 20130101 |
Class at
Publication: |
257/25 |
International
Class: |
H01L 029/06 |
Claims
What is claimed is:
1. A resonant tunneling diode comprising: (a) a substrate of (100)
GaAs; (b) a multilayer resonant tunneling diode structure grown on
the (100) GaAs substrate, the resonant tunneling diode structure
comprising a quantum well layer of low band-gap material between
barrier layers of AlGaAs, and wherein the material of the quantum
well layer is selected such that the second energy level of the
quantum well layer is at or slightly above the conduction band edge
in GaAs, the quantum well layer grown to be a strained layer with
smooth interfaces with the barrier layers.
2. The resonant tunneling diode device of claim 1 wherein the
quantum well layer comprises InGaAs.
3. The resonant tunneling diode device of claim 2 wherein the
barrier layers are composed of Al.sub.0.8Ga.sub.0.2As, and the
quantum well layer is formed of In.sub.0.3Ga.sub.0.7As.
4. The resonant tunneling diode device of claim 3 wherein the
barrier layers are about 14 .ANG. thick and the quantum well layer
is about 57 .ANG. thick.
5. The resonant tunneling diode device of claim 2 including a
spacer layer of intrinsic GaAs adjacent to each barrier layer.
6. The resonant tunneling diode device of claim 5 further including
a layer of n-doped GaAs adjacent to each GaAs intrinsic layer.
7. The resonant tunneling diode device of claim 6 wherein the
substrate is doped GaAs and the resonant tunneling diode structure
is isolated on a mesa with a doped GaAs layer at the top of the
mesa and further including an insulating layer over the exposed
surfaces of the substrate and the mesa and a contact formed through
the insulating layer to the doped GaAs layer, and a contact on the
doped GaAs substrate opposite the mesa.
8. The resonant tunneling diode device of claim 1 wherein the
resonant tunneling diode structure is grown on a nominally exact
(100) .+-.0.5.degree. GaAs substrate.
9. The resonant tunneling diode device of claim 1 wherein the
resonant tunneling diode structure is grown on a nominally exact
(100) .+-.0.1.degree. GaAs substrate.
10. The resonant tunneling diode device of claim 1 wherein the
resonant tunneling diode structure is grown on the GaAs substrate
by metal organic chemical vapor deposition.
11. A resonant tunneling diode comprising: (a) a substrate of (100)
GaAs; (b) a multilayer resonant tunneling diode structure grown on
the (100) GaAs substrate, the resonant tunneling diode structure
comprising a quantum well layer of InGaAs between barrier layers of
AlGaAs, a spacer layer of intrinsic GaAs adjacent to each barrier
layer, and a layer of n-doped GaAs adjacent to each GaAs intrinsic
layer, wherein the second energy level of the quantum well layer is
at or slightly above the conduction band edge in GaAs, the quantum
well layer grown by metal organic chemical vapor deposition to be a
strained layer with smooth interfaces with the barrier layers.
12. The resonant tunneling diode device of claim 11 wherein the
barrier layers are composed of Al.sub.0.8Ga.sub.0.2As, and the
quantum well layer is formed of In.sub.0.3Ga.sub.0.7As.
13. The resonant tunneling diode device of claim 12 wherein the
barrier layers are about 14 .ANG. thick and the quantum well layer
is about 57 .ANG. thick.
14. The resonant tunneling diode device of claim 11 wherein the
substrate is doped GaAs and the resonant tunneling diode structure
is isolated on a mesa with a doped GaAs layer at the top of the
mesa and further including an insulating layer over the exposed
surfaces of the substrate and the mesa and a contact formed through
the insulating layer to the doped GaAs layer and a contact on the
doped GaAs substrate opposite the mesa.
15. The resonant tunneling diode device of claim 11 wherein the
resonant tunneling diode structure is grown on a nominally exact
(100) .+-.0.5.degree. GaAs substrate.
16. The resonant tunneling diode device of claim 11 wherein the
resonant tunneling diode structure is grown on a nominally exact
(100) .+-.0.1.degree. GaAs doped substrate.
17. A method of making a resonant tunneling diode comprising the
steps of: (a) providing a substrate of nominally exact (100) GaAs;
(b) growing on the substrate by metal organic chemical vapor
deposition successive layers comprising at least a barrier layer of
AlGaAs, a strained quantum well layer of low band-gap material, and
a barrier layer of AlGaAs, the quantum well layer grown with smooth
interfaces with the barrier layers with the second energy level of
the quantum well layer at or slightly above the conduction band
edge in GaAs.
18. The method of claim 17 wherein the quantum well layer material
is InGaAs.
19. The method of claim 15 wherein the barrier layers are formed to
be composed of Al.sub.0.8Ga.sub.0.2As, and the quantum well layer
is formed to be composed of In.sub.0.3Ga.sub.0.7As.
20. The method of claim 17 further including growing by metal
organic chemical vapor deposition a spacer layer of intrinsic GaAs
adjacent to each barrier layer.
21. The method of claim 20 further including growing by metal
organic chemical vapor deposition a layer of n-doped GaAs adjacent
to each GaAs intrinsic layer.
22. The method of claim 21 wherein the substate is doped GaAs and
including isolating the resonant tunneling diode structure on a
mesa with a doped GaAs layer at the top of the mesa and further
including forming an insulating layer over the exposed surfaces of
the substrate and the mesa and forming a contact through the
insulating layer to the doped GaAs layer and forming a contact on
the doped GaAs substrate opposite the mesa.
23. The method of claim 17 wherein the substrate is nominally exact
(100) .+-.0.5.degree. GaAs.
24. The method of claim 17 wherein the substrate is nominally exact
(100) .+-.0.1.degree. GaAs.
Description
[0001] This application claims the benefit of U.S. provisional
application No. 60/020,141, filed Jun. 21, 1996.
FIELD OF THE INVENTION
[0002] This invention pertains generally to the field of
semiconductor devices and more particularly to resonant tunneling
diodes.
BACKGROUND OF THE INVENTION
[0003] Resonant tunneling diodes comprise semiconductor structures
having two large band-gap barrier layers with a single low band-gap
quantum well between them. Collector 30 and emitter 31 contact
regions are provided in the semiconductor structure to provide
collection and supply of electrons as illustrated in the simplified
band diagram of FIG. 1. The thicknesses of barrier layers 34 and 35
and the thickness of the quantum well 36 between them, and the
composition of these structures, are chosen so that quantum effects
create a single resonant energy level 37 slightly above the emitter
conduction band edge 38. As the emitter 31 is negatively biased,
the two bands will come into alignment at a peak voltage V.sub.p,
as illustrated in FIG. 2, and electrons will tunnel through to the
collector region 30 where they are collected. As the negative bias
is increased still further, the emitter conduction band 38 rises
above the resonant energy level 37, as illustrated in FIG. 3,
drastically reducing the tunneling current. The result is a
negative resistance region that creates the utility of the resonant
tunneling diode (RTD). As the emitter bias is increased still
further, current will rise again as electrons are emitted over the
barrier. FIG. 4 shows a typical current-voltage relationship curve
40 for a typical RTD.
[0004] The high speed voltage transition occurs when the RTD is
switched from the stable point "a" in FIG. 4 to the stable point
"b". The voltage swing is maximized by making the voltage V.sub.p
low and the voltage V.sub.v high. Switching speed is maximized by
making the peak current I.sub.p as large as possible for a given
conduction area. The valley current at the voltage V.sub.v is of
great significance for high-speed applications, and should be as
low as possible to maximize the current available to charge the
load capacitance thus reducing the switching time.
[0005] It is desirable that RTDs be highly reliable and stable over
time and with temperature changes, and have typical performance
characteristics that include voltage swings of one to two volts,
peak current densities of 100 to 200 kA/cm.sup.2, peak currents of
10 to 20 mA, peak voltages of 1 volt, peak to valley current ratios
of at least 3, and a rise time of less than 2 picoseconds. Such
characteristics have been achieved previously in devices made of
pseudomorphic AlAs/InAs/AlAs quantum wells fed by lattice-matched
InGaAs contact layers, and grown on InP by molecular beam epitaxy.
However, the InP material system is not well suited for practical
applications, and the technology is immature. GaAs would be ideal,
but GaAs/AlAs RTDs cannot reach the performances of InP-based
devices.
SUMMARY OF THE INVENTION
[0006] The resonant tunneling diode (RTD) of the present invention
combines all of the desirable characteristics for such a diode in a
single device which can be produced in a gallium arsenide material
system using the processing techniques compatible with large scale
production, particularly metal organic chemical vapor deposition
(MOCVD). The device is capable of peak current densities in excess
of 300 kA/cm.sup.2 at relatively low peak voltages in the range of
1 volt. Switching times in the range of 1 picosecond can be
obtained.
[0007] The multilayer RTD structure preferably is formed of barrier
layers of AlGaAs with a quantum well layer formed of low band-gap
material between them. The material of the well is selected to
adjust the second energy level to, i.e., at or slightly above, the
edge of the conduction band in GaAs. A preferred material for the
quantum well layer is InGaAs. The RTD structure is grown by an
MOCVD process on the surface of a nominally exact (100) GaAs
substrate. To complete the device, layers of doped GaAs may
similarly be formed on either side of the multilayer RTD structure.
Spacer layers of GaAs may also be provided as part of the RTD
structure on either side of the barrier layers to reduce the
intrinsic capacitance of the structure.
[0008] It has been found that in the present invention a structure
grown by the MOCVD process on the exact (100) GaAs substrate will
produce smooth interfaces between the various layers, including the
strained layer quantum well structure, to allow the achievement of
high current density and other desirable characteristics at
conventional operating temperatures (e.g., 300 K). The resulting
structure provides resonant tunneling through the second energy
level in a strained-layer quantum-well. The growth of
strained-layer InGaAs quantum well structures using exact
on-orientation substrates produces distinct layers with relatively
abrupt transitions at interfaces, significantly improving the
smoothness of the interfaces and consequent device performance over
devices which are grown off-orientation. Specifically, rough
interfaces cause carrier scattering which significantly increases
the valley current and thus makes the device impractical. By
smoothing the interfaces, high peak-to-valley ratios can thus be
obtained.
[0009] Further objects, features and advantages of the invention
will be apparent from the following detailed description when taken
in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] In the drawings:
[0011] FIG. 1 is a simplified band diagram of a typical resonant
tunneling diode (RTD) structure.
[0012] FIG. 2 is a band diagram as in FIG. 1 illustrating negative
bias of the emitter.
[0013] FIG. 3 is a band diagram as in FIG. 2 with further negative
bias of the emitter.
[0014] FIG. 4 is a typical current-voltage relationship curve for a
typical RTD.
[0015] FIG. 5 is a simplified band diagram for the RTD of the
present invention.
[0016] FIG. 6 is a simplified schematic view of the multilayer
structure of an embodiment of an RTD in accordance with the present
invention.
[0017] FIG. 7 is a cross-sectional view of an RTD semiconductor
device formed in accordance with the present invention.
[0018] FIG. 8 are calculated peak current density (stars) and peak
voltage (blank circles) as a function of well width for the RTD
embodiment of FIG. 6.
[0019] FIG. 9 is a measured current-voltage curve for a 6*6
.mu.m.sup.2 RTD device in accordance with the present invention
operating at room temperature.
DETAILED DESCRIPTION OF THE INVENTION
[0020] The present invention achieves all of the desirable
characteristics for an RTD in a device structure in the GaAs
material system. GaAs is a preferred material because it is less
expensive than InP, its technology is the most mature of all III-V
material systems, and it provides the possibility of integration
with other high-speed devices. A conduction band diagram for an RTD
quantum well of a preferred resonant tunneling diode in accordance
with the present invention is illustrated in simplified form in
FIG. 5, illustrating a GaAs emitter region 50, a first barrier
layer 51 and a second barrier layer 52, both formed of AlGaAs, a
quantum well layer 53 between the layers 51 and 52, which is formed
of InGaAs, and a GaAs collector layer 55 adjacent to the barrier
layer 52. In such a multilayer RTD structure the second level band
56 is slightly above the emitter conduction band edge 57. The first
level band is illustrated at 58 in FIG. 5. The second level is
preferably just at or, as a practical matter, slightly above the
conduction band edge because peak voltage for the device increases
rapidly as the second level is raised further above the conduction
band edge.
[0021] A schematic view of a practical RTD multilayer structure 60
grown by metal organic chemical vapor deposition (MOCVD) is given
in FIG. 6. In this device, n-type gallium arsenide (GaAs) is used
as a substrate 61. A suitable dopant is silicon. On this substrate
is grown a layer of GaAs 62, followed by the multilayer RTD
structure 60 formed of the GaAs spacer layer 55, the barrier layer
52, the quantum well layer 53, the barrier layer 51, and the GaAs
intrinsic layer 50, and then followed by a further layer 63 of
n-doped GaAs. A cross-sectional view of the physical arrangement of
the device is shown in FIG. 7. The RTD structure 60 is preferably
grown on the exact-orientation (100) GaAs substrate 61. An
insulating layer of silicon dioxide (SiO.sub.2) 72 is formed over
the substrate 61 and the structure 60 is grown on the substrate,
with an opening provided in the insulating layer 72 over an already
deposited Ge--Au/Ge--Ni--Au contact 73. A conducting layer 75 of,
e.g., Ti--Pt--Au is deposited over the SiO.sub.2 insulating layer
72 and forms an electrical connection to a contact 73 to form one
externally accessible terminal of the device.
[0022] By taking advantage of resonant tunneling through the second
energy level of a deep quantum well in a strained-layer structure,
this RTD structure provides two times higher peak current densities
(PCD's) than conventional GaAs-based resonant tunneling diodes
(RTD's) and more than 3 times higher PCD values than those typical
of MOCVD-grown RTD's. PCD values higher than 300 kA/cm.sup.2, peak
voltages as low as 1.2 volts, and peak-to-valley current ratios
(PVR's) of 3:1 at 300 K are obtained from the structures of FIGS. 7
with, e.g., 14 .ANG.-thick Al.sub.0.8Ga.sub.0.2As barriers 51 and
52 and a 57 .ANG.-thick In.sub.0.3Ga.sub.0.7As well 53. The
thickness of the various layers can be measured by transmission
electron microscopy (TEM).
[0023] The GaAs-based RTDs of the present invention have practical
advantages over GaSb- and InP-based structures due to the maturity
of growth and material processing techniques for GaAs, as well as
the possibility of integration of these RTD's with other high-speed
devices. The need for relatively high current density, which is
basically the crucial figure of merit for high-speed RTD switching
applications, has been a major drawback for previous GaAs-based
RTD's. As reported in T. P. E. Broekaert, et al., Appl. Phys.
Lett., 53 (16), pp. 1545-1547, October 1988, the peak current
density associated with the second resonant energy level of an RTD
is almost 10 times greater than the one resulting from the first
energy level for the same structure, but this level has, however,
been attainable only at high peak voltages (.apprxeq.4 volts). In
the present invention, by using a low-bandgap material,
In.sub.0.3Ga.sub.0.7As, for the well, the second resonant energy
level is well-adjusted to the edge of the conduction band of GaAs,
and thus provides a relatively low peak voltage. FIG. 8 shows
calculated data demonstrating that, for the structure of FIGS. 6
and 7, (an In.sub.0.3Ga.sub.0.7As well, 14 .ANG.-thick barriers,
and a 300 .ANG.-thick spacer layer), very high PCD values together
with a relatively low peak voltage are obtained, while the well
thickness stays below the critical value for In.sub.0.3Ga.sub.0.7As
grown on GaAs substrate (.apprxeq.100 .ANG.).
[0024] FIG. 9 shows the measured I-V curve for a 6*6 .mu.m.sup.2
device as in FIG. 7. Circuit simulations show that this device, if
fabricated with minimal parasitic capacitance, can switch 1 volt in
less than 3 ps. Optimized spacer layer structures that minimize
intrinsic capacitance can be utilized to reduce the switching time
by a factor of two or more, resulting in subpicosecond switching
speed. The relatively good peak-to-valley current ratio shown in
FIG. 9 results from the use of a deep quantum well, good ohmic
contacts made by a 2-step process (i.e., as shown in FIG. 7), and
the growth on an exact-orientation (100)-GaAs substrate 61, which
results in smooth interfaces between the strained-layer quantum
well 53 and the barriers 51 and 52.
[0025] The following is an illustrative example of a fabrication
process in accordance with the invention. The fabrication process
consists of two major steps: structure growth and device
fabrication.
[0026] Material growth is carried out by the Metal Organic Chemical
Vapor Deposition (MOCVD) technique, and the quality of the grown
structures can be examined by transmission electron microscopy
(TEM). By running TEM on several test structures, the growth rates
for various layers are very well calibrated (at the level of a few
i). The process is composed of various steps to fabricate proper
contacts for emitter and collector sides, and to etch mesas to form
isolated devices. Due to the crucial effect of series resistance on
the negative differential resistance of RTD's, a two-step process
is used to make a low-resistance ohmic contact on top of the mesa
(emitter side). Metal contacts are deposited by e-beam metal
deposition and patterned by the lift-off technique. The structure
may also be grown on a semi-insulating GaAs substrate in accordance
with conventional planar processing techniques, in which case all
contacts are formed on the same side of the substrate.
[0027] A total of three different masks are used throughout the
fabrication process; the most precise alignment needed in the
process is the alignment of windows in an SiO.sub.2 isolation layer
with the top metal contacts. The fabrication process is explained
in greater detail below.
[0028] The RTD structure is grown using low-pressure (50 mbar)
metalorganic chemical vapor deposition (LP-MOCVD) in an Aixtron
A-200 system, at a growth temperature of 700.degree. C. The
metalorganic precursors are trimethylgallium, trimethylaluminum,
and trimethylindium. The group V source is arsine with silane used
as an n-type dopant. Prior to growth of the RTD structure, the
solid composition (x) of Al.sub.xGa.sub.1-xAs is measured using
x-ray diffraction, as a function of the aluminum gas-phase
mole-fraction. Growth rates are obtained from film-thickness
measurements using scanning electron microscopy. Similarly, the
solid composition (y) of In.sub.yGa.sub.1-yAs is determined from
x-ray diffraction rocking curve measurements on thick (relaxed)
layers.
[0029] To improve the quantum-well interfacial morphology, RTD
structures are grown on nominally exact (100), 0.degree. to
.+-.0.5.degree., and preferably .+-.0.1.degree., GaAs substrates.
Such a substrate orientation is selected because recent studies of
strained-layer InGaAs quantum-well structures, via atomic force
microscopy (AFM) and low-temperature photoluminescence, indicate
that growth using exact on-orientation substrates significantly
improves the interfacial structure by eliminating step-bunching. By
contrast, the growth of strained-layer InGaAs quantum wells on
misoriented substrates will generally result in increased surface
roughness and broadening of low-temperature photoluminescence.
After growth of the RTD structure, the thicknesses of the layers
are confirmed using high-resolution TEM lattice imaging. The TEMs
of In.sub.0.3Ga.sub.0.7As/Al.sub.0.8Ga.sub.0.2As/GaAs structures
show a clear image of distinct layers with relatively abrupt
transitions at interfaces. From a high-resolution TEM lattice
image, it is possible to estimate the thicknesses of the first
barrier 52 (from the bottom), well 53, and second barrier 51 as
being 14.5 .ANG., 57 .ANG., and 13 .ANG., respectively, which
estimates are in good agreement with the target values. A schematic
view of the grown structure 60 in FIG. 6 includes (from bottom to
top): a 300 .ANG. spacer layer 55 to reduce the intrinsic
capacitance of the device, a 14 .ANG. Al.sub.0.8Ga.sub.0.2As
barrier layer 52, a 57 .ANG. In.sub.0.3Ga.sub.0.7As well 53, the
second barrier layer 51, and a 100 .ANG. layer of intrinsic GaAs to
separate the structure from the doped top layer 63.
[0030] The device fabrication starts with the deposition of the top
metal contact using e-beam metal deposition. In order to make a
good ohmic contact, a sequence of various metal layers are used,
such as Ge--Au/Ge--Ni--Au. The deposited metal is patterned to
3.times.3 .mu.m.sup.2 squares, separated by 1 mm from each other.
Then, using chemical etching, mesas of different sizes (from
5.times.5 .mu.m.sup.2 to 8.times.8 .mu.m.sup.2) are etched around
contacts. After covering the whole wafer with a 1000 .ANG.-thick
SiO.sub.2 film 72 as an isolation layer, 3.times.3 .mu.m.sup.2
windows are opened on top of the buried contacts. Then, the second
layer of metal, composed of Ti--Pt--Au layers, is deposited on the
wafer. In order to facilitate cleaving the wafer into devices, the
wafer is thinned to 150 .mu.m by mechanical lapping. After
depositing the back contact 76 (Ge--Au/Ge--Ni--Au), the contacts
are alloyed by rapid thermal annealing in order not to damage the
structure (at 400.degree. C. for 30 seconds). The last step is to
cleave the wafer into devices.
[0031] The major fabrication process steps are summarized below,
with further details for steps 4-11:
[0032] 1. System calibration.
[0033] 2. Wafer preparation (if necessary).
[0034] 3. MOCVD device growth.
[0035] 4. Patterning top contact by lift-off method;
[0036] a) Using mask 2 and negative photoresist to pattern 3 .mu.m
by 3 .mu.m contacts.
[0037] b) Metal evaporation Ge--Au/Ge--Ni--Au.
[0038] c) Removing extra metal.
[0039] 5. Chemical etching to isolate devices:
[0040] a) Photolithography using mask 1.
[0041] b) Chemical etching for a thickness of greater than 1
.mu.m.
[0042] 6. SiO.sub.2 deposition by PE-CVD.
[0043] 7. Patterning SiO.sub.2 to open 3 .mu.m by 3 .mu.m windows,
using mask 2.
[0044] 8. Top contact deposition and patterning by lift-off (mask
3) Ti--Pt--Au.
[0045] 9. Wafer thinning.
[0046] 10. Bottom contact deposition Ge--Au/Ge--Ni--Au.
[0047] 11. Making ohmic contacts by annealing @400C. for 30
seconds.
[0048] 12. Cleaving.
[0049] Step 4-a:
[0050] In order to be able to pattern metal contacts on wafer
through the lift-off technique, the thickness of photoresist must
be greater than the thickness of deposited metal. Therefore, for
this step Shipley AZ 1375 negative photoresist is used.
[0051] Spinning: 4500 RPM for 30 seconds
[0052] Prebake: 30 min. @90.degree. C.
[0053] Exposure time: 45 sec. using mask aligner Karl Suss MJB3
(mask 2).
[0054] Developing: MF 321 for 1 min.
[0055] Postbake: 30 min. @120.degree. C.
[0056] Step 4-b:
[0057] The metal is deposited on top of the patterned photoresist
by E-beam metal deposition (CHA Industries) at a pressure below
10.sup.-6 Torr.
[0058] Ge: 200 .ANG.
[0059] Au/Ge: 800 .ANG.
[0060] Ni: 300 .ANG.
[0061] Au: 1000 .ANG.
[0062] Step 4-c:
[0063] By placing the wafer in acetone and using ultrasound
agitation, the extra metal from the surface of wafer is lifted (2
min.).
[0064] Step 5-a:
[0065] Shipley AZ 1805 negative photoresist is used as the mask for
mesa definition during the wet etching process. Mask 1 is used to
pattern the photoresist.
[0066] Spinning: 5000 RPM for 30 seconds
[0067] Prebake: 30 min. @90.degree. C.
[0068] Exposure time: 2.7 sec. (mask 1).
[0069] Developing: MF 321 for 45 sec.
[0070] Postbake: 30 min. @120.degree. C.
[0071] Step 5-b:
[0072] Isolated mesa structures are formed by the wet etching
process using H.sub.3PO.sub.4/H.sub.2O.sub.2/H.sub.2O (5:1:1)
solution. The mesas are etched as high as 1 .mu.m at a rate of 4000
.ANG./min at 9.degree. C.
[0073] Step 6:
[0074] Through Plasma Enhanced Chemical Vapor Deposition (PE-CVD)
(Waf'r/Batch Plasma-Therm 70 series system), a 1000 .ANG.-thick
layer of SiO.sub.2 is deposited on the structures.
[0075] Pressure: 900 mTorr.
[0076] Temperature: 250.degree. C.
[0077] Step 7:
[0078] In order to open windows in the SiO.sub.2 layer, Shipley AZ
1813 negative photoresist is used which is thick enough to cover
the mesas, and forms a planar surface proper for
photolithography.
[0079] Spinning: 4000 RPM for 30 seconds
[0080] Prebake: 30 min. @90.degree. C.
[0081] Exposure time: 7 sec (mask 2).
[0082] Developing: MF 321 for 1 min.
[0083] Postbake: 30 min @120.degree. C.
[0084] Step 8:
[0085] The second layer of top metal was deposited by e-beam metal
deposition and patterned by lift-off (mask 3).
[0086] Ti: 500 .ANG.
[0087] Pt: 600 .ANG.
[0088] Au: 1000 .ANG.
[0089] Step 9:
[0090] In order to facilitate cleaving the wafer into devices, it
is thinned to 150 .mu.m by mechanical lapping (LOGITECH PM2A
machine and 3 .mu.m Aluminum Oxide powder).
[0091] Step 10:
[0092] Deposition of bottom contact: The same as step 4-b.
[0093] Ge: 200 .ANG.
[0094] Au/Ge: 1000 .ANG.
[0095] Ni: 300 .ANG.
[0096] Au: 3000 .ANG.
[0097] Step 11:
[0098] By Rapid Thermal Annealing (RTA), the contacts are alloyed
at 400.degree. C. for 30 seconds which is short enough not to
damage the grown structure.
[0099] It is understood that the present invention is not limited
to the embodiments disclosed herein, but encompasses all such forms
thereof that come within the scope of the following claims.
* * * * *