U.S. patent application number 10/191336 was filed with the patent office on 2004-01-08 for memory utilizing oxide-conductor nanolaminates.
This patent application is currently assigned to Micron Technology, Inc.. Invention is credited to Ahn, Kie Y., Forbes, Leonard.
Application Number | 20040004245 10/191336 |
Document ID | / |
Family ID | 29999976 |
Filed Date | 2004-01-08 |
United States Patent
Application |
20040004245 |
Kind Code |
A1 |
Forbes, Leonard ; et
al. |
January 8, 2004 |
Memory utilizing oxide-conductor nanolaminates
Abstract
Structures, systems and methods for floating gate transistors
utilizing oxide-conductor nanolaminates are provided. One floating
gate transistor embodiment includes a first source/drain region, a
second source/drain region, and a channel region therebetween. A
floating gate is separated from the channel region by a first gate
oxide. The floating gate includes oxide-conductor nanolaminate
layers to trap charge in potential wells formed by different
electron affinities of the oxide-conductor nanolaminate layers.
Inventors: |
Forbes, Leonard; (Corvallis,
OR) ; Ahn, Kie Y.; (Chappaqua, NY) |
Correspondence
Address: |
SCHWEGMAN, LUNDBERG, WOESSNER & KLUTH, P.A.
P.O. BOX 2938
MINNEAPOLIS
MN
55402
US
|
Assignee: |
Micron Technology, Inc.
|
Family ID: |
29999976 |
Appl. No.: |
10/191336 |
Filed: |
July 8, 2002 |
Current U.S.
Class: |
257/315 ;
257/E27.103; 257/E29.306 |
Current CPC
Class: |
H01L 27/115 20130101;
H01L 29/42332 20130101; G11C 16/0416 20130101; G11C 11/5671
20130101; H01L 29/7885 20130101 |
Class at
Publication: |
257/315 |
International
Class: |
H01L 029/788 |
Claims
What is claimed is:
1. A floating gate transistor, comprising: a first source/drain
region a second source/drain region a channel region between the
first and the second source/drain regions, a floating gate
separated from the channel region by a first oxide layer, wherein
the floating gate includes oxide-conductor nanolaminate layers with
charge trapping in potential wells formed by different electron
affinities of the oxide-conductor nanolaminate layers; and a
control gate separated from the floating gate by a second oxide
layer.
2. The floating gate transistor of claim 1, wherein the
oxide-conductor nanolaminate layers include Tantalum Nitride
(TaN).
3. The floating gate transistor of claim 1, wherein the
oxide-conductor nanolaminate layers include Titanium Nitride
(TiN).
4. The floating gate transistor of claim 1, wherein the
oxide-conductor nanolaminate layers include Tungsten Nitride
(WN).
5. The floating gate transistor of claim 1, wherein the
oxide-conductor nanolaminate layers include Niobium Nitride
(NbN).
6. The floating gate transistor of claim 1, wherein the
oxide-conductor nanolaminate layers include Molybdenum Nitride
(MoN).
7. The floating gate transistor of claim 1, wherein the
oxide-conductor nanolaminate layers include Zinc-Oxide-Silicon
(ZnOS).
8. The floating gate transistor of claim 1, wherein the
oxide-conductor nanolaminate layers include Tungsten (W).
9. The floating gate transistor of claim 1, wherein the
oxide-conductor nanolaminate layers include Nickel (Ni).
10. A vertical multistate cell, comprising: a vertical floating
gate transistor extending outwardly from a substrate, the floating
gate transistor having a source region, a drain region, a channel
region between the souce and the drain regions, and a floating gate
separated from the channel region by a gate insulator, wherein the
floating gate includes oxide-conductor nanolaminate layers adapted
to trap charge in potential wells formed by different electron
affinities of the oxide-conductor nanolaminate layers; a sourceline
coupled to the source region; a transmission line coupled to the
drain region; and wherein the floating gate transistor is a
programmed floating gate transistor having one of a number of
charge levels trapped in the floating gate.
11. The vertical multistate cell of claim 10, wherein the
oxide-conductor nanolaminate layers include Tantalum Nitride
(TaN).
12. The vertical multistate cell of claim 10, wherein the
oxide-conductor nanolaminate layers include Titanium Nitride
(TiN).
13. The vertical multistate cell of claim 10, wherein the
oxide-conductor nanolaminate layers include Tungsten Nitride
(WN).
14. The vertical multistate cell of claim 10, wherein the
oxide-conductor nanolaminate layers include Niobium Nitride
(NbN).
15. The vertical multistate cell of claim 10, wherein the
oxide-conductor nanolaminate layers include Molybdenum Nitride
(MoN).
16. The vertical multistate cell of claim 10, wherein the
oxide-conductor nanolaminate layers include Zinc-Oxide-Silicon
(ZnOS).
17. The vertical multistate cell of claim 10, wherein the
oxide-conductor nanolaminate layers include Tungsten (W).
18. The vertical multistate cell of claim 10, wherein the
oxide-conductor nanolaminate layers include Nickel (Ni).
19. A vertical multistate cell, comprising: a vertical floating
gate transistor extending outwardly from a substrate, the floating
gate transistor having a source region, a drain region, a channel
region between the source region and the drain region, a floating
gate separated from the channel region by a first gate oxide, and a
control gate separated from the floating gate by a second gate
oxide, wherein the floating gate includes oxide-conductor
nanolaminate layers formed of metallic conductors; a wordline
coupled to the control gate; a sourceline formed in a trench
adjacent to the vertical floating gate transistor, wherein the
source region is coupled to the sourceline; a bit line coupled to
the drain region; and wherein the floating gate transistor is a
programmed floating gate transistor having a number of charge
levels trapped in the floating gate.
20. The vertical multistate cell of claim 19, wherein the
oxide-conductor nanolaminate layers include Tantalum Nitride
(TaN).
21. The vertical multistate cell of claim 19, wherein the
oxide-conductor nanolaminate layers include Titanium Nitride
(TiN).
22. The vertical multistate cell of claim 19, wherein the
oxide-conductor nanolaminate layers include Tungsten Nitride
(WN).
23. The vertical multistate cell of claim 19, wherein the
oxide-conductor nanolaminate layers include Niobium Nitride
(NbN).
24. The vertical multistate cell of claim 19, wherein the
oxide-conductor nanolaminate layers include Molybdenum Nitride
(MoN).
25. The vertical multistate cell of claim 19, wherein the
oxide-conductor nanolaminate layers have atomic dimensions with
precisely controlled interfaces and layer thickness formed by
atomic layer deposition (ALD).
26. A vertical multistate cell, comprising: a vertical floating
gate transistor extending outwardly from a substrate, the floating
gate transistor having a source region, a drain region, a channel
region between the source region and the drain region, a floating
gate separated from the channel region by a first gate oxide, and a
control gate separated from the floating gate by a second gate
oxide, wherein the floating gate includes oxide-conductor
nanolaminate layers formed of doped oxide conductors; a wordline
coupled to the control gate; a sourceline formed in a trench
adjacent to the vertical floating gate transistor, wherein the
source region is coupled to the sourceline; a bit line coupled to
the drain region; and wherein the floating gate transistor is a
programmed floating gate transistor having a number of charge
levels trapped in the floating gate.
27. The vertical multistate cell of claim 26, wherein the
oxide-conductor nanolaminate layers include Zinc-Oxide-Silicon
(ZnOS).
28. A vertical multistate cell, comprising: a vertical floating
gate transistor extending outwardly from a substrate, the floating
gate transistor having a source region, a drain region, a channel
region between the source region and the drain region, a floating
gate separated from the channel region by a first gate oxide, and a
control gate separated from the floating gate by a second gate
oxide, wherein the floating gate includes oxide-conductor
nanolaminate layers formed of metals; a wordline coupled to the
control gate; a sourceline formed in a trench adjacent to the
vertical floating gate transistor, wherein the source region is
coupled to the sourceline; a bit line coupled to the drain region;
and wherein the floating gate transistor is a programmed floating
gate transistor having a number of charge levels trapped in the
floating gate.
29. The vertical multistate cell of claim 28, wherein the
oxide-conductor nanolaminate layers include Tungsten (W).
30. The vertical multistate cell of claim 28, wherein the
oxide-conductor nanolaminate layers include Nickel (Ni).
31. A floating gate transistor array, comprising: a number of
floating gate transistor cells formed on a substrate, wherein each
floating gate transistor cell includes a source region, a drain
region, a channel region between the source and the drain regions,
and a floating gate separated from the channel region by a first
gate oxide, and a control gate separated from the floating gate by
a second gate oside, and wherein the floating gate insulator
includes oxide-conductor nanolaminate layers with charge trapping
in potential wells formed by different electron affinities of the
oxide-conductor nanolaminate layers; a number of bit lines coupled
to the drain region of each floating gate transistor cell along
rows of the floating gate transistor array; a number of word lines
coupled to the control gate of each floating gate transistor cell
along columns of the memory array; a number of sourcelines, wherein
the source region of each floating gate transistor cell is coupled
to the number of sourcelines along rows of the floating gate
transistor cells; and wherein at least one of floating gate
transistor cells is a programmed floating gate transistor having
one of a number of charge levels trapped in the floating gate.
32. The floating gate transistor array of claim 31, wherein the
oxide-conductor nanolaminate layers include Tantalum Nitride
(TaN).
33. The floating gate transistor of claim 31, wherein the
oxide-conductor nanolaminate layers include Titanium Nitride
(TiN).
34. The floating gate transistor array of claim 31, wherein the
oxide-conductor nanolaminate layers include Tungsten Nitride
(WN).
35. The floating gate transistor array of claim 31, wherein the
oxide-conductor nanolaminate layers include Niobium Nitride
(NbN).
36. The floating gate transistor array of claim 31, wherein the
oxide-conductor nanolaminate layers include Molybdenum Nitride
(MoN).
37. The floating gate transistor array of claim 31, wherein the
oxide-conductor nanolaminate layers include Zinc-Oxide-Silicon
(ZnOS).
38. The floating gate transistor array of claim 31, wherein the
oxide-conductor nanolaminate layers include Tungsten (W).
39. The floating gate transistor array of claim 31, wherein the
oxide-conductor nanolaminate layers include Nickel (Ni).
40. The floating gate transistor array of claim 31, wherein the one
of a number of charge levels trapped in the floating gate insulator
includes a charge of approximately 100 electrons.
41. The floating gate transistor array of claim 31, wherein the
first source/drain region of the floating gate transistor cell
includes a source region and the second source/drain region of the
floating gate transistor cell includes a drain region.
42. The floating gate transistor array of claim 31, wherein the
number of floating gate transistor cells extending from a substrate
operate as equivalent to a floating gate transistor having a size
equal to or less than 2.0 lithographic feature squared
(2F.sup.2).
43. A memory array, comprising: a memory array, wherein the memory
array includes a number of vertical pillars formed in rows and
columns extending outwardly from a substrate and separated by a
number of trenches, wherein the number of vertical pillars serve as
floating gate transistors including a source region, a drain
region, a channel region between the source and the drain regions,
a floating gate in the trenches along rows of pillars separated
from the channel region by a first gate oxide, and a control gate
separated from the floating gate by a second gate oxide, wherein
the gate insulator includes oxide-conductor nanolaminate layers
with charge trapping in potential wells formed by different
electron affinities of the oxide-conductor nanolaminate layers,
wherein along columns of the pillars adjacent pillars include a
floating gate transistor which operate as a multistate cell on one
side of a trench and a floating gate transistor which operates as a
reference cell having a programmed conductivity state on the
opposite side of the trench; a number of bit lines coupled to the
drain region of each floating gate transistor along rows of the
memory array; a number of word lines coupled to the control gate of
each floating gate transistor along columns of the memory array; a
number of sourcelines formed in a bottom of the trenches between
rows of the pillars and coupled to the source regions of each
floating gate transistor along rows of pillars, wherein along
columns of the pillars the source region of each floating gate
transistor in column adjacent pillars couple to the sourceline in a
shared trench such that a multistate cell floating gate transistor
and a reference cell floating gate transistor share a common
sourceline; a wordline address decoder coupled to the number of
wordlines; a bitline address decoder coupled to the number of
bitlines; a sense amplifier coupled to the number of bitlines; and
wherein at least one of multistate cell floating gate transistors
is a programmed floating gate transistor having one of a number of
charge levels trapped in the floating gate.
44. The memory array of claim 43, wherein the number of sourcelines
formed in a bottom of the trenches between rows of the pillars
include a doped region implanted in the bottom of the trench.
45. The memory array of claim 43, wherein the one of a number of
charge levels trapped in the gate insulator includes a charge
adjacent to the source region of approximately 100 electrons.
46. The memory array of claim 43, wherein the oxide-conductor
nanolaminate layers include Tantalum Nitride (TaN).
47. The memory array of claim 43, wherein the oxide-conductor
nanolaminate layers include Titanium Nitride (TiN).
48. The memory array of claim 43, wherein the oxide-conductor
nanolaminate layers include Tungsten Nitride (WN).
49. The memory array of claim 43, wherein the oxide-conductor
nanolaminate layers include Niobium Nitride (NbN).
50. The memory array of claim 43, wherein the oxide-conductor
nanolaminate layers include Molybdenum Nitride (MoN).
51. The memory array of claim 43, wherein the oxide-conductor
nanolaminate layers include Zinc-Oxide-Silicon (ZnOS).
52. The memory array of claim 43, wherein the oxide-conductor
nanolaminate layers include Tungsten (W).
53. The memory array of claim 43, wherein the oxide-conductor
nanolaminate layers include Nickel (Ni).
54. The memory array of claim 43, wherein the wordline address
decoder and the bitline address decoder each include conventionally
fabricated MOSFET floating gate transistors having thin gate
insulators formed of silicon dioxide (SiO.sub.2).
55. The memory array of claim 43, wherein the sense amplifier
includes conventionally fabricated MOSFET floating gate transistors
having thin gate insulators formed of silicon dioxide
(SiO.sub.2).
56. A programmable logic array, comprising: a plurality of input
lines for receiving an input signal; a plurality of output lines;
and one or more arrays having a first logic plane and a second
logic plane connected between the input lines and the output lines,
wherein the first logic plane and the second logic plane comprise a
plurality of logic cells arranged in rows and columns for providing
a sum-of-products term on the output lines responsive to a received
input signal, wherein each logic cell includes a floating gate
transistor cell including: a first source/drain region; a second
source/drain region; a channel region between the first and the
second source/drain regions; a floating gate separated from the
channel region by a first gate oxide, wherein the floating gate
includes oxide-conductor nanolaminate layers to trap charge in
potential wells formed by different electron affinities of the
oxide-conductor nanolaminate layers; and a control gate separated
from the floating gate by a second gate oxide.
57. The programmable logic array of claim 56, wherein the
oxide-conductor nanolaminate layers include Tantalum Nitride
(TaN).
58. The programmable logic array of claim 56, wherein the
oxide-conductor nanolaminate layers include Titanium Nitride
(TiN).
59. The programmable logic array of claim 56, wherein the
oxide-conductor nanolaminate layers include Tungsten Nitride
(WN).
60. The programmable logic array of claim 56, wherein the
oxide-conductor nanolaminate layers include Niobium Nitride
(NbN).
61. The programmable logic array of claim 56, wherein the
oxide-conductor nanolaminate layers include Molybdenum Nitride
(MoN).
62. The programmable logic array of claim 56, wherein the
oxide-conductor nanolaminate layers include Zinc-Oxide-Silicon
(ZnOS).
63. The programmable logic array of claim 56, wherein the
oxide-conductor nanolaminate layers include Tungsten (W).
64. The programmable logic array of claim 56, wherein the
oxide-conductor nanolaminate layers include Nickel (Ni).
65. An electronic system, comprising: a processor; and a memory
device coupled to the processor, wherein the memory device
includes; a memory array, wherein the memory array includes a
number of vertical pillars formed in rows and columns extending
outwardly from a substrate and separated by a number of trenches,
wherein the number of vertical pillars serve as floating gate
transistors including a source region, a drain region, a channel
region between the source and the drain regions, a floating gate
separated from the channel region by a first gate oxide in the
trenches along rows of pillars, a control gate separated from the
floating gate by a second gate oxide, wherein the floating gate
includes oxide-conductor nanolaminate layers to trap charge in
potential wells formed by different electron affinities of the
oxide-conductor nanolaminate layers, wherein along columns of the
pillars adjacent pillars include a floating gate transistor which
operates as a multistate cell on one side of a trench and a
floating gate transistor which operates as a reference cell having
a programmed conductivity state on the opposite side of the trench;
a number of bit lines coupled to the drain region of each floating
gate transistor along rows of the memory array; a number of word
lines coupled to the control gate of each floating gate transistor
along columns of the memory array; a number of sourcelines formed
in a bottom of the trenches between rows of the pillars and coupled
to the source regions of each floating gate transistor along rows
of pillars, wherein along columns of the pillars the source region
of each floating gate transistor in column adjacent pillars couple
to the sourceline in a shared trench such that a multistate cell
floating gate transistor and a reference cell floating gate
transistor share a common sourceline; a wordline address decoder
coupled to the number of wordlines; a bitline address decoder
coupled to the number of bitlines; a sense amplifier coupled to the
number of bitlines; and wherein at least one of multistate cell
floating gate transistors is a programmed floating gate transistor
having one of a number of charge levels trapped in the floating
gate.
66. The electronic system of claim 65, wherein the number of
sourcelines formed in a bottom of the trenches between rows of the
pillars include a doped region implanted in the bottom of the
trench.
67. The electronic system of claim 65, wherein the one of a number
of charge levels trapped in the floating gate includes a charge of
approximately 100 electrons.
68. The electronic system of claim 65, wherein the oxide-conductor
nanolaminate layers include Tantalum Nitride (TaN).
69. The electronic system of claim 65, wherein the oxide-conductor
nanolaminate layers include Titanium Nitride (TiN).
70. The electronic system of claim 65, wherein the oxide-conductor
nanolaminate layers include Tungsten Nitride (WN).
71. The electronic system r of claim 65, wherein the
oxide-conductor nanolaminate layers include Niobium Nitride
(NbN).
72. The electronic system of claim 65, wherein the oxide-conductor
nanolaminate layers include Molybdenum Nitride (MoN).
73. The electronic system of claim 65, wherein the oxide-conductor
nanolaminate layers include Zinc-Oxide-Silicon (ZnOS).
74. The electronic system of claim 65, wherein the oxide-conductor
nanolaminate layers include Tungsten (W).
75. The electronic system of claim 65, wherein the oxide-conductor
nanolaminate layers include Nickel (Ni).
76. The electronic system of claim 65, wherein each floating gate
transistor operates as equivalent to a floating gate transistor
having a size equal to or less than 2.0 lithographic feature
squared (2F.sup.2).
77. The electronic system of claim 65, wherein, in a read
operation, a sourceline for two column adjacent pillars sharing a
trench is coupled to a ground potential, the drain regions of the
column adjacent pillars sharing a trench are precharged to a
fractional voltage of VDD, and the control gate for each of the
column adjacent pillars sharing a trench is addressed such that a
conductivity state of a multistate cell floating gate transistor
can be compared to a conductivity state of a reference cell
floating gate transistor.
78. The electronic system of claim 65, wherein, in a write
operation, a sourceline for two column adjacent pillars sharing a
trench is biased to a voltage higher than VDD, one of the drain
regions of the column adjacent pillars sharing a trench is coupled
to a ground potential, and the control gate for each of the column
adjacent pillars sharing a trench is addressed with a wordline
potential.
79. A method for operating a floating gate transistor array,
comprising: programming one or more floating gate transistors in
the array, wherein each floating gate transistor includes a source
region, a drain region, a channel region between the source and the
drain regions, a floating gate separated from the channel region by
a first gate oxide, and a control gate separated from the floating
gate by a second gate oxide, wherein the floating gate includes
oxide-conductor nanolaminate layers to trap charge in potential
wells formed by different electron affinities of the
oxide-conductor nanolaminate layers, wherein the array includes a
number of sourcelines coupled to the source regions of each
floating gate transistor along rows in the array, and wherein the
array includes a number of bitlines coupled to the drain region
along rows in the array, and wherein programming the one or more
floating gate transistors includes: applying a first voltage
potential to a drain region of the floating gate transistor;
applying a second voltage potential to a source region of the
floating gate transistor; applying a control gate potential to the
control gate of the floating gate transistor; and wherein applying
the first, second and gate potentials to the one or more floating
gate transistors includes creating a hot electron injection into
the floating gate of the one or more floating gate transistors such
that the one or more floating gate transistors become programmed
floating gate transistors having one of a number of charge levels
trapped in the floating gate.
80. The method of claim 79, wherein applying a first voltage
potential to the drain region of the floating gate transistor
includes grounding the drain region of the floating gate
transistor.
81. The method of claim 80, wherein applying a second voltage
potential to the source region includes applying a high voltage
potential (VDD) to a sourceline coupled thereto.
82. The method of claim 81, wherein applying a gate potential to
the gate of the floating gate transistor includes applying a gate
potential to the gate in order to create a conduction channel
between the source and drain regions of the floating gate
transistor.
83. The method of claim 79, wherein the method further includes
reading one or more floating gate transistors, wherein reading the
one or more floating gate transistors includes: grounding the
source region for an addressed floating gate transistor;
precharging the drain region for the addressed floating gate
transistor to a fractional voltage of VDD; and applying a gate
potential of approximately 1.0 Volt to the floating gate for the
addressed floating gate transistor such that a conductivity state
of the addressed floating gate transistor can be compared to a
conductivity state of a reference cell.
84. A method for multistate memory, comprising: writing to one or
more vertical floating gate transistors arranged in rows and
columns extending outwardly from a substrate and separated by
trenches in a DRAM array, wherein each floating gate transistor in
the DRAM array includes a source region, a drain region, a channel
region between the source and the drain regions, a floating gate in
the trenches separated from the channel region by a first gate
oxide, and a control gate separated from the floating gate by a
second gate oxide, wherein the floating gate insulator includes
oxide-conductor nanolaminate layers to trap charge in potential
wells formed by different electron affinities of the
oxide-conductor nanolaminate layers, wherein the DRAM array
includes a number of sourcelines formed in a bottom of the trenches
between rows of the vertical floating gate transistors and coupled
to the source regions of each floating gate transistor along rows
the vertical floating gate transistors, wherein along columns of
the vertical floating gate transistors the source region of each
column adjacent vertical floating gate transistors couple to the
sourceline in a shared trench, and wherein the DRAM array includes
a number of bitlines coupled to the drain region along rows in the
DRAM array, and wherein programming the one or more vertical
floating gate transistors includes; biasing a sourceline for two
column adjacent vertical floating gate transistors sharing a trench
to a voltage higher than VDD; grounding a bitline coupled to one of
the drain regions of the two column adjacent vertical floating gate
transistors in the vertical floating gate transistors to be
programmed applying a gate potential to the control gate for each
of the two column adjacent vertical floating gate transistors to
create a hot electron injection into the floating gate of the
vertical floating gate transistor to be programmed such that an
addressed floating gate transistor becomes a programmed floating
gate; reading one or more vertical floating gate transistors in the
DRAM array, wherein reading the one or more floating gate
transistors includes; grounding a sourceline for two column
adjacent vertical floating gate transistors sharing a trench;
precharging the drain regions of the two column adjacent vertical
floating gate transistors sharing a trench to a fractional voltage
of VDD; and applying a gate potential of approximately 1.0 Volt to
the control gate for each of the two column adjacent vertical
floating gate transistors sharing a trench such that a conductivity
state of an addressed vertical floating gate transistor can be
compared to a conductivity state of a reference cell.
85. The method of claim 84, wherein creating a hot electron
injection into the floating gate of the addressed floating gate
transistor includes trapping charge in potential wells formed by
different electron affinities of the oxide-conductor nanolaminate
layers.
86. The method of claim 84, wherein reading one or more vertical
floating gate transistors in the DRAM array includes using a sense
amplifier to detect whether an addressed vertical floating gate
transistor is a programmed vertical floating gate transistor,
wherein a programmed vertical floating gate transistor will not
conduct, and wherein an un-programmed vertical floating gate
transistor addressed over approximately 10 ns will conduct a
current of approximately 12.5 .mu.A such that the method includes
detecting an integrated drain current having a charge of 800,000
electrons using the sense amplifier.
87. The method of claim 84, wherein in creating a hot electron
injection into the floating gate of an addressed vertical floating
gate transistor includes changing a threshold voltage for the
vertical floating gate transistor by approximately 0.5 Volts.
88. The method of claim 84, wherein creating a hot electron
injection into the floating gate of the addressed vertical floating
gate transistor includes trapping a stored charge in the floating
gate of the addressed vertical floating gate transistor of
approximately 10.sup.12 electrons/cm.sup.2.
89. The method of claim 84, wherein creating a hot electron
injection into the floating gate of the addressed vertical floating
gate transistor includes trapping a stored charge in the gate
insulator of the addressed vertical floating gate transistor of
approximately 100 electrons.
90. The method of claim 84, wherein the method further includes
using the vertical floating gate transistor as active device with
gain, and wherein reading a programmed vertical floating gate
transistor includes providing an amplification of a stored charge
in the floating gate from 100 to 800,000 electrons over a read
address period of approximately 10 ns.
91. A method for forming a floating gate transistor, comprising:
forming a first source/drain region, a second source/drain region,
and a channel region therebetween in a substrate; forming a
floating gate opposing the channel region and separated therefrom
by a first gate oxide, wherein forming the floating gate includes
forming oxide-conductor nanolaminate layers to trap charge in
potential wells formed by different electron affinities of the
oxide-conductor nanolaminate layers; and forming a control gate
opposing the floating gate and separated therefrom by a second gate
oxide.
92. The method of claim 91, wherein forming oxide-conductor
nanolaminate layers includes forming oxide-conductor nanolaminate
layers of Tantalum Nitride (TaN).
93. The method of claim 91, wherein forming oxide-conductor
nanolaminate layers includes forming oxide-conductor nanolaminate
layers of Titanium Nitride (TiN).
94. The method of claim 91, wherein forming oxide-conductor
nanolaminate layers includes forming oxide-conductor nanolaminate
layers of Tungsten Nitride (WN).
95. The method of claim 91, wherein forming oxide-conductor
nanolaminate layers includes forming oxide-conductor nanolaminate
layers of Niobium Nitride (NbN).
96. The method of claim 91, wherein forming oxide-conductor
nanolaminate layers includes forming oxide-conductor nanolaminate
layers of Molybdenum Nitride (MoN).
97. The method of claim 91, wherein forming oxide-conductor
nanolaminate layers includes forming oxide-conductor nanolaminate
layers of Zinc-Oxide-Silicon (ZnOS).
98. The method of claim 91, wherein forming oxide-conductor
nanolaminate layers includes forming oxide-conductor nanolaminate
layers of Tungsten (W).
99. The method of claim 91, wherein forming oxide-conductor
nanolaminate layers includes forming oxide-conductor nanolaminate
layers of Nickel (Ni).
100. A method for forming a multistate memory array, comprising:
forming a number of vertical pillars in rows and columns extending
outwardly from a substrate and separated by a number of trenches,
wherein the number of vertical pillars serve as floating gate
transistors including a first source/drain region, a second
source/drain region, a channel region between the first and the
second source/drain regions, a floating gate in the trenches along
rows of pillars and separated from the channel region by a first
gate oxide, and a control gate separated from the floating gate by
a second gate oxide, wherein along columns of the pillars adjacent
pillars include a floating gate transistor which operates as a
multistate cell on one side of a trench and a floating gate
transistor which operates as a reference cell having a programmed
conductivity state on the opposite side of the trench, and wherein
forming the floating gate includes forming oxide-conductor
nanolaminate layers to trap charge in potential wells formed by
different electron affinities of the oxide-conductor nanolaminate
layers; forming a number of bit lines coupled to the second
source/drain region of each floating gate transistor along rows of
the memory array; forming a number of word lines coupled to the
control gate of each floating gate transistor along columns of the
memory array; forming a number of sourcelines formed in a bottom of
the trenches between rows of the pillars and coupled to the first
source/drain regions of each floating gate transistor along rows of
pillars, wherein along columns of the pillars the first
source/drain region of each floating gate transistor in column
adjacent pillars couple to the sourceline in a shared trench such
that a multistate cell floating gate transistor and a reference
cell floating gate transistor share a common sourceline; and
wherein the number of vertical pillars can be programmed to have a
one of a number of charge levels trapped in the floating gate by
biasing a sourceline to a voltage higher than VDD, grounding a
bitline, and selecting a control gate by a wordline address.
101. The method of claim 100, wherein forming a number of
sourcelines formed in a bottom of the trenches between rows of the
pillars includes implanting a doped region in the bottom of the
trench.
102. The method of claim 100, wherein forming oxide-conductor
nanolaminate layers includes forming oxide-conductor nanolaminate
layers of Tantalum Nitride (TaN).
103. The method of claim 100, wherein forming oxide-conductor
nanolaminate layers includes forming oxide-conductor nanolaminate
layers of Titanium Nitride (TiN).
104. The method of claim 100, wherein forming oxide-conductor
nanolaminate layers includes forming oxide-conductor nanolaminate
layers of Tungsten Nitride (WN).
105. The method of claim 100, wherein forming oxide-conductor
nanolaminate layers includes forming oxide-conductor nanolaminate
layers of Niobium Nitride (NbN).
106. The method of claim 100, wherein forming oxide-conductor
nanolaminate layers includes forming oxide-conductor nanolaminate
layers of Molybdenum Nitride (MoN).
107. The method of claim 100, wherein forming oxide-conductor
nanolaminate layers includes forming oxide-conductor nanolaminate
layers of Zinc-Oxide-Silicon (ZnOS).
108. The method of claim 100, wherein forming oxide-conductor
nanolaminate layers includes forming oxide-conductor nanolaminate
layers of Tungsten (W).
109. The method of claim 100, wherein forming oxide-conductor
nanolaminate layers includes forming oxide-conductor nanolaminate
layers of Nickel (Ni).
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is related to the following co-pending,
commonly assigned U.S. patent applications: "Memory Utilizing Oxide
Nanolaminates," attorney docket no. 1303.065US1, Ser. No. ______,
and "Memory Utilizing Oxide-Nitride Nanolaminates," attorney docket
no. 1303.067US1, Ser. No. ______, each of which disclosure is
herein incorporated by reference.
FIELD OF THE INVENTION
[0002] The present invention relates generally to semiconductor
integrated circuits and, more particularly, to memory utilizing
oxide-conductor nanolaminates.
BACKGROUND OF THE INVENTION
[0003] Many electronic products need various amounts of memory to
store information, e.g. data. One common type of high speed, low
cost memory includes dynamic random access memory (DRAM) comprised
of individual DRAM cells arranged in arrays. DRAM cells include an
access transistor, e.g a metal oxide semiconducting field effect
transistor (MOSFET), coupled to a capacitor cell.
[0004] Another type of high speed, low cost memory includes
floating gate memory cells. A conventional horizontal floating gate
transistor structure includes a source region and a drain region
separated by a channel region in a horizontal substrate. A floating
gate is separated by a thin tunnel gate oxide. The structure is
programmed by storing a charge on the floating gate. A control gate
is separated from the floating gate by an intergate dielectric. A
charge stored on the floating gate effects the conductivity of the
cell when a read voltage potential is applied to the control gate.
The state of cell can thus be determined by sensing a change in the
device conductivity between the programmed and un-programmed
states.
[0005] With successive generations of DRAM chips, an emphasis
continues to be placed on increasing array density and maximizing
chip real estate while minimizing the cost of manufacture. It is
further desirable to increase array density with little or no
modification of the DRAM optimized process flow.
[0006] Multilayer insulators have been previously employed in
memory devices. (See generally, U.S. Pat. No. 3,877,054, Boulin et
al., Apr. 8, 1975, entitled "Semiconductor memory apparatus with a
multi-layer insulator contacting the semiconductor," and U.S. Pat.
No. 3,964,085, Kahng et al., Jun. 15, 1976, entitled "Method for
fabricating multilayer insulator-semiconductor memory apparatus").
The devices in the above references employed oxide-tungsten
oxide-oxide layers. Other previously described structures described
have employed charge-trapping layers implanted into graded layer
insulator structures. (See generally, an article by DiMaria, D. J.,
"Graded or stepped energy band-gap-insulator MIS structures (GI-MIS
or SI-MIS)," Journal of Applied Physics, 50(9), 5826-9 (September
1979); U.S. Pat. No. 4,217,601, DeKeersmaecker et al., Aug. 12,
1980, entitled "Non-volatile memory devices fabricated from graded
or stepped energy band gap insulator MIM or MIS structure," also
RE31,083 DeKeersmaecker et al., Nov. 16, 1982, "Non-volatile memory
devices fabricated from graded or stepped energy band gap insulator
MIM or MIS structure;" and U.S. Pat. No. 5,768,192 Eitan, Jun. 16,
1998, entitled "Non-volatile semiconductor memory cell utilizing
asymmetrical charge trapping").
[0007] More recently oxide-nitride-oxide structures have been
described for high density nonvolatile memories. (See generally,
Eitan, B. et al., "NROM: A novel localized Trapping, 2-Bit
Nonvolatile Memory Cell," IEEE Electron Device Lett., 21(11),
543-545 (November 2000), and Eitan, B. et al., "Characterization of
Channel Hot Electron Injection by the Subthreshold Slope of NROM
device, IEEE Electron Device Lett., 22(11), 556-558 (November
2001)). All of these are variations on the original MNOS memory
structure (see generally, Frohman-Bentchkowsky, D., "An integrated
metal-nitride-oxide-silicon (MNOS) memory," Proceedings of the
IEEE, 57(6), 1190-2 (June 1969)) described by Fairchild
Semiconductor in 1969 which was conceptually generalized to include
trapping insulators in general for constructing memory arrays. (See
generally, U.S. Pat. No. 3,665,423 Nakamuma et al., May 23, 1972,
entitled "Memory matrix using MIS semiconductor element").
[0008] Studies of charge trapping in MNOS structures have also been
conducted by White and others. (See generally, White, M. H.,
"Direct tunneling in metal-nitride-oxide-silicon (MNOS)
structures," Conference: Program of the 31st physical electronics
conference (abstracts), page: 1 pp., Publisher: U.S. Dept.
Commerce, Washington, D.C., USA, 1971, viii+46 Pages, Sponsor:
American Phys. Soc., division of electron and atomic phys, Mar.
15-17, 1971, Gaithersburg, Md., USA; White, M. H., Cricchi, J. R.,
"Characterization of thin-oxide MNOS memory transistors," IEEE
Transactions on Electron Devices, ED-19(12), 1280-8 (December
1972), Wei, L. S., Simmons, J. G. "Trapping, emission and
generation in MNOS memory devices," Solid-State Electronics, 17(6),
591-8 (June 1974), Ferris-Prabhu, A. V., "Charge transfer in
layered insulators," Solid-State Electronics, 16(9), 1086-7
(September 1973); Ferris-Prabhu, A. V., Lareau, L. J., "Amnesia in
layered insulator FET memory devices," Conference: 1973
International Electron Devices Meeting Technical Digest, Page:
75-7, Publisher: IEEE, New York, N.Y., USA, 1973, xvi+575 Pages,
Sponsor: IEEE, Dec. 3-5, 1973, Washington, D.C., USA;
Ferris-Prabhu, A. V., "Tunneling theories of non-volatile
semiconductor memories," Physica Status Solidi A, 35(1), 243-50
(May 16, 1976)).
[0009] Some commercial and military applications utilized
non-volatile MNOS memories. (See generally, Britton, J. et al.,
"Metal-nitride-oxide IC memory retains data for meter reader,"
Electronics, 45(22); 119-23 (Oct. 23, 1972); and Cricchi, J. R. et
al., "Hardened MNOS/SOS electrically reprogrammable nonvolatile
memory," IEEE Transactions on Nuclear Science, ns-24(6), 2185-9
(December 1977), Conference: IEEE Annual Conference on Nuclear and
Space Radiation Effects, Sponsor: IEEE, Jul. 12-15, 1977,
Williamsburg, Va., USA).
[0010] However, these structures did not gain widespread acceptance
and use due to their variability in characteristics and
unpredictable charge trapping phenomena. They all depended upon the
trapping of charge at interface states between the oxide and other
insulator layers or poorly characterized charge trapping centers in
the insulator layers themselves. Since the layers were deposited by
CVD, they are thick, have poorly controlled thickness and large
surface state charge-trapping center densities between the
layers.
[0011] Flash memories based on electron trapping are well known and
commonly used electronic components. (See generally; B. Dipert and
L. Hebert, "Flash Memory goes Mainstream," IEEE Spectrum, No. 10,
pp. 48-52, (October 1993); R. Goodwins, "New Memory Technologies on
the Way," http://zdnet.com.com/2100-1103-846950.html). Recently
NAND flash memory cells have become common in applications
requiring high storage density while NOR flash memory cells are
used in applications requiring high access and read speeds. (See
generally, C.-G. Hwang, "Semiconductor Memories for the IT Era,"
Abst. IEEE Int. Solid-State Circuits Conf., San Francisco, 2002,
pp. 24-27). NAND flash memories have a higher density because 16 or
more devices are placed in series, this increases density at the
expense of speed. (See generally; R. Shirota et al., "A 2.3
mu.sup.2 memory cell structure for 16 Mb NAND EEPROMs," Digest of
IEEE Int. Electron Device Meeting, San Francisco, 1990, pp.
103-106)
[0012] Thus, there is an ongoing need for improved DRAM technology
compatible floating gate transistor cells. It is desirable that
such floating gate transistor cells be fabricated on a DRAM chip
with little or no modification of the DRAM process flow. It is
further desirable that such floating gate transistor cells provide
increased density and high access and read speeds.
SUMMARY OF THE INVENTION
[0013] The above mentioned problems for creating DRAM technology
compatible floating gate transistor cells as well as other problems
are addressed by the present invention and will be understood by
reading and studying the following specification. This disclosure
describes a flash memory device, programmable logic array device or
memory address and decode correction device with an oxide-conductor
nanolaminate floating gate rather than a conventional polysilicon
floating gate.
[0014] In particular, an embodiment of the present invention
includes a floating gate transistor utilizing oxide-conductor
nanolaminates. The floating gate transistor includes a first
source/drain region, a second source/drain region, and a channel
region therebetween. A floating gate is separated from the channel
region by a first gate oxide. The floating gate includes
oxide-conductor nanolaminate layers to trap charge in potential
wells formed by different electron affinities of the
oxide-conductor nanolaminate layers.
[0015] These and other embodiments, aspects, advantages, and
features of the present invention will be set forth in part in the
description which follows, and in part will become apparent to
those skilled in the art by reference to the following description
of the invention and referenced drawings or by practice of the
invention. The aspects, advantages, and features of the invention
are realized and attained by means of the instrumentalities,
procedures, and combinations particularly pointed out in the
appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] FIG. 1A is a block diagram of a metal oxide semiconductor
field effect floating gate transistor (MOSFET) in a substrate
according to the teachings of the prior art.
[0017] FIG. 1B illustrates the MOSFET of FIG. 1A operated in the
forward direction showing some degree of device degradation due to
electrons being trapped in the gate oxide near the drain region
over gradual use.
[0018] FIG. 1C is a graph showing the square root of the current
signal (Ids) taken at the drain region of the conventional MOSFET
versus the voltage potential (VGS) established between the gate and
the source region.
[0019] FIG. 2A is a diagram of an embodiment for a programmed
floating gate transistor, having oxide-conductor nanolaminate
layers, which can be used as a floating gate transistor cell
according to the teachings of the present invention.
[0020] FIG. 2B is a diagram suitable for explaining a method
embodiment by which a floating gate transistor, having
oxide-conductor nanolaminate layers, can be programmed to achieve
the embodiments of the present invention.
[0021] FIG. 2C is a graph plotting the current signal (Ids)
detected at the drain region versus a voltage potential, or drain
voltage, (VDS) set up between the drain region and the source
region (Ids vs. VDS).
[0022] FIG. 3 illustrates a portion of an embodiment of a memory
array according to the teachings of the present invention.
[0023] FIG. 4 illustrates an embodiment for an electrical
equivalent circuit for the portion of the memory array shown in
FIG. 3.
[0024] FIG. 5 illustrates an energy band diagram for an embodiment
of a gate stack according to the teachings of the present
invention.
[0025] FIG. 6 is a graph which plots electron affinity versus the
energy bandgap for various insulators.
[0026] FIGS. 7A-7B illustrates an embodiment for the operation of a
floating gate transistor cell having oxide-conductor nanolaminate
layers according to the teachings of the present invention.
[0027] FIG. 8 illustrates the operation of a conventional DRAM
cell.
[0028] FIG. 9 illustrates an embodiment of a memory device
according to the teachings of the present invention.
[0029] FIG. 10 is a schematic diagram illustrating a conventional
NOR-NOR programmable logic array.
[0030] FIG. 11 is a schematic diagram illustrating generally an
architecture of one embodiment of a programmable logic array (PLA)
with logic cells, having oxide-conductor nanolaminate layers
according to the teachings of the present invention.
[0031] FIG. 12 is a block diagram of an electrical system, or
processor-based system, utilizing oxide nanolaminates constructed
in accordance with the present invention.
DETAILED DESCRIPTION
[0032] In the following detailed description of the invention,
reference is made to the accompanying drawings which form a part
hereof, and in which is shown, by way of illustration, specific
embodiments in which the invention may be practiced. In the
drawings, like numerals describe substantially similar components
throughout the several views. These embodiments are described in
sufficient detail to enable those skilled in the art to practice
the invention. Other embodiments may be utilized and structural,
logical, and electrical changes may be made without departing from
the scope of the present invention.
[0033] The terms wafer and substrate used in the following
description include any structure having an exposed surface with
which to form the integrated circuit (IC) structure of the
invention. The term substrate is understood to include
semiconductor wafers. The term substrate is also used to refer to
semiconductor structures during processing, and may include other
layers that have been fabricated thereupon. Both wafer and
substrate include doped and undoped semiconductors, epitaxial
semiconductor layers supported by a base semiconductor or
insulator, as well as other semiconductor structures well known to
one skilled in the art. The term conductor is understood to include
semiconductors, and the term insulator is defined to include any
material that is less electrically conductive than the materials
referred to as conductors. The following detailed description is,
therefore, not to be taken in a limiting sense, and the scope of
the present invention is defined only by the appended claims, along
with the full scope of equivalents to which such claims are
entitled.
[0034] FIG. 1A is useful in illustrating the conventional operation
of a MOSFET such as can be used in a DRAM array. FIG. 1A
illustrates the normal hot electron injection and degradation of
devices operated in the forward direction. As is explained below,
since the electrons are trapped near the drain they are not very
effective in changing the device characteristics.
[0035] FIG. 1A is a block diagram of a metal oxide semiconductor
field effect floating gate transistor (MOSFET) 101 in a substrate
100. The MOSFET 101 includes a source region 102, a drain region
104, a channel region 106 in the substrate 100 between the source
region 102 and the drain region 104. A gate 108 is separated from
the channel region 108 by a gate oxide 110. A sourceline 112 is
coupled to the source region 102. A bitline 114 is coupled to the
drain region 104. A wordline 116 is coupled to the gate 108.
[0036] In conventional operation, a drain to source voltage
potential (Vds) is set up between the drain region 104 and the
source region 102. A voltage potential is then applied to the gate
108 via a wordline 116. Once the voltage potential applied to the
gate 108 surpasses the characteristic voltage threshold (Vt) of the
MOSFET a channel 106 forms in the substrate 100 between the drain
region 104 and the source region 102. Formation of the channel 106
permits conduction between the drain region 104 and the source
region 102, and a current signal (Ids) can be detected at the drain
region 104.
[0037] In operation of the conventional MOSFET of FIG. 1A, some
degree of device degradation does gradually occur for MOSFETs
operated in the forward direction by electrons 117 becoming trapped
in the gate oxide 110 near the drain region 104. This effect is
illustrated in FIG. 1B. However, since the electrons 117 are
trapped near the drain region 104 they are not very effective in
changing the MOSFET characteristics.
[0038] FIG. 1C illustrates this point. FIG. 1C is a graph showing
the square root of the current signal (Ids) taken at the drain
region versus the voltage potential (VGS) established between the
gate 108 and the source region 102. The change in the slope of the
plot of {square root}{square root over (Ids)} versus VGS represents
the change in the charge carrier mobility in the channel 106.
[0039] In FIG. 1C, .DELTA.VT represents the minimal change in the
MOSFET's threshold voltage resulting from electrons gradually being
trapped in the gate oxide 110 near the drain region 104, under
normal operation, due to device degradation. This results in a
fixed trapped charge in the gate oxide 110 near the drain region
104. Slope 1 represents the charge carrier mobility in the channel
106 for FIG. 1A having no electrons trapped in the gate oxide 110.
Slope 2 represents the charge mobility in the channel 106 for the
conventional MOSFET of FIG. 1B having electrons 117 trapped in the
gate oxide 110 near the drain region 104. As shown by a comparison
of slope 1 and slope 2 in FIG. 1C, the electrons 117 trapped in the
gate oxide 110 near the drain region 104 of the conventional MOSFET
do not significantly change the charge mobility in the channel
106.
[0040] There are two components to the effects of stress and hot
electron injection. One component includes a threshold voltage
shift due to the trapped electrons and a second component includes
mobility degradation due to additional scattering of carrier
electrons caused by this trapped charge and additional surface
states. When a conventional MOSFET degrades, or is "stressed," over
operation in the forward direction, electrons do gradually get
injected and become trapped in the gate oxide near the drain. In
this portion of the conventional MOSFET there is virtually no
channel underneath the gate oxide. Thus the trapped charge
modulates the threshold voltage and charge mobility only
slightly.
[0041] The inventors have previously described programmable memory
devices and functions based on the reverse stressing of MOSFET's in
a conventional CMOS process and technology in order to form
programmable address decode and correction. (See generally, L.
Forbes, W. P. Noble and E. H. Cloud, "MOSFET technology for
programmable address decode and correction," application Ser. No.
09/383804). That disclosure, however, did not describe write once
read only memory solutions, but rather address decode and
correction issues. The inventors also describe write once read only
memory cells employing charge trapping in gate insulators for
conventional MOSFETs and write once read only memory employing
floating gates. The same are described in co-pending, commonly
assigned U.S. patent applications, entitled "Write Once Read Only
Memory Employing Charge Trapping in Insulators," attorney docket
no. 1303.052US1, Ser. No. ______, and "Write Once Read Only Memory
Employing Floating Gates," attorney docket no. 1303.051US1, Ser.
No. ______. The present application, however, describes floating
gate transistor cells having oxide-conductor nanolaminate layers
and used in integrated circuit device structures.
[0042] According to the teachings of the present invention, normal
flash memory cells can be programmed by operation in the reverse
direction and utilizing avalanche hot electron injection to trap
electrons on the floating gate of the floating gate transistor.
When the programmed floating gate transistor is subsequently
operated in the forward direction the electrons trapped on the
floating gate cause the channel to have a different threshold
voltage. The novel programmed floating gate transistors of the
present invention conduct significantly less current than
conventional flash cells which have not been programmed. These
electrons will remain trapped on the floating gate unless negative
control gate voltages are applied. The electrons will not be
removed from the floating gate when positive or zero control gate
voltages are applied. Erasure can be accomplished by applying
negative control gate voltages and/or increasing the temperature
with negative control gate bias applied to cause the trapped
electrons on the floating gate to be re-emitted back into the
silicon channel of the MOSFET.
[0043] FIG. 2A is a diagram of an embodiment for a programmed
floating gate transistor cell 201 having oxide-conductor
nanolaminate layers according to the teachings of the present
invention. As shown in FIG. 2A the floating gate transistor cell
201 includes a floating gate transistor in a substrate 200 which
has a first source/drain region 202, a second source/drain region
204, and a channel region 206 between the first and second
source/drain regions, 202 and 204. In one embodiment, the first
source/drain region 202 includes a source region 202 for the
floating gate transistor cell 201 and the second source/drain
region 204 includes a drain region 204 for the floating gate
transistor cell 201. FIG. 2A further illustrates the floating gate
transistor cell 201 having oxide-conductor nanolaminate layers 208
serving as a floating gate 208 and separated from the channel
region 206 by a first gate oxide 210. An sourceline or array plate
212 is coupled to the first source/drain region 202 and a
transmission line 214 is coupled to the second source/drain region
204. In one embodiment, the transmission line 214 includes a bit
line 214. Further as shown in FIG. 2A, a control gate 216 is
separated from the oxide-conductor nanolaminate layers 208, or
floating gate 208, by a second gate oxide 218.
[0044] As stated above, floating gate transistor cell 201
illustrates an embodiment of a programmed floating gate transistor.
This programmed floating gate transistor has a charge 217 trapped
in potential wells in the oxide-conductor nanolaminate layers 208,
or floating gate 208, formed by the different electron affinities
of the insulators 208, 210 and 218. In one embodiment, the charge
217 trapped on the floating gate 208 includes a trapped electron
charge 217.
[0045] FIG. 2B is a diagram suitable for explaining the method by
which the oxide-conductor nanolaminate layers 208, or floating gate
208, of the floating gate transistor cell 201 of the present
invention can be programmed to achieve the embodiments of the
present invention. As shown in FIG. 2B the method includes
programming the floating gate transistor. Programming the floating
gate transistor includes applying a first voltage potential V1 to a
drain region 204 of the floating gate transistor and a second
voltage potential V2 to the source region 202.
[0046] In one embodiment, applying a first voltage potential V1 to
the drain region 204 of the floating gate transistor includes
grounding the drain region 204 of the floating gate transistor as
shown in FIG. 2B. In this embodiment, applying a second voltage
potential V2 to the source region 202 includes biasing the array
plate 212 to a voltage higher than VDD, as shown in FIG. 2B. A gate
potential VGS is applied to the control gate 216 of the floating
gate transistor. In one embodiment, the gate potential VGS includes
a voltage potential which is less than the second voltage potential
V2, but which is sufficient to establish conduction in the channel
206 of the floating gate transistor between the drain region 204
and the source region 202. As shown in FIG. 2B, applying the first,
second and gate potentials (V1, V2, and VGS respectively) to the
floating gate transistor creates a hot electron injection into the
oxide-conductor nanolaminate layers 208, or floating gate 208, of
the floating gate transistor. In other words, applying the first,
second and gate potentials (V1, V2, and VGS respectively) provides
enough energy to the charge carriers, e.g. electrons, being
conducted across the channel 206 that, once the charge carriers are
near the source region 202, a number of the charge carriers get
excited into the oxide-conductor nanolaminate layers 208. Here the
charge carriers become trapped in potential wells in the
oxide-conductor nanolaminate layers 208 formed by the different
electron affinities of the insulators 208, 210 and 218.
[0047] In an alternative embodiment, applying a first voltage
potential V1 to the drain region 204 of the floating gate
transistor includes biasing the drain region 204 of the floating
gate transistor to a voltage higher than VDD. In this embodiment,
applying a second voltage potential V2 to the source region 202
includes grounding the sourceline or array plate 212. A gate
potential VGS is applied to the control gate 216 of the floating
gate transistor. In one embodiment, the gate potential VGS includes
a voltage potential which is less than the first voltage potential
V1, but which is sufficient to establish conduction in the channel
206 of the floating gate transistor between the drain region 204
and the source region 202. Applying the first, second and gate
potentials (V1, V2, and VGS respectively) to the floating gate
transistor creates a hot electron injection into the
oxide-conductor nanolaminate layers 208 of the floating gate
transistor. In other words, applying the first, second and gate
potentials (V1, V2, and VGS respectively) provides enough energy to
the charge carriers, e.g. electrons, being conducted across the
channel 206 that, once the charge carriers are near the drain
region 204, a number of the charge carriers get excited into the
oxide-conductor nanolaminate layers 208, or floating gate 208. Here
the charge carriers become trapped in potential wells in the
oxide-conductor nanolaminate layers 208 formed by the different
electron affinities of the insulators 208, 210 and 218, as shown in
FIG. 2A.
[0048] In one embodiment of the present invention, the method is
continued by subsequently operating the floating gate transistor in
the forward direction in its programmed state during a read
operation. Accordingly, the read operation includes grounding the
source region 202 and precharging the drain region a fractional
voltage of VDD. If the device is addressed by a wordline coupled to
the gate, then its conductivity will be determined by the presence
or absence of stored charge in the oxide-conductor nanolaminate
layers 208, or floating gate 208. That is, a gate potential can be
applied to the gate 216 by a wordline 220 in an effort to form a
conduction channel between the source and the drain regions as done
with addressing and reading conventional DRAM cells.
[0049] However, now in its programmed state, the conduction channel
206 of the floating gate transistor will have a higher voltage
threshold and will not conduct.
[0050] FIG. 2C is a graph plotting a current signal (IDS) detected
at the second source/drain region 204 versus a voltage potential,
or drain voltage, (VDS) set up between the second source/drain
region 204 and the first source/drain region 202 (IDS vs. VDS). In
one embodiment, VDS represents the voltage potential set up between
the drain region 204 and the source region 202. In FIG. 2C, the
curve plotted as D1 represents the conduction behavior of a
conventional floating gate transistor which is not programmed
according to the teachings of the present invention. The curve D2
represents the conduction behavior of the programmed floating gate
transistor, described above in connection with FIG. 2A, according
to the teachings of the present invention. As shown in FIG. 2C, for
a particular drain voltage, VDS, the current signal (IDS2) detected
at the second source/drain region 204 for the programmed floating
gate transistor (curve D2) is significantly lower than the current
signal (IDS1) detected at the second source/drain region 204 for
the conventional floating gate transistor cell which is not
programmed according to the teachings of the present invention.
Again, this is attributed to the fact that the channel 206 in the
programmed floating gate transistor of the present invention has a
different voltage threshold.
[0051] Some of these effects have recently been described for use
in a different device structure, called an NROM, for flash
memories. This latter work in Israel and Germany is based on
employing charge trapping in a silicon nitride layer in a
non-conventional flash memory device structure. (See generally, B.
Eitan et al., "Characterization of Channel Hot Electron Injection
by the Subthreshold Slope of NROM device," IEEE Electron Device
Lett., Vol. 22, No. 11, pp. 556-558, (November 2001); B. Etian et
al., "NROM: A novel localized Trapping, 2-Bit Nonvolatile Memory
Cell," IEEE Electron Device Lett., Vol. 21, No. 11, pp. 543-545,
(November 2000)). Charge trapping in silicon nitride gate
insulators was the basic mechanism used in MNOS memory devices (see
generally, S. Sze, Physics of Semiconductor Devices, Wiley, N.Y.,
1981, pp. 504-506), charge trapping in aluminum oxide gates was the
mechanism used in MIOS memory devices (see generally, S. Sze,
Physics of Semiconductor Devices, Wiley, N.Y., 1981, pp. 504-506),
and the present inventors have previously disclosed charge trapping
at isolated point defects in gate insulators (see generally, L.
Forbes and J. Geusic, "Memory using insulator traps," U.S. Pat. No.
6,140,181, issued Oct. 31, 2000). However, none of the above
described references addressed forming floating gate transistor
cells utilizing charge trapping in potential wells in
oxide-conductor nanolaminate layers formed by the different
electron affinities of the insulators.
[0052] FIG. 3 illustrates an embodiment for a portion of a memory
array 300 according to the teachings of the present invention. The
memory in FIG. 3, is shown illustrating a number of vertical
pillars, or floating gate transistor cells, 301-1, 301-2, . . . ,
301-N, formed according to the teachings of the present invention.
As one of ordinary skill in the art will appreciate upon reading
this disclosure, the number of vertical pillar are formed in rows
and columns extending outwardly from a substrate 303. As shown in
FIG. 3, the number of vertical pillars, 301-1, 301-2, . . . ,
301-N, are separated by a number of trenches 340. According to the
teachings of the present invention, the number of vertical pillars,
301-1, 301-2, . . . , 301-N, serve as floating gate transistors
including a first source/drain region, e.g. 302-1 and 302-2
respectively. The first source/drain region, 302-1 and 302-2, is
coupled to a sourceline 304. As shown in FIG. 3, the sourceline 304
is formed in a bottom of the trenches 340 between rows of the
vertical pillars, 301-1, 301-2, . . . , 301-N. According to the
teachings of the present invention, the sourceline 304 is formed
from a doped region implanted in the bottom of the trenches 340. A
second source/drain region, e.g. 306-1 and 306-2 respectively, is
coupled to a bitline (not shown). A channel region 305 is located
between the first and the second source/drain regions.
[0053] As shown in FIG. 3, oxide-conductor nanolaminate layers or
floating gate, shown generally as 309, are separated from the
channel region 305 by a first oxide layer 307 in the trenches 340
along rows of the vertical pillars, 301-1, 301-2, . . . , 301-N. In
the embodiment shown in FIG. 3, a wordline 313 is formed across the
number of pillars and in the trenches 340 between the
oxide-conductor nanolaminate layers 309. The wordline 313 is
separated from the pillars and the oxide-conductor nanolaminate
layers 309, or floating gate 309, by a second oxide layer 317. Here
the wordline 313 serves as a control gate 313 for each pillar.
[0054] FIG. 4 illustrates an electrical equivalent circuit 400 for
the portion of the memory array shown in FIG. 3. As shown in FIG.
4, a number of vertical floating gate transistor cells, 401-1,
401-2, . . . , 401-N, are provided. Each vertical floating gate
transistor cell, 401-1, 401-2, . . . , 401-N, includes a first
source/drain region, e.g. 402-1 and 402-2, a second source/drain
region, e.g. 406-1 and 406-2, a channel region 405 between the
first and the second source/drain regions, and oxide-conductor
nanolaminate layers serving as a floating gate, shown generally as
409, separated from the channel region by a first oxide layer.
[0055] FIG. 4 further illustrates a number of bit lines, e.g. 411-1
and 411-2. According to the teachings of the present invention as
shown in the embodiment of FIG. 4, a single bit line, e.g. 411-1 is
coupled to the second source/drain regions, e.g. 406-1 and 406-2,
for a pair of floating gate transistor cells 401-1 and 401-2 since,
as shown in FIG. 3, each pillar contains two floating gate
transistor cells. As shown in FIG. 4, the number of bit lines,
411-1 and 411-2, are coupled to the second source/drain regions,
e.g. 406-1 and 406-2, along rows of the memory array. A number of
word lines, such as wordline 413 in FIG. 4, are coupled to a
control gate 412 of each floating gate transistor cell along
columns of the memory array. According to the teachings of the
present invention, a number of sourcelines, 415-1, 415-2, . . . ,
415-N, are formed in a bottom of the trenches between rows of the
vertical pillars, described in connection with FIG. 3, such that
first source/drain regions, e.g. 402-2 and 402-3, in column
adjacent floating gate transistor cells, e.g. 401-2 and 401-3,
separated by a trench, share a common sourceline, e.g. 415-1. And
additionally, the number of sourcelines, 415-1, 415-2, . . . ,
415-N, are shared by column adjacent floating gate transistor
cells, e.g. 401-2 and 401-3, separated by a trench, along rows of
the memory array 400. In this manner, by way of example and not by
way of limitation referring to column adjacent floating gate
transistor cells, e.g. 401-2 and 401-3, separated by a trench, when
one column adjacent floating gate transistor cell, e.g. 401-2, is
being read its complement column adjacent floating gate transistor
cell, e.g. 401-3, can operate as a reference cell.
[0056] FIG. 5 illustrates an energy band diagram for an embodiment
of a gate stack according to the teachings of the present
invention. As shown in FIG. 5, the embodiment consists of insulator
stacks, 501-1, 501-2 and 501-3, e.g. SiO.sub.2/oxide-conductor
nanolaminate layers/SiO.sub.2. The structure shown in FIG. 5
illustrates the present invention's use in various embodiments of
metallic conductors, doped oxide conductors, and metals as a
nanolaminate between two layers of silicon oxide.
[0057] Tantalum nitride, titanium nitride, and tungsten nitride are
mid-gap work function metallic conductors described for use in CMOS
devices. (See generally, A. Yagishita et al., "Dynamic threshold
voltage damascene metal gate MOSFET(DT-DMG-MOS) with low threshold
voltage, high drive current and uniform electrical
characteristics," Digest Technical Papers Int. Electron Devices
Meeting, San Francisco, pp. 663-666 (December 2000); H. Shimada et
al., "Tantalum nitride metal gate FD-SOI CMOS FETs using low
resistivity self-grown bcc-tantalum layer," IEEE Trans. Electron
Devices, Vol. 48, No. 8, pp. 1619-1626 (2000); M. Moriwaki et al.
"Improved metal gate process by simultaneous gate-oxide nitridation
during W/WN/sub x/gate formation," Jpn. J. Appl. Phys., Vol. 39,
No. 4B, pp. 2177-2180 (2000)). Tantalum nitride, titanium nitride,
and tungsten nitride are employed in the present invention as
oxide-conductor nanolaminate layers, formed by atomic layer
deposition (ALD). These metallic conductors have large electron
affinities around 4.7 eV which is larger than the 4.1 ev electron
affinity of silicon oxide.
[0058] In some embodiments according to the teachings of the
present invention, atomic layer deposition, ALD, of a number of
other conductors is used to form the nanolaminate structures. As
described in more detail below, the oxide-conductor nanolaminate
layers used in the present invention include:
[0059] (i) Metallic Conductors, TaN, TiN, WN, NbN, MoN
[0060] (ii) Doped Oxide Conductors, ZnOS
[0061] (iii) Metals, including tungsten, W, and Nickel, Ni
[0062] As mentioned above, Titanium nitride, tantalum nitride and
tungsten nitride are mid-gap work function metallic conductors,
with no or zero band gaps and large electron affinities as shown in
FIG. 6, commonly described for use in CMOS devices. (See generally,
A. Yagishita et al., "Dynamic threshold voltage damascene metal
gate MOSFET(DT-DMG-MOS) with low threshold voltage, high drive
current and uniform electrical characteristics," Digest Technical
Papers Int. Electron Devices Meeting, San Francisco, December 2000,
pp. 663-666; H. Shimada et al., "Tantalum nitride metal gate FD-SOI
CMOS FETs using low resistivity self-grown bcc-tantalum layer,"
IEEE Trans. Electron Devices, Vol. 48, No. 8, pp. 1619-1626, 2000;
M. Moriwaki et al. "Improved metal gate process by simultaneous
gate-oxide nitridation during W/WN/sub x/gate formation," Jpn. J.
Appl. Phys., Vol. 39. No. 4B, pp. 2177-2180, 2000).
[0063] Method of Formation
[0064] This disclosure describes the use of oxide-conductor
nanolaminate layers as floating gates to trap charge in potential
wells formed by the different electron affinities of the insulator
layers. These layers formed by ALD are of atomic dimensions, or
nanolaminates, with precisely controlled interfaces and layer
thickness. Operation of the device specifically depends on and
utilizes the electron affinity of the oxide-conductor nanolaminate
layers being higher than that of silicon oxide. This creates a
potential energy well in the multi-layer nanolaminate gate
insulator structure.
[0065] Atomic Layer Deposition of Metallic Conductors
[0066] TaN: Plasma-enhanced atomic layer deposition (PEALD) of
tantalum nitride (Ta--N) thin films at a deposition temperature of
260.degree. C. using hydrogen radicals as a reducing agent for
Tertbutylimidotris(diethy- lamido)tantalum has been described. (See
generally, Jin-Seong Park et al, "Plasma-Enhanced Atomic Layer
Deposition of Tantalum Nitrides Using Hydrogen Radicals as a
Reducing Agent," Electrochemical and Solid-State Lett.). The PEALD
yielded superior Ta--N films with an electric resistivity of 400
.mu..OMEGA.cm and no aging effect under exposure to air. The film
density is higher than that of Ta--N films formed by typical ALD,
in which NH.sub.3 is used instead of hydrogen radicals. In
addition, the as-deposited films are not amorphous, but rather
polycrystalline structure of cubit TaN. The density and
crystallinity of the films increased with the pulse time of
hydrogen plasma. The films are Ta-rich in composition and contain
around 15 atomic % of carbon impurity. In the PEALD of Ta--N films,
hydrogen radicals are used a reducing agent instead of NH.sub.3,
which is used as a reactant gas in typical Ta--N ALD. Films are
deposited on SiO.sub.2 (100 nm)/Si wafers at a deposition
temperature of 260.degree. C. and a deposition pressure of 133 Pa
in a cold-walled reactor using (Net.sub.2).sub.3Ta=Nbu.sup.t
[tertbutylimidotris(diethylamido)tantalum, TBTDET] as a precursor
of Ta. The liquid precursor is contained in a bubbler heated at
70.degree. C. and carried by 35 sccm argon. One deposition cycle
consist of an exposure to a metallorganic precursor of TBTDET, a
purge period with Ar, and an exposure to hydrogen plasma, followed
by another purge period with Ar. The Ar purge period of 15 seconds
instead between each reactant gas pulse isolates the reactant gases
from each other. To ignite and maintain the hydrogen plasma
synchronized with the deposition cycle, a rectangular shaped
electrical power is applied between the upper and lower electrode.
The showerhead for uniform distribution of the reactant gases in
the reactor, capacitively coupled with an rf (13.56 MHz) plasma
source operated at a power of 100 W, is used, as the upper
electrode. The lower electrode, on which a wafer resides, is
grounded. Film thickness and morphology are analyzed by field
emission scanning electron microscopy.
[0067] TiN: Atomic layer deposition (ALD) of amorphous TiN films on
SiO2 between 170.degree. C. and 210.degree. C. has been achieved by
the alternate supply of reactant sources, Ti[N(C2H5CH3)2]4
[tetrakis(ethylmethylamino)titanium:TEMAT] and NH3. These reactant
sources are injected into the reactor in the following order: TEMAT
vapor pulse, Ar gas pulse, NH3 gas pulse and Ar gas pulse. Film
thickness per cycle saturated at around 1.6 monolayers per cycle
with sufficient pulse times of reactant sources at 200.degree. C.
The results suggest that film thickness per cycle could exceed 1
ML/cycle in ALD, and are explained by the rechemisorption mechanism
of the reactant sources. An ideal linear relationship between
number of cycles and film thickness has been confirmed. (See
generally, J.-S. Min et al., "Atomic layer deposition of TiN films
by alternate supply on Tetrakis (ethylmethyllamino)titanium and
ammonia," Jpn. J. Appl. Phys., Vol. 37, Part 1, No. 9A, pp.
4999-5004 (Sep. 15, 1998)).
[0068] TiN and TaN: Deposition of thin and conformal copper films
of has been examined using atomic layer deposition, ALD, of TiN and
TaN as possible seed layer for subsequent electro-deposition. (See
generally, Raj Solanki et al., "Atomic Layer Deposition of Copper
Seed Layers," Electrochemical and Solid-State Letters, 3 (10)
479-480 (2000)). The copper films are deposited on glass as well as
Ta, TIN, and TaN films on Si wafers. Typical resistivities of these
films range from 4.25 .mu..OMEGA.cm for 20 nm thick copper films to
1.78 .mu..OMEGA.cm for 120 nm thick films. The adhesion of the
copper films deposited on TiN and TaN at 300.degree. C. is
excellent. These films are highly conformal over high aspect ratio
trenches.
[0069] TiN, TaN.sub.x, NbN, and MoN.sub.x: Atomic layer deposition
of Tin, TaN.sub.x, NbN, and MoN.sub.x thin films from the
corresponding metal chlorides and 1,1-dimethyl-hydrazine (DMHy)
have been studied. (See generally, Marika Juppo et al., "Use of
1,1-Dimethylhydrazine in the Atomic Layer Deposition of Transition
Metal Nitride Thin Films," Jour. of the Electrochemical Soc., 147
(9) 3377-3381 (2000)). Generally, the same films deposited at
400.degree. C. exhibit better characteristics compared to the films
deposited at the same temperature using NH.sub.3 as the nitrogen
source. In addition, films can be deposited at lower temperatures
down to 200.degree. C. Even though the carbon content in the films
is quite high, in the range of 10 atom %, the results encourage
further studies. The effect of carbon on the barrier properties and
the use of other possibly less carbon-contaminating hydrazine
derivatives can be considered.
[0070] WN: Tungsten nitride films have been deposited with atomic
layer control using sequential surface reactions. The tungsten
nitride film growth is accomplished by separating the binary
reaction 2WF.sub.6+NH.sub.3->W.sub.2N+3HF+9/2 F.sub.2 into two
half-reactions. (See generally, Kraus, J. W. et al., "Atomic layer
deposition of tungsten nitride films using sequential surface
reactions," Jour. of the Electrochemical Soc., Vol. 147, No. 3,
1173-1181 (2000)). Successive application of the WF.sub.6 and
NH.sub.3 half-reactions in an ABAB . . . sequence produce tungsten
nitride deposition at substrate temperatures between 600 and 800 K.
Transmission Fourier transform infrared (FTIR) spectroscopy has
been used to monitor the coverage of WF.sub.x* and NH.sub.y*
surface species on high surface area particles during the WF.sub.6
and NH.sub.3 half-reactions. The FTIR spectroscope results
demonstrate the WF.sub.6 and NH.sub.3 half-reactions are complete
and self-limiting at temperatures >600 K. In situ spectroscopic
ellipsometry has been used to monitor the film growth on Si(100)
substrate vs. temperature and reactant exposure. A tungsten nitride
deposition rate of 2.55 .ANG./AB cycle is measured at 600-800 K for
WF.sub.6 and NH.sub.3 reactant exposure >3000 L and 10,000 L,
respectively. X-ray photoelectron spectroscopy depth-profiling
experiments have been used to determine that the films had a
W.sub.2N stoichiometry with low C and O impurity concentrations.
X-ray diffraction investigations reveal that the tungsten nitride
films are microcrystalline. Atomic force microscopy measurements of
the deposited films illustrate remarkably flat surface indicating
smooth film growth. These smooth tungsten nitride films deposited
with atomic layer have been be used as diffusion control for Cu on
contact and via holes.
[0071] Atomic Layer Deposition of Doped Oxide Conductors
[0072] ZnO: ZnO can be deposited by ALD. The aim of previous
experiments is to improve the performance of Cd-free
ZnO/Cu(InGa)Se.sub.2 solar cells using a high-resistivity ZnO
buffer layer. (See generally, Suticai Chaitsak et al,
"Cu(InGa)Se.sub.2 Thin-Film Solar Cells with High Resistivity ZnO
Buffer Layers Deposited by Atomic Layer Deposition," Jpn. J. Appl.
Phys., Vol. 38, pp. 4989-4992 (1999)). Buffer layers are deposited
by atomic layer deposition (ALD) using diethylzinc (DEZn) and
H.sub.2O as reactant gases. The structural and electrical
properties of the ZnO films on glass substrates have been
characterized. A high resistivity of more than 10.sup.3 .OMEGA.cm
and a transmittance of above 80% in the visible range were
obtained. Suticai Chaitsak et al. focused on determining the
optimum deposition parameters for the ALD-ZnO buffer layer. Results
indicate that the thickness and resistivity of the ALD-ZnO buffer
layer, as well as the heat treatment prior to the deposition of the
buffer layer, affect the device characteristics. The best
efficiency obtained with an ALD-ZnO buffer layer of solar cells
without an antireflective coating is 12.1%. The reversible light
soaking effect is observed in these devices. ZoO itself however is
highly resistive, doping ZnO as described below is required to make
it conductive and useful here.
[0073] ZnOS: The chemical vapor atomic layer deposition technique
is used to deposit thin films of ZnO.sub.1-xS.sub.x on glass and
silicon substrates. (See generally, B. W. Sanders et al, "Zinc
Oxysulfide Thin Films Grown by Atomic Layer Deposition," Chem.
Mater. 1992, 4, 1005-1011). Film composition is varied from x=0 to
x=0.95, and measurements of bandgap and resistivity yielded
surprising minima at x.about.0.6. Results of Rutherford
backscattering, X-ray, and luminescence measurements are also
presented. Both one- and two phase films are visible in scanning
electron microcopy, and an amorphous phases is also apparent. A
continuously variable mixed film is not observed due to the large
lattice mismatch between ZnO and ZnS. Films of ZnO.sub.1-xS.sub.x
are deposited using dimethyzinc, 1% hydrogen sulfide in nitrogen,
and the trace oxygen and/or water present (up to 2 ppm) in
ultrahigh-purity (UHP) nitrogen. The dimethyzinc is contained in a
stainless steel cylinder equipped with a dip tube. To lower the
dimethylzinc vapor pressure, the cylinder is held at 273 K using an
ice water bath. Prepurified nitrogen served as a carrier gas for
the dimethylzinc. Gas pressure are given in the table below:
1 Nitrogen flush pressure 50 psig Dimethylzinc cylinder pressure 50
psig Hydrogen sulfide cylinder pressure 30, 50, or 70 psig
Dimethylzinc reaction time 2 s Hydrogen sulfide reaction time 5 s
Nitrogen purge times 11 s at a standard flow rate of 1 L/mm Delay
to allow nitrogen back- 0 8 s pressure to drop
[0074] The electrical resistivity, mobility, and carrier
concentration results from Hall measurements on some samples are
given in the following table:
2 X in Resistivity, Donor concentration, Mobility,
ZnO.sub.1-xS.sub.x .OMEGA. cm cm.sup.-3 cm.sup.2/V s 0 0.0048 4.8
.times. 10.sup.19 13.2 0.25 0.101 1.7 .times. 10.sup.18 36.1 0.56
0.042 1.66 .times. 10.sup.19 32.2 0.66 1.28 2.0 .times. 10.sup.17
24 0.82 8.27 2.4 .times. 10.sup.16 28 0.92 67.9 2.61 .times.
10.sup.15 94
[0075] Atomic Layer Deposition of Metal Films
[0076] W: The atomic layer deposition (ALD) of tungsten (W) films
has been demonstrated using alternate exposure of tungsten
hexafluoride (WF.sub.6) and disilane (Si.sub.2H.sub.6). (See
generally, Elam, J. W. et al., "Kinetics of the WF.sub.6 and
Si.sub.2H.sub.6 surface reactions during tungsten atomic layer
deposition," Surface Science, Vol. 479, No. 1-3, pp. 121-135
(2001)). The present investigation explored the kinetics of the
WF.sub.6 and Si.sub.2H.sub.6 surface reactions during W ALD at
303-623 K using Auger electron spectroscopy technique. The reaction
of WF.sub.6 with the Si.sub.2H.sub.6-saturated W surface proceeded
to completion at 373-573 Kelvin (K). The WF.sub.6 reaction
displayed a reactive sticking coefficient of S=0.4 and required an
exposure of 30 L (1 L=1*10.sup.-6 Torr s) to achieve saturation at
573 K. The WF.sub.6 exposures necessary to reach saturation
increased with decreasing temperature. At surface temperatures
<373 K, the WF.sub.6 reaction did not consume all the silicon
(Si) surface species remaining from the previous Si.sub.2H.sub.6
exposure. The reaction of Si.sub.2H.sub.6 with the
WF.sub.6-saturated W surface displayed three kinetic regimes. In
the first region at slow Si.sub.2H.sub.6 exposures < or =50 L,
the Si.sub.2H.sub.6 reaction is independent of temperature and had
a reactive striking coefficient of S.about.5*10.sup.-2. In the
second kinetic region at intermediate Si.sub.2H.sub.6 exposure of
50-300 L, the Si.sub.2H.sub.6 reaction showed an apparent
saturation behavior with Si thickness at saturation at increased at
substrate temperature. At high Si.sub.2H.sub.6 exposures of
300-1*10.sup.5/L, additional Si is deposited with an approximately
logarithmic dependence on Si.sub.2H.sub.6 exposure. The
Si.sub.2H.sub.6 reaction in this third kinetic region had an
activation energy E=2.6 kcal/mol and the Si thickness deposited by
a 1.6*10.sup.5 L Si.sub.2H.sub.6 exposure increased with
temperature from 3.0 .ANG. at 303 K to 6.6 .ANG. at 623 K. These
kinetic results should help to explain W ALD growth rates observed
at different exposures and substrate temperatures.
[0077] Ni: A thin film of elementary nickel is formed by atomic
layer deposition (ALD). (See generally, Junghun Chea et al.,
"Atomic Layer Deposition of Nickel by the Reduction of Preformed
Nickel Oxide," Electrochemical and Solid-State Letters, 5, (6)
C4-C66 (2002)). The deposition cycle consisted of two consecutive
chemical reaction steps: an oxidizing step and a reducing step. An
atomic layer of nickel oxide is made by sequentially supplying
bis(cyclopentadienyl)-nickel as a nickel precursor and water as an
oxidation agent; the preformed atomic layer of nickel oxide is then
reduced to elementary nickel metal by exposure to hydrogen radical
at a deposition temperature of 165.degree. C. Auger electron
spectroscopy analysis detected negligible oxygen content in the
grown films, indicating that the hydrogen radical had completely
reduced the nickel oxide to metallic film films. In addition,
carbon impurities in the film dropped from 16 atomic % to less than
5 atomic % during the reaction. The proposed two-stage ALD method
for elementary metal is successful in forming continuous and
conformal nickel films. The nickel films formed an effective glue
layer between chemical vapor deposited copper and diffusion barrier
layer of TiN. The addition of a 1 .mu.m thick copper film to a 15
nm thick nickel glue layer over a TiN barrier film is excellent,
with no failures occurring during adhesive tape peel tests.
[0078] Memory Devices
[0079] This disclosure describes a flash memory device,
programmable logic array device or memory address and decode
correction device with a conductor nanolaminate floating gate
rather than a conventional polysilicon floating gate. In some
embodiments acccording to the teachings of the present invention,
the gate insulator structure shown in FIG. 5 is employed in a wide
variety of different flash memory type devices. That is, in
embodiments of the present invention, the gate structure embodiment
of FIG. 5, having silicon oxide-conductor-silicon
oxide-nanolaminates, is used in place of the gate structure
provided in the following commonly assigned patents: U.S. Pat. Nos.
5,936,274; 6,143,636; 5,973,356; 6,238,976; 5,991,225; 6,153,468;
and 6,124,729.
[0080] In embodiments of the present invention, the gate structure
embodiment of FIG. 5, having silicon oxide-conductor silicon
oxide-nanolaminates, is used in place of the gate structure
provided in the following commonly assigned pending applications:
Forbes, L., "Write once read only memory based on DRAM technology
employing charge trapping in gate insulators," application Ser. No.
______; Forbes, L., "Write once read only memory based on a
modification of DRAM technology employing floating gates,"
application Ser. No. ______; Forbes, L., "Write once read only
memory with long retention for archival storage," application Ser.
No. ______; Forbes, L., "Nanoncrystal write once read only memory
with long retention for archival storage," application Ser. No.
______; Forbes, L., "Ferroelectric write once read only memory with
long retention for archival storage," application Ser. No. ______;
Forbes, L., "Vertical NROM 1F.sup.2/bit flash memory cell,"
application Ser. No. ______; Forbes, L., "Multistate NROM with
<<1F.sup.2/bit storage density," application Ser. No. ______;
Forbes, L., "NOR flash memory cell with high storage density,"
application Ser. No. ______.
[0081] According to the teachings of the present invention,
embodiments of the novel floating gate transistor herein, which are
substituted for the gate structures described in the references
above, are programmed by grounding a source line and applying a
gate voltage and a voltage to the drain to cause channel hot
electron injection. To read the memory state, the drain and ground
or source have the normal connections and the conductivity of the
floating gate transistor determined using low voltages so as not to
disturb the memory state. The devices can be erased by applying a
large negative voltage to the gate.
[0082] In embodiments of the present invention, the gate structure
embodiment of FIG. 5, having silicon oxide-conductor-silicon
oxide-nanolaminates, is used in place of the gate structure
provided in the following commonly assigned patents: U.S. Pat. Nos.
5,936,274, 6,143,636, 5,973,356 and 6,238,976 (vertical flash
memory devices with high density); U.S. Pat. Nos. 5,991,225 and
6,153,468 (programmable memory address and decode circuits); and
U.S. Pat. No. 6,124,729 (programmable logic arrays).
[0083] Further, in embodiments of the present invention, the gate
structure embodiment of FIG. 5, having silicon oxide-metal
oxide-silicon oxide-conductor nanolaminates, is used in place of
the gate structure provided in the following U.S. patents: Eitan,
B. et al., "NROM: A novel localized Trapping, 2-Bit Nonvolatile
Memory Cell," IEEE Electron Device Lett., 21(11), 543-545 (November
2000); Eitan, B. et al., "Characterization of Channel Hot Electron
Injection by the Subthreshold Slope of NROM device, IEEE Electron
Device Lett., 22(11), 556-558 (November 2001); Maayan, E. et al.,
"A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate,"
Dig. IEEE Int. Solid-State Circuits Conf., 100-101 (2002). In these
embodiments, the gate structure embodiment of FIG. 5, having
silicon oxide-metal oxide-silicon oxide-conductor nanolaminates
used in place of the gate structures in those references, can be
programmed in the reverse direction and read in the forward
direction to obtain more sensitivity in the device characteristics
to the stored charge.
[0084] All of the above references are incorporated herein in full.
The gate structure embodiment of FIG. 5, having silicon
oxide-conductor-silicon oxide-nanolaminates, are herein used in
place of the gate structure provided in those references to support
the various embodiments of the present invention. That is, the
present invention incorporates the multitude of device structures
described in those references to create a multitude of new
embodiments which utilize electron trapping in potential wells
formed by the floating gate oxide-conductor nanolaminate structure
shown in FIG. 5, rather than employing other floating gates, as
recited in many of the above references.
[0085] Sample Operation
[0086] FIGS. 7A-B and 8 are embodiments useful in illustrating the
use of charge storage in the oxide-conductor nanolaminate layers to
modulate the conductivity of the floating gate transistor cell
according to the teachings of the present invention. That is, FIGS.
7A-7B illustrates the operation of an embodiment for a novel
floating gate transistor cell 701 formed according to the teachings
of the present invention. And, FIG. 8 illustrates the operation of
a conventional DRAM cell 701. As shown in FIG. 7A, the embodiment
consists of a gate insulator stack having insulator layers, 710,
708 and 718, e.g. 1. SiO.sub.2/oxide-conductor nanolaminate
layers/SiO.sub.2. In the embodiment of FIG. 7A, the gate insulator
stack having insulator layers, 710, 708 and 718, is made thicker
than in a conventional DRAM cell, e.g. 801 and is equal to or
greater than 10 nm or 100 .ANG. (10.sup.-6 cm). In the embodiment
shown in FIG. 7A a floating gate transistor cell is illustrated
having dimensions of 0.1 .mu.m (10.sup.-5 cm) by 0.1 .mu.m. The
capacitance, Ci, of the structure depends on the dielectric
constant, .di-elect cons..sub.1, (given here as
0.3.times.10.sup.-12 F/cm), and the thickness of the insulating
layers, t, (given here as 10.sup.-6 cm), such that Ci=.di-elect
cons.i/t, Farads/cm.sup.2 or 3.times.10.sup.-7 F/cm.sup.2. In one
embodiment, a charge of 10.sup.12 electrons/cm.sup.2 is programmed
into the oxide-conductor nanolaminate layers of the floating gate
transistor cell. Here the charge carriers become trapped in
potential wells in the oxide-conductor nanolaminate layers 708
formed by the different electron affinities of the insulators 710,
708 and 718, as shown in FIG. 7A. This produces a stored charge
.DELTA.Q=10.sup.12 electrons/cm.sup.2.times.1.6.times.10.sup.-19
Coulombs. In this embodiment, the resulting change in the threshold
voltage (.DELTA.Vt) of the floating gate transistor cell will be
approximately 0.5 Volts (.DELTA.Vt=.DELTA.Q/Ci or
1.6.times.10.sup.-7/3.times.10.sup.-7=1/2 Volt). For
.DELTA.Q=10.sup.12 electrons/cm.sup.3 in the dimensions given
above, this embodiment of the present invention involves trapping a
charge of approximately 100 electrons in the oxide-conductor
nanolaminate layers 708 of the floating gate transistor cell.
[0087] FIG. 7B aids to further illustrate the conduction behavior
of the novel floating gate transistor cell of the present
invention. As one of ordinary skill in the art will understand upon
reading this disclosure, if the floating gate transistor cell is
being driven with a control gate voltage of 1.0 Volt (V) and the
nominal threshold voltage without the floating gate charged is 1/2
V, then if the oxide-conductor nanolaminate layers are charged the
floating gate transistor cell of the present invention will be off
and not conduct. That is, by trapping a charge of approximately 100
electrons in the oxide-conductor nanolaminate layers of the
floating gate transistor cell, having dimensions of 0.1 .mu.m
(10.sup.-5 cm) by 0.1 .mu.m, will raise the threshold voltage of
the floating gate transistor cell to 1.0 Volt and a 1.0 Volt
control gate potential will not be sufficient to turn the device
on, e.g. Vt=1.0 V, I=0.
[0088] Conversely, if the nominal threshold voltage without the
oxide-conductor nanolaminate layers charged is 1/2 V, then
I=.mu.C.sub.ox.times.(W/L).times.((Vgs-Vt).sup.2/2), or 12.5 .mu.A,
with .mu.C.sub.ox=.mu.C.sub.1=100 .mu.A/V.sup.2 and W/L=1. That is,
the floating gate transistor cell of the present invention, having
the dimensions describe above will produce a current I=100
.mu.A/V.sup.2.times.(1/4).times.(1/2)=12.5 .mu.A. Thus, in the
present invention an un-written, or un-programmed floating gate
transistor cell can conduct a current of the order 12.5 .mu.A,
whereas if the oxide-conductor nanolaminate layers are charged then
the floating gate transistor cell will not conduct. As one of
ordinary skill in the art will understand upon reading this
disclosure, the sense amplifiers used in DRAM arrays, and as
describe above, can easily detect such differences in current on
the bit lines.
[0089] By way of comparison, in a conventional DRAM with 30
femtoFarad (fF) storage capacitors charged to 50 femtoColumbs (fC),
if these are read over 5 nS then the average current on the bit
line is only 10 .mu.A. This is illustrated in connection with FIG.
8. As shown in FIG. 8, storing a 50 fC charge on the storage
capacitor equates to storing 300,000 electrons.
[0090] According to the teachings of the present invention, the
floating gate transistor cells, having the gate structure with
oxide-conductor nanolaminate layers, in the array are utilized not
just as passive on or off switches as transfer devices in DRAM
arrays but rather as active devices providing gain. In the present
invention, to program the floating gate transistor cell "off,"
requires only a stored charge in the oxide-conductor nanolaminate
layers of about 100 electrons if the area is 0.1 .mu.m by 0.1
.mu.m. And, if the floating gate transistor cell is un-programmed,
e.g. no stored charge trapped in the oxide-conductor nanolaminate
layers, and if the floating gate transistor cell is addressed over
10 nS a current of 12.5 .mu.A is provided. The integrated drain
current then has a charge of 125 fC or 800,000 electrons. This is
in comparison to the charge on a DRAM capacitor of 50 fC which is
only about 300,000 electrons. Hence, the use of floating gate
transistor cells, having the gate structure with oxide-conductor
nanolaminate layers, in the array as active devices with gain,
rather than just switches, provides an amplification of the stored
charge, in the oxide-conductor nanolaminate layers, from 100 to
800,000 electrons over a read address period of 10 nS.
[0091] Sample Device Applications
[0092] In FIG. 9 a memory device is illustrated according to the
teachings of the present invention. The memory device 940 contains
a memory array 942, row and column decoders 944, 948 and a sense
amplifier circuit 946. The memory array 942 consists of a plurality
of floating gate transistor cells 900, having oxide-conductor
nanolaminate layers in the gate stack, whose word lines 980 and bit
lines 960 are commonly arranged into rows and columns,
respectively. The bit lines 960 of the memory array 942 are
connected to the sense amplifier circuit 946, while its word lines
980 are connected to the row decoder 944. Address and control
signals are input on address/control lines 961 into the memory
device 940 and connected to the column decoder 948, sense amplifier
circuit 946 and row decoder 944 and are used to gain read and write
access, among other things, to the memory array 942.
[0093] The column decoder 948 is connected to the sense amplifier
circuit 946 via control and column select signals on column select
lines 962. The sense amplifier circuit 946 receives input data
destined for the memory array 942 and outputs data read from the
memory array 942 over input/output (I/O) data lines 963. Data is
read from the cells of the memory array 942 by activating a word
line 980 (via the row decoder 944), which couples all of the memory
cells corresponding to that word line to respective bit lines 960,
which define the columns of the array. One or more bit lines 960
are also activated. When a particular word line 980 and bit lines
960 are activated, the sense amplifier circuit 946 connected to a
bit line column detects and amplifies the conduction sensed through
a given floating gate transistor cell and transferred to its bit
line 960 by measuring the potential difference between the
activated bit line 960 and a reference line which may be an
inactive bit line. Again, in the read operation the source region
of a given cell is couple to a grounded sourceline or array plate
(not shown). The operation of Memory device sense amplifiers is
described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and
5,042,011, all assigned to Micron Technology Inc., and incorporated
by reference herein.
[0094] FIG. 10 shows a conventional NOR-NOR logic array 1000 which
is programmable at the gate mask level by either fabricating a thin
oxide gate transistor, e.g. logic cells 1001-1, 1001-2, . . . ,
1001-N and 1003-1, 1003-2, . . . , 1003-N, at the intersection of
lines in the array or not fabricating a thin oxide gate transistor,
e.g. missing thin oxide transistors, 1002-1, 1002-2, . . . ,
1002-N, at such an intersection. As one of ordinary skill in the
art will understand upon reading this disclosure, the same
technique is conventionally used to form other types of logic
arrays not shown. As shown in FIG. 10, a number of depletion mode
NMOS transistors, 1016 and 1018 respectively, are used as load
devices.
[0095] The conventional logic array shown in FIG. 10 includes a
first logic plane 1010 which receives a number of input signals at
input lines 1012. In this example, no inverters are provided for
generating complements of the input signals. However, first logic
plane 1010 can include inverters to produce the complementary
signals when needed in a specific application.
[0096] First logic plane 1010 includes a number of thin oxide gate
transistors, e.g. transistors 1001-1, 1001-2, . . . , 1001-N. The
thin oxide gate transistors, 1001-1, 1001-2, . . . , 1001-N, are
located at the intersection of input lines 1012, and interconnect
lines 1014. In the conventional PLA of FIG. 10, this selective
fabrication of thin oxide gate transistor, e.g. transistors 1001-1,
1001-2, . . . , 1001-N, is referred to as programming since the
logical function implemented by the programmable logic array is
entered into the array by the selective arrangement of the thin
oxide gate transistors, or logic cells, 1001-1, 1001-2, . . . ,
1001-N, at the intersections of input lines 1012, and interconnect
lines 1014 in the array.
[0097] In this embodiment, each of the interconnect lines 1014 acts
as a NOR gate for the input lines 1012 that are connected to the
interconnect lines 1014 through the thin oxide gate transistors,
1001-1, 1001-2, . . . , 1001-N, of the array. For example,
interconnection line 1014A acts as a NOR gate for the signals on
input lines 1012A and 1012B. That is, interconnect line 1014A is
maintained at a high potential unless one or more of the thin oxide
gate transistors, 1001-1, 1001-2, . . . , 1001-N, that are coupled
to interconnect line 1014A are turned on by a high logic level
signal on one of the input lines 1012. When a control gate address
is activated, through input lines 1012, each thin oxide gate
transistor, e.g. transistors 1001-1, 1001-2, . . . , 1001-N,
conducts which performs the NOR positive logic circuit function, an
inversion of the OR circuit function results from inversion of data
onto the interconnect lines 1014 through the thin oxide gate
transistors, 1001-1, 1001-2, . . . , 1001-N, of the array.
[0098] As shown in FIG. 10, a second logic plane 1024 is provided
which includes a number of thin oxide gate transistor, e.g.
transistors 1003-1, 1003-2, . . . , 1003-N. The thin oxide gate
transistors, 1003-1, 1003-2, . . . , 1003-N, are located at the
intersection of interconnect lines 1014, and output lines 1020.
Here again, the logical function of the second logic plane 1024 is
implemented by the selective arrangement of the thin oxide gate
transistors, 1003-1, 1003-2, . . . , 1003-N, at the intersections
of interconnect lines 1014, and output lines 1020 in the second
logic plane 1024. The second logic plane 1024 is also configured
such that the output lines 1020 comprise a logical NOR function of
the signals from the interconnection lines 1014 that are coupled to
particular output lines 1020 through the thin oxide gate
transistors, 1003-1, 1003-2, . . . , 1003-N, of the second logic
plane 1024. Thus, in FIG. 10, the incoming signals on each line are
used to drive the gates of transistors in the NOR logic array as
the same is known by one of ordinary skill in the art and will be
understood by reading this disclosure.
[0099] FIG. 11 illustrates an embodiment of a novel in-service
programmable logic array (PLA) formed with logic cells having a
floating gate structure with oxide-conductor nanolaminate layers,
according to the teachings of the present invention. In FIG. 11,
PLA 1100 implements an illustrative logical function using a two
level logic approach. Specifically, PLA 1100 includes first and
second logic planes 1110 and 1122. In this example, the logic
function is implemented using NOR-NOR logic. As shown in FIG. 11,
first and second logic planes 1110 and 1122 each include an array
of, logic cells, having a gate structure with oxide-conductor
nanolaminate layers, which serve as driver floating gate
transistors, 1101-1, 1101-2, . . . , 1101-N, and 1102-1, 1102-2, .
. . , 1102-N respectively, formed according to the teachings of the
present invention. The driver floating gate transistors, 1101-1,
1101-2, . . . , 1101-N, and 1102-1, 1102-2, . . . , 1102-N, have
their first source/drain regions coupled to source lines or a
conductive source plane. These driver floating gate transistors,
1101-1, 1101-2, . . . , 1101-N, and 1102-1, 1102-2, . . . , 1102-N
are configured to implement the logical function of FPLA 1100. The
driver floating gate transistors, 1101-1, 1101-2, . . . , 1101-N,
and 1102-1, 1102-2, . . . , 1102-N are shown as n-channel floating
gate transistors. However, the invention is not so limited. Also,
as shown in FIG. 11, a number of p-channel metal oxide
semiconductor (PMOS) floating gate transistors are provided as load
device floating gate transistors, 1116 and 1124 respectively,
having their source regions coupled to a voltage potential (VDD).
These load device floating gate transistors, 1116 and 1124
respectively, operate in complement to the driver floating gate
transistors, 1101-1, 1101-2, . . . , 1101-N, and 1102-1, 1102-2, .
. . , 1102-N to form load inverters.
[0100] It is noted that the configuration of FIG. 11 is provided by
way of example and not by way of limitation. Specifically, the
teachings of the present application are not limited to
programmable logic arrays in the NOR-NOR approach. Further, the
teachings of the present application are not limited to the
specific logical function shown in FIG. 11. Other logical functions
can be implemented in a programmable logic array, with the driver
floating gate transistors, having a gate structure with
oxide-conductor nanolaminate layers, 1101-1, 1101-2, . . . ,
1101-N, and 1102-1, 1102-2, . . . , 1102-N and load device floating
gate transistors, 1116 and 1124 respectively, of the present
invention, using any one of the various two level logic
approaches.
[0101] First logic plane 1110 receives a number of input signals at
input lines 1112. In this example, no inverters are provided for
generating complements of the input signals. However, first logic
plane 1110 can include inverters to produce the complementary
signals when needed in a specific application.
[0102] First logic plane 1110 includes a number of driver floating
gate transistors, having a gate structure with oxide-conductor
nanolaminate layers, 1101-1, 1101-2, . . . , 1101-N, that form an
array. The driver floating gate transistors, 1101-1, 1101-2, . . .
, 1101-N, are located at the intersection of input lines 1112, and
interconnect lines 1114. Not all of the driver floating gate
transistors, 1101-1, 1101-2, . . . , 1101-N, are operatively
conductive in the first logic plane. Rather, the driver floating
gate transistors, 1101-1, 1101-2, . . . , 1101-N, are selectively
programmed, as has been described herein, to respond to the input
lines 1112 and change the potential of the interconnect lines 1114
so as to implement a desired logic function. This selective
interconnection is referred to as programming since the logical
function implemented by the programmable logic array is entered
into the array by the driver floating gate transistors, 1101-1,
1101-2, . . . , 1101-N, that are used at the intersections of input
lines 1112, and interconnect lines 1114 in the array.
[0103] In this embodiment, each of the interconnect lines 1114 acts
as a NOR gate for the input lines 1112 that are connected to the
interconnect lines 1114 through the driver floating gate
transistors, 1101-1, 1101-2, . . . , 1101-N, of the array 1100. For
example, interconnection line 1114A acts as a NOR gate for the
signals on input lines 1112A, 1112B and 1112C. Programmability of
the driver floating gate transistors, 1101-1, 1101-2, . . . ,
1101-N is achieved by trapping charge carriers in potential wells
in the oxide-conductor nanolaminate layers of the gate stack, as
described herein. When the oxide-conductor nanolaminate layers are
charged, that driver floating gate transistor, 1101-1, 1101-2, . .
. , 1101-N will remain in an off state until it is reprogrammed.
Applying and removing a charge to the oxide-conductor nanolaminate
layers, is performed by tunneling charge into the oxide-conductor
nanolaminate layers of the driver floating gate transistors,
1101-1, 1101-2, . . . , 1101-N. A driver floating gate transistors,
1101-1, 1101-2, . . . , 1101-N programmed in an off state remains
in that state until the charge is removed from the oxide-conductor
nanolaminate layers.
[0104] Driver floating gate transistors, 1101-1, 1101-2, . . . ,
1101-N not having their corresponding gate structure with
oxide-conductor nanolaminate layers charged operate in either an on
state or an off state, wherein input signals received by the input
lines 1112A, 1112B and 1112C determine the applicable state. If any
of the input lines 1112A, 1112B and 1112C are turned on by input
signals received by the input lines 1112A, 1112B and 1112C, then a
ground is provided to load device floating gate transistors 1116.
The load device floating gate transistors 1116 are attached to the
interconnect lines 1114. The load device floating gate transistors
1116 provide a low voltage level when any one of the driver
floating gate transistors, 1101-1, 1101-2, . . . , 1101-N connected
to the corresponding interconnect line 1114 is activated. This
performs the NOR logic circuit function, an inversion of the OR
circuit function results from inversion of data onto the
interconnect lines 1114 through the driver floating gate
transistors, 1101-1, 1101-2, . . . , 1101-N of the array 1100. When
the driver floating gate transistors, 1101-1, 1101-2, . . . ,
1101-N are in an off state, an open is provided to the drain of the
load device floating gate transistors 1116. The VDD voltage level
is applied to corresponding input lines, e.g. the interconnect
lines 1114 for second logic plane 1122 when a load device floating
gate transistors 1116 is turned on by a clock signal received at
the gate of the load device floating gate transistors 1116. Each of
the driver floating gate transistors, 1101-1, 1101-2, . . . ,
1101-N described herein are formed according to the teachings of
the present, having a gate structure with oxide-conductor
nanolaminate layers.
[0105] In a similar manner, second logic plane 1122 comprises a
second array of driver floating gate transistors, 1102-1, 1102-2, .
. . , 1102-N that are selectively programmed to provide the second
level of the two level logic needed to implement a specific logical
function. In this embodiment, the array of driver floating gate
transistors, 1102-1, 1102-2, . . . , 1102-N is also configured such
that the output lines 1120 comprise a logical NOR function of the
signals from the interconnection lines 1114 that are coupled to
particular output lines 1120 through the driver floating gate
transistors, 1102-1, 1102-2, . . . , 1102-N of the second logic
plane 1122.
[0106] Programmability of the driver floating gate transistors,
1102-1, 1102-2, . . . , 1102-N is achieved by trapping charge
carriers in potential wells in the oxide-conductor nanolaminate
layers of the gate stack, as described herein. When the
oxide-conductor nanolaminate layers are charged, that driver
floating gate transistor, 1102-1, 1102-2, . . . , 1102-N will
remain in an off state until it is reprogrammed. Applying and
removing a charge to the oxide-conductor nanolaminate layers are
performed by tunneling charge into the oxide-conductor nanolaminate
layers of the driver floating gate transistors, 1101-1, 1101-2, . .
. , 1101-N. A driver floating gate transistor, e.g. 1102-1, 1102-2,
. . . , 1102-N, programmed in an off state remains in that state
until the charge is removed from the oxide-conductor nanolaminate
layers.
[0107] Driver floating gate transistors, 1102-1, 1102-2, . . . ,
1102-N not having their corresponding gate structure with
oxide-conductor nanolaminate layers charged operate in either an on
state or an off state, wherein signals received by the interconnect
lines 1114 determine the applicable state. If any of the
interconnect lines 1114 are turned on, then a ground is provided to
load device floating gate transistors 1124 by applying a ground
potential to the source line or conductive source plane coupled to
the floating gate transistors first source/drain region as
described herein. The load device floating gate transistors 1124
are attached to the output lines 1120. The load device floating
gate transistors 1124 provide a low voltage level when any one of
the driver floating gate transistors, 1102-1, 1102-2, . . . ,
1102-N connected to the corresponding output line is activated.
This performs the NOR logic circuit function, an inversion of the
OR circuit function results from inversion of data onto the output
lines 1120 through the driver floating gate transistors, 1102-1,
1102-2, . . . , 1102-N of the array 1100. When the driver floating
gate transistors, 1102-1, 1102-2, . . . , 1102-N are in an off
state, an open is provided to the drain of the load device floating
gate transistors 1124. The VDD voltage level is applied to
corresponding output lines 1120 for second logic plane 1122 when a
load device floating gate transistor 1124 is turned on by a clock
signal received at the gate of the load device floating gate
transistors 1124. In this manner a NOR-NOR electrically
programmable logic array is most easily implemented utilizing the
normal PLA array structure. Each of the driver floating gate
transistors, 1102-1, 1102-2, . . . , 1102-N described herein are
formed according to the teachings of the present, having a gate
structure with oxide-conductor nanolaminate layers.
[0108] Thus FIG. 11 shows an embodiment for the application of the
novel floating gate transistor cells, having a gate structure with
oxide-conductor nanolaminate layers, in a logic array. If a driver
floating gate transistors, 1101-1, 1101-2, . . . , 1101-N, and
1102-1, 1102-2, . . . , 1102-N, is programmed with a negative
charge trapped in potential wells, formed with the oxide-conductor
nanolaminate layers, it is effectively removed from the array. In
this manner the array logic functions can be programmed even when
the circuit is in the final circuit or in the field and being used
in a system.
[0109] The absence or presence of charge trapped in potential
wells, formed by the oxide-conductor nanolaminate layers, is read
by addressing the input lines 1112 or control gate lines and
y-column/sourcelines to form a coincidence in address at a
particular logic cell. The control gate line would for instance be
driven positive at some voltage of 1.0 Volts and the
y-column/sourceline grounded, if the oxide-conductor nanolaminate
layers are not charged with electrons then the floating gate
transistor would turn on tending to hold the interconnect line on
that particular row down indicating the presence of a stored "one"
in the cell. If this particular floating gate transistor cell has
charge trapped in potential wells, formed by the oxide-conductor
nanolaminate layers, the floating gate transistor will not turn on
and the presence of a stored "zero" is indicated in the cell. In
this manner, data stored on a particular floating gate transistor
cell can be read.
[0110] Programming can be achieved by hot electron injection. In
this case, the interconnect lines, coupled to the second
source/drain region for the floating gate transistor cells in the
first logic plane, are driven with a higher drain voltage like 2
Volts for 0.1 micron technology and the control gate line is
addressed by some nominal voltage in the range of twice this value.
Erasure is accomplished by driving the control gate line with a
large positive voltage and the sourceline and/or backgate or
substrate/well address line of the floating gate transistor with a
negative bias so the total voltage difference is in the order of 3
Volts causing electrons to tunnel out of the oxide-conductor
nanolaminate layers of the driver floating gate transistors.
Writing can be performed, as also described above, by normal
channel hot electron injection
[0111] One of ordinary skill in the art will appreciate upon
reading this disclosure that a number of different configurations
for the spatial relationship, or orientation of the input lines
1112, interconnect lines 1114, and output lines 1120 are
possible.
[0112] FIG. 12 is a block diagram of an electrical system, or
processor-based system, 1200 utilizing floating gate transistor
cells with a gate structure having oxide-conductor nanolaminate
layers. By way of example and not by way of limitation, memory 1212
is constructed in accordance with the present invention to have
floating gate transistor cells with a gate structure having
oxide-conductor nanolaminate layers. The same applies to floating
gate transistors in the CPU, etc., the invention is not so limited.
The processor-based system 1200 may be a computer system, a process
control system or any other system employing a processor and
associated memory. The system 1200 includes a central processing
unit (CPU) 1202, e.g., a microprocessor, that communicates with the
NOR flash memory 1212 and an I/O device 1208 over a bus 1220. It
must be noted that the bus 1220 may be a series of buses and
bridges commonly used in a processor-based system, but for
convenience purposes only, the bus 1220 has been illustrated as a
single bus. A second I/O device 1210 is illustrated, but is not
necessary to practice the invention. The processor-based system
1200 can also includes read-only memory (ROM) 1214 and may include
peripheral devices such as a floppy disk drive 1204 and a compact
disk (CD) ROM drive 1206 that also communicates with the CPU 1202
over the bus 1220 as is well known in the art.
[0113] It will be appreciated by those skilled in the art that
additional circuitry and control signals can be provided, and that
the memory device 1200 has been simplified to help focus on the
invention. In one embodiment, at least one of the floating gate
transistor cells, having a gate structure with oxide-conductor
nanolaminate layers in memory 1212 includes a programmed floating
gate transistor cell according to the teachings of the present
invention.
[0114] It will be understood that the embodiment shown in FIG. 12
illustrates an embodiment for electronic system circuitry in which
the novel floating gate transistor cells of the present invention
are used. The illustration of system 1200, as shown in FIG. 12, is
intended to provide a general understanding of one application for
the structure and circuitry of the present invention, and is not
intended to serve as a complete description of all the elements and
features of an electronic system using the novel floating gate
transistor cell structures. Further, the invention is equally
applicable to any size and type of memory device 1200 using the
novel floating gate transistor cells of the present invention and
is not intended to be limited to that described above. As one of
ordinary skill in the art will understand, such an electronic
system can be fabricated in single-package processing units, or
even on a single semiconductor chip, in order to reduce the
communication time between the processor and the memory device.
[0115] Applications containing the novel floating gate transistor
cell of the present invention as described in this disclosure
include electronic systems for use in memory modules, device
drivers, power modules, communication modems, processor modules,
and application-specific modules, and may include multilayer,
multichip modules. Such circuitry can further be a subcomponent of
a variety of electronic systems, such as a clock, a television, a
cell phone, a personal computer, an automobile, an industrial
control system, an aircraft, and others.
Conclusion
[0116] This disclosure describes the use of oxide-conductor
nanolaminate layers as floating gates to trap charge in potential
wells formed by the different electron affinities of the
oxide-conductor nanolaminate layers. That is, this disclosure
describes a flash memory device, programmable logic array device or
memory address and decode correction device with a conductor
nanolaminate floating gate rather than a conventional polysilicon
floating gate.
[0117] It is to be understood that the above description is
intended to be illustrative, and not restrictive. Many other
embodiments will be apparent to those of skill in the art upon
reviewing the above description. The scope of the invention should,
therefore, be determined with reference to the appended claims,
along with the full scope of equivalents to which such claims are
entitled.
* * * * *
References