U.S. patent application number 10/404630 was filed with the patent office on 2003-11-27 for extracting semiconductor device model parameters.
Invention is credited to Chen, Ping, Xie, Jushan.
Application Number | 20030220779 10/404630 |
Document ID | / |
Family ID | 29553369 |
Filed Date | 2003-11-27 |
United States Patent
Application |
20030220779 |
Kind Code |
A1 |
Chen, Ping ; et al. |
November 27, 2003 |
Extracting semiconductor device model parameters
Abstract
The present invention includes a method for extracting
semiconductor device model parameters for a device model such as
the BSIMPD model. The method comprises obtaining terminal current
data corresponding to various bias conditions in a set of test
devices and extracting a portion of a plurality of DC model
parameters for the device model from the terminal current data. The
terminal current are then modified based on the extracted portion
of the DC model parameters before extracting additional DC model
parameters. The present invention also includes novel methods for
extracting some of the DC model parameters.
Inventors: |
Chen, Ping; (San Jose,
CA) ; Xie, Jushan; (Campbell, CA) |
Correspondence
Address: |
Pennie & Edmonds, LLP
3300 Hillview Avenue
Palo Alto
CA
94304
US
|
Family ID: |
29553369 |
Appl. No.: |
10/404630 |
Filed: |
March 31, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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60368599 |
Mar 29, 2002 |
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Current U.S.
Class: |
703/14 ;
703/22 |
Current CPC
Class: |
G06F 30/367
20200101 |
Class at
Publication: |
703/14 ;
703/22 |
International
Class: |
G06F 017/50; G06F
009/45 |
Claims
What is claimed:
1. A method for extracting semiconductor device model parameters,
comprising: obtaining terminal current data corresponding to
various bias conditions in a set of test devices; extracting first
and second current related parameters from the terminal current
data; modifying the terminal current data using said extracted
first current related parameters and second current related
parameters; and extracting additional DC parameters from the
modified terminal current data.
2. The method of claim 1, wherein extracting additional DC
parameters further comprises: extracting voltage related
parameters; using the extracted voltage related parameters to
extract length related parameters, and first and second resistance
related parameters; additionally using said extracted first and
second resistance related parameters to extract mobility related
parameters and width related parameters; additionally using said
extracted mobility and width related parameters to extract
sub-threshold region related parameters; using the extracted
voltage related parameters to extract drain induced barrier lower
related parameters; and using the extracted voltage related
parameters, length related parameters, first and second resistance
related parameters, mobility related parameters, width related
parameters, sub-threshold region related parameters, and drain
induced barrier lower related parameters to extract drain
saturation current related parameters.
3. A method for extracting semiconductor device model parameters
comprising: obtaining terminal current data corresponding to
various bias conditions in a set of test devices; extracting
I.sub.diode related parameters and I.sub.bjt related parameters
from the terminal current data; modifying the terminal current data
using the extracted I.sub.diode related parameters and I.sub.bjt
related parameters; and extracting additional DC parameters from
the modified terminal current data.
4. The method of claim 4, wherein extracting additional DC
parameters further comprises: extracting V.sub.th related
parameters; using the extracted V.sub.th related parameters to
extract L.sub.eff related parameters, R.sub.d related parameters
and R.sub.s related parameters; using the extracted V.sub.th
related parameters, L.sub.eff related parameters, R.sub.d related
parameters and R.sub.s related parameters to extract mobility
related parameters and W.sub.eff related parameters; using the
extracted V.sub.th related parameters, L.sub.eff related
parameters, R.sub.d related parameters, R.sub.s related parameters,
mobility related parameters and W.sub.eff related parameters to
extract sub-threshold region related parameters; using the
extracted V.sub.th related parameters to extract drain induced
barrier lower related parameters; and using the extracted V.sub.th
related parameters, L.sub.eff related parameters, R.sub.d related
parameters, R.sub.s related parameters, mobility related parameters
and W.sub.eff related parameters, sub-threshold region related
parameters, and drain induced barrier lower related parameters to
extract I.sub.dsat related parameters.
5. The method of claim 3, wherein extracting additional DC
parameters further comprises: extracting junction related
parameters.
6. The method of claim 3, wherein the terminal current data
comprises I.sub.d v. V.sub.gs curves, and wherein extracting
I.sub.diode related parameters further comprises: extracting
J.sub.sbjt and n.sub.dio using a middle part of at least one
I.sub.d v. V.sub.gs curve measured in a largest device among the
set of test devices; extracting R.sub.body using high current parts
of I.sub.d v. V.sub.gs curves measured in test devices having
different sizes; and extracting n.sub.recf and j.sub.srec using one
or more I.sub.d v. V.sub.gs curves measured in a shortest device
among the set of test devices.
7. The method of claim 3, wherein extracting I.sub.bjt related
parameters further comprises: constructing from the terminal
current data a set of I.sub.c/I.sub.p v. V.sub.gs curves for a
shortest device; and extracting L.sub.n using the set of
I.sub.c/I.sub.p v. V.sub.gs curves.
8. The method of claim 3, wherein extracting additional DC
parameters comprises: extracting I.sub.ii related parameters;
9. The method of claim 8, wherein the terminal current data
comprises I.sub.p v. V.sub.gs curves and I.sub.d v. V.sub.gs
curves, and wherein extracting I.sub.ii related parameters further
comprises: constructing a set of I.sub.ii/I.sub.d V. V.sub.gs
curves from I.sub.p v. V.sub.gs curves and I.sub.d v. V.sub.gs
curves measured in a shortest device and modified using the
extracted I.sub.diode related parameters and I.sub.bjt related
parameters; extracting .alpha..sub.0, .beta..sub.0, .beta..sub.1,
and .beta..sub.2 using the constructed I.sub.ii/I.sub.d v. V.sub.gs
curves; extracting V.sub.dsatii by averaging over an array of
V.sub.dsatii values, the array of V.sub.dsatii values being
obtained by finding a point in each I.sub.ii/I.sub.d v. V.sub.gs
curve where I.sub.p/I.sub.d=.alpha..sub.0; and extracting L.sub.ii
using the array of V.sub.dsatii values.
10. The method of claim 9, further comprising: optimizing the
extracted .alpha..sub.0, .beta..sub.0, .beta..sub.1, .beta..sub.2,
V.sub.dsatii, and L.sub.ii parameters
11. A method for extracting semiconductor device model parameters
comprising: obtaining terminal current data corresponding to
various bias conditions in a set of test devices; extracting
I.sub.dgid1 related parameters, I.sub.sdig1 related parameters, and
I.sub.g related parameters from the terminal current data;
modifying the terminal current data using the extracted I.sub.dgid1
related parameters, I.sub.sdig1 related parameters, and I.sub.g
related parameters; and extracting additional DC parameters from
the modified terminal current data.
12. The method of claim 11, wherein obtaining terminal current data
further comprises: obtaining measured terminal current data
corresponding to various bias conditions in a set of test devices;
extracting I.sub.diode related parameters and I.sub.bjt related
parameters from the terminal current data; and modifying the
measured terminal current data using the extracted I.sub.diode
related parameters and I.sub.bjt related parameters.
13. The method of claim 11, wherein extracting additional DC
parameters further comprises: extract L.sub.eff related parameters,
R.sub.d related parameters and R.sub.s related parameters; using
the extracted L.sub.eff related parameters, R.sub.d related
parameters and R.sub.s related parameters to extract mobility
related parameters and W.sub.eff related parameters; using the
extracted L.sub.eff related parameters, R.sub.d related parameters,
R.sub.s related parameters, mobility related parameters and
W.sub.eff related parameters to extract sub-threshold region
related parameters; and using the extracted L.sub.eff related
parameters, R.sub.d related parameters, R.sub.s related parameters,
mobility related parameters, W.sub.eff related parameters, and
sub-threshold region related parameters to extract I.sub.dsat
related parameters
14. The method of claim 11, wherein extracting additional DC
parameters comprises: extracting junction related parameters.
15. A method of extracting I.sub.diode related parameters for
modeling a SOI MOSFET device, comprising: obtaining terminal
current data corresponding to various bias conditions in a set of
test devices, the terminal current data including I.sub.d v.
V.sub.ps curves; extracting J.sub.sbjt and n.sub.dio using a middle
part of at lease one I.sub.d v. V.sub.ps curve measured in a
largest device among the set of test devices; extracting R.sub.body
using high current parts of the I.sub.d v. V.sub.ps curves measured
in test devices having different sizes; and extracting n.sub.recf
and j.sub.srec using I.sub.d v. V.sub.ps curves measured in a
shortest device among the set of test devices.
16. A method of extracting I.sub.bjt related parameters for
modeling a SOI MOSFET device, comprising: obtaining terminal
current data corresponding to various bias conditions in a set of
test devices, the terminal current data including I.sub.d v.
V.sub.ps curves; constructing from the terminal current data a set
of I.sub.c/I.sub.p v. V.sub.ps curves for a shortest device; and
extracting L.sub.n using the set of I.sub.c/I.sub.p v. V.sub.ps
curves.
17. A method of extracting I.sub.ii related parameters for modeling
a SOI MOSFET device, comprising: obtaining terminal current data
corresponding to various bias conditions in a set of test devices,
the terminal current data including I.sub.p v. V.sub.gs curves and
I.sub.d v. V.sub.gs curves; constructing a set of I.sub.ii/I.sub.d
v. V.sub.gs curves from I.sub.p v. V.sub.gs curves and I.sub.d v.
V.sub.gs curves measured in a shortest device; extracting
.alpha..sub.0, .beta..sub.0, .beta..sub.1, and .beta..sub.2 using
the constructed I.sub.ii/I.sub.d v. V.sub.gs curves; extracting
V.sub.dsatii by averaging over an array of V.sub.dsatii values, the
array of V.sub.dsatii values being obtained by finding a point in
each I.sub.ii/I.sub.d v. V.sub.gs curve where
I.sub.p/I.sub.d=.alpha..sub.0; and extracting L.sub.ii using the
array of V.sub.dsatii values.
18. A computer program product for use in conjunction with a
computer system, the computer program product comprising a computer
readable storage medium and a computer program mechanism embedded
therein, the computer program mechanism comprising: logic for
obtaining terminal current data corresponding to various bias
conditions in a set of test devices; logic for extracting first and
second current related parameters from the terminal current data;
logic for modifying the terminal current data using said extracted
first current related parameters and second current related
parameters; and logic for extracting additional DC parameters from
the modified terminal current data.
19. The computer program product of claim 18, wherein the logic for
extracting additional DC parameters further comprises: logic for
extracting voltage related parameters; logic for using the
extracted voltage related parameters to extract length related
parameters, and first and second resistance related parameters;
logic for additionally using said extracted first and second
resistance related parameters to extract mobility related
parameters and width related parameters; logic for additionally
using said extracted mobility and width related parameters to
extract sub-threshold region related parameters; logic for using
the extracted voltage related parameters to extract drain induced
barrier lower related parameters; and logic for using the extracted
voltage related parameters, length related parameters, first and
second resistance related parameters, mobility related parameters,
width related parameters, sub-threshold region related parameters,
and drain induced barrier lower related parameters to extract drain
saturation current related parameters.
20. A system for extracting semiconductor device model parameters,
comprising: a central processing unit (CPU); a port or I/O device
communicating with the central processing unit to provide terminal
current data to the CPU corresponding to various bias conditions in
a set of test devices; a memory communicating with the CPU and
containing instructions executable by the CPU to extract
I.sub.diode related parameters and I.sub.bjt related parameters
from said terminal current data, to modify said terminal current
data based on the extracted I.sub.diode and I.sub.bjt related
parameters and to extract additional DC parameters based on said
modified terminal current data.
21. The system according to claim 20, wherein said memory further
contains instructions executable by the CPU to: extract V.sub.th
related parameters; use the extracted V.sub.th related parameters
to extract L.sub.eff related parameters, R.sub.d related parameters
and R.sub.s related parameters; use the extracted V.sub.th related
parameters, L.sub.eff related parameters, R.sub.d related
parameters and R.sub.s related parameters to extract mobility
related parameters and W.sub.eff related parameters; use the
extracted V.sub.th related parameters, L.sub.eff related
parameters, R.sub.d related parameters, R.sub.s related parameters,
mobility related parameters and W.sub.eff related parameters to
extract sub-threshold region related parameters; use the extracted
V.sub.th related parameters to extract drain induced barrier lower
related parameters; and use the extracted V.sub.th related
parameters, L.sub.eff related parameters, R.sub.d related
parameters, R.sub.s related parameters, mobility related
parameters, W.sub.eff related parameters, sub-threshold region
related parameters, and drain induced barrier lower related
parameters to extract I.sub.dsat related parameters.
22. The system of claim 20, wherein the terminal current data
comprises I.sub.d v. V.sub.ps curves, and wherein the instructions
for extracting I.sub.diode related parameters comprise instructions
to: extract J.sub.sbjt and n.sub.dio using a middle part of I.sub.d
v. V.sub.ps curves measured in a largest device among the set of
test devices; extract R.sub.body using a high current part of the
I.sub.d v. V.sub.ps curves measured in test devices having
different sizes; and extract n.sub.recf and j.sub.srec using
I.sub.d v. V.sub.ps curves measured in a shortest device among the
set of test devices.
23. The system of claim 20, wherein the instructions for extracting
I.sub.bjt related parameters comprise instructions to: construct
from the terminal current data a set of I.sub.c/I.sub.p v. V.sub.ps
curves for a shortest device; and extract L.sub.n using the set of
I.sub.c/I.sub.p v. V.sub.ps curves.
24. The system of claim 20, wherein the terminal current data
comprises I.sub.p v. V.sub.gs curves and I.sub.d v. V.sub.gs
curves, and wherein the instructions for extracting additional DC
parameters include instructions for extracting I.sub.ii related
parameters, and the instructions for extracting I.sub.ii related
parameters comprises instructions to: construct a set of
I.sub.ii/I.sub.d v. V.sub.gs curves from I.sub.p v. V.sub.gs curves
and I.sub.d v. V.sub.gs curves measured in a shortest device and
modified using the extracted I.sub.diode related parameters and
I.sub.bjt related parameters; extract .alpha..sub.0, .beta..sub.0,
.beta..sub.1, and .beta..sub.2 using the constructed
I.sub.ii/I.sub.d v. V.sub.gs curves; extract V.sub.dsatii by
averaging over an array of V.sub.dsatii values, the array of
V.sub.dsatii values being obtained by finding a point in each
I.sub.ii/I.sub.d v. V.sub.gs curve where
I.sub.p/I.sub.d=.alpha..sub.0; and extract L.sub.ii using the array
of V.sub.dsatii values.
Description
[0001] This patent claims priority pursuant to 35 U.S.C. .sctn.
119(e)1 to U.S. Provisional Patent Application Serial No.
60/368,599, filed Mar. 29, 2002.
FIELD OF THE INVENTION
[0002] The invention relates generally to computer-aided electronic
circuit simulation, and more particularly, to a method of
extracting semiconductor device model parameters for use in
integrated circuit simulation.
BACKGROUND OF THE INVENTION
[0003] Computer aids for electronic circuit designers are becoming
more prevalent and popular in the electronic industry. This move
toward electronic circuit simulation was prompted by the increase
in both complexity and size of circuits. As circuits have become
more complex, traditional breadboard methods have become burdensome
and overly complicated. With increased computing power and
efficiency, electronic circuit simulation is now standard in the
industry. Examples of electronic circuit simulators include the
Simulation Program with Integrated Circuit Emphasis (SPICE)
developed at the University of California, Berkeley (UC Berkeley),
and various enhanced versions or derivatives of SPICE, such as,
SPICE2 or SPICE3, also developed at UC Berkeley; HSPICE, developed
by Meta-software and now owned by Avant!; PSPICE, developed by
Micro-Sim; and SPECTRE, developed by Cadence. SPICE and its
derivatives or enhanced versions will be referred to hereafter as
SPICE circuit simulators.
[0004] SPICE is a program widely used to simulate the performance
of analog electronic systems and mixed mode analog and digital
systems. SPICE solves sets of non-linear differential equations in
the frequency domain, steady state and time domain and can simulate
the behavior of transistor and gate designs. In SPICE, any circuit
is handled in a node/element fashion; it is a collection of various
elements (resistors, capacitors, etc.). These elements are then
connected at nodes. Thus, each element must be modeled to create
the entire circuit. SPICE has built in models for semiconductor
devices, and is set up so that the user need only specify model
parameter values.
[0005] An electronic circuit may contain any variety of circuit
elements such as resistors, capacitors, inductors, mutual
inductors, transmission lines, diodes, bipolar junction transistors
(BJT), junction field effect transistors (JFET), and
metal-oxide-semiconductor field effect transistors (MOSFET), etc. A
SPICE circuit simulator makes use of built-in or plug-in models for
semiconductor device elements such as diodes, BJTs, JFETs, and
MOSFETs. If model parameter data is available, more sophisticated
models can be invoked. Otherwise, a simpler model for each of these
devices is used by default.
[0006] A model for a device mathematically represents the device
characteristics under various bias conditions. For example, for a
MOSFET device model, in DC and AC analysis, the inputs of the
device model are the drain-to-source, gate-to-source,
bulk-to-source voltages, and the device temperature. The outputs
are the various terminal currents. A device model typically
includes model equations and a set of model parameters. The model
parameters, along with the model equations in the device model,
directly affect the final outcome of the terminal currents. In
order to represent actual device performance, a successful device
model is tied to the actual fabrication process used to manufacture
the device represented. This connection is represented by the model
parameters, which are dependent on the fabrication process used to
manufacture the device.
[0007] SPICE has a variety of preset models. However, in modern
device models, such as BSIM (Berkeley Short-Channel IGFET Model)
and its derivatives, BSIM3, BSIM4, and BSIMPD (Berkeley
Short-Channel IGFET Model Partial Depletion), all developed at UC
Berkeley, only a few of the model parameters can be directly
measured from actual devices. The rest of the model parameters are
extracted using nonlinear equations with complex extraction
methods. See Daniel Foty, "MOSFET Modeling with Spice--Principles
and Practice," Prentice Hall PTR, 1997.
[0008] Since the sets of equations utilized in a modern
semiconductor device model are complex with numerous unknowns,
there is a need to extract the model parameters in the equations in
an efficient and accurate manner so that using the extracted
parameters, the model equations will closely emulate the actual
process.
SUMMARY OF THE INVENTION
[0009] The present invention includes a method for extracting
semiconductor device model parameters for a device model such as
the BSIMPD model. The device model parameters for the device model
includes a plurality of base parameters, DC model parameters,
temperature dependent related parameters, and AC parameters. The
method comprises obtaining terminal current data corresponding to
various bias conditions in a set of test devices and extracting a
first portion of the DC model parameters for the device model from
the terminal current data. The terminal current data are then first
modified based on the extracted first portion of the DC model
parameters. The method may further comprise extracting a second
portion of the DC model parameters and further modifying the
first-modified terminal current data based on the extracted second
portion of the DC model parameters. The method further comprises
extracting additional DC model parameters based on the
first-modified or the further-modified terminal current data.
[0010] The present invention also includes novel methods for
extracting the first portion of the DC model parameters, the second
portion of the DC model parameters, and some of the additional DC
model parameters, as explained in more detail below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is a block diagram of a system according to an
embodiment of the present invention;
[0012] FIG. 2 is a flow chart illustrating a modeling process in
accordance with an embodiment of the present invention;
[0013] FIG. 3A is a block diagram of a model definition input file
in accordance with an embodiment of the present invention;
[0014] FIG. 3B is a block diagram of an object definition input
file in accordance with an embodiment of the present invention;
[0015] FIG. 4 is a diagrammatic cross sectional view of a
silicon-on-insulator MOSFET device for which model parameters are
extracted in accordance with an embodiment of the present
invention;
[0016] FIG. 5 is a graph illustrating sizes of test devices used to
obtain experimental data for model parameter extraction in
accordance with an embodiment of the present invention;
[0017] FIG. 6 is a graph illustrating sizes of test devices used to
obtain experimental data for model parameter extraction in
accordance with an alternative embodiment of the present
invention;;
[0018] FIGS. 7A-7D are examples of current-voltage (I-V) curves
representing some of the terminal current data for the test
devices;
[0019] FIG. 8 is a flow chart illustrating in further detail a
parameter extraction process in accordance with an embodiment of
the present invention;
[0020] FIG. 9 is a flow chart illustrating in further detail a DC
parameter extraction process in accordance with an embodiment of
the present invention;
[0021] FIG. 10 is a flow chart illustrating a process for
extracting diode current related parameters in accordance with an
embodiment of the present invention; and
[0022] FIG. 11 is a flow chart illustrating a process for
extracting impact ionization current related parameters in
accordance with an embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0023] As shown in FIG. 1, system 100, according to one embodiment
of the invention, comprises a central processing unit (CPU) 102,
which includes a RAM, and a disk memory 110 coupled to the CPU 102
through a bus 108. The system 100 further comprises a set of
input/output (I/O) devices 106, such as a keypad, a mouse, and a
display device, also coupled to the CPU 102 through the bus 108.
The system 100 may further include an input port 104 for receiving
data from a measurement device (not shown), as explained in more
detail below. The system 100 may also include other devices 122. An
example of system 100 is a Pentium 233 PC/Compatible computer
having RAM larger than 64 MB and a hard disk larger than 1 GB.
[0024] Memory 110 has computer readable memory spaces such as
database 114 that stores data, memory space 112 that stores
operating system 112 such as Windows 95/98/NT4.0/2000, which has
instructions for communicating, processing, accessing, storing and
searching data, and memory space 116 that stores program
instructions (software) for carrying out the method of the present
invention. Memory space 116 may be further subdivided as
appropriate, for example to include memory portions 118 and 120 for
storing modules and plug-in models, respectively, of the
software.
[0025] A set of model parameters for a semiconductor device is
often referred to as a model card for the device. Together with the
model equations, the model card is used by a circuit simulator to
emulate the behavior of the semiconductor device in an integrated
circuit. A model card may be determined by process 200 as shown in
FIG. 2. Process 200 includes step 210 in which one or more input
files are loaded into the RAM of the CPU 102. The input files may
include a model definition file and an object definition file. The
object definition file provides information of the object (device)
to be simulated. The model definition file provides information
associated with the device model for modeling the behavior of the
object. These files are discussed in further detail below in
connection with FIGS. 3A and 3B.
[0026] Process 200 further includes step 220 in which the
measurement data is loaded from database 114. The measurement data
includes physical measurements from a set of test devices, as will
be explained in more detail below. Once the measurement data has
been loaded, process 200 proceeds to extract in step 230 the model
parameters. The parameter extraction step 230 is discussed in
detail in connection with FIGS. 8, 9, 10 and 11 below.
[0027] After the parameters are extracted, binning may be performed
in step 240. The binning step 240 is an optional step and it may
depend on whether the device model is binnable or not. Process 200
further includes step 250, in which the extracted model parameters
are verified. Once verified, the extracted parameters are output in
step 260 as a model card. An error report may be generated
afterwards in step 270, and the process 200 is then complete. More
detailed discussion about the binning step 240 and verification
step 250 can be found in the BSIMPro+ User Mannual--Basic
Operation, by Celestry Design Technologies, released in September,
2001, which is incorporated by reference in its entirety
herein.
[0028] Referring to FIG. 3A, the model definition file 300A
comprises a general model information field 310, a parameter
definition field 320, an intermediate variable definition field
330, and an operation point definition field 340. The general model
information field 310 includes general information about the device
model, such as a model name, a model version, a model type,
compatible circuit simulators, and binning information. The
parameter definition field 320 defines the parameters in the model.
As an example, a list of the model parameters in the BSIMPD model
are provided in Appendix A. For each parameter, the model
definition file also specifies information associated with the
parameter, such as a parameter name, a default value, a parameter
unit, a data type, and optimization information. The operation
point definition section 340 defines operation point or output
variables, such as device terminal currents, threshold voltage,
etc., used by the model.
[0029] Referring to FIG. 3B, object definition file 300B defines
object related information, including input variables 350, output
variables 360, instance variables 370, and object and node
information 380. Input variables 350 and output variables 360 are
associated with the inputs and outputs, respectively, of the device
in an integrated circuit. The instance variables 370 are associated
with the geometric characteristics of the device to be modeled. The
object node information 380 includes information regarding the
nodes or terminals of the device to be modeled.
[0030] Process 200 can be used to generate model cards for models
describing semiconductor devices such as BJTs, JFETs, and MOSFETs,
etc. Discussions about the use of some of these models can be found
in the BSIMPro+ User Mannual--Device Modeling Guide, by Celestry
Design Technologies, released in September, 2001, which is
incorporated by reference in its entirety herein. As an example,
the BSIMPD model, which was developed by UC Berkley to model
silicon-on-insulator (SOI) MOSFET devices, is used here to
illustrate the parameter extraction step 230 of the process 200.
The model equations for the BSIMPD model are provided in Appendix
B. More detailed discussion about the BSIMPD model can be found in
the BSIMPD2.2 MOSFET Model Users' Manual by the Department of
Electrical Engineering and Computer Sciences, UC Berkeley,
Copyright 1999, which is incorporated herein by reference in its
entirety.
[0031] As shown in FIG. 4, an SOI MOSFET device 400 may comprise a
thin silicon on oxide (SOI) film 480, having a thickness T.sub.si,
on top of a layer of buried oxide 460, having a thickness
T.sub.box. The SOI film 480 has two doped regions, a source 430 and
a drain 450, separated by a body region 440. The SOI MOSFET also
comprises a gate 410 on top of the body region 440 and is separated
from SOI film 480 by a thin layer of gate oxide 420. The SOI MOSFET
400 is formed on a semiconductor substrate 470.
[0032] The SOI MOSFET as described can be considered a five
terminal (node) device. The five terminals are the gate terminal
(node g), the source terminal (node s), the drain terminal (node
d), the body terminal (node p), and the substrate terminal (node
e). Nodes g, s, d, and e can be connected to different voltage
sources while node p can be connected to a voltage source or left
floating. In the floating body configuration there are four
external biases , the gate voltage (V.sub.g), the drain voltage
(V.sub.d), the source voltage (V.sub.s) and the substrate bias
V.sub.e. If body contact is applied, there will be an additional
external bias, the body contact voltage (V.sub.p).
[0033] For ease of further discussion, Table I below lists the
symbols corresponding to the physical variables associated with the
operation of SOI MOSFET device 400.
1TABLE I C.sub.pd body to drain capacitance C.sub.ps body to source
capacitance I.sub.c parasitic bipolar transistor collector current
I.sub.p current through body (p) node I.sub.bjt parasitic bipolar
junction transistor current I.sub.d current through drain (d) node
I.sub.dgidl gate induced leakage current at the drain I.sub.diode
diode current I.sub.ds current flowing from source to drain
I.sub.dsat drain saturation current I.sub.e current through
substrate (e) node I.sub.g (or J.sub.gb) gate oxide tunneling
current I.sub.gs current flowing from source to gate I.sub.ii
impact ionization current I.sub.s current through source (s) node
I.sub.sgidl gate induced drain leakage current at the source
L.sub.drawn drawn channel length L.sub.eff effective channel length
R.sub.d drain resistance R.sub.s source resistance R.sub.ds
drain/source resistance R.sub.out output resistance V.sub.b
internal body voltage V.sub.bs voltage between node p and node s
V.sub.d drain voltage V.sub.DD maximum operating DC voltage
V.sub.ds voltage between node d and node s V.sub.e substrate
voltage V.sub.g gate voltage V.sub.gs voltage between node g and
node s V.sub.p body contact voltage V.sub.s source voltage V.sub.th
threshold voltage W.sub.drawn drawn channel width W.sub.eff
effective channel width
[0034] In order to model the behavior of the SOI MOSFET device 400
using the BSIMPD model, experimental data are used to extract model
parameters associated with the model. These experimental data
include terminal current data and capacitance data measured in test
devices under various bias conditions. In one embodiment of the
present invention, the measurement is done using a conventional
semiconductor device measurement tool that is coupled to system 100
through input port 104. The measured data are thus organized by CPU
102 and stored in database 114. The test devices are typically
manufactured using the same or similar process technologies for
fabricating the SOI MOSFET device. In one embodiment of the present
invention, a set of test devices having different device sizes,
meaning different channel widths and channel lengths are used for
the measurement. The device size requirement can vary with
different applications. Ideally, as shown in FIG. 5, the set of
devices include:
[0035] a. one largest device, meaning the device with the longest
drawn channel length and widest drawn channel width that is
available, as represented by dot 502;
[0036] b. one smallest device, meaning the device with the shortest
drawn channel length and smallest drawn channel width that is
available, as represented by dot 516;
[0037] c. one device with the smallest drawn channel width and
longest drawn channel length, as represented by dot 510;
[0038] d. one device with the widest drawn channel width and
shortest drawn channel length, as represented by dot 520;
[0039] e. three devices having the widest drawn channel width and
different drawn channel lengths, as represented by dots 504, 506,
and 508;
[0040] f. two devices with the shortest drawn channel length and
different drawn channel widths, as represented by dots 512 and
514;
[0041] g. two devices with the longest drawn channel length and
different drawn channel widths, as represented by dots 522 and
524;
[0042] h. (optionally) up to three devices with smallest drawn
channel width and different drawn channel lengths, as represented
by dots 532, 534, and 536; and
[0043] i. (optionally) up to three devices with medium drawn
channel width (about halfway between the widest and smallest drawn
channel width) and different drawn channel lengths, as represented
by dots 538, 540, and 542.
[0044] If in practice, it is difficult to obtain measurements for
all of the above devices sizes, a smaller set of different sized
devices can be used. For example, the different device sizes shown
in FIG. 6 are sufficient in one embodiment of the present
invention. The test devices as shown in FIG. 6 include:
[0045] a. one largest device, meaning the device with the longest
drawn channel length and widest drawn channel width, as represented
by dot 602;
[0046] b. one smallest device, meaning the device with the shortest
drawn channel length and smallest drawn channel width, as
represented by dot 616;
[0047] c. (optional) one device with the smallest drawn channel
width and longest drawn channel length, as represented by dot
610;
[0048] d. one device with the widest drawn channel width and
shortest drawn channel length, as represented by dot 620;
[0049] e. one device and two optional devices having the widest
drawn channel width and different drawn channel lengths, as
represented by dots 604, 606, and 608, respectively;
[0050] f. (optional) two devices with the shortest drawn channel
length and different drawn channel widths, as represented by dots
612 and 614.
[0051] For each test device, terminal currents are measured under
different terminal bias conditions: These terminal current data are
put together as I-V curves representing the I-V characteristics of
the test device. In one embodiment of the present invention, for
each test device, the following I-V curves are obtained:
[0052] 1. Linear region I.sub.d vs. V.sub.gs curves for a set of
V.sub.p values. These curves are obtained by grounding the s node
and the e node, setting V.sub.d to a low value, such as 0.05V, and
for each of the set of V.sub.p values, measuring I.sub.d while
sweeping V.sub.g in step values across a range such as from 0 to
V.sub.DD.
[0053] 2. Saturation region I.sub.d vs. V.sub.gs curves for a set
of V.sub.p values. These curves are obtained by grounding the s
node and the e node, setting V.sub.d to a high value, such as
V.sub.DD, and for each of the set of V.sub.p values, measuring
I.sub.d while sweeping V.sub.g in step values across a range such
as from 0 to V.sub.DD.
[0054] 3. I.sub.d vs. V.sub.gs curves for different V.sub.d,
V.sub.p and V.sub.e values, obtained by grounding the s node, and
for each combination of V.sub.d, V.sub.p and V.sub.e values,
measuring I.sub.d while sweeping V.sub.g in step values across a
range such as from -V.sub.DD to V.sub.DD.
[0055] 4. I.sub.g vs. V.sub.gs curves for different V.sub.d,
V.sub.p and V.sub.e values, obtained by grounding the s node, and
for each combination of V.sub.d V.sub.p and V.sub.e values,
measuring I.sub.g while sweeping V.sub.g in step values across a
range such as from -V.sub.DD to V.sub.DD.
[0056] 5. I.sub.s vs. V.sub.ds curves for different V.sub.g,
V.sub.p and V.sub.e values, obtained by grounding the s node, and
for each combination of V.sub.g, V.sub.p and V.sub.e values,
measuring I.sub.s while sweeping V.sub.d in step values across a
range such as from 0 to V.sub.DD.
[0057] 6. I.sub.p vs. V.sub.gs curves for different V.sub.d,
V.sub.p and V.sub.e values, obtained by grounding the s node, and
for each combination of V.sub.d, V.sub.p and V.sub.e values,
measuring I.sub.p while sweeping V.sub.g in step values across a
range such as from -V.sub.DD to V.sub.DD.
[0058] 7. I.sub.d vs. V.sub.gs curves for different V.sub.d,
V.sub.p and V.sub.e values, obtained by grounding the s node, and
for each combination of V.sub.p, V.sub.d and V.sub.e values,
measuring I.sub.d while sweeping V.sub.g in step values across a
range such as from -V.sub.DD to V.sub.DD.
[0059] 8. I.sub.d vs. V.sub.ps curves for different V.sub.d,
V.sub.g and V.sub.e values, obtained by grounding the s node, and
for each combination of V.sub.g, V.sub.d and V.sub.e values,
measuring I.sub.d while sweeping V.sub.p in step values across a
range such as from -V.sub.DD to V.sub.DD.
[0060] 9. Floating body I.sub.d vs. V.sub.gs curves for different
V.sub.d and V.sub.e values, obtained by grounding the s node,
floating the b node, and for each combination of V.sub.d and
V.sub.e values, measuring I.sub.d while sweeping V.sub.g in step
values across a range such as from 0 to V.sub.DD.
[0061] 10. Floating body I.sub.d vs. V.sub.ds curves for different
V.sub.g and V.sub.e values, obtained by grounding the s node,
floating the b node, and for each combination of V.sub.g and
V.sub.e values, measuring I.sub.d while sweeping V.sub.d in step
values across a range such as from 0 to V.sub.DD.
[0062] As examples, FIG. 7A shows a set of linear region I.sub.d
vs. V.sub.gs curves for different V.sub.ps values, FIG. 7B shows a
set of saturation region I.sub.d vs. V.sub.gs curves for different
V.sub.ps values, FIG. 7C shows a set of I.sub.d vs. V.sub.ds curves
for different V.sub.gs values while V.sub.ps=0.5V and V.sub.es=0;
FIG. 7D shows a set of I.sub.d vs. V.sub.ds curves for different
V.sub.gs values while V.sub.ps=0.25V and V.sub.es=0.
[0063] In addition to the terminal current data, for each test
device, capacitance data are also collected from the test devices
under various bias conditions. The capacitance data can be put
together into capacitance-current (C-V) curves. In one embodiment
of the present invention, the following C-V curves are
obtained:
[0064] a. C.sub.ps vs. V.sub.ps curve obtained by grounding s node,
setting I.sub.e and I.sub.d to zero, or to very small values, and
measuring C.sub.ps while sweeping V.sub.p in step values across a
range such as from -V.sub.DD to V.sub.DD.
[0065] b. C.sub.pd vs. V.sub.ps curve obtained by grounding s node,
setting I.sub.e and I.sub.s to zero, or to very small values, and
measuring C.sub.pd while sweeping V.sub.p in step values across a
range such as from -V.sub.DD to V.sub.DD.
[0066] As shown in FIG. 8, in one embodiment of the present
invention, the parameter extraction step 230 comprises step 810 for
extracting base parameters, step 820 for extracting other DC model
parameters, step 830 for extracting temperature dependent related
parameters; and step 840 for extracting AC parameters. In step 810,
base parameters, such as V.sub.th (the threshold voltage when
V.sub.bs=0), K.sub.1 (the first order body effect coefficient), and
K.sub.2 ( the second order body effect coefficient) are extracted
based on process parameters corresponding to the process technology
used to fabricate the SOI MOSFET device to be modeled. The base
parameters are then used to extract other DC model parameters at
step 820, which is explained in more detail in connection with
FIGS. 9, 10, and 11 below.
[0067] The temperature dependent parameters are parameters that may
vary with the temperature of the device and include parameters such
as: Ktl1(temperature coefficient for threshold voltage); Ua1
(temperature coefficient for U.sub.a), and Ub1 (temperature
coefficient for U.sub.b), etc. These parameters can be extracted
using a conventional parameter extraction method.
[0068] The AC parameters are parameters associated with the AC
characteristics of the SOI MOSFET device and include parameters
such as: CLC (the constant term for the short chanel model) and
moin (the coefficient for the gate-bias dependent surface
potential), etc. These parameters can also be extracted using a
conventional parameter extraction method.
[0069] As shown in FIG. 9, the DC parameter extraction step 820
further comprises: extracting I.sub.diode related parameters (step
902); extracting I.sub.bjt related parameters (step 904);
extracting V.sub.th related parameters (step 906); extracting
I.sub.dgid1 and I.sub.sgid1 related parameters (step 908);
extracting I.sub.g (or J.sub.gb) related parameters (step 910);
extracting L.sub.eff related parameters, R.sub.d related parameters
and R.sub.s related parameters (step 912); extracting mobility
related parameters and W.sub.eff related parameters (step 914);
extracting V.sub.th geometry related parameters (step 916);
extracting sub-threshold region related parameters (step 918);
extracting parameters related to drain-induced barrier lower than
regular (DIBL) (step 920); extracting I.sub.dsat related parameters
(step 922); extracting I.sub.ii related parameters (step 924); and
extracting junction parameters (step 926).
[0070] The equation numbers below refer to the equations set forth
in Appendix B.
[0071] In step 902, parameters related to the calculation of the
diode current I.sub.diode are extracted. These parameters include,
J.sub.sbjt, n.sub.dio, R.sub.body, n.sub.recf and j.sub.srec. As
shown in more detail in FIG. 10, step 902 comprises: extracting
J.sub.sbjt and n.sub.dio (step 1010); extracting R.sub.body (step
1020); and extracting n.sub.recf and j.sub.srec (step 1030).
[0072] Model parameters J.sub.sbjt and n.sub.dio are extracted in
step 1010 from the recombination current in neutral body equations
(Equations 14.5a -14.5.f) using measured data in the middle part of
the I.sub.d vs V.sub.ps curves taken from the largest test device
(test device having longest L.sub.drawn and widest W.sub.drawn). By
using the largest device, .alpha..sub.bjt.fwdarw.0. Then, assuming
A.sub.hli=0, E.sub.hlid will also equal zero. Therefore Equations
14.5.d -14.5.f can be eliminated. The set of equations is thus
reduced to two equations (14.5.b and 14.5.c) with two unknowns,
resulting in a quick solution for J.sub.sbjt and n.sub.dio. In one
embodiment of the present invention, the middle part of an I.sub.d
vs V.sub.ps curve corresponds to the part of the I.sub.d vs
V.sub.ps curve with V.sub.ps ranging from about 0.3V to about 0.8V.
In another embodiment, the middle part of the I.sub.d vs V.sub.ps
curve corresponds to V.sub.ps ranging from about 0.4V to about
0.7V.
[0073] R.sub.body is extracted in step 1020 from the body contact
current equation (Equations 13.1-13.3) using measured data in the
high current part of the I.sub.d vs V.sub.ps curves. In one
embodiment of the present invention, the high current part of an
I.sub.d vs V.sub.ps curve corresponds to the part of the I.sub.d vs
V.sub.ps curve with V.sub.ps ranging from about 0.8V to about
1V.
[0074] The parameters n.sub.recf and j.sub.srec are extracted in
step 1030 from the recombination/trap-assisted tunneling current in
the depletion region equations (Equations 14.3.a and 14.3.b), also
using the I.sub.d vs I.sub.ps curves taken from a shortest device.
The remaining I.sub.diode related parameters are second order
parameters and may be neglected.
[0075] Referring back to FIG. 9, the parasitic lateral bipolar
junction transistor current (I.sub.bjt) related parameter L.sub.n
is extracted in step 904. In this step, a set of I.sub.c/I.sub.p v.
V.sub.ps curves are constructed from the I.sub.d vs. V.sub.ps
curves taken from a shortest device. Then the bipolar transport
factor equations (Equation 14.1) wherein
I.sub.c/I.sub.b=.alpha..sub.bjt/1-.alpha..sub.bjt are used to
extract L.sub.n.
[0076] In step 906, threshold voltage V.sub.th related parameters,
such as V.sub.th0, k1, k2, and Nch, are extracted by using the
linear I.sub.d vs V.sub.gs curves measured from the largest
device.
[0077] In step 908, parameters related to the gate-induced drain
leakage current at the drain and at the source (I.sub.dgid1) and
the gate-induced drain leakage current at the source (I.sub.sgid1,)
are extracted. The I.sub.dgid1 and I.sub.sgid1 related parameters
include parameters such as .alpha..sub.gid1 and .beta..sub.gid1,
and are extracted using the I.sub.d vs. V.sub.gs curves and
Equations 12.1 and 12.2.
[0078] In step 910 the oxide tunneling current (I.sub.g, also
designated as J.sub.gb) related parameters are extracted. The
I.sub.g related parameters include parameters such as V.sub.EvB,
.alpha..sub.gb1, .beta..sub.gb1, V.sub.gb1, V.sub.ECB,
.alpha..sub.gb2, .beta..sub.gb2, and V.sub.gb2, and are extracted
using the I.sub.g vs. V.sub.gs curves and equations 17.1a-f and
17.2 a-f.
[0079] In step 912, parameters related to the effective channel
length L.sub.eff, the drain resistance R.sub.d and source
resistance R.sub.s are extracted. The L.sub.eff, R.sub.d and
R.sub.s related parameters include parameters such as L.sub.int,
and R.sub.dsw, and are extracted using data from the linear I.sub.d
vs V.sub.gs curves as well as the extracted V.sub.th related
parameters from step 906.
[0080] In step 914, parameters related to the mobility and
effective channel width W.sub.eff, such as .mu..sub.0, U.sub.a,
U.sub.b, U.sub.c, Wint, Wri, Prwb, Wr, Prwg, R.sub.dsw, Dwg, and
Dwb, are extracted, using the linear I.sub.d vs V.sub.gs curves,
the extracted V.sub.th related parameters, L.sub.eff related
parameters, R.sub.d related parameters, and R.sub.s related
parameters from steps 906 and 912.
[0081] Steps 906, 912, and 914 can be performed using a
conventional BSIMPD model parameter extraction method. Discussion
of extracting parameters involved in these steps can be found in
the following articles: Terada K., Muta H., "A new method to
determine effective MOSFET channel length", Japan J Appl. Phys.
1979:18:953-9; Chern J., Chang P., Motta R., Godinho N., "A new
Method to determine MOSFET channel length" IEEE Trans Electron Dev
1980:ED-27:1846-8; and Hassan Md Rofigul, Liou J J, et al. "Drain
and source resistances of short-channel LDD MOSFETs," Solid-State
Electron 1997:41:778-80; which are incorporated by reference
herein.
[0082] In step 916, the threshold voltage V.sub.th geometry related
parameters, such as D.sub.VT0, D.sub.VT1, D.sub.VT2, N.sub.LX1,
D.sub.VT0W, D.sub.VT1W, D.sub.VT2W, k.sub.3, and k.sub.3b, are
extracted, using the linear I.sub.d vs V.sub.g curve, the extracted
V.sub.th related parameters, L.sub.eff related parameters, mobility
related parameters, and W.sub.eff related parameters from steps
906, 912, and 914, and Equations 3.1 to 3.10.
[0083] In step 918, sub-threshold region related parameters, such
as C.sub.it, Nfactor, V.sub.off, D.sub.dsc, and C.sub.dscd, are
extracted, using the linear I.sub.d vs V.sub.gs curves, the
extracted V.sub.th related parameters, L.sub.eff related
parameters, R.sub.d related parameters, R.sub.s related parameters,
mobility related parameters, and W.sub.eff related parameters from
steps 906, 912, and 914, and Equations 5.1 and 5.2.
[0084] In step 920, DIBL related parameters, such as D.sub.sub,
Eta0, and Etab, are extracted, using the saturation I.sub.d vs
V.sub.gs curves and the extracted V.sub.th related parameters from
step 906, and Equations 3.1 to 3.10.
[0085] In step 922, the drain saturation current I.sub.dsat related
parameters, such as B0, B1, A0, Keta, and A.sub.gs, are extracted
using the saturation I.sub.d vs V.sub.d curves, the extracted
V.sub.th related parameters, L.sub.eff related parameters, R.sub.d
related parameters, R.sub.s related parameters, mobility related
parameters, W.sub.eff related parameters, V.sub.th geometry related
parameters, sub-threshold region related parameters, and DIBL
related parameters from steps 906, 912, 914, 916, and 918, and
Equations 9.1 to 9.10.
[0086] In step 924, the impact ionization current I.sub.ii related
parameters, such as .alpha..sub.0, .beta..sub.0, .beta..sub.1,
.beta..sub.2, V.sub.dsatii, and L.sub.ii, are extracted, as
discussed in detail in connection to FIG. 11 below.
[0087] FIG. 11 is a flow chart illustrating in further detail the
extraction of the impact ionization current I.sub.ii related
parameters (step 924). In one embodiment of the present invention,
data from the I.sub.p v V.sub.gs and I.sub.d v V.sub.gs curves
measured from one or more shortest devices are used to construct
the I.sub.ii/I.sub.d vs V.sub.ds curves for the one or more
shortest devices (step 1110). This begins by identifying the point
where V.sub.gs is equal to V.sub.th for each I.sub.p v V.sub.gs
curve, which point is found by setting V.sub.gst=0. When
V.sub.gst=0, V.sub.gsstep=0. Then, using the impact ionization
current equation, Equation 11.1, the I.sub.ii/I.sub.d vs V.sub.ds
curve can be obtained.
[0088] After the I.sub.ii/I.sub.d vs V.sub.ds curve is obtained,
L.sub.ii is set to zero and V.sub.dsatti0 is set to 0.8 (the
default value). Using the I.sub.ii/I.sub.d vs V.sub.ds curve,
.beta..sub.1, .alpha..sub.0, .beta..sub.2, .beta..sub.0 are
extracted in step 1115 from the impact ionization current equation
for I.sub.ii, Equation 11.1.
[0089] In step 1120, V.sub.dsatii is interpolated from a
constructed I.sub.ii/I.sub.d vs V.sub.ds curve by identifying the
point at which I.sub.p/I.sub.d=.alpha..sub.0.
[0090] Following the interpolation, using a conventional optimizer
such as the one using the well known Newton-Raphson algorithm,
.beta..sub.1, .beta..sub.2, .beta..sub.0 are optimized in step
1125.
[0091] Step 1120 is repeated for each constructed I.sub.ii/I.sub.d
vs V.sub.ds curve. This results in an array of values for
V.sub.dsatii. Using these values for V.sub.dsatii, L.sub.ii is
extracted in step 1135 from the V.sub.dsatii equation for the
impact ionization current (Equation 11.3).
[0092] The extracted .beta..sub.1, .alpha..sub.0, .beta..sub.2,
.beta..sub.0, L.sub.ii, and V.sub.dsatti0 are optimized in step
1140 by comparing calculated and measured I.sub.ii/I.sub.d vs
V.sub.ds curves for the one or more shorted devices.
[0093] In step 1145, the extracted parameters from the I.sub.ii and
V.sub.dsatii equations are used to calculate V.sub.gsstep using
Equation 11.4 for the largest device. Then in step 1150, S.sub.ii1,
S.sub.ii2, S.sub.ii0 are determined using a local optimizer such as
the Newton-Raphson algorithm and the V.sub.gsstep equation
(Equation 11.4).
[0094] In the next step 1155, the last of the I.sub.ii related
parameters is extracted using the shortest device. In this step,
E.sub.satii is solved for by using the V.sub.gsstep equation,
Equation 11.4, and the I.sub.ii/I.sub.d vs V.sub.ds curve. The
extraction of the I.sub.ii, related parameters is then
complete.
[0095] Referring back to FIG. 9, in step 926, the junction
parameters, such as Cjswg, Pbswg, and Mjswg, are extracted using
the C.sub.ps vs. V.sub.ps and C.sub.pd vs. V.sub.ps curves, and
Equations 21.4.b.1 and 21.4.b.2.
[0096] In performing the DC parameter extraction steps (steps
901-926), it is preferred that after the I.sub.diode and I.sub.bjt
related parameters are extracted in steps 902 and 904, I.sub.diode
and I.sub.bjt are calculated based on these parameters and the
model equations. This calculation is done for the bias condition of
each data point in the measured I-V curves. The I-V curves are then
modified for a first time based on the calculated I.sub.diode and
I.sub.bjt values. In one embodiment of the present invention, the
I-V curves are first modified by subtracting the calculated
I.sub.diode and I.sub.bjt values from respective I.sub.s, I.sub.d,
and I.sub.p data values. For example, for a test device having
drawn channel length L.sub.T and drawn channel width W.sub.T, if
under the bias condition where V.sub.s=V.sub.s.sup.T,
V.sub.d=V.sub.d.sup.T, V.sub.p=V.sub.p.sup.T,
V.sub.e=V.sub.e.sup.T, and V.sub.g=V.sub.g.sup.T, the measured
drain current is I.sub.d.sup.T, then after the first modification,
the drain current will be
I.sub.d.sup.first-modified=I.sub.d.sup.T-I.sub.diode.sup.T-I.sub.bjt.sup.-
T, where I.sub.diode.sup.T and I.sub.bjt.sup.T are calculated
I.sub.diode and I.sub.bjt values, respectively, for the same test
device under the same bias condition. The first-modified I-V curves
are then used for additional DC parameter extraction. This results
in higher degree of accuracy in the extracted parameters. In one
embodiment, the I.sub.diode and I.sub.bjt related parameters are
extracted before extracting other DC parameters, so that I-V curve
modification may be done for more accurate extraction of the other
DC parameters. However, if such accuracy is not required, one can
choose not to do the above modification and the I.sub.diode and
I.sub.bjt related parameters can be extracted at any point in the
DC parameter extraction step 820.
[0097] Similalry, after the I.sub.dgid1, I.sub.sgidi1 and I.sub.g
related parameters are extracted in steps 908 and 910, I.sub.dgid1,
I.sub.sgid1 and I.sub.g are calculated based on these parameters
and the model equations. This calculation is done for the bias
condition of each data point in the measured I-V curves. The I-V
curves or the first-modified I-V curves are then modified or
further modified based on the calculated I.sub.dgid1, I.sub.sgid1
and I.sub.g values. In one embodiment of the present invention, the
I-V curves or first-modified I-V curves are modified or further
modified by subtracting the calculated I.sub.dgid1, I.sub.sgid1 and
I.sub.g values from respective measured or first-modified I.sub.s,
I.sub.d, and I.sub.p data values. For example, for a test device
having drawn channel length L.sub.T and drawn channel width
W.sub.T, if under bias condition where V.sub.s=V.sub.s.sup.T,
V.sub.d=V.sub.d.sup.T, V.sub.p=V.sub.p.sup.T,
V.sub.e=V.sub.e.sup.T, and V.sub.g=V.sub.g.sup.T, the measured
drain current is I.sub.d.sup.T, then after the above modification
or further modification, the drain current will be
I.sub.d.sup.modified=I.sub.d.sup.T-I.sub.dgid1-I.sub.sgid1-I.sub.g,
or
I.sub.d.sup.further-modified=I.sub.d.sup.first-modified-I.sub.dgid1-I.sub-
.sgid1-I.sub.g, where I.sub.dgid1, I.sub.sgid1 and I.sub.g are
calculated I.sub.dgid1, I.sub.sgid1 and I.sub.g values,
respectively, for the same test device under the same bias
condition. The modified or further modified I-V curves are then
used for additional DC parameter extraction. This results in higher
degree of accuracy in the parameters extracted afterwards. In one
embodiment the I.sub.dgid1, I.sub.sgid1 and I.sub.g related
parameters are extracted before extracting other DC parameters that
can be affected by the modifications, so that I-V curve
modification may be done for more accurate extraction of these
other DC parameters. However, if such accuracy is not required, one
can choose not to do the above modification and the I.sub.dgid1,
I.sub.sgid1 and I.sub.g related parameters can be extracted at any
point in the DC parameter extraction step 820.
[0098] The forgoing descriptions of specific embodiments of the
present invention are presented for purpose of illustration and
description. They are not intended to be exhaustive or to limit the
invention to the precise forms disclosed, obviously many
modifications and variations are possible in view of the above
teachings. The embodiments were chosen and described in order to
best explain the principles of the invention and its practical
applications, to thereby enable others skilled in the art to best
utilize the invention and various embodiments with various
modifications as are suited to the particular use contemplated.
Furthermore, the order of the steps in the method are not
necessarily intended to occur in the sequence laid out. It is
intended that the scope of the invention be defined by the
following claims and their equivalents.
* * * * *