U.S. patent application number 10/437592 was filed with the patent office on 2003-11-06 for kill index analysis for automatic defect classification in semiconductor wafers.
This patent application is currently assigned to APPLIED MATERIALS, INC.. Invention is credited to Ben-Porath, Ariel, Pnueli, Ayelet.
Application Number | 20030207519 10/437592 |
Document ID | / |
Family ID | 25237327 |
Filed Date | 2003-11-06 |
United States Patent
Application |
20030207519 |
Kind Code |
A1 |
Pnueli, Ayelet ; et
al. |
November 6, 2003 |
Kill index analysis for automatic defect classification in
semiconductor wafers
Abstract
A kill index classification method for prioritizing relational
aspects of topological defect intersections, particularly in
association with an intermediate analytical testing stage of a
multi-stage semiconductor fabrication process. The method relates
to an analysis of the geometrical relationship between
non-predetermined portion(s), generally referred to as defects, and
the surrounding predetermined topology of a conductive
semiconductor pattern, to determine the effect of defects on the
functionality and reliability of a wafer, and particularly an
examined die thereon. Further, in accordance with this geometrical
information, a preferred classification of the effects of defects
into a numerical value, the "kill index", is achieved. Preferably,
this kill index is strongly linked, correlated and related to the
damage caused by the defect to the functionality and/or reliability
of the underlying integrated circuit.
Inventors: |
Pnueli, Ayelet; (Rehovot,
IL) ; Ben-Porath, Ariel; (Rehovot, IL) |
Correspondence
Address: |
Patent Counsel, MS/2061
Legal Affairs Department
APPLIED MATERIALS, INC.
P.O. Box 450A
Santa Clara
CA
95052
US
|
Assignee: |
APPLIED MATERIALS, INC.
Santa Clara
CA
|
Family ID: |
25237327 |
Appl. No.: |
10/437592 |
Filed: |
May 13, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10437592 |
May 13, 2003 |
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09822919 |
Mar 30, 2001 |
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6605478 |
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Current U.S.
Class: |
438/200 ;
257/E21.525 |
Current CPC
Class: |
H01L 22/20 20130101 |
Class at
Publication: |
438/200 |
International
Class: |
H01L 021/332 |
Claims
What is claimed is:
1. In a semiconductor fabrication process, a kill index
classification method for prioritizing relational aspects of
topological defect intersections, said method including the steps
of a) locating a region having at least one non-predetermined
portion therein; b) determining a predetermined topology for the
region; c) calculating evaluation parameters based on the at least
one non-predetermined portion in relation to the predetermined
topology for the region; and d) assigning a kill index
classification using the calculated evaluation parameters.
2. The kill index classification method according to claim 1
wherein the step of locating a region having at least one
non-predetermined portion therein includes the steps of a1)
accepting at least one appropriate resolution image of the region;
and a2) using the at least one appropriate resolution image,
analyzing the region to determine if there is a rule violating
shaped portion located therein.
3. The kill index classification method according to claim 2
wherein the step of accepting at least one appropriate resolution
image of the region includes the steps of i) accepting a reference
image, and ii) accepting a defect image, and wherein the step of
analyzing the region to determine if there is a rule violating
shaped portion located therein includes the step of comparing the
reference image with the defect image.
4. The kill index classification method according to claim 2
wherein the step of accepting at least one appropriate resolution
image of the region includes the steps of i) accepting a reference
map, and ii) accepting a defect image, and wherein the step of
analyzing the region to determine is there is a rule violating
shaped portion located therein includes the step of comparing the
reference map with the defect image.
5. The kill index classification method according to claim 2
wherein the step of accepting at least one appropriate resolution
image of the region includes the steps of i) accepting a reference
rule set, and ii) accepting a defect image; and wherein the step of
analyzing the region to determine if there is a rule violating
shaped portion located therein includes the step of comparing the
reference rule set with the defect image.
6. The kill index classification method according to claim 5
wherein the reference rule set includes a threshold for at least
one topological feature selected from the list of i) a detected
edge discontinuity, ii) a detected edge curvature, iii) an interior
angle formed from two intersecting detected edges, iv) an exterior
angle formed from two intersecting detected edges, or v) a
fabrication mask topology design principle.
7. The kill index classification method according to claim 1
wherein the step of determining a predetermined topology for the
region includes at least one step selected from the list of i)
examining a reference image;, ii) examining a reference map; or
iii) examining a fabrication mask topology design algorithm
methodology used to produce the reference map.
8. The kill index classification method according to claim 1
wherein the step of calculating evaluation parameters based on the
at least one non-predetermined portion in relation to the
predetermined topology for the region includes the step of
assigning a topology intersection parameter for the juxtaposition
of the at least one non-predetermined portion with the
predetermined topology.
9. The kill index classification method according to claim 1
wherein the step of assigning a kill index classification using the
calculated evaluation parameters includes convoluting the
calculated evaluation parameters into a numeric classification.
10. The kill index classification method according to claim 1
wherein the step of assigning a kill index classification using the
calculated evaluation parameters includes convoluting the
calculated evaluation parameters into a multi-parametric
classification coordinate.
11. The kill index classification method according to claim 1
wherein the step of locating a region having at least one
non-predetermined portion therein includes locating a region having
at least one defect footprint.
12. The kill index classification method according to claim 11
wherein locating a region having at least one defect footprint
includes locating a region having at least one multi-component
footprint.
13. The kill index classification method according to claim 1
wherein the step of calculating evaluation parameters based on the
at least one non-predetermined portion in relation to the
predetermined topology for the region includes said at least one
non-predetermined portion having at least one non-predetermined
portion core class selected from the list: a) at least one pattern
non-predetermined portion selected from the list: i) extra pattern
connected, ii) extra pattern isolated, iii) missing pattern, and
iv) deformed pattern; or b) at least one non-predetermined particle
portion selected from the list: i) crater in pattern, ii) crater in
background, iii) particle on pattern, iv) particle on background,
v) particle on distortion, vi) embedded under pattern, and vii)
embedded under background.
14. The kill index classification method according to claim 1
wherein the step of calculating evaluation parameters based on the
at least one non-predetermined portion in relation to the
predetermined topology for the region includes said evaluation
parameters having at least one parameter selected from the list: a)
a non-predetermined portion isolated from the predetermined
topology; b) a non-predetermined portion close to the predetermined
topology; c) a non-predetermined portion connected to the
predetermined topology; d) a non-predetermined portion bridging the
predetermined topology; and e) a non-predetermined portion close to
bridging the predetermined topology.
15. The kill index classification method according to claim 14
wherein said non-predetermined portion isolated from the
predetermined topology includes a distance greater than a
predetermined distance between the at least one non-predetermined
portion and a pattern portion of the predetermined topology.
16. The kill index classification method according to claim 14
wherein said non-predetermined portion close to the predetermined
topology includes a distance less than a predetermined distance
between the at least one non-predetermined portion and a pattern
portion of the predetermined topology.
17. The kill index classification method according to claim 14
wherein said non-predetermined portion connected to the
predetermined topology includes the at least one non-predetermined
portion being in contact with a pattern portion of the
predetermined topology.
18. The kill index classification method according to claim 14
wherein said non-predetermined portion bridging the predetermined
topology includes at least one parameter selected from the list: a)
at least one non-predetermined portion connecting at least two
pattern portions of the predetermined topology; b) at least one
non-predetermined portion connecting at least one pattern portion
and intersecting at least one other pattern portion of the
predetermined topology; and c) at least one non-predetermined
portion intersecting at least two pattern portions of the
predetermined topology.
19. The kill index classification method according to claim 14
wherein said non-predetermined portion close to bridging the
predetermined topology includes the at least one non-predetermined
portion being close to at least two pattern portions of the
predetermined topology.
20. A computer program product including a computer usable medium
having computer readable program code embodied therein for a kill
index classification method for prioritizing relational aspects of
topological defect intersections in a semiconductor fabrication
process, the computer readable program code in said computer usable
medium including at least one program code selected from: a) first
computer readable program code for causing a computer to locate a
region having at least one non-predetermined portion therein; b)
tied to the first computer readable program code, second computer
readable program code for causing the computer to determine a
predetermined topology for the region; c) tied to the second
computer readable program code, third computer readable program
code for causing the computer to calculate evaluation parameters
based on the at least one non-predetermined portion in relation to
the predetermined topology for the region; and d) tied to the third
computer readable program code, fourth computer readable program
code for causing the computer to assign a kill index classification
using the calculated evaluation parameters; wherein the kill index
classification method includes the steps of a) locating a region
having at least one non-predetermined portion therein; b)
determining a predetermined topology for the region; c) calculating
evaluation parameters based on the at least one non-predetermined
portion in relation to the predetermined topology for the region;
and d) assigning a kill index classification using the calculated
evaluation parameters.
21. A program storage device readable by machine, tangibly
embodying a program of instructions executable by the machine to
perform a kill index classification method for prioritizing
relational aspects of topological defect intersections in a
semiconductor fabrication process, said method including the steps
of: a) locating a region having at least one non-predetermined
portion therein; b) determining a predetermined topology for the
region; c) calculating evaluation parameters based on the at least
one non-predetermined portion in relation to the predetermined
topology for the region; and d) assigning a kill index
classification using the calculated evaluation parameters.
22. Apparatus for performing a kill index classification method for
prioritizing relational aspects of topological defect intersections
in a semiconductor fabrication process, wherein said apparatus
includes: a) a locator module for locating a region having at least
one non-predetermined portion therein; b) in communication with the
locator module, a determiner module for determining a predetermined
topology for the region; c) in communication with the determiner
module, a calculator module for calculating evaluation parameters
based on the at least one non-predetermined portion in relation to
the predetermined topology for the region; and d) in communication
with the calculator module, an assignor module for assigning a kill
index classification using the calculated evaluation
parameters.
23. A system for operating a multi-stage semiconductor fabrication
process in association with at least two intermediate analytical
testing stages, wherein, at each stage, a kill index classification
method is performed for prioritizing relational aspects of
topological defect intersections, wherein said system includes a
management module for operating said multi-stage semiconductor
fabrication process, and wherein, in association with the
management module, there are at least two apparatus for using a
kill index classification method for prioritizing relational
aspects of topological defect intersections, and each said
apparatus includes: a) a locator module for locating a region
having at least one non-predetermined portion therein; b) in
communication with the locator module, a determiner module for
determining a predetermined topology for the region; c) in
communication with the determiner module, a calculator module for
calculating evaluation parameters based on the at least one
non-predetermined portion in relation to the predetermined topology
for the region; and d) in communication with the calculator module,
an assignor module for assigning a kill index classification using
the calculated evaluation parameters.
24. A method according to claim 1, wherein said semiconductor
fabrication process is a multi-stage semiconductor fabrication
process, and wherein said kill index classification method is
performed after each stage of said multi-stage semiconductor
fabrication process.
25. A method according to claim 20, wherein said semiconductor
fabrication process is a multi-stage semiconductor fabrication
process, and wherein said kill index classification method is
performed after each stage of said multi-stage semiconductor
fabrication process.
26. A method according to claim 21, wherein said semiconductor
fabrication process is a multi-stage semiconductor fabrication
process, and wherein said kill index classification method is
performed after each stage of said multi-stage semiconductor
fabrication process.
27. A method according to claim 22, wherein said semiconductor
fabrication process is a multi-stage semiconductor fabrication
process, and wherein said kill index classification method is
performed after each stage of said multi-stage semiconductor
fabrication process.
Description
FIELD OF THE INVENTION
[0001] The present invention generally relates to a metric for
automatic defect classification in semiconductor wafers. More
specifically, for a predetermined stage in a semiconductor
fabrication process, the present invention relates to a method for
automatic defect classification in a die or integrated circuit of
semiconductor wafers for estimating the effect of defects on
functionality. Furthermore, the present invention's method of
classification gives rise to new possible classes, based on the
actual damage caused by a specific defect.
BACKGROUND OF THE INVENTION
[0002] Numerous methods are known and described in the literature
of semiconductor fabrication process testing and quality assurance.
Essentially these processes define the calculation of statistical
metrics which vaguely correspond to theoretical intersections
between, on the one hand, an area measure for defects and the like
and, on the other hand, an area measure for the intentionally
printed conductive pattern found on a predetermined region of a
semiconductor wafer.
[0003] There is a need in the art for an improved method of testing
and assurance, be it an improved statistical method, or an improved
deterministic method, or an improved combination thereof. It should
be recalled that another critical aspect of semiconductor testing
and assurance relates to the amount of time consumed by such a
method. In terms of an in process testing and assurance method,
speed is of the essence. Therefore, a reduction of delays in
process testing would likewise represent a significant improvement
to the art. Furthermore, an improved testing and assurance method
that will facilitate reprocessing of defective batches of wafers
would also constitute an improvement to the prior art.
[0004] There is a further need in the art to classify defects on
semiconductor wafer layers or dies in terms of the relationship
between the defects and the surrounding conductive patterns, and to
classify defects in terms of their effect on production yield.
Additionally, there is a need in the art for the classification of
defects relating to missing conductive patterns or portions
thereof.
[0005] The present invention will be described with the requisite
particularity based on preferred embodiments. However, those versed
in the art will readily appreciate that various modifications and
alterations may be carried out without departing from either the
spirit or scope, as hereinafter claimed.
[0006] In describing the present invention, explanations are
presented in light of currently accepted scientific Technological
or Process Control theories and models. Such theories and models
are subject to changes, both adiabatic and radical. Often these
changes occur because representations for fundamental component
elements are developed, because new transformations between these
elements are conceived, or because new interpretations arise for
these elements or for their transformations. Therefore, it is
important to note that the present invention relates to specific
technological actualization in embodiments. Accordingly, theory or
model dependent explanations herein, related to these embodiments,
are presented for the purpose of teaching ordinarily skilled
artisans how these embodiments may be substantially realized in
practice. Alternative or equivalent explanations for these
embodiments may neither deny nor alter their realization.
[0007] In addition, the following definitions will be useful for
understand the invention as described herein:
[0008] Kill Index: Generally, the kill index is a descriptor
carrying information regarding the estimated kill rate of a defect.
A "kill rate" implies a rate, which is an average (i.e. statistical
entity)--and statistical decision making is often employed using a
kill rate in order to determine the fate of a batch according to an
examination and classification of a few constituent members of that
batch. Nevertheless, the "Kill Index", per se, is not a statistical
measure. It is a deterministic metric, derived from the topological
relationship between the defect and surrounding imprinted pattern
objects, that is related to the damage caused by this defect to the
specific integrated circuit. "Kill" is used to denote a
dysfunctional integrated circuit.
[0009] Killer Defect: A defect, which renders a single die (which
corresponds to a single integrated circuit) or portions thereof
unable to function adequately or reliably.
[0010] Pattern blobs: Distinct pattern areas in a wafer layer or
die, defined by a continuous border separating them from the
background; for example conductive pattern portions in a wafer
layer.
[0011] Reference Image: A magnified segment of a layer or die of a
semiconductor wafer having no defects either relating to faults in
the predetermined topology of the pattern or to additional
particles.
[0012] Defect Image: A magnified segment of a layer or die of a
semiconductor wafer having defects either relating to faults in the
predetermined topology of the pattern or to additional
particles.
[0013] Reference Map: A predetermined image mask of the required
pattern topology of each layer of a semiconductor wafer.
[0014] Reference Rule Set: A protocol relating to definitions of
the geometric shapes and sizes of elements of the topology of a
layer or die of a semiconductor wafer such as a straight edge, a
specific curvature, intersecting angles and specific lengths.
[0015] Non-predetermined Portion: Defects in a semiconductor wafer
or layer thereof, random with respect to position even if
systematic with respect to process.
[0016] Also, the following acronyms are referred to in the
following description:
[0017] ADC: Automatic defect classification.
[0018] CDM: Chamfer distance map.
[0019] DFP: Defect's footprint.
[0020] EDS: Electron dispersion spectroscopy.
[0021] FOV: Field of view.
[0022] IPDM: Integer pattern dilated map.
[0023] ND: Number of dilations.
[0024] PBM: Pattern binary map.
[0025] PCZSM: Pattern Complement Zoomed Segment Map (ZSM).
[0026] RCFR: Reference to class FOV ratio.
[0027] SEM: Scanning Electron Microscopy.
[0028] ZSM: Zoomed Segment Map.
SUMMARY OF THE INVENTION
[0029] In the process of manufacturing semiconductor wafers,
quality control and assurance testing of all parameters is needed
after each processing step. An important aspect of this testing
relates to classification and detection of the presence and
location of defects resulting from the previous manufacturing step.
Furthermore, it is necessary to determine if such defects will
render the currently exposed layer, die or integrated circuit of
the wafer, or presumptively a batch of wafers, incapable of
functioning adequately and reliably. Defects that result in a batch
of wafers being unsatisfactory are termed "killer defects". This
stage-wise testing and defect classification procedure relates to
the exposed layer portion of each wafer subsequent to each
manufacturing step.
[0030] The present invention relates to embodiments of a kill index
classification method for prioritizing relational aspects of
topological defect intersections, particularly in association with
an intermediate analytical testing stage of a multi-stage
semiconductor fabrication process. This method includes the steps
of
[0031] a) locating a region having at least one non-predetermined
portion therein;
[0032] b) determining a predetermined topology for the region;
[0033] c) calculating evaluation parameters based on the at least
one non-predetermined portion in relation to the predetermined
topology for the region; and
[0034] d) assigning a kill index classification using the
calculated evaluation parameters.
[0035] More specifically, the kill index that is assigned is
linked, correlated and related to the damage caused by the defect
to the functionality and/or reliability of the underlying
integrated circuit.
[0036] Simply stated, the method relates to an analysis of the
geometrical relationship between a non-predetermined portion,
generally referred to as defects, and the surrounding predetermined
topology of the conductive semiconductor pattern, to determine the
effect of defects on the functionality and reliability of the
currently exposed layer, die or integrated circuit of the wafer.
Further, in accordance with this geometrical information, a
classification of the effects of defects into a numerical value,
the "kill index", is achieved.
[0037] According to an embodiment of the present invention, the
kill index classification method in which the step of locating a
region having at least one non-predetermined portion therein
includes the steps of
[0038] a) accepting at least one appropriate resolution image of
the region and
[0039] b) using the at least one appropriate resolution image
analyzing the region to determine if there is a rule violating
shaped portion located therein.
[0040] According to a variation of an embodiment of the present
invention, the kill index classification method in which the step
of accepting at least one appropriate resolution image of the
region includes the steps of accepting a reference image, and
accepting a defect image. Furthermore, the step of analyzing the
region to determine if there is a rule violating shaped portion
located therein includes the step of comparing the reference image
with the defect image.
[0041] According to another variation of an embodiment of the
present invention, the kill index classification method in which
the step of accepting at least one appropriate resolution image of
the region includes the steps of accepting a reference map, and of
accepting a defect image. Additionally, the step of analyzing the
region to determine if there is a rule violating shaped portion
located therein includes the step of comparing the reference map
with the defect image.
[0042] According to an additional variation of an embodiment of the
present invention, the kill index classification method in which
the step of accepting at least one appropriate resolution image of
the region includes the steps of accepting a reference rule set,
and of accepting a defect image. Furthermore, the step of analyzing
the region to determine if there is a rule violating shaped portion
located therein includes the step of comparing the reference rule
set with the defect image.
[0043] According to a variant of an additional variation of the
abovementioned embodiment of the present invention, the kill index
classification method in which the step of accepting a reference
rule set includes a threshold for at least one topological feature
selected from the list of a detected edge discontinuity, a detected
edge curvature, an interior angle formed from two intersecting
detected edges, an exterior angle formed from two intersecting
detected edges, a fabrication mask topology design principle, or
the like.
[0044] Simply stated, in the application of this embodiment of the
present invention, a set of rules or standards, generally geometric
in nature, replaces or supplements the use of a defect-free
reference image on a reference map segment to determine the
existence of defects. This technique facilitates detection of
defects relating to pattern deformation, additional patterns and
absence of pattern portions as well as detection of defects such as
unwanted particles.
[0045] According to another embodiment of the present invention,
the kill index classification method, having the step of
determining a predetermined topology for the region, includes at
least one step selected from the list of examining a reference
image, examining a reference map, or examining a fabrication mask
topology design algorithm methodology used to produce the reference
map.
[0046] According to an additional embodiment of the present
invention, the kill index classification method in which the step
of calculating evaluation parameters based on the at least one
non-predetermined portion in relation to the predetermined topology
for the region includes the step of assigning a topology
intersection parameter for the juxtaposition of the at least one
non-predetermined portion with the predetermined topology.
[0047] According to a further embodiment of the present invention,
the kill index classification method in which the step of assigning
a kill index classification using the calculated evaluation
parameters includes convoluting the calculated evaluation
parameters into a numeric classification.
[0048] Furthermore, according to an embodiment of the present
invention, the kill index classification method in which the step
of assigning a kill index classification using the calculated
evaluation parameters includes convoluting the calculated
evaluation parameters into a multi-parametric classification
coordinate.
[0049] Simply stated, a kill index relating to the relative
positions of defects and pattern is specified substantially as a
numerical value or as a chart of these factors or as a
three-dimensional metric, as a multi-parametric function or the
like..
[0050] According to another embodiment of the present invention,
the kill index classification method in which the step of locating
a region having at least one non-predetermined portion therein
includes locating a region having at least one defect footprint.
According to a variation of an embodiment of the present invention,
the kill index classification method in which locating a region
having at least one defect footprint includes locating a region
having at least one multi-component footprint. This implies that a
defect footprint includes the presence of multiple defects and not
simply the largest or most significant defect.
[0051] Moreover, according to yet a further embodiment of the
present invention, the kill index classification method in which
the step of calculating evaluation parameters based on the at least
one non-predetermined portion in relation to the predetermined
topology for the region includes the at least one non-predetermined
portion having at least one non-predetermined portion core class of
at least one pattern non-predetermined portion selected from the
group comprising an extra pattern connected, an extra pattern
isolated, a missing pattern, a deformed pattern and the like.
Alternatively, at least one particle non-predetermined portion
includes an element selected from the group comprising a crater in
the pattern, a crater in the background, a particle on the pattern,
a particle on the background, a particle on distortion, an embedded
under pattern, or an embedded under background.
[0052] According to a further embodiment of the present invention,
the kill index classification method in which the step of
calculating evaluation parameters based on the at least one
non-predetermined portion in relation to the predetermined topology
for the region the evaluation parameters include at least one
parameter selected from the list:
[0053] a) a non-predetermined portion isolated from the
predetermined topology;
[0054] b) a non-predetermined portion close to the predetermined
topology;
[0055] c) a non-predetermined portion connected to the
predetermined topology;
[0056] d) a non-predetermined portion bridging the predetermined
topology; and
[0057] e) a non-predetermined portion close to bridging the
predetermined topology.
[0058] More specifically, the relative distance between a defect
particle and an adjacent pattern is relevant to whether the defect
will adversely affect the functionality of a wafer. Generally,
defect particles at a sufficiently large distance from the pattern,
will not interfere with functionality. Similarly, a particle close
to or connected to a single pattern portion or blob is unlikely to
cause a problem. Clearly, a particle causing a short across two or
more pattern blobs by bridging is problematic, and such a defect is
classified as a "killer defect". Where a defect particle is defined
as close to bridging, whether this will be termed a killer defect,
depends on whether the closeness is of the order of a single pixel
in the defect map, making distinguishing between touching and close
problematic.
[0059] According to a variation of the abovementioned embodiment of
the present invention, the non-predetermined portion isolated from
the predetermined topology includes a distance greater than a
predetermined distance between the at least one non-predetermined
portion and a pattern portion of the predetermined topology.
[0060] According to another variation of the aforementioned
embodiment of the present invention, the non-predetermined portion
close to the predetermined topology includes a distance less than a
predetermined distance between the at least one non-predetermined
portion and a pattern portion of the predetermined topology.
[0061] According to an additional variation of the aforementioned
embodiment of the present invention, the non-predetermined portion
connected to the predetermined topology includes the at least one
non-predetermined portion being in contact with a pattern portion
of the predetermined topology.
[0062] According to a further variation of the aforementioned
embodiment of the present invention, the non-predetermined portion
bridging the predetermined topology includes at least one parameter
selected from the list:
[0063] a) at least one non-predetermined portion connecting at
least two pattern portions of the predetermined topology;
[0064] b) at least one non-predetermined portion connecting at
least one pattern portion and intersecting at least one other
pattern portion of the predetermined topology; and
[0065] c) at least one non-predetermined portion intersecting at
least two pattern portions of the predetermined topology.
[0066] According to another variation of an embodiment of the
present invention, the non-predetermined portion close to bridging
the predetermined topology includes the at least one
non-predetermined portion being close to at least two pattern
portions of the predetermined topology.
[0067] Generally there are two basic embodiment families of the
present invention, which relate to assigning a kill index
classification for any imaged region of the exposed layer of an
in-process wafer. One of these families relates to the exposed
layer as a two-dimensional image while the other uses relative
height information for each pixel or pixel-cluster in the image to
provide a more refined kill index classification. Each of these
basic embodiment families can be adapted for use in the context of
any explicitly described embodiments, variants, and so on.
[0068] It should be recalled that the killer index classification
of the present invention is preferably used in conjunction with a
system for specifying the material properties (conductive,
capacitive, resistive, non-conductive and so on) of each mapped
pixel or pixel-cluster in a critical process control decision such
as disqualifying the currently exposed layer, die or integrated
circuit of the wafer or wafer batch or directing a wafer batch to a
corrective step such as pattern stripping or reworking.
BRIEF DESCRIPTION OF THE DRAWINGS
[0069] In order to understand the invention and to see how it may
be carried out in practice, embodiments including the preferred
embodiment will now be described, by way of non-limiting example
only, with reference to the accompanying drawings, in which:
[0070] FIG. 1A illustrates a flow diagram of a wafer production and
inspection process;
[0071] Figure 1B illustrates a schematic view of the most general
embodiment of the kill index classification method of the present
invention;
[0072] FIG. 2 illustrates a schematic view of the notion of
"connectivity";
[0073] FIG. 3 illustrates schematic views demonstrating an isolated
defect, a defect close to the pattern, a defect connected to the
pattern, a defect bridging across two pattern blobs, a defect close
to bridging and another defect connected to a pattern blob and
close to bridging across another;
[0074] FIG. 4 illustrates a schematic view demonstrating bridging,
connected and close to bridging;
[0075] FIG. 5 illustrates a flow diagram of the quality control
decision making process;
[0076] FIG. 6 illustrates a flow diagram of the preparation of a
class image;
[0077] FIG. 7 illustrates a schematic view of a defect not touching
the pattern;
[0078] FIG. 8A illustrates a schematic view of a defect connected
to a pattern blob;
[0079] FIG. 8B illustrates a schematic view of a defect close to
bridging two pattern blobs;
[0080] FIG. 8C illustrates a schematic view of a defect bridging
two pattern blobs;
[0081] FIG. 9 illustrates a schematic view of various missing
pattern and deformed pattern defects;
[0082] FIG. 10 illustrates a flow diagram of the algorithm to
determine the kill index;
[0083] FIG. 11 illustrates a flow diagram of the procedure to
calculate the distance of a dilated DPF to a pattern blob;
[0084] FIG. 12 illustrates a flow diagram of the procedure to
calculate the Kill Index, i.e. the number of pattern blobs which
the DFP shorts;
[0085] FIG. 13 illustrates a schematic view of examples
demonstrating calculations of the Kill Index;
[0086] FIG. 14 illustrates a schematic view of a computer program
product including a computer usable medium having computer readable
program code embodied therein for the kill index classification
method of the present invention;
[0087] FIG. 15 illustrates a schematic view of a machine-readable
program storage device, tangibly embodying a program of
instructions executable by the machine to perform method steps for
the kill index classification method of the present invention;
[0088] FIG. 16 illustrates a schematic view of an apparatus for
using the kill index classification method of the present
invention; and
[0089] FIG. 17 illustrates a schematic view of a system for
operating a multi-stage semiconductor fabrication process wherein
is included at least one embodiment of the kill index
classification method of the present invention.
DETAILED DESCRIPTION OF EMBODIMENTS
[0090] In the manufacture of semiconductor wafers, it is necessary
to subject as many parameters as possible to quality control at
every step in the manufacturing process. FIG. 1A is a flow diagram
100A indicating some of the steps 101, 102, 103 and 104 in the
manufacturing process. These steps 101-104 are not specified, but
are well known to the ordinarily skilled artisan, and need not be
detailed here. Control checks 105, 106, 107 and 108 are carried out
on random defects, generally "dirt" particles, extra pattern
segments or missing pattern segments, after each manufacturing step
on the most recently created exposed layer. This quality control
procedure is statistical, and is not carried out on every item
manufactured. Furthermore, testing is automated and not performed
by an operator.
[0091] In this context (turning to FIG. 1B), the present invention
relates to embodiments of a kill index classification method
100B--for example, such as 105, 106, 107 and 108 in 100A--for
prioritizing relational aspects of topological defect
intersections, particularly in association with an intermediate
analytical testing stage of a multi-stage semiconductor fabrication
process. This method includes the steps of
[0092] a) locating (step 109) a region having at least one
non-predetermined portion therein;
[0093] b) determining (step 110) a predetermined topology for the
region;
[0094] c) calculating (step 111) evaluation parameters based on the
at least one non-predetermined portion in relation to the
predetermined topology for the region; and
[0095] d) assigning (step 112) a kill index classification using
the calculated evaluation parameters.
[0096] A defect in a currently exposed layer, die or integrated
circuit of the wafer, which renders a wafer unable to function
adequately or reliably, is termed a "killer defect". Generally,
there are two types of killer defects: defects that "short" between
pattern blobs; and defects that cause a "disconnection". A
significant question, with regard to a step by step quality control
procedure, is whether a specific defect will or will not have the
effect of "killing" the currently exposed layer, die or integrated
circuit of the wafer. It is necessary that a wafer manufacturer be
able to detect the presence of any defect, the location of such
defects, and whether these defects are "killer defects". Generally
there are defects that may be ignored by the manufacturer, while
killer defects are extremely important, so that even a small number
cannot be tolerated.
[0097] If the spread of defects were completely random, information
regarding yield would be obtainable in terms of the defect
classification and size. However, in practice, defect distribution
is not necessarily random.
[0098] Knowing the presence and location of a "killer defect" at
various stages in the manufacturing process is additionally
significant, in that this knowledge will facilitate reworking of a
defective batch of wafers to effect recovery of these wafers.
[0099] Defects Types
[0100] The initial stage of the scheme for core classification of
defects is the differentiation between "particle" and "pattern"
defects. Thereafter, each class needs to be separately defined.
[0101] Particle Defects are defined as defects such as:
[0102] Crater In Pattern,
[0103] Crater In Background,
[0104] Particle On Pattern,
[0105] Particle On Background,
[0106] Particle On Distortion,
[0107] Embedded Under Pattern,
[0108] Embedded Under Background.
[0109] Pattern Defects are defined as core classes such as:
[0110] Extra Pattern Connected,
[0111] Extra Pattern Isolated,
[0112] Missing Pattern, and
[0113] Deformed Pattern.
[0114] FIG. 2 illustrates a schematic view 200 of the notion of
"connectivity". By redefining the notion of "connectivity", for
example, the two defects 201 and 202 are both categorized as
"killer defects". Currently, defect 201 is classified as "extra
pattern isolated", and defect 202 is classified as "extra pattern
connected". The same classifications apply to the defects 203 and
204, which are both non-bridging pattern defects.
[0115] In addition to the core classification, the output of the
classification contains the "segment level" of the defect: for
particles, the segment level contains the segments on which the
defect lies (a "segment" can be pattern1, background or pattern2).
For pattern defects, additional information regarding which pattern
is extra or missing is included.
[0116] Extra Material Defects
[0117] FIG. 3 illustrates schematic views 300 demonstrating an
isolated defect 301, a defect close to the pattern 302, a defect
connected to the pattern 303, a defect bridging across two pattern
blobs 304, a defect close to bridging 305 and another defect
connected to a pattern blob and close to bridging across another
306. A defect (either a pattern or a particle defect) is defined as
"connected" if it touches the pattern; "isolated" if it is far away
from the pattern; and "close to pattern" if it does not touch the
pattern, but is close to it.
[0118] A defect is "bridging" if it connects two (or more) pattern
areas. A defect is "close to bridging" if it is either connected to
one pattern area and close to another, or close to two pattern
areas.
[0119] For two pattern layers (poly layers), the definition has to
be somewhat modified. FIG. 4 illustrates a schematic view 400,
demonstrating bridging 401, connected 402 and close to bridging 403
for two pattern layers. The definition of connectivity remains
substantially the same. The only change, in this case, is that a
defect can be connected to pattern1, pattern2 or both. For a
definition of bridging, pattern1 and pattern2 are treated as
one-segment, in which case, the same definition as above
applies.
[0120] Missing Pattern Defects
[0121] All extra pattern defects are concerned with "extra
material" defects (or missing material which caused a connection to
a previous layer pattern). The situation with a "missing pattern"
is slightly different. Firstly, a missing pattern is always
"connected"--a pattern can be missing only where there should be a
pattern. Secondly, a missing pattern defect is not necessarily a
killer--the "kill rate" depends on the defect size relative to the
pattern "size" (width for a line, area for a contact and so on).
With regard to a missing pattern, the definitions of pattern and
background are effectively reversed.
[0122] Pattern defects include pattern deformed/broken, pattern
deformed/continuous, pattern deformed/bridging and pattern
deformed/close as well as pattern missing/completely and pattern
missing/partially. If the defect cuts off a pattern line, if a
deformed pattern causes bridging or if a contact is completely
missing, the defect is a killer.
[0123] Non-Killers Bridging Defects
[0124] There are defects that cannot create shorts, unless they are
"high". An example of this non-killer defect class is a
micro-scratch: a shallow micro-scratch does not "bridge" patterns.
For such classes, bridging information will not be added to the
defect core class.
[0125] Defect Location
[0126] FIG. 5 illustrates a flow diagram 500 of the quality control
decision making process, wherein the "killer" geometric analysis
501 gives rise to a numerical index 502 indicating the defect
classification. Furthermore, information regarding the core class
503, (that is, the magnified details of defects) and the defect
composition 504 all contribute to a decision-making module 505,
which enables the refining of the index information.
[0127] The core class encodes two kinds of information: the defect
"type", and defect "location". Not included in the core
classification is information relating to "bridging" (the defect
connects different pattern pieces), "close" (the defect is not
connected to the pattern, but it is very close to it), and so on.
This information is not connected with the "root cause" of the
defect, but nonetheless is very helpful for deciding the kill rate
of a defect.
[0128] FIG. 6 illustrates a flow diagram 600 of the preparation of
a class image 606. In order to evaluate the "killer" effects of
defects, it is necessary to examine defective segments from the
segment map of the currently exposed layer, die or integrated
circuit of the wafer 601. A defect free reference segment image
604, generally about 10 to 20 micron (.mu.) in size, is used to
comparatively determine the presence of defects on a defect image
605. When such a defect image is detected, the image is dilated to
more clearly show the magnified defect in the Class Image 606 which
is a 2 to 4 micron segment of the wafer segment map. The defect
footprint (DFP) shows the shape and size of the defect as well as
its position relative to the pattern blobs in the class image.
Using this class image, the Kill Index for the class image is
determined.
[0129] Kill Index
[0130] The Kill Index is a descriptor, which describes the
geometrical relationship between the defect and the surrounding
pattern object for the purpose of estimating the effect of the
defect on the functionality and/or reliability of the wafer. The
Kill Index is based largely on the segmentation map and the
defect's footprint (DFP). The "footprint" refers to the
multi-component DFP, and not only to the largest component.
[0131] More specifically, the kill index that is assigned is
linked, correlated and related to the damage caused by the defect
to the functionality and/or reliability of the underlying
integrated circuit.
[0132] FIG. 7 illustrates a schematic view 700 of a defect not
touching the pattern. Furthermore, FIG. 8A illustrates a schematic
view 800A of a defect connected to a pattern blob, FIG. 8B
illustrates a schematic view 800B of a defect close to bridging two
pattern blobs and FIG. 8C illustrates a schematic view 800C of a
defect bridging two pattern blobs.
[0133] FIG. 9 illustrates a series of schematic views of missing
pattern 900A, 900B, 900C and 900D and deformed pattern 900E and
900F defects.
[0134] View 900A illustrates a missing pattern close to a
disconnected defect where "d" is a measure of the closeness to
disconnection, which is not necessarily a killer defect.
[0135] View 900B illustrates a missing pattern disconnection defect
which is classified as a killer defect.
[0136] View 900C illustrates an almost missing contact.
[0137] View 900D illustrates a missing contact which is classified
as a killer defect.
[0138] View 900E illustrates a deformed pattern defect which is
classified as a killer defect.
[0139] View 900F illustrates a deformed pattern defect.
[0140] The Kill Index is defined according to the following
criteria:
[0141] If the defect's footprint does not touch the pattern, as in
schematic view 700 in FIG. 7, the kill index is negative, and its
absolute value is equal to the distance "d", in microns, between
the footprint and the pattern closest to it. For example, a kill
index of minus6 would indicate a defect footprint 6 microns distant
from and not touching a pattern blob.
[0142] If there is no pattern in the class image, distance "d" is
set to the field of view (FOV) of the class image, that is,
typically 480 pixels.
[0143] If the footprint touches the pattern, as in 800A, 800B and
800C in FIGS. 8A, 8B, and 8C, respectively, the kill index is
greater than or equal to one. The kill rate counts the number of
pattern blobs which the footprint touches. For a kill rate greater
than or equal to 2, the inference is that the defect footprint
shorts at least two adjacent pattern blobs or segments, effectively
creating a single blob.
[0144] If the footprint touches a pattern blob, as in 800B and is
close to an adjoining pattern blob, the kill index is equal to
1+(D-d)/D (alternatively stated as (2D-d)/D), where "D" is the
distance between the adjacent pattern blobs in the vicinity of the
defect footprint and "d" is the distance between the defect
footprint and the adjacent close pattern blob.
[0145] Algorithm to Calculate the Kill Index "N"
[0146] FIG. 10 illustrates a flow diagram 1000 of the algorithm to
determine the kill index.
[0147] The main steps of the algorithm are:
[0148] Step 1001; Check if there is pattern in the class image. If
there is not, return a large negative value equal to the FOV of the
class image, typically 480 pixels.
[0149] Step 1002: If there is a pattern in the class image, dilate
the DFP.
[0150] Step 1003: Check if the footprint intersects the
pattern.
[0151] Step 1004: If there is not, then calculate the distance d,
between the pattern and the footprint, and return -d.
[0152] Step 1005: If the footprint intersects the pattern in step
1003, calculate how many pattern blobs, N, the footprint touches or
intersects.
[0153] Step 1006: If N is greater than or equal to 2, return N as
the killer index.
[0154] Step 1007: If N is not greater than or equal to 2, calculate
the kill index, N=1+(D-d)/D.
[0155] Calculation of distance d from a dilated DFP to a
pattern:
[0156] FIG. 11 illustrates a flow diagram 1100 of the procedure to
calculate the distance from a dilated DPF to a pattern. The steps
indicated are:
[0157] Step 1101: From a Zoomed Segment Map (ZSM), create a binary
map, the output of which is a Pattern Complement ZSM (PCZSM).
[0158] Step 1102: Perform a chamfer distance transform on PCZSM,
the output of which is a Chamfer Distance Map (CDM).
[0159] Step 1103: From the dilated DFP, calculate the minimal value
of CDM inside the dilated DFP, the output of which is the distance
d of the dilated DFP from the pattern.
[0160] Calculation of the Kill Index N:
[0161] FIG. 12 illustrates a flow diagram 1200 of the procedure for
calculating the Kill Index, that is, the number of pattern blobs,
which the DFP shorts. The calculation steps include:
[0162] Step 1201: From the PCZSM and the dilated DFP, create a
binary map, the output from which is a Pattern Binary Map
(PBM).
[0163] Step 1202: Perform a pattern blob analysis to calculate the
number of pattern blobs, N.sub.p.
[0164] Step 1203: Create an integer map, where IPDM=(PBM+2*(Dilated
DFP)).
[0165] Step 1204: Perform a blob analysis on the IPDM and calculate
the number of pattern and defect footprint blobs, N.sub.pd. Also
calculate the minimum and maximum value of IPDM on each blob. It
should be noted that this calculation creates the inference that
each short between pattern blobs reduces the total number of blobs
by one. However, if the defect is a multi-component defect, each
isolated component increases N.sub.pd by one.
[0166] Step 1205: Find the number of isolated DFP blobs, i.e. those
having minimum value=maximum value=2, and the number of isolated
DFP blobs is N.sub.di.
[0167] Step 1206: Calculate the kill index N, from the number of
pattern blobs which the DFP shorts from the formula:
N32 N.sub.p-N.sub.pd+N.sub.di+1
[0168] (the added "1" is to allow that a defect which touches a
pattern segment will give rise to a kill index of one, implying
that there is no reduction in the number of pattern blobs due to
shorting by any DFP).
[0169] FIG. 13 illustrates a schematic view 1300 of examples
demonstrating calculations of the Kill Index.
[0170] In accordance with the above-described embodiments, the
ordinarily skilled artisan will appreciate that the calculation of
the two types of killer defects, those causing "shorts" and those
causing "disconnection" will be selected according to the core
classification. Therefore, for missing or deformed pattern, a
different definition is needed. If the only aspect of interest
relates to disconnections, then the kill index is the number of
background segments shorted by the missing pattern. This gives rise
to a difficulty with regard to missing contacts which do not
"short" background segments. Nevertheless, missing contacts do
represent killer defects.
[0171] Furthermore, it is to be understood that embodiments of the
present invention are not limited to multi-component defect
footprints but will additionally include all large and significant
defects as well.
[0172] Turning to FIG. 14, the present invention also relates to a
computer program product 1400 including a computer usable medium
having computer readable program code 1401 embodied therein for a
kill index classification method for prioritizing relational
aspects of topological defect intersections, the computer readable
program code in the article of manufacture including at least one
program code selected from:
[0173] a) first computer readable program code 1402 for causing a
computer to locate a region having at least one non-predetermined
portion therein;
[0174] b) tied to the first computer readable software, second
computer readable program code 1403 for causing the computer to
determine a predetermined topology for the region;
[0175] c) tied to the second computer readable software, third
computer readable program code 1404 for causing the computer to
calculate evaluation parameters based on the at least one
non-predetermined portion in relation to the predetermined topology
for the region; and
[0176] d) tied to the third computer readable software, fourth
computer readable program code 1405 for causing the computer to
assign a kill index classification using the calculated evaluation
parameters;
[0177] wherein the at least one program code is for use in the
context of the kill index classification method for prioritizing
relational aspects of topological defect intersections, wherein the
method includes the steps of
[0178] a) locating a region having at least one non-predetermined
portion therein;
[0179] b) determining a predetermined topology for the region;
[0180] c) calculating evaluation parameters based on the at least
one non-predetermined portion in relation to the predetermined
topology for the region; and
[0181] d) assigning a kill index classification using the
calculated evaluation parameters.
[0182] Turning now to FIG. 15, the present invention further
relates to a program storage device 1501 readable by machine,
tangibly embodying a program of instructions executable by the
machine to perform method steps for a kill index classification
method for prioritizing relational aspects of topological defect
intersections, the method steps including at least one step
selected from:
[0183] a) locating (step 1502) a region having at least one
non-predetermined portion therein;
[0184] b) determining (step 1503) a predetermined topology for the
region;
[0185] c) calculating (step 1504) evaluation parameters based on
the at least one non-predetermined portion in relation to the
predetermined topology for the region; and
[0186] d) assigning (step 1505) a kill index classification using
the calculated evaluation parameters.
[0187] Turning now to FIG. 16, the present invention additionally
relates to apparatus 1600 for using a kill index classification
method for prioritizing relational aspects of topological defect
intersections, wherein the method is especially useful in
association with an intermediate analytical testing stage of a
multi-stage semiconductor fabrication process, wherein the
apparatus includes
[0188] a) a locator module 1601 for locating a region having at
least one non-predetermined portion therein;
[0189] b) in communication with the locator module, a determiner
module 1602 for determining a predetermined topology for the
region;
[0190] c) in communication with the determiner module, a calculator
module 1603 for calculating evaluation parameters based on the at
least one non-predetermined portion in relation to the
predetermined topology for the region; and
[0191] d) in communication with the calculator module, an assignor
module 1604 for assigning a kill index classification using the
calculated evaluation parameters.
[0192] Furthermore, turning to FIG. 17 the present invention
relates to a system 1700 for operating a multi-stage semiconductor
fabrication process 1705--such as indicated in 100A--in association
with at least two intermediate analytical testing stages, wherein
each stage is using a kill index classification method for
prioritizing relational aspects of topological defect
intersections, wherein said system includes a management module for
operating a multi-stage semiconductor fabrication process and
associated with the management module there are at least two
apparatus for using a kill index classification method for
prioritizing relational aspects of topological defect
intersections, and each said apparatus includes:
[0193] a) a locator module 1701 for locating a region having at
least one non-predetermined portion therein;
[0194] b) in communication with the locator module, a determiner
module 1702 for determining a predetermined topology for the
region;
[0195] c) in communication with the determiner module, a calculator
module 1703 for calculating evaluation parameters based on the at
least one non-predetermined portion in relation to the
predetermined topology for the region; and
[0196] d) in communication with the calculator module, an assignor
module 1704 for assigning a kill index classification using the
calculated evaluation parameters.
[0197] While the present invention has been described in detail
above with reference to several embodiments, various modifications
within the spirit of the invention will be apparent to those of
working skill in this technological field. Accordingly, the scope
of the invention is to be determined by the appended claims.
* * * * *