U.S. patent application number 10/401678 was filed with the patent office on 2003-10-02 for non-volatile semiconductor memory device having memory cell array suitable for high density and high integration.
Invention is credited to Arai, Fumitaka, Shimizu, Kazuhiro.
Application Number | 20030183883 10/401678 |
Document ID | / |
Family ID | 18735626 |
Filed Date | 2003-10-02 |
United States Patent
Application |
20030183883 |
Kind Code |
A1 |
Shimizu, Kazuhiro ; et
al. |
October 2, 2003 |
Non-volatile semiconductor memory device having memory cell array
suitable for high density and high integration
Abstract
First and second semiconductor regions are formed apart from
each other on a semiconductor body. A stacked gate is formed on the
semiconductor body between the first and second semiconductor
regions. The stacked gate has a first side surface, a second side
surface opposed to the first side surface, and an upper surface. A
contact material is buried in an interlayer insulating film above
the semiconductor body, to be adjacent to the first side surface of
the stacked gate. The contact material contacts the first
semiconductor region. A first insulating film is formed on the
second side surface and the upper surface, except the first side
surface of the stacked gate adjacent to the contact material. A
second insulating film is formed on the first side surface of the
stacked gate adjacent to the contact material, and the first
insulating film.
Inventors: |
Shimizu, Kazuhiro;
(Yokohama-shi, JP) ; Arai, Fumitaka;
(Yokohama-shi, JP) |
Correspondence
Address: |
OBLON, SPIVAK, MCCLELLAND, MAIER & NEUSTADT, P.C.
1940 DUKE STREET
ALEXANDRIA
VA
22314
US
|
Family ID: |
18735626 |
Appl. No.: |
10/401678 |
Filed: |
March 31, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10401678 |
Mar 31, 2003 |
|
|
|
09925418 |
Aug 10, 2001 |
|
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Current U.S.
Class: |
257/390 ;
257/E21.682; 257/E27.103; 257/E29.129 |
Current CPC
Class: |
H01L 29/42324 20130101;
H01L 27/11524 20130101; H01L 27/115 20130101; H01L 27/11521
20130101; H01L 2924/0002 20130101; H01L 27/11529 20130101; H01L
27/11526 20130101; H01L 2924/0002 20130101; H01L 2924/00
20130101 |
Class at
Publication: |
257/390 |
International
Class: |
H01L 029/76 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 11, 2000 |
JP |
2000-245029 |
Claims
What is claimed is:
1. A non-volatile semiconductor memory device comprising: a
semiconductor body of a first conductivity type; first and second
semiconductor regions of a second conductivity type, formed apart
from each other on the semiconductor body; a stacked gate formed on
the semiconductor body between the first and second semiconductor
regions, with a gate insulating film inserted therebetween, the
stacked gate having a first side surface, a second side surface
opposed to the first side surface, and an upper surface; an
interlayer insulating film formed above the semiconductor body; a
contact material buried to be adjacent to the first side surface of
the stacked gate, in the interlayer insulating film, the contact
material contacting the first semiconductor region; a first
insulating film formed on the second side surface and the upper
surface, except the first side surface of the stacked gate adjacent
to the contact material; and a second insulating film formed on the
first side surface adjacent to the contact material, and the first
insulating film.
2. The device according to claim 1, wherein the stacked gate
includes a charge storage layer on the gate insulating film, a
control gate on the charge storage layer, a cap insulating film on
the control gate, and the first side surface of the stacked gate
includes side surfaces of the charge storage layer, the control
gate, and the cap insulating film.
3. The device according to claim 2, wherein the first insulating
film is made of a material different from the cap insulating film,
and the second insulating film is made of the same material as the
cap insulating film.
4. The device according to claim 2, wherein the contact material
has a side surface, the side surface contacts the second insulating
film, and a part of the side surface extends over the cap
insulating film.
5. The device according to claim 1, wherein the first insulating
film is an oxide-based insulating film having a film thickness of
200 .ANG. or less, and the second insulating film is a
nitride-based insulating film having a film thickness of 400 .ANG.
or less.
6. A non-volatile semiconductor memory device comprising: a
semiconductor body of a first conductivity type; first and second
semiconductor regions of a second conductivity type, formed apart
from each other on the semiconductor body; a stacked gate formed on
the semiconductor body between the first and second semiconductor
regions, with a gate insulating film inserted therebetween, the
stacked gate including a charge storage layer on the gate
insulating film, a control gate on the charge storage layer, and a
cap insulating film on the control gate, and the stacked gate
having a first side surface, a second side surface opposed to the
first side surface, and an upper surface, the first and second
surfaces each including side surfaces of the charge storage layer,
the control gate, and the cap insulating film; an interlayer
insulating film formed above the semiconductor body; a contact
material buried to be adjacent to the first side surface of the
stacked gate, in the interlayer insulating film, the contact
material contacting the first semiconductor region; a first
insulating film formed on at least a part of the side surface of
the control gate on the first side surface, all of the side surface
of the charge storage layer; and a second insulating film formed on
the first side surface adjacent to the contact material to cover
the first insulating film.
7. The device according to claim 6, wherein the first insulating
film is made of a material different from the cap insulating film,
and the second insulating film is made of the same material as the
cap insulating film.
8. The device according to claim 6, wherein the contact material
has a side surface, the side surface contacts the second insulating
film, and a part of the side surface extends over the cap
insulating film.
9. The device according to claim 6, wherein the first insulating
film is an oxide-based insulating film having a film thickness of
200 .ANG. or less, and the second insulating film is a
nitride-based insulating film having a film thickness of 400 .ANG.
or less.
10. A non-volatile semiconductor memory device comprising: a
semiconductor body of a first conductivity type; first and second
semiconductor regions of a second conductivity type, formed apart
from each other on the semiconductor body; a stacked gate formed on
the semiconductor body between the first and second semiconductor
regions, with a gate insulating film inserted therebetween, the
stacked gate including a charge storage layer on the gate
insulating film, a control gate on the charge storage layer, and a
cap insulating film on the control gate, and the stacked gate
having a first side surface, a second side surface opposed to the
first side surface, and an upper surface, the first and second
surfaces each including side surfaces of the charge storage layer,
the control gate, and the cap insulating film; an interlayer
insulating film formed above the semiconductor body; a contact
material buried to be adjacent to the first side surface of the
stacked gate, in the interlayer insulating film, the contact
material contacting the first semiconductor region; a first
insulating film formed on at least a part of the side surface of
the control gate on the first side surface, all of the side surface
of the charge storage layer on the first side surface, at least a
part of the side surface of the control gate on the second side
surface, and all of the side surface of the charge storage layer on
the second side surface; and a second insulating film formed on the
first side surface adjacent to the contact material to cover first
insulating film, the second side surface to cover first insulating
film, and the upper surface.
11. The device according to claim 10, wherein the first insulating
film is made of a material different from the cap insulating film,
and the second insulating film is made of the same material as the
cap insulating film.
12. The device according to claim 10, wherein the contact material
has a side surface, the side surface contacts the second insulating
film, and a part of the side surface extends over the cap
insulating film.
13. The device according to claim 10, wherein the first insulating
film is an oxide-based insulating film having a film thickness of
200 .ANG. or less, and the second insulating film is a
nitride-based insulating film having a film thickness of 400 .ANG.
or less.
14. A non-volatile semiconductor memory device comprising: a
plurality of element separation regions made of element separation
insulating material buried in a plurality of trenches formed in a
semiconductor body; a stacked gate formed on the semiconductor body
between the element separation regions, with a gate insulating film
inserted therebetween, the stacked gate including a charge storage
layer on the gate insulating film, a control gate on the charge
storage layer, and a gap insulating film on the control gate; and
an interlayer insulating film formed above the semiconductor body;
wherein the charge storage layer is provided with a side surface
thereof aligned with the element separation regions, and upper
surfaces of the element separation regions below the control gate
are higher than the upper surfaces of the element separation
regions between control gates.
15. The device according to claim 14, further comprising: a
plurality of first semiconductor regions of a first conductivity
type, electrically separated from each other by the element
separation regions; second and third semiconductor regions of a
second conductivity type, formed apart from each other on the first
semiconductor regions; a contact material buried in the interlayer
insulating film, the contact material contacting the second
semiconductor region.
16. The device according to claim 15, wherein the upper surfaces of
the element separation regions between the control gates are lower
than an upper surface of the charge storage layer.
17. The device according to claim 15, further comprising: a bit
line formed on the interlayer insulating film, for
inputting/outputting a signal; a source line formed on the
interlayer insulating film, for inputting/outputting a signal; and
a peripheral circuit including a peripheral transistor, for
controlling signals to the bit line, the source line, and the
control gate, wherein the peripheral transistor has a gate
insulating film, a gate electrode, a source region, and a drain
region, and the gate insulating film adjacent to the contact
material connected to one of the source and drain regions has a
film thickness smaller than that of the gate insulating film below
the gate electrode.
18. The device according to claim 17, wherein the stacked gate, the
first, second, and third semiconductor regions construct a memory
cell transistor, the peripheral transistor is a
high-withstanding-voltage-base- d transistor for driving high
voltages for writing and erasure applied to the memory cell
transistor during operation of supplying/receiving charges to/from
the memory cell transistor, and the gate insulating film below the
gate electrode has a film thickness greater than that of the gate
insulating film below the charge storage layer of the memory cell
transistor.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from the prior Japanese Patent Application No.
2000-245029, filed Aug. 11, 2000, the entire contents of which are
incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a non-volatile
semiconductor memory device, and particularly to a non-volatile
semiconductor memory device having a memory cell array suitable for
high density and high integration.
[0004] 2. Description of the Related Art
[0005] A flash memory is well known as a non-volatile semiconductor
memory device, which enables electric re-writing of data and is
suitable for high density and large capacity. Generally, in a flash
memory, a plurality of memory cells each having a MOS transistor
structure with a stacked gate in which a charge storage layer and a
control gate are layered are provided in a matrix. A word-line
signal is inputted to the control gates of these memory cells, and
a bit-line signal is inputted to sources or drains of the memory
cells.
[0006] FIG. 1A is a plan view showing the structure of the memory
cell array in a NOR-type flash memory. FIG. 1B is a cross-sectional
view cut along the line 1B-1B of the memory cell array shown in
FIG. 1A.
[0007] As shown in FIG. 1B, a charge storage layer 103 is formed on
a p-type silicon semiconductor substrate 101 with a tunnel gate
insulating film 102 inserted therebetween. A control gate 105 is
formed on the charge storage layer 103 with an inter-gate
insulating film 104 inserted therebetween. Each memory cell has a
stacked gate in which the charge storage layer 103 and the control
gate 105 are layered. This stacked gate is processed vertically in
a self-aligning manner such that side end parts thereof are
aligned.
[0008] Also, the memory cells each have a source region 106A and a
drain region 106B which are formed of an n-type diffusion layer.
The source region 106A and the drain region 106B are formed in the
semiconductor substrate 101 at both sides of the stacked gate. One
of the source region 106A and the drain region 106B is connected to
a bit line 108 through a bit-line contact material 107, and the
other is connected to a common source line 110 through a common
source line contact material 109.
[0009] A structure interposing a contact material like the bit
line, a structure directly connected through a buried metal line, a
structure in which sources of memory cells of each bit line are
connected with use of a diffusion layer, or the like is widely used
to connect the common source line 110 and the source region 106A to
each other. The case of connection to the common source line 110
through the contact material 109 is now shown.
[0010] The bit-line contact material 107 described above has a side
end part adjacent to a stacked gate and is constructed in a
so-called self-aligned contact structure in which a part of the
contact material 107 extends over the stacked gate, at its
connecting part to a bit line 108. This structure is adopted to
eliminate a dimensional margin between the bit-line contact
material 107 and the stacked gate, so that the memory cell array
can be downsized.
[0011] To attain the self-aligned contact structure, the stacked
gate is covered with a cap material 111, e.g., a silicon nitride
film. In particular, the cap material 111 is formed thick on the
control gate 105. In this manner, the contact material 107 buried
in a contact hole and the control gate 105 are prevented from being
short-circuited. A conductive material such as low-resistance
poly-silicon or metal material is used for the contact material
107. Note that the reference 112 denotes an inter-layer insulating
film made of a BPSG film or the like.
[0012] The common source-line contact material 109 is not
constructed in a self-aligned contact structure but a special
margin is maintained between the stacked gate and the contact
material 109. This is because a potential difference of about 10 V
occurs in a NOR-type memory when erasure operation is carried out.
Since the withstanding voltage at this time is maintained, it is
difficult to make a self-aligned contact.
[0013] FIG. 2A is a plan view showing the structure of a memory
cell array in a NAND-type flash memory. FIG. 2B is a
cross-sectional view of the memory cell array shown in FIG. 2A, cut
along the line 2B-2B.
[0014] A plurality of memory cells are connected in series, with
sources and drains shared between each other, thereby to construct
a NAND column. At both ends of the NAND column, selection
transistors are provided. Of the selection transistors provided at
both ends, a drain or source of one selection transistor is
connected to a bit line 208 through a bit-line contact material
207. A drain or source of the other selection transistor is
connected to a common source line 210 through a common source line
contact material 209.
[0015] The memory cells and selection transistors have stacked
gates in which charge storage layer 203 and the control gate 205
are layered, like the NOR-type memory cell. The charge storage
layer 203 of the selection transistor or the charge storage layer
203 and the control gate 205 are connected to the gate signal line
at another portion than the region shown in the figure.
[0016] The bit-line contact material 207 has a side end part
adjacent to a stacked gate and is constructed in a so-called
self-aligned contact structure in which a part of the contact
material 207 extends over the stacked gate, at its connecting part
to a bit line 208. This structure is adopted to eliminate a
dimensional margin between the bit-line contact material 207 and
the stacked gate, so that the memory cell array can be downsized.
To attain the self-aligned contact structure, the stacked gate is
covered with a cap material 211, e.g., a silicon nitride film. In
particular, the cap material 211 on the control gate 205 is formed
thick on the control gate 205. In this manner, the contact material
207 buried in a contact hole and the control gate 205 are prevented
from being short-circuited. A conductive material such as
low-resistance poly-silicon or metal material is used for the
contact material 207.
[0017] Like the bit line contact material 207, the common source
line contact material 209 is also constructed in a self-aligned
contact structure, in the NAND type memory. This is because only a
small potential difference (about 3 V) exists between the common
source line 210 and the control gate 205 of the selection
transistor adjacent to the source line in the NAND type memory, so
there will not appear a problem of dielectric breakdown even if a
self-aligned contact is made.
[0018] The self-aligned contact structure is adopted to reduce the
dimensional margin between the contact material and the gate,
thereby to shorten the cell array length in the direction of the
bit-line 208. The method of using the self-aligned contact
structure to shorten the cell array length is very effective
regardless of whether the memory cell is of the NAND type or NOR
type.
[0019] In accordance with reduction of the design rule, the
self-aligned contact structure is considered to have much higher
effectiveness as the gate length is shortened. This is because it
is difficult to scale variants and the like at the time of
lithography, at the same ratio as that of the reduction of the gate
length. Therefore, the distance between the contact material and
the gate is not reduced to the level as that of the gate
length.
[0020] Formation of the bit line contact material 207 and the
common source line contact material 209 is normally performed as
follows. At first, a stacked gate is buried by an inter-layer
insulating film 213 such as a BPSG film or the like. Flattening
processing is carried out by CMP or the like. The BPSG film is a
film which attains an improved melting property by mixing
impurities such as boron, phosphors, and the like into a silicon
dioxide film.
[0021] Thereafter, contact holes are opened by dry etching. When
these contact holes are opened, the cap material 211 on the control
gate 205 is thinned or is perfectly removed so that the control
gate 205 is exposed, if the etching election ratio between the cap
material 211 covering the control gate 205 and the inter-layer
insulating film 213 is not high. In this case, a short-circuiting
defect occurs when a contact material is buried. Therefore, a
silicon-dioxide-based film is widely used for the inter-layer
insulating film 213, and a silicon-nitride-based film which attains
a relatively high selection ratio relative to the
silicon-dioxide-based film is widely used for the cap material
211.
[0022] However, if the silicon-nitride-based film is formed
covering the gate of a transistor, a stack insulating film
structure constructed by a gate film mainly made of a silicon
dioxide film and a silicon nitride film is formed on the diffusion
layer in the side of the gate. Therefore, hot electrons generated
at channels during operation of a pentode of a transistor are
caught by the inter-layer insulating film interface (the interface
between the gate insulating film and the silicon nitride film),
causing an electronic trap. It is generally known that modulation
of an ON-current of a transistor, change of a threshold voltage,
deterioration of a surface junction withstanding voltage, or the
like is caused if this electronic trap thus occurs.
[0023] The flash memory has a memory cell array and a peripheral
circuit. The peripheral circuit is a circuit which generates a
signal for driving the memory cell array and is formed outside the
region of the memory cell array. This peripheral circuit, for
example, generates a control gate signal and a bit-line signal. In
many cases, the peripheral transistor is also constructed in a gate
structure similar to that of the memory cell, to reduce processing
steps and to share processes, in the flash memory described above.
Therefore, the peripheral transistor is formed into a shape in
which the gate is covered with a cap material and causes
deterioration of characteristics at high possibility, like the
memory cell and the selection transistor.
[0024] To solve this problem, a structure in which a
silicon-dioxide-based film is sandwiched between a silicon nitride
film and a gate has been proposed. The object of sandwiching a
silicon-dioxide-based film between a thin gate insulating film on a
diffusion layer and the silicon nitride film is to widen the
distance between the diffusion layer and the silicon nitride film
to reduce caught hot electrons.
[0025] However, it is difficult to realize simultaneously the
structure in which a silicon-dioxide-based film is sandwiched
between the silicon nitride film and the gate, and the structure
self-aligned contact structure described above.
[0026] FIGS. 3A, 3B, 4A, and 4B are cross-sectional views showing
steps of forming a self-aligned contact in a structure in which a
silicon-dioxide-based film is sandwiched between a silicon nitride
film and a stacked gate.
[0027] After forming a stacked gate, a silicon dioxide film 214 is
formed with a thickness of, for example, about 200 .ANG., on the
stacked gate. Further, a silicon nitride film 215 is formed with a
thickness of, for example, about 400 .ANG., on the silicon dioxide
film 214. Further, an interlayer insulating film 213 is formed the
above-described silicon nitride film 215. Thereafter, as shown in
FIG. 3A, the interlayer insulating film 213 is flattened by CMP or
the like.
[0028] Subsequently, a resist film 216 is applied onto the
structure shown in FIG. 3A. Thereafter, as shown in FIG. 3B, a part
of the resist film which corresponds to a contact part is opened by
a lithography method.
[0029] Next, the interlayer insulating film 213 is etched by dry
etching, using the resist film 216 as a mask, as shown in FIG. 4A.
At this time, the silicon nitride film 215 and the silicon nitride
film of the cap material 211 are etched in correspondence with the
etching selection ratio between the interlayer insulating film 213
and the silicon nitride film. Generally, etching is concentrated on
end parts of the gate, so that the film is reduced more. Therefore,
a silicon dioxide film 214 is exposed at a part. In the worst case,
the silicon dioxide film 214 can be etched back.
[0030] Thereafter, interfacial cleaning is performed on the
structure shown in FIG. 4A. Thereafter, a contact material 217,
e.g., metal such as a low-resistance polysilicon or tungsten (W) is
buried. Further, as shown in FIG. 4B, the contact material 217 is
flattened to finish a contact.
[0031] In the manufacturing method described above, the silicon
dioxide film 214 in the contact hole is etched back. As a result,
the contact material 217 (buried-electrode material) enters into
the etched-back part, so that the possibility of short-circuiting
between the contact material 217 and the control gate 205 rises.
Hence, in a conventional technique, it is difficult to use the
structure in which the silicon dioxide film 214 is sandwiched
between the silicon nitride film 215 and the stacked gate to
improve the reliability, together with the self-aligned contact
structure.
[0032] As another problem in case of using the self-aligned contact
structure for the bit-line contact part and the common source line
contact part, residual parts of a film on gap parts of an element
separation insulating film.
[0033] FIG. 5 is a cross-sectional view in case where the memory
cell array shown in FIG. 4B is cut along the line 5-5 in FIG.
2A.
[0034] As shown in FIG. 5, on the semiconductor region sandwiched
by the element separation insulation films 217, the bit-line
contact material 207 and the semiconductor region are electrically
connected with each other. On the side surfaces in both sides of
the element separation insulating film 217, the silicon dioxide
film 214 and the silicon nitride film 215 remain like spacers.
These residues greatly reduce the contact area between the bit-line
contact material 207 and the semiconductor region. Reduction of the
contact area involves effective lowering of the cell current, so
that the silicon nitride film 215 on the semiconductor region must
be perfectly removed when opening the contact hole.
[0035] On the other hand, however, the silicon nitride film 215 on
the control gate 205 must be left for a self-aligned contact. Thus,
there is a trade-off that the silicon nitride film 215 on the
semiconductor region must be removed while the silicon nitride film
215 on the control gate 205 must be left, so that the processing
margin greatly decreases.
[0036] The above problem is conspicuous particularly when the
element separation insulating film 217 is formed to be higher than
the semiconductor region. If element separation is carried out with
use of a self-alignment STI (Shallow Trench Isolation) method, the
element separation insulating film 217 is formed to be higher than
the semiconductor substrate, so that its influence is greater than
an element separation structure based on a LOCOS method. The
above-described self-alignment STI method is a method of forming an
element separation region with use of a shallow trench formed by a
self-alignment method. More specifically, in this method, a trench
is formed after depositing a charge storage layer. Further, an
insulating material is buried in the trench, thereby to form an
element separation structure.
[0037] Also, if low-resistance polysilicon is used as a contact
material to be buried in the bit-line contact hole, there is a
characteristic that ohmic contact is obtained between the contact
material and the semiconductor region, without using a barrier
metal material such as Ti, TiN, or the like as a buffer film and
without causing the problem of abnormal contact resistance or
increase of junction leakage even when the impurity density of the
semiconductor region (diffusion layer) is relatively low.
[0038] Therefore, the contact resistance increases to be greater
than in the case of using metal material for the contact material.
However, there is a case that the contact part using the same
buried material as that of the bit-line contact part is used for a
peripheral transistor forming part of a peripheral circuit, for the
purpose of reducing the dimensional margin between the contact
material and the semiconductor region, to down-size the
elements.
[0039] In this case, the contact hole of the
high-withstanding-voltage-bas- ed transistor needs to be opened at
the same time when the contact hole of the bit-line contact part is
opened. However, the gate insulating film of the
high-withstanding-voltage-based transistor is much thicker,
compared with the memory cell. For example, the film thickness of
the gate insulating film of the high-withstanding-voltage-based
transistor is 150 .ANG. to 200 .ANG. in case of an NOR-type flash
memory or 300 .ANG. to 400 .ANG. in case of an NAND-type flash
memory, in relation to the film thickness of the gate insulating
film of the memory cell which is about 100 .ANG.. Therefore, the
silicon nitride film on the diffusion layer needs to be opened, and
further, the gate insulating film needs to be etched by 150 .ANG.
to 400 .ANG., to open perfectly a contact hole in the diffusion
layer of the high-withstanding-voltage-based transistor.
[0040] However, if additional etching is carried out, a defect
occurs in that the film of the cap material on the control gate is
reduced at the bit-line contact part or the element separation film
partially overlapping the contact part is etched back. That is, in
case where a self-aligned contact structure is adopted to form the
bit-line contact part, there is a problem that it is very difficult
to form the contact part of a peripheral transistor through the
same process as that of forming the bit-line contact part.
[0041] As has been described above, there is a problem that
techniques which have been conventionally proposed cannot be used
in case where the bit-line contact part is constructed in a
self-aligned contact structure. That is, a conventional
non-volatile semiconductor memory device has a problem in that the
above-described techniques for attaining high reliability and for
downsizing peripheral transistors cannot be used if a self-aligned
contact structure is adopted at the bit-line contact part.
BRIEF SUMMARY OF THE INVENTION
[0042] According to an aspect of the present invention, a
non-volatile semiconductor memory device comprises: a semiconductor
body of a first conductivity type; first and second semiconductor
regions of a second conductivity type, formed apart from each other
on the semiconductor body; a stacked gate formed with a gate
insulating film inserted thereunder, on the semiconductor body
between the first and second semiconductor regions, the stacked
gate having a first side surface, a second side surface opposed to
the first side surface, and an upper surface; an interlayer
insulating film formed above the semiconductor body; a contact
material buried to be adjacent to the first side surface of the
stacked gate, in the interlayer insulating film, the contact
material contacting the first semiconductor region; a first
insulating film formed on the second side surface and the upper
surface, except the first side surface of the stacked gate adjacent
to the contact material; and a second insulating film formed on the
first side surface adjacent to the contact material, and the first
insulating film.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0043] FIG. 1A is a plan view showing the structure of a memory
cell array in a conventional NOR-type flash memory;
[0044] FIG. 1B is a cross-sectional view showing the memory cell
array, cut along the line 1B-1B;
[0045] FIG. 2A is a plan view showing the structure of a
conventional NAND-type flash memory;
[0046] FIG. 2B is a cross-sectional view of the memory cell array,
cut along the line 2B-2B;
[0047] FIGS. 3A and 3B are cross-sectional views showing a first
step of forming a self-aligned contact in a NAND-type memory cell
array having a structure in which a silicon dioxide film is
sandwiched between a silicon nitride film and a stacked gate;
[0048] FIGS. 4A and 4B are cross-sectional views showing a second
step of forming a self-aligned contact in the NAND-type memory cell
array having the structure sandwiching a silicon dioxide film;
[0049] FIG. 5 is a cross-sectional view in case where the memory
cell array shown in FIG. 4B is cut along the line 5-5 in FIG.
2A;
[0050] FIG. 6A is a plan view showing the structure of a memory
cell array in a NOR-type non-volatile semiconductor memory device
according to the first embodiment of the present invention;
[0051] FIG. 6B is a cross-sectional view showing the memory cell
array in the NOR-type non-volatile semiconductor memory device
according to the first embodiment, cut along the line 6B-6B;
[0052] FIG. 7A is a plan view showing the structure of a memory
cell array in a NAND-type non-volatile semiconductor memory device
according to the second embodiment of the present invention;
[0053] FIG. 7B is a cross-sectional view showing the memory cell
array in the NAND-type non-volatile semiconductor memory device
according to the first embodiment, cut along the line 7B-7B;
[0054] FIGS. 8A and 8B are cross-sectional views of a main first
step, showing a method of manufacturing the NAND-type memory cell
according to the second embodiment;
[0055] FIGS. 9A and 9B are cross-sectional views of a main second
step, showing a method of manufacturing the NAND-type memory cell
according to the second embodiment;
[0056] FIG. 10 is a cross-sectional view showing a memory cell
array in a NAND-type non-volatile semiconductor memory device
according to the third embodiment of the present invention;
[0057] FIG. 11 is a cross-sectional view showing a memory cell
array in a NAND-type non-volatile semiconductor memory device
according to the fourth embodiment of the present invention;
[0058] FIG. 12A is a plan view showing the structure of a memory
cell array in the NAND-type non-volatile semiconductor memory
device according to the fifth embodiment of the present
invention;
[0059] FIG. 12B is a cross-sectional view showing the memory cell
array in the NAND-type non-volatile semiconductor memory device
according to the fifth embodiment, cut along the line 12B-12B.
[0060] FIG. 12C is a cross-sectional view showing the memory cell
array in the NAND-type non-volatile semiconductor memory device
according to the fifth embodiment, cut along the line 12C-12C.
[0061] FIG. 12D is a cross-sectional view showing the memory cell
array in the NAND-type non-volatile semiconductor memory device
according to the fifth embodiment, cut along the line 12D-12D.
[0062] FIG. 13A is a plan view of a peripheral transistor forming
part of a peripheral circuit in the NAND-type non-volatile
semiconductor memory device according to the fifth embodiment of
the present invention;
[0063] FIG. 13B is a cross-section of the peripheral transistor
forming part of a peripheral circuit in the NAND-type non-volatile
semiconductor memory device according to the fifth embodiment, cut
along the line 13B-13B.
DETAILED DESCRIPTION OF THE INVENTION
[0064] In the following, embodiments of the present invention will
be explained with reference to the drawings.
[0065] First Embodiment
[0066] At first, explanation will be made of a NOR-type
non-volatile semiconductor memory device as a first embodiment of
the present invention.
[0067] FIG. 6A is a plan view showing the structure of a memory
cell array in the NOR-type non-volatile semiconductor memory device
according to the first embodiment of the present invention. FIG. 6B
is a cross-sectional view showing the memory cell array shown in
FIG. 6B, cut along the line 6B-6B.
[0068] A trench for separating an element is formed in a p-type
silicon semiconductor substrate (or p-type well) 11, and an element
separation insulating material such as a silicon dioxide material
is buried in the trench. In this manner, an element separation
region where a silicon dioxide material is buried and an element
region separated by the element separation region, where no silicon
dioxide material is buried are formed. A thin tunnel insulating
film 12 where a tunnel current can flow is formed on the entire
surface of the channel region in the element region inside the
semiconductor substrate.
[0069] A charge storage layer 13 is formed on the tunnel insulating
film 12. This charge storage layer 13 is formed such that side end
parts are aligned with the element separation region. The charge
storage layer 13 partially extends over the element separation
region and is cut above the element separation region, such that
memory cells are separated from each other. A control gate 15 is
formed on the charge storage layer 13 through an inter-gate
insulating film 14.
[0070] A gate cap film 16 is formed on the control gate 15. This
gate cap film 16 is made of, for example, a silicon nitride film.
The gate cap film 16 and the control gate 15 are processed to be
vertical to the surface of the semiconductor substrate, in a
self-alignment manner, such that the side end parts of the film 16
are aligned with the charge storage layer 13. A stacked gate is
formed by the charge storage layer 13, the control gate 15, and the
gate cap film 16. Formed in both sides of the stacked gate in the
semiconductor substrate 11 are a source region 17A and a drain
region 17B doped with impurities of the conductivity type different
from the p-type semiconductor substrate (or p-type well) 11 in the
channel region. The source regions 17A and drain region 17B are
formed of an n-type diffusion layer.
[0071] A bit-line contact material 18 connected with the drain
region 17B is formed on the drain region 17B. A common source line
contact material 19 connected to the source region 17A is formed on
the source region 17A. The bit line contact material 18 and the
common source line contact material 19 are made of low-resistance
polysilicon, metal material, or the like which is conductive
material. The upper parts of the contact materials 18 and 19 are
each flattened. The bit-line contact material 18 is connected to a
bit line 20 made of a metal electrode. The common source contact
material 19 is connected to the common source line 21.
[0072] The stacked gate of the memory cell is covered with a gate
barrier film 22 made of a silicon dioxide film. Further, a contact
barrier film 23 made of a silicon nitride film covers the gate
barrier film 22.
[0073] From the side surface of the stacked gate adjacent to the
bit-line contact material 18, the gate barrier film 22 is removed
as shown in FIG. 6B. The structure is therefore arranged such that
this side surface is directly covered with the contact barrier film
23. In other words, the gate barrier film 22 is formed on the side
surface of the stacked gate adjacent to the common source line
contact material 19, and the contact barrier film 23 is further
formed on the gate barrier film 22. Meanwhile, the gate barrier
film 22 is not formed on the side surface of the stacked gate
adjacent to the bit-line contact material 18, but the contact
barrier film 23 is formed directly on this side surface.
[0074] As shown in FIG. 6B, an interlayer insulating film 24, e.g.,
a BPSG film or the like is formed on the semiconductor substrate
11.
[0075] The source line contact material 19 is provided with a
predetermined distance maintained from the contact barrier film 23
formed on the side surface of the stacked gate. The bit line
contact material 18 is provided in contact with the contact barrier
film 23 formed on the side surface of the stacked gate, without
maintaining any distance.
[0076] Further, the bit line contact material 18 is formed so as to
extend partially over the contact barrier film 23 on two stacked
gates provided to be adjacent to each other. This bit line contact
material 18 is formed to be buried between contact barrier films
(silicon nitride films) 23 on adjacent gates, on the semiconductor
substrate 11. The structure of the part of the bit line contact
material 18 is constructed into a self-aligned contact structure.
This self-aligned contact structure is formed through the steps
described below. Using a contact barrier film 23 and a gate cap
film 16 as masks, a contact hole 18 is formed by self-aligning
process. Thereafter, a contact material is buried in the contact
hole, to form a bit-line contact material 18. In practice, the
bit-line contact material 18 is filled in the contact hole between
stacked gates, in which a part of the gate cap film 16 made of a
silicon nitride film and a part of the contact barrier film 23 are
etched.
[0077] In the NOR-type memory cell shown in this embodiment, a
self-aligned contact structure is used to reduce the space between
the bit-line contact material 18 and the stacked gates as much as
possible, in the side of the bit-line contact material 18. Thus,
the memory cell array is downsized.
[0078] Meanwhile, in the side of the source line contact material
19, the withstanding voltage between the common source line contact
material 19 and the stacked gate is maintained without adopting a
self-aligned contact structure. During operation of erasing data
stored in the memory cell, a high voltage is applied between the
source region 17A and the control gate 15, and therefore, it is
difficult to use a self-aligned contact structure in which no
withstanding voltage is maintained.
[0079] Also, change of the electric characteristic in the memory
cell is reduced by forming a gate barrier film 22 on the side
surface of the stacked gate and the surface of the gate insulating
film 12 which are the common source line contact material 19. By
covering the surface of the gate insulating film 12 with the gate
barrier film 22, hot carriers (mainly positive holes) generated
between the source region 17A and the semiconductor substrate 11 by
a high voltage applied during erasure operation are prevented from
being injected into the gate insulating film 12 and being caught
between the gate insulating film 12 and the contact barrier film
23.
[0080] The film thickness of the gate barrier film 22 needs to be
about 100 .ANG. to 200 .ANG. thick in order to prevent hot carriers
being injected by tunneling. The film thickness of the contact
barrier film 23 needs to be, for example, about 200 .ANG. to 400
.ANG. thick, in consideration of the etching selection ratio when
forming a contact hole by self-alignment.
[0081] Although a silicon dioxide film is used as the gate barrier
film 22, another oxide-based insulating film may be used. The
another oxide-based insulating film may be, for example, a metal
oxide film such as an aluminum oxide film (Al.sub.2O.sub.3 or the
like), a tantalum oxide film (Ta.sub.3O.sub.5 or the like), or the
like. Although a silicon nitride film is used as the contact
barrier film 23, another nitride-based insulating film may be
used.
[0082] According to the NOR-type non-volatile semiconductor memory
device as the first embodiment, the gate barrier film (a silicon
dioxide film) 22 is not formed on the side surface of stacked gate,
which is adjacent to the bit-line contact material 18, when forming
a contact hole at the bit-line contact part having a self-aligned
contact structure. Therefore, the contact material does not enter
into the cavity area where the gate barrier film is etched, as
shown in FIG. 4B. It is thus possible to prevent the contact
material and the control gate from being short-circuited.
[0083] Further, the gate barrier film (silicon dioxide film) 22 is
formed between the gate insulating film 12 and the contact barrier
film (silicon nitride film) 23 which are adjacent to the source
region 17A. Therefore, it is possible to reduce hot carriers caught
between the gate insulating film 12 and the contact barrier film
23.
[0084] Second Embodiment
[0085] Next explanation will be made of an NAND-type non-volatile
semiconductor memory device according to a second embodiment of the
present invention.
[0086] FIG. 7A is a plan view showing the structure of a memory
cell array in the NAND-type non-volatile semiconductor memory
device according to the second embodiment. FIG. 7B is a
cross-sectional view of the memory cell array cut along a line
7B-7B.
[0087] A trench for separating an element is formed in a p-type
silicon semiconductor substrate (or p-type well) 31, and an element
separation insulating material such as a silicon dioxide material
is buried in the trench. In this manner, an element separation
region where a silicon dioxide material is buried and an element
region separated by the element separation region, where no silicon
dioxide material is buried are formed. A thin tunnel insulating
film 32 where a tunnel current can flow is formed on the entire
surface of the channel region in the element region inside the
semiconductor substrate.
[0088] A charge storage layer 33 is formed on the tunnel insulating
film 32. This charge storage layer 33 is formed such that side end
parts are aligned with the element separation region. The charge
storage layer 33 partially extends over the element separation
region and is cut above the element separation region, such that
memory cells are separated from each other. A control gate 35 is
formed on the charge storage layer 13 through an inter-gate
insulating film 34.
[0089] A gate cap film 36 is formed on the control gate 35. This
gate cap film 36 is made of, for example, a silicon nitride film.
The gate cap film 36 and the control gate 35 are processed to be
vertical to the surface of the semiconductor substrate, in a
self-alignment manner, such that the side end parts thereof are
aligned with the charge storage layer 33. A stacked gate is formed
by the charge storage layer 33, the control gate 35, and the gate
cap film 36. Formed in both sides of the stacked gate in the
semiconductor substrate 31 is an n-type diffusion layer 37 doped
with impurities of the conductivity type different from the p-type
semiconductor substrate (or p-type well) 31 in the channel region.
The n-type diffusion layer 37 forms a source or drain.
[0090] A plurality of stacked gates are provided and connected in
series so as to share the n-type diffusion layer 37. A bit-line
contact material 38 and a common source-line contact material 39
are formed on each of the n-type diffusion layer 37 at the end of
the stacked gates connected in series. The stacked gate adjacent to
the contact materials 38 and 39 operates as a selection transistor.
At the selection transistor, the charge storage layer 33 and the
control gate 35 are short-circuited, so that a signal is directly
applied to the charge storage layer 33. A plurality of stacked
gates sandwiched between selection transistors operate as memory
cells.
[0091] The bit line contact material 38 and the common source line
contact material 39 are made of low-resistance polysilicon, metal
material, or the like which is conductive material. The upper parts
of the contact materials 38 and 39 are each flattened. The bit-line
contact material 38 is connected to a bit line 40 made of a metal
electrode. The common source contact material 39 is connected to
the common source line 41.
[0092] The stacked gate of the memory cell and the stacked gate of
the selection transistor are covered with a gate barrier film 42
made of a silicon dioxide film. Further, a contact barrier film 43
made of a silicon nitride film covers the gate barrier film 42.
[0093] In the stacked gate of the selection transistor adjacent to
the bit-line contact material 38, the gate barrier film 42 is
removed from the side surface adjacent to the bit-line contact
material 38. The structure is therefore constructed in a structure
in which the side surface is directly covered with the contact
barrier film 43.
[0094] Also, in the stacked gate of the selection transistor
adjacent to the common source line contact material 39, the gate
barrier film 42 is removed from the side surface adjacent to the
common source line contact material 39. The structure is therefore
constructed in a structure in which the side surface is directly
covered with the contact barrier film 43.
[0095] In other words, the gate barrier film 42 is formed on the
side surface of the stacked gate which is adjacent to the memory
cell, and the contact barrier film 43 is further formed on the gate
barrier film 42. However, the gate barrier film 42 is not formed on
the side surface of the stacked gate of the selection transistor,
which is adjacent to the bit-line contact material 38 or the common
source line contact material 39, but the contact barrier film 43 is
formed directly on this side surface.
[0096] As shown in FIG. 7B, an interlayer insulating film 44, e.g.,
a BPSG film or the like is formed on the semiconductor substrate
31.
[0097] The bit line contact material 38 is provided so as to
contact the contact barrier film 43 formed on the side surface of
the stacked gate of the selection transistor, without maintaining
any distance therebetween.
[0098] Further, the bit line contact material 38 is formed so as to
extend partially over the stacked gates in both sides. This bit
line contact material 38 is formed to be buried between contact
barrier films (silicon nitride films) 43 on adjacent gates, on the
semiconductor substrate 31. The structure of the part of the bit
line contact material 38 is constructed into a self-aligned contact
structure. This self-aligned contact structure is formed through
the steps described below. Using a contact barrier film 43 and a
gate cap film 36 as masks, a contact hole is formed by
self-aligning process. Thereafter, a contact material is buried in
the contact hole, to form a bit-line contact material 38. In
practice, as shown in FIG. 7B, the bit-line contact material 38 is
filled in the contact hole between stacked gates, in which a part
of the gate cap film 36 made of a silicon nitride film and a part
of the contact barrier film 43 are etched.
[0099] Likewise, the source line contact material 39 is provided so
as to contact the contact barrier film 43 formed on the side
surface of the stacked gate of the selection transistor, with not
distance maintained therebetween. Further, the common source line
contact material 39 is formed so as to extend partially over the
stacked gates in both sides. This common source line contact
material 39 is formed to be buried between contact barrier films
(silicon nitride films) 43 on gates of selection transistors
adjacent to each other, on the semiconductor substrate 31. The
structure of the part of the common source line contact material 39
is constructed through the steps described below. Using the contact
barrier film 43 and the gate cap film 36 as masks, a contact hole
is formed by self-aligning process. Thereafter, a contact material
is buried in the contact hole, to form a common source line contact
material 39. In practice, as shown in FIG. 7B, the common source
line contact material 39 is filled in the contact hole between
stacked gates, in which a part of the gate cap film 36 and a part
of the contact barrier film 43 are etched.
[0100] In the NAND-type memory cell shown in this embodiment, the
stacked gate of the memory cell is covered with the gate barrier
film 42 made of a silicon dioxide film, and the gate barrier film
42 is covered with the contact barrier film 43 made of a silicon
nitride film. Meanwhile, the stacked gate of the selection
transistor has a structure in which the side surface which is
adjacent to the contact material 38 or 39 is not covered with the
gate barrier film 42 but is directly covered with the contact
barrier film 43.
[0101] The stacked gate of the memory cell is covered with the gate
barrier film 42 and the gate barrier film 42 is formed on the gate
insulating film 32 between the stacked gates because hot carriers
(mainly positive holes) generated between the source region 17A and
the semiconductor substrate 11 by a high voltage applied during
erasure operation can be prevented from being injected into the
gate insulating film 12 and being caught between the gate
insulating film 12 and the contact barrier film 23, like the case
of the NOR-type memory cell according to the first embodiment.
[0102] The film thickness of the gate barrier film 22 needs to be
about 100 .ANG. to 200 .ANG. thick in order to prevent hot carriers
being injected by tunneling. The film thickness of the contact
barrier film 43 needs to be, for example, about 200 .ANG. to 400
.ANG. thick, in consideration of the etching selection ratio when
forming a contact hole by self-alignment.
[0103] Although a silicon dioxide film is used as the gate barrier
film 42, another oxide-based insulating film may be used. The
another oxide-based insulating film may be, for example, a metal
oxide film such as an aluminum oxide film (Al.sub.2O.sub.3 or the
like), a tantalum oxide film (Ta.sub.3O.sub.5 or the like), or the
like. Although a silicon nitride film is used as the contact
barrier film 43, another nitride-based insulating film may be
used.
[0104] According to the NAND-type non-volatile semiconductor memory
device as the second embodiment having the structure as described
above, the gate barrier film (a silicon dioxide film) 42 is not
formed on the side surface of stacked gate, which is adjacent to
the bit-line contact material 38, when forming a contact hole at
the bit-line contact material 38 (or the common source line contact
material 39) having a self-aligned contact structure. Therefore,
the contact material does not enter into the cavity area where the
gate barrier film is etched. It is thus possible to prevent the
contact material and the control gate from being
short-circuited.
[0105] Further, the gate barrier film (silicon dioxide film) 42 is
formed between the gate insulating film 32 in both sides of the
stacked gate of the memory cell (on the n-type diffusion layer 37
forming a source or drain) and the contact barrier film (silicon
nitride film) 43. Therefore, it is possible to reduce hot carriers
caught between the gate insulating film 32 and the contact barrier
film 43. The electric characteristics of the memory can hence be
prevented from being changed due to influences from caught hot
carriers.
[0106] Next explanation will be made of a method of manufacturing
the NAND-type memory cell.
[0107] FIGS. 8A, 8B, 9A, and 9B are cross-sectional views showing
main steps of the method of manufacturing the NAND-type memory
cell.
[0108] As shown in FIG. 8A, a silicon nitride film to form the
contact barrier film 43 when opening a contact hole is deposited as
shown in FIG. 8B. Further, an interlayer insulating film (e.g.,
BPSG film) 44 is formed on the contact barrier film 32. Thereafter,
the interlayer insulating film 44 is melted by thermal annealing,
and thereafter, the interlayer insulating film 44 is flattened, for
example, by CMP or the like.
[0109] Next, as shown in FIG. 9A, a contact hole is opened by
lithography and dry etching. At this time, a part of the gate cap
film (silicon nitride film) 36 is etched in correspondence with the
etching selection ratio between the interlayer insulating film
(BPSG film) 44 and the contact barrier film (silicon nitride film)
43.
[0110] Subsequently, interface cleaning processing such as
hydrofluoric acid (HF) processing or the like is carried out.
Thereafter, for example, metal such as low-resistance polysilicon
or tungsten (W) to form the contact material is buried, as shown in
FIG. 9B. Further, the contact material is polished and flattened,
thereby to form the bit-line contact material 38 and the common
source line contact material 39.
[0111] In this method of manufacturing a NAND-type memory cell, the
gate barrier film 42 on the side surface of the stacked gate, which
is adjacent to the bit-line contact material or the common source
line contact material 39, is previously pealed. In this manner,
when opening a contact hole, the gate barrier film 42 is exposed
and the gate barrier film 42 is locally etched back. Thereafter,
when contact material is buried, the contact material and the
control gate 35 are prevented from being short-circuited.
[0112] Third Embodiment
[0113] Next explanation will be made of a NAND-type non-volatile
semiconductor memory device as a third embodiment of the present
invention. In the second embodiment, all of the gate barrier film
42 which covers the side surface of the stacked gate adjacent to
the contact material 38 or 39 is peeled off. In the present third
embodiment, however, dry-etching conditions are optimized to remove
only the gate barrier film 42 covering the side surface of the gate
cap film 36.
[0114] FIG. 10 is a cross-sectional view showing a memory cell
array in the NAND-type non-volatile semiconductor memory device
according to the third embodiment.
[0115] As shown in FIG. 10, the gate barrier film 42A covering the
side surface of the stacked gate, which is adjacent to the contact
material 38 or 39, covers only all areas of the side surface of the
charge storage layer 33 and the side surface of the inter-gate
insulating film 34, and a part of the side surface of the control
gate 35. The other points of the structure are the same as those of
the second embodiment.
[0116] To form the structure as shown in FIG. 10, the gate barrier
film 42A covering the side surface of the stacked gate needs only
to shift back to the side surface of the control gate 35 by
optimizing dry-etching conditions when opening a contact hole.
[0117] Also, in the third embodiment having this structure, the
gate barrier film (silicon dioxide film) 42A is not formed on the
side surface of the gate cap film 36 which is adjacent to the
bit-line contact material 38 (or the common source line contact
material 39). Therefore, the gate barrier film 42A is not exposed
when forming a contact hole. Accordingly, no contact material
enters into the cavity region in the exposed gate barrier film 42,
which is exposed to and etched by an etching agent, when a contact
hole is formed. The contact material and the control gate can thus
be prevented from being short-circuited.
[0118] Further, the gate barrier film (silicon dioxide film) 42A is
formed between the contact barrier film 43 and the gate insulating
film 32 in both sides of the stacked gate of the selection
transistor and the memory cell (on the n-type diffusion layer 37).
It is therefore possible to reduce hot carriers caught between the
gate insulating film 32 and the contact barrier film 43. In this
manner, electric characteristics can be prevented from being
changed by influences from the caught hot carriers.
[0119] Although a silicon dioxide film is used as the gate barrier
film 42A, another oxide-based insulating film may be used. The
another oxide-based insulating film may be, for example, a metal
oxide film such as an aluminum oxide film (Al.sub.2O.sub.3 or the
like), a tantalum oxide film (Ta.sub.3O.sub.5 or the like), or the
like.
[0120] Fourth Embodiment
[0121] Next explanation will be made of a NAND-type non-volatile
semiconductor memory device according to the fourth embodiment of
the present invention. In the third embodiment described above,
only the gate barrier film covering the side surface of the gate
cap film 36 of the selection transistor, which is adjacent to the
contact material 38 or 39, is removed. In the present fourth
embodiment, the gate barrier film 42 covering the side surfaces of
the gate cap films 36 of both the selection transistor and the
memory cell is removed.
[0122] FIG. 11 is a cross-sectional view of a memory cell array in
the NAND-type non-volatile semiconductor memory device according to
the fourth embodiment.
[0123] As shown in FIG. 11, the gate barrier film 42A covering the
side surface of the stacked gate, which is adjacent to the contact
material 38 or 39, covers all areas of the side surface of the
charge storage layer 33 and the side surface of the inter-gate
insulating film 34, and only a part of the side surface of the
control gate 35. Further, the gate barrier film 42A covering the
side surface of the stacked gate of the memory cell covers all
areas of the side surface of the charge storage layer 33 and the
side surface of the inter-gate insulating film 34, and only a part
of the side surface of the control gate 35. The other points of the
structure are the same as those of the second embodiment.
[0124] To form the structure as shown in FIG. 11, dry-etching
conditions need to be optimized without using lithography, and the
gate barrier film 42 covering the side surface of the gate cap film
36 of the selection transistor and the gate barrier film 42
covering the side surface of the gate cap film 36 of the stacked
gate of the memory cell need to be etched simultaneously. Further,
the gate barrier film 42 needs to shift back to the side surface of
the control gate 35.
[0125] Also, in the fourth embodiment having this kind of
structure, the gate barrier film (silicon dioxide film) 42A is not
formed on the side surface of the gate cap film 36 which is
adjacent to the bit-line contact material 38 (or the common source
line contact material 39). Therefore, the gate barrier film 42A is
not exposed when forming a contact hole. Accordingly, no contact
material enters into the cavity region in the exposed gate barrier
film 42, which is exposed to and etched by an etching agent, when a
contact hole is formed. The contact material and the control gate
35 can thus be prevented from being short-circuited.
[0126] Further, the gate barrier film (silicon dioxide film) 42A is
formed between the contact barrier film 43 and the gate insulating
film 32 in both sides of the stacked gate of the selection
transistor and the memory cell (on the n-type diffusion layer 37
forming a source or drain). It is therefore possible to reduce hot
carriers caught between the gate insulating film 32 and the contact
barrier film 43. In this manner, electric characteristics can be
prevented from being changed by influences from the caught hot
carriers.
[0127] Although a silicon dioxide film is used as the gate barrier
film 42A, another oxide-based insulating film may be used. The
another oxide-based insulating film may be, for example, a metal
oxide film such as an aluminum oxide film (Al.sub.2O.sub.3 or the
like), a tantalum oxide film (Ta.sub.3O.sub.5 or the like), or the
like.
[0128] Fifth Embodiment
[0129] Next explanation will be made of a NAND-type non-volatile
semiconductor memory device according to the fifth embodiment of
the present invention. The fifth embodiment has been proposed to
solve the following two problems. One is a problem that the contact
area between the bit-line contact material and the semiconductor
substrate is greatly reduced. Another is a problem that the
bit-line contact part and the contact part of a peripheral
transistor cannot be formed by one same step.
[0130] The non-volatile semiconductor memory device according to
the fifth embodiment has a memory cell array and a peripheral
circuit. The peripheral circuit has a plurality of peripheral
transistors and serves to control the operation of the memory cell
array. More specifically, the peripheral circuit controls the
signals supplied to the bit line, source line, and control gate, or
controls signals received through these lines. The peripheral
transistor is a high-withstanding-voltage type transistor whose
gate insulating film is much thicker than that of the memory cell.
In the fifth embodiment, those parts that are common to the second
embodiment will be denoted at common reference symbols.
[0131] Explained at first will be the structure of the memory cell
array in the non-volatile semiconductor memory device according to
the fifth embodiment.
[0132] FIG. 12A is a plan view showing a memory cell array in the
NAND-type non-volatile semiconductor memory device according to the
fifth embodiment. FIG. 12B is a cross-sectional view of the memory
cell array cut along the line 12B-12B. FIG. 12C is a
cross-sectional view of the memory cell array cut along the line
12C-12C. FIG. 12D is a cross-sectional view of the memory cell
array cut along the line 12D-12D.
[0133] FIG. 12B shows a cross-section along a word line of memory
cells forming part of the memory cell array. As shown in FIG. 12B,
a trench groove is formed in the p-type silicon semiconductor
substrate (or p-type well). In the trench groove, an element
separation insulating material such as silicon dioxide material is
filled. In this manner, an element separation region 52 filled with
the silicon dioxide material, and an element region separated by
the element separation region 52 and not filled with the silicon
dioxide material are formed. A thin tunnel insulating film 32
through which a tunnel current flows is formed in the entire
surface of the channel region of the element region in the
semiconductor substrate.
[0134] A charge storage layer 33 is formed on the tunnel insulating
film 32. This charge storage layer 33 is formed such that a side
end part thereof is aligned with the element separation region 52.
The charge storage layer 33 partially extends over the element
separation region 52 and is cut above the element separation region
52 to be separated for every memory cell. A control gate 35 is
formed above the charge storage layer 33 with an inter-gate
insulating film 34 inserted therebetween.
[0135] A gate cap film 36 is formed on the control gate 35. This
gate insulating film 36 is made of, for example, a silicon nitride
film. The gate cap film 36 and the control gate 35 are processed in
a self-aligning manner to be vertical to the surface of the
semiconductor substrate, such that the end parts of the film 36 and
the gate 35 are aligned with the charge storage layer 33. A stacked
gate is formed by the charge storage layer 33, the control gate 35,
and the gate cap film 36.
[0136] A gate barrier film 42 made of a silicon dioxide film is
formed on the gate cap film 36. A contact barrier film 43 made of a
silicon nitride film is formed on the gate barrier film 42. An
interlayer insulating film 44 is formed on the contact barrier film
43. Further, a bit line 40 is formed on the interlayer insulating
film 44.
[0137] FIG. 12C shows a cross-section in the word line direction
between word lines of the memory cell array. As shown in FIG. 12C,
the element separation region 51 which is made of, for example,
silicon dioxide material filled therein is formed in the trench
groove. The element separation region 51 is formed to be thinner
than the element separation region 52 exiting below the control
gate 35. That is, the surface level of the element separation
region 51 is lower than the surface level of the element separation
region 52.
[0138] The gate barrier film 42 is formed on the semiconductor
substrate 31 and the element separation region 51. The contact
barrier film 43 is formed on the gate barrier film 42. The
interlayer insulating film 44 is formed on the contact barrier film
43. Further, a bit line 40 is formed on the interlayer insulating
film 44.
[0139] FIG. 12D shows a cross-section of the bit-line contact part
of the memory cell array in the word line direction. As shown in
FIG. 12D, for example, the element separation region 51 which is
made of a silicon dioxide film filled therein is formed in the
trench groove of the p-type silicon semiconductor substrate (or
p-type well). The element separation region 51 is formed to be
thinner than the element separation region 52 existing below the
control gate 35. That is, the surface level of the element
separation region 51 is lower than the surface level of the element
separation region 52.
[0140] The contact barrier film 43 is formed on the semiconductor
substrate 31 and the element separation region 51. The interlayer
insulating film 44 is formed on the contact barrier film 43. Also,
a bit-line contact material 38 is filled between the element
separation regions 51 on the semiconductor substrate 31, such that
the material 38 is in contact with the semiconductor substrate 31.
Further, a bit line 40 is formed on the bit-line contact material
38. The contact barrier film 43 does not remain on the side surface
in the side of the contact material 38 of the element separation
region 51, but only the gate barrier film 42 remains thin. However,
if the surface level of the element separation region 51 is much
lower than the surface level of the element separation region 52,
the gate barrier film 42 does not remain in some cases.
[0141] Next, explanation will be made of a peripheral transistor
forming part of a peripheral circuit in the non-volatile
semiconductor substrate according to the fifth embodiment.
[0142] FIG. 13A is a plan view of a peripheral transistor forming
part of a peripheral circuit in the NAND-type non-volatile
semiconductor memory device according to the fifth embodiment. FIG.
13B is a cross-section of the peripheral transistor cut along the
line 13B-13B.
[0143] As shown in FIG. 13B, the element separation region 51 which
is made of, for example, silicon dioxide material filled in the
trench groove, and an element region, which is separated by the
element separation region 51 and is not filled with silicon dioxide
material, are formed on the p-type silicon semiconductor substrate
(or p-type well) 31. The element separation region 51 is formed to
be thinner than the element separation region 52 existing below the
control gate 35. That is, the surface level of the element
separation region 51 is lower than the surface level of the element
separation region 52.
[0144] A gate insulating film 54 which is much thicker than the
gate insulating film 32 which the memory cells have is formed on
the element region (channel region) in the semiconductor substrate
31. A charge storage layer 33 is formed on the gate insulating film
54. A control gate 35 is formed on the charge storage layer 33 with
an inter-gate insulating film 34 inserted therebetween. A gate cap
film 36 is formed on the control gate 35. This gate insulating film
36 is made of, for example, a silicon nitride film. The gate cap
film 36 and the control gate 35 are processed in a self-aligning
manner to be vertical to the surface of the semiconductor substrate
such that side end parts of the film 36 and the gate 35 are aligned
with the charge storage layer 33. A stacked gate is formed by the
charge storage layer 33, the control gate 35, and the gate cap film
36.
[0145] Also, on the gate cap film 36, a gate barrier film 42 made
of a silicon dioxide film is formed so as to cover the gate cap
film 36. The gate barrier film 42 is also formed on the
semiconductor substrate 31. A contact barrier film 43 made of a
silicon nitride film is formed on the gate barrier film 42. The
contact barrier film 43 is also formed on the element separation
region 51. Further, an interlayer insulating film 44 is formed on
the contact barrier film 43.
[0146] A contact material 53 is filled between the element
separation region 51 and the stacked gate on the semiconductor
substrate 31, such that the contact material 53 contacts the
semiconductor substrate 31. A contact interconnection 55 is formed
on the contact material 53. Between the element separation region
51 and the stacked gate, the gate insulating film 54 is removed (or
thinned), on the semiconductor substrate 31. Therefore, only the
gate barrier film 42 and the contact barrier film 43 are formed
orderly on the semiconductor substrate 31. Therefore, in case of
forming a contact hole in the semiconductor substrate 31 between
the element separation region 51 and the stacked gate, the contact
hole can be formed in the same step as that of forming a contact
hole in the semiconductor substrate 31 between the element
separation regions 51 as shown in FIG. 12D. As has been described
above, the memory cell array according to the fifth embodiment and
a peripheral transistor forming part of a peripheral circuit
respectively have the structures described above.
[0147] A self-aligned STI structure in which a side end part of the
charge storage layer is aligned with a trench forming part of an
element separation region is effective as an element separation
structure in a flash memory. However, as shown in FIG. 5, the
element separation region 217 is formed to be higher than the
semiconductor substrate. Therefore, there is a problem that the
gate barrier film 214 and the contact barrier film 215 remain, like
spacers, on the side surface of the element separation region 217,
in a region between adjacent control gates.
[0148] In this embodiment, the film thickness of the element
separation region 51 between adjacent control gates (see FIG. 12D)
is thinner than the film thickness of the element separation film
52 below the control gate 35 (see FIG. 12B). Thus, the element
separation region 51 is thinned to reduce the gate barrier film 42
and the contact barrier film 43 on the side surface of the element
separation region 51. In this manner, the exposed area of the
semiconductor substrate 31 can be enlarged to lower the contact
resistance, at the part where the bit line contact material 38 is
formed.
[0149] In a non-volatile semiconductor memory device, particularly,
the film thickness of the gate insulating film of the
high-withstanding-volta- ge-based transistor of the peripheral
transistor forming part of the peripheral circuit is generally much
thicker than that of the gate insulating film of the memory cell.
Therefore, in a step of forming a contact hole in the peripheral
transistor, the contact barrier film and the gate barrier film are
etched, and thereafter, the thick gate insulating film of the
peripheral transistor needs to be removed. If a contact hole in the
high-withstanding-voltage-based peripheral transistor and a
bit-line contact hole having a self-aligned contact structure are
formed simultaneously in one same step, drawbacks occur in that the
gate cap film 36 is reduced and the element separation region 51
partially extending over the contact hole shifts back. It is
therefore difficult to form a contact hole in the peripheral
transistor at the same time when a bit-line contact hole is
formed.
[0150] In contrast, in the present embodiment, as shown in FIGS.
13A and 13B, a gate insulating film 54 on the diffusion layer (the
semiconductor substrate 31) where a contact hole (contact material
53) of a high-withstanding-voltage-based transistor is previously
formed is thinned or removed. In this manner, it is possible to
form a contact hole of the high-withstanding-voltage-based
transistor, at the same time when a contact hole of the bit-line
contact part is formed.
[0151] Explanation will now be made of a method of forming the
non-volatile semiconductor memory device according to the fifth
embodiment.
[0152] At first, a stacked gate including a gate cap film 36 is
formed by vertical process. Thereafter, the element separation
region 51 between stacked gates and the gate insulating film 54
between stacked gates are etched, with the gate cap mask 36 used as
a mask. At this time, it is important to subject the silicon
nitride film as the gate cap film 36 and the silicon substrate 31
to etching which attains a high selection ratio. In addition, the
etching amount must be set to such an amount that can remove the
gate insulating film 54 of the high-withstanding-voltage-based
transistor.
[0153] Further, the surface level of the element separation region
51 must be higher than the surface of the semiconductor substrate
31 where the trench is formed and must be lower than the upper
surface of the charge storage layer 33. By this etching, the
thickness of the element separation region 51 between the stacked
gates becomes smaller than the film thickness of the element
separation region 52 below the stacked gates. Thereafter, surface
processing is performed on the side surface of the stacked gates by
thermal oxidation or the like, and the gate barrier film 42 and the
contact barrier film 43 are formed thereafter.
[0154] According to the manufacturing method as described above,
the element separation region 51 is thinned previously, so that the
height of the exposed side surface of the element separation region
51 is lowered. Therefore, residues like spacers (the gate barrier
film 42 and the contact barrier film 43) can be prevented from
remaining when a contact hole is opened.
[0155] The present invention is not limited to the embodiments
described above. The thickness of the gate insulating film and the
materials of the electrodes can be selected arbitrarily.
[0156] Preferred embodiments of the present invention will now be
described below.
[0157] 1. The conductive material forming the charge storage layer
is, for example, a polycrystalline or non-crystalline silicon
material having a high electric conductance by doping
impurities.
[0158] 2. The charge storage layer is formed on, for example, a
thermal oxide film having a film thickness of about 100 .ANG..
[0159] 3. The control gate is a single layer made of a silicon
material such as a polycrystalline or non-crystalline silicon
material having a high electric conductance by doping impurities, a
high-melting-point metal material such as tungsten (W) or the like,
a layered structure of silicide such as tungsten silicide (WSi) or
the like and silicon, silicide formed by depositing metal such as
titanium (Ti) or the like on the above-described silicon material
and by letting the resultant chemically reacting silicon by thermal
annealing, or a low-resistance metal material such as aluminum (Al)
or the like.
[0160] 4. The control gate is formed on, for example, a silicon
dioxide film having a thickness of about 100 .ANG. to 200 .ANG., or
a layered film comprised of a silicon dioxide film and a silicon
nitride film, which is formed on the charge storage layer.
[0161] 5. The element separation insulating film is a silicon
dioxide material having an excellent burring characteristic with a
high aspect ratio, PSG or BPSG containing impurities such as
phosphorus (P) or boron (B), or a layered structure of the
materials described above.
[0162] In the embodiments of the present invention, of a memory
cell and a selection transistor which are covered with a first
insulating film (e.g., silicon dioxide film) and a second
insulating film (e.g., a silicon nitride film), the first
insulating film is removed from the side surfaced of the stacked
gate which is adjacent to the bit-line contact. Further, the
element separation insulating film between control gates is
arranged to be thinner than the element separation insulating film
below the control gate, to lower the height of the side wall of the
element separation insulating film at the bit-line contact part.
Further, the film thickness of the gate insulating film at the
contact part connected to the source diffusion layer or drain
diffusion layer of the high-withstanding-voltage-based transistor
is arranged to be smaller than the film thickness of the gate
insulating film below the gate electrode of the transistor. In this
manner, the processing margin which is taken to construct the
bit-line contact into a self-aligned contact structure can be set
to be high. Accordingly, it is possible to realize a non-volatile
semiconductor memory device capable of achieving high density and
high reliability.
[0163] Although a silicon dioxide film is used as a first
insulating film, another oxide-based insulating film may be used.
The another oxide-based insulating film may be, for example, a
metal oxide film such as an aluminum oxide film (Al.sub.2O.sub.3 or
the like), a tantalum oxide film (Ta.sub.3O.sub.5 or the like), or
the like. Although a silicon nitride film is used as a second
insulating film, another nitride-based insulating film may be
used.
[0164] As has been described above, according to an embodiment of
the present invention, it is possible to provide a non-volatile
semiconductor memory device which is capable of attaining a high
processing margin when the bit-line contact is constructed into a
self-aligned contact structure and is also capable of achieving
high density and high reliability.
[0165] Additional advantages and modifications will readily occur
to those skilled in the art. Therefore, the invention in its
broader aspects is not limited to the specific details and
representative embodiments shown and described herein. Accordingly,
various modifications may be made without departing from the spirit
or scope of the general inventive concept as defined by the
appended claims and their equivalents.
* * * * *