U.S. patent application number 10/453049 was filed with the patent office on 2003-09-18 for grooved heat spreader for stress reduction in ic package.
Invention is credited to Chen, Ken, Tsao, Pei-Haw, Wang, Jones.
Application Number | 20030176020 10/453049 |
Document ID | / |
Family ID | 27735047 |
Filed Date | 2003-09-18 |
United States Patent
Application |
20030176020 |
Kind Code |
A1 |
Tsao, Pei-Haw ; et
al. |
September 18, 2003 |
Grooved heat spreader for stress reduction in IC package
Abstract
A new design is provided for the heat spreader of a
semiconductor package. Grooves are provided in a surface of the
heat spreader, subdividing the heat spreader for purposes of stress
distribution into four or more sections. This division of the heat
spreader results in a reduction of the mechanical and thermal
stress that is introduced by the heat spreader into the device
package. Mechanical and heat stress, using conventional heat
spreader designs, has a negative, stress induced, effect on the
semiconductor die, on the contact points (bump joints) of the
semiconductor die and on the solder ball connections of the
package.
Inventors: |
Tsao, Pei-Haw; (Taichung,
TW) ; Wang, Jones; (Junghe City, TW) ; Chen,
Ken; (Hsinchu, TW) |
Correspondence
Address: |
George O. Saile
28 Davis Avenue
Poughkeepsie
NY
12603
US
|
Family ID: |
27735047 |
Appl. No.: |
10/453049 |
Filed: |
June 3, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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10453049 |
Jun 3, 2003 |
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09912739 |
Jul 26, 2001 |
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Current U.S.
Class: |
438/122 ;
257/706; 257/707; 257/E23.069; 257/E23.092; 257/E23.101 |
Current CPC
Class: |
H01L 2224/73204
20130101; H01L 2224/73253 20130101; H01L 2224/45099 20130101; H01L
2224/16225 20130101; H01L 23/36 20130101; H01L 2224/05599 20130101;
H01L 2924/00014 20130101; H01L 2924/00 20130101; H01L 2924/00014
20130101; H01L 2224/73204 20130101; H01L 2224/16225 20130101; H01L
2224/16225 20130101; H01L 2224/32225 20130101; H01L 2924/00014
20130101; H01L 2224/32225 20130101; H01L 2924/00 20130101; H01L
2924/207 20130101; H01L 2924/00012 20130101; H01L 2224/45015
20130101; H01L 2224/45099 20130101; H01L 2924/00012 20130101; H01L
2924/00014 20130101; H01L 2924/181 20130101; H01L 2224/85399
20130101; H01L 2924/15311 20130101; H01L 2224/48095 20130101; H01L
2224/05599 20130101; H01L 2224/16 20130101; H01L 2924/181 20130101;
H01L 2224/32245 20130101; H01L 2224/48227 20130101; H01L 2924/3025
20130101; H01L 2224/32225 20130101; H01L 2224/48095 20130101; H01L
2924/00014 20130101; H01L 2924/14 20130101; H01L 2924/00014
20130101; H01L 23/3128 20130101; H01L 2924/16195 20130101; H01L
24/48 20130101; H01L 23/4334 20130101; H01L 2224/73204 20130101;
H01L 23/49816 20130101; H01L 2924/15311 20130101; H01L 2224/85399
20130101; H01L 2924/14 20130101 |
Class at
Publication: |
438/122 ;
257/707; 257/706 |
International
Class: |
H01L 023/34 |
Claims
What is claimed is:
1. A method of creating a heat spreader for use in a semiconductor
package, comprising the steps of: providing a heat spreader for a
semiconductor package; and providing at least one groove across
said heat spreader.
2. The method of claim 1, said heat spreader being a rectangular
cube having two large parallel first and a second surfaces of equal
surface area bounded by four interconnecting surfaces, a surface
area of said interconnecting surfaces being smaller than the
surface area of said first and a second large surfaces by a
measurable amount, the first surface of said heat spreader having
been designated as being the side that faces a semiconductor die
after mounting said die in a package of which said heat spreader is
an integral part, said first surface facing said die.
3. The method of claim 1 wherein said at least one groove comprises
two grooves provided at distances from side boundaries of said
first surface, said two grooves intersecting.
4. The method of claim 1 wherein said at least one groove comprises
four grooves, a first and a second of said four grooves
intersecting a third and a fourth of said four grooves, said first
and said second of said four grooves being provided at a distance
from side boundaries of said first surface in accordance with a
first equation, said third and said fourth of said four grooves
being provided at a distance side boundaries of said first surface
in accordance with a second equation.
5. The method of claim 1 wherein said at least one groove comprises
a multiplicity of grooves, a first half of said multiplicity of
grooves intersecting a second half of said multiplicity of grooves,
said first half of said multiplicity of grooves being provided at
distances from side boundaries of said first surface in accordance
with a first equation, said second half of said multiplicity of
grooves being provided at a distance from side boundaries of said
first surface in accordance with a second equation.
6. The method of claim 1 wherein said providing at least one groove
across said first surface of said heat spreader comprises using
methods of etching or machining or punching of the first surface of
the heat spreader.
7. A heat spreader for a semiconductor package, comprising: a heat
spreader; and at least one groove formed on the surface of said
heat spreader.
8. The heat spreader of claim 7, wherein said heat spreader is a
rectangular cube having two large parallel first and second
surfaces, said first surface of said heat spreader facing a
semiconductor die, said at least one groove being formed across
said first surface.
9. The heat spreader of claim 8, wherein said at least one groove
divides the surface area of said first surface.
10. The heat spreader of claim 8, said at least one groove
comprising two grooves, said two grooves intersecting under an
angle of 90 degrees.
11. A method of creating a semiconductor package, comprising the
steps of: providing a semiconductor device mounting support, said
semiconductor device mounting support having a first and a second
surface, first points of electrical contact having been provided in
said first surface of said semiconductor device mounting support,
second points of electrical contact having been provided in said
second surface of said semiconductor device mounting support, one
or more layers of interconnect lines having been provided in said
semiconductor device mounting support or on the first or second
surface of said semiconductor device mounting support; providing a
semiconductor devices, said semiconductor device having been
provided with points of electrical contact in a first surface of
said semiconductor device; positioning said semiconductor device
above the second surface of said semiconductor device mounting
support, said first surface of said semiconductor device facing
said second surface of said semiconductor device mounting support,
aligning and establishing contact between said points of electrical
contact provided in said first surface of said semiconductor device
and said points of electrical contact provided in said second
surface of said semiconductor device mounting support; establishing
electrical continuity between said points of electrical contact
provided in said first surface of said semiconductor device and
said points of electrical contact provided in said second surface
of said semiconductor device mounting support by a reflow of said
points of electrical contact provided in the first surface of said
semiconductor device; providing an underfill for said semiconductor
device, leaving a second surface of said semiconductor device
exposed; applying a first adhesive layer over the second surface
area of the said semiconductor device mounting support that is not
being covered by said underfill; providing a semiconductor device
stiffener having a first and a second surface, said stiffener
having been provided with an opening penetrating from said first to
said second surface of said stiffener and of adequate size for
insertion of said semiconductor device; positioning said stiffener
over the first adhesive layer applied over the second surface of
said semiconductor device mounting support, said first surface of
said stiffener facing said first adhesive layer, said opening
provided in said stiffener being aligned with said semiconductor
device mounted on the second surface of said semiconductor device
mounting support, said stiffener making contact with said first
adhesive layer; applying a second adhesive layer over the second
surface of said semiconductor device and the second surface of said
stiffener; providing a heat spreader having a first and a second
surface, said first surface of said heat spreader having been
provided with a pattern of grooves, said pattern of grooves
comprising at least one groove dividing the surface area of said
first surface in sections; positioning the first surface of said
heat spreader over the surface of said second adhesive layer;
providing said first surface of said semiconductor device mounting
support with a solder mask, openings in said solder mask exposing
said contact points provided in said first surface of said
semiconductor device mounting support; inserting solder balls into
said openings provided in said solder mask; and establishing
electrical continuity between said solder balls inserted in said
openings in said solder mask and said contact points provided in
said first surface of said semiconductor device mounting support by
a process of reflow.
12. The method of claim 11 wherein said semiconductor device
mounting support is selected from the group consisting of a Printed
Circuit Board and a metallized structure and a glass substrate.
13. The method of claim 11 wherein said pattern of grooves
comprises two grooves provided at distances from side boundaries of
said first surface.
14. The method of claim 11 wherein said pattern of grooves
comprises four grooves, a first and a second of said four grooves
intersecting a third and a fourth of said four grooves, said first
and said second of said four grooves being provided at a distance
from side boundaries of said first surface in accordance with a
first equation, said third and said fourth of said four grooves
being provided at a distance from side boundaries of said first
surface in accordance with a second equation.
15. The method of claim 11 wherein said pattern of grooves
comprises a multiplicity of grooves, a first half of said
multiplicity of grooves intersecting a second half of said
multiplicity of grooves, said first half of said multiplicity of
grooves being provided at distances from side boundaries of said
first surface in accordance with a first equation, said second half
of said multiplicity of grooves being provided at a distance from
side boundaries of said first surface in accordance with a second
equation.
16. The method of claim 11 wherein said pattern of grooves is
provided across said first surface of said heat spreader comprises
using methods of etching or machining or punching of the first
surface of the heat spreader.
17. A semiconductor package, comprising: a semiconductor device
mounting support; a semiconductor device, said semiconductor device
being mounted on a surface of said semiconductor device mounting
support; a semiconductor device stiffener mounted on said
semiconductor mounting support, said stiffener having been provided
with an opening, said opening having adequate size for insertion of
said semiconductor device; and a heat spreader having a first and a
second surface, said first surface of said heat spreader having
been provided with a pattern of grooves, said pattern of grooves
comprising at least one groove dividing the surface area of said
first surface in sections, the first surface of said heat spreader
having been positioned over the surface of said semiconductor
device.
18. The semiconductor package of claim 17 wherein said
semiconductor device mounting support is selected from the group
consisting of a Printed Circuit Board and a metallized structure
and a glass substrate.
19. The semiconductor package of claim 17 wherein said pattern of
grooves comprises two grooves provided at distances from side
boundaries of said first surface.
20. The semiconductor package of claim 17 wherein said pattern of
grooves comprises four grooves, a first and a second of said four
grooves intersecting a third and a fourth of said four grooves,
said first and said second of said four grooves being provided at a
distance from side boundaries of said first surface in accordance
with a first equation, said third and said fourth of said four
grooves being provided at a distance from side boundaries of said
first surface in accordance with a second equation.
21. The semiconductor package of claim 17 wherein said pattern of
grooves comprises a multiplicity of grooves, a first half of said
multiplicity of grooves intersecting a second half of said
multiplicity of grooves, said first half of said multiplicity of
grooves being provided at distances from side boundaries of said
first surface in accordance with a first equation, said second half
of said multiplicity of grooves being provided at a distance from
side boundaries of said first surface in accordance with a second
equation.
Description
BACKGROUND OF THE INVENTION
[0001] (1) Field of the Invention
[0002] The invention relates to the fabrication of integrated
circuit devices, and more particularly, to a method and package
that provides reduced surface and internal stress in the packaging
medium.
[0003] (2) Description of the Prior Art
[0004] Semiconductor devices are typically produced by
simultaneously creating a large number of identical integrated
circuit (IC) devices (also referred to as semiconductor die or
simply as die) in or on the surface of a semiconductor substrate in
arrays of rectangular elements. Electrical access is provided to
the individual die by providing contact pads, also referred to as
Input/Output (I/O) pads, on the surface of the die. The I/O pads
are further connected to elements within the die by means of
interconnect metal that is used as signal lines, ground planes and
power lines.
[0005] The process of packaging semiconductor devices typically
starts with a leadframe of a substrate that is ceramic or plastic
based, such as Dual-In-Line packages (DIP), Pin Grid Arrays (PGA),
Plastic Leaded Chip Carriers (PLCC), Quad Flat Packages (QFP) and
Ball Grid Array (BGA) packages.
[0006] The Quad Flat Package (QFP) has been created to achieve high
pin count integrated packages with various pin configurations. The
pin Input/Output (I/O) connections for these packages are typically
established by closely spaced leads distributed along the four
edges of the flat package. This limits the I/O count of the
packages and therefore the usefulness of the QFP. The Ball Grid
Array (BGA) package has been created whereby the I/O connects for
the package are distributed around the periphery of the package and
over the complete bottom of the package. The BGA package can
therefore support more I/O points and provides a more desirable
package for high circuit density with high I/O count. The BGA
contact points are solder balls that in addition facilitate the
process of flow soldering of the package onto a printed circuit
board. The solder balls can be mounted in an array configuration
and can use 40, 50 and 60 mil spacings in a regular or staggered
pattern.
[0007] Another packaging concept is realized with the use of
so-called flip chips. The flip chip is a semiconductor device that
has conductive layers formed on its top surface. The top surface of
the flip chip is further provided with so-called solder bumps. At
the time of assembly of the flip chip, the chip is turned over
(flipped over) so that the solder bumps are now facing downwards
and toward the circuit board, typically a printed circuit board, on
which the flip chip is to be mounted.
[0008] The invention addresses the aspect of a semiconductor device
package that contains a heat spreader, the design of the heat
spreader of the invention is such that stress is significantly
reduced in surfaces of the package.
[0009] U.S. Pat. No. 5,905,633 (Shirn et al.) shows a heat spreader
with grooves 68.
[0010] U.S. Pat. No. 6,158,502 (Thomas) shows a heat spreader with
grooves, this reference differs from the invention.
[0011] U.S. Pat. No. 6,117,352 (Weaver et al. shows an etched heat
spreader.
[0012] U.S. Pat. No. 6,011,304 (Mertol), U.S. Pat. No. 5,949,137
(Dornadia et al.), U.S. Pat. No. 5,484,959 (Burns) show related
heat spreaders.
SUMMARY OF THE INVENTION
[0013] A principle objective of the invention is to provide a
semiconductor device package comprising a heat spreader, whereby
the design of the heat spreader is such that stress is
significantly reduced in surfaces of the package.
[0014] In accordance with the objectives of the invention a new
design is provided for the heat spreader of a semiconductor
package. Grooves are provided in a surface of the heat spreader,
subdividing the heat spreader for purposes of stress distribution
into multiple sections. This division of the heat spreader results
in a reduction of the mechanical and thermal stress that is
introduced by the heat spreader into the device package. Mechanical
and thermal stress, using conventional heat spreader designs, has a
negative, stress induced effect on the semiconductor die, on the
contact points (bump joints) of the semiconductor die and on the
solder ball connections of the package.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIG. 1 shows a cross section of a first prior art
semiconductor package.
[0016] FIG. 2 shows a cross section of a second prior art
semiconductor package.
[0017] FIGS. 3a through 3c show simplified cross sections and the
heat spreader of a third prior art semiconductor package, this
package best compares with the package of the invention, as
follows:
[0018] FIG. 3a shows a cross section where the semiconductor die is
mounted on the surface of a PCB,
[0019] FIG. 3b shows a cross section after the stiffener and a heat
spreader have been attached,
[0020] FIG. 3c shows a bottom view of the heat spreader.
[0021] FIGS. 4a and 4b show cross sections of the package of the
invention, FIGS. 4c and 4d show top views of the heat spreader of
the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0022] FIG. 1 shows across section of a prior art package. The
elements that are highlighted in FIG. 1 are the following:
[0023] 10, a Printed Circuit Board (PCB) on the surface of which a
semiconductor die is mounted
[0024] 12, a semiconductor die
[0025] 14, a layer of metal traces (interconnect lines) that is
used for interconnect distribution
[0026] 16, a solder resist layer that protects the surface of the
layer 14 of interconnect traces
[0027] 18, a dielectric interconnect substrate containing
interconnect traces; an opening has been created in the
interconnect substrate, the die 12 is placed inside this opening;
this interconnect substrate can take forms others than the form
that is shown in cross section in FIG. 1 such as single strips and
the like; the number of layers of interconnect traces contained
within the interconnect substrate is also not determinate
[0028] 19, bond wires that connect contact points (not shown) on
the top surface of die 12 with contact points (not shown) that have
been provided in the top surface of the interconnect substrate
18
[0029] 20, an encapsulant the encapsulates die 12, the
interconnects 19 and the interconnect substrate 18
[0030] 21, an (symbolic and representative) interconnect between
contact points (not shown) on the top surface of interconnect
substrate 18 and contact points (not shown) on the bottom surface
of the interconnect substrate 18
[0031] 22, a layer of interconnect traces that is provided over the
bottom surface of PCB 10
[0032] 24, a solder mask overlying the interconnect traces 22,
openings have been created in the solder mask 24 which expose
points of electrical contact (not shown) of the interconnect traces
22
[0033] 26, contact balls that have been inserted into the solder
mask 22 and that make electrical contact with points of contact
(not shown) of the interconnect traces 22.
[0034] FIG. 2 shows a cross section of a second prior art
semiconductor package, this cross section is based on U.S. Pat. No.
5,905,633 (Shim et al.) and is introduced in order to (at a later
time) highlight differences between the instant invention and the
Shim et al. invention.
[0035] While element 10 has been described above as being a Printed
Circuit Board, it must be realized that this element is not limited
to being a Printed circuit Board but can be a flex circuit or a
metallized or glass substrate or semiconductor device mounting
support.
[0036] Highlighted in cross section shown in FIG. 2 are the
following elements of the semiconductor package:
[0037] 10, a Printed Circuit Board (PCB) on the surface of which a
semiconductor die is mounted
[0038] 12, a semiconductor die
[0039] 14, a layer of metal traces (interconnect lines) that is
used for interconnect distribution
[0040] 16, a solder resist layer that protects the surface of the
layer 14 of interconnect traces
[0041] 19, bond wires that connect contact points on the top
surface of die 12 with contact points that have been provided in
the top surface of the interconnect traces 14
[0042] 20, an encapsulant the encapsulates die 12
[0043] 22, a layer of interconnect traces the is provided over the
bottom surface of PCB 10
[0044] 24, a solder mask overlying the interconnect traces 22,
openings have been created in the solder mask 24 which expose
points of electrical contact (not shown) of the interconnect traces
22
[0045] 26, contact balls that have been inserted into the solder
mask 22 and that make electrical contact with points of contact
(not shown) of the interconnect traces 22
[0046] 28, a bonding agent that has been deposited over the surface
of layer 16 of solder resist; this bonding mask forms the
interconnection between the solder resist 16 and the overlying
carrier/heat spreader 30
[0047] 30, the heat spreader of the package; this elements is also
referred to as a PCB carrier which refers to the method that is
used to assembly (multiple) packages of which one is shown in cross
section in FIG. 2
[0048] 32, a protective layer, typically comprising, according to
Shim et al., silver, nickel or paladium; this layer is to prevent
oxidation and corrosion of the metal carrier 30
[0049] 34, grooves that are formed in a surface of the metal
carrier 30; these grooves have, according to Shim et al.,
preferably a V-shaped cross section.
[0050] It must be noted from the cross section that is shown in
FIG. 2 that the heat spreader (heat sink) 30 is directly attached
to the package PCB 10, with intervening layers 14, 16 and 28.
Furthermore, the heat sink 30 surrounds the wire bond die 12 and is
partially covered by molding compound 20. The functions of grooves
34, FIG. 2, is to provide improved adhesion between the mold
compound 20 and the underlying layer 28 of bonding agent by means
of improved mechanical interlocking and by extending the moisture
penetration path, enhancing the package reliability.
[0051] Referring now specifically to the FIGS. 3a through 3c, FIG.
3a shows the following prior art elements:
[0052] 10, a substrate such as a PCB on the surface of which a
semiconductor die is mounted
[0053] 12, a semiconductor die
[0054] 11, solder bumps that have been provided on a surface of die
12 for electrical interconnection of die 12
[0055] 13, underfill that has been inserted underneath the die 12
and that surrounds the solder bumps 11, and
[0056] 26, contact balls.
[0057] FIG. 3b shows in cross section, in addition to the elements
that have already been highlighted under the cross section of FIG.
3a, the following prior art elements:
[0058] 15, layers of adhesive that have been deposited over the
surface of substrate 10, over the surface of stiffeners 23 and over
the surface of semiconductor die 12
[0059] 23, stiffeners of the package
[0060] 25, the heat spreader of the package.
[0061] FIG. 3c shows a bottom view of the heat spreader of the
package. This bottom surface of the heat spreader that is shown in
top view in FIG. 3c is the surface that interfaces with the
adhesive layer 15 that has been deposited over the surface of
substrate 10, over the surface of stiffeners 25 and over the
surface of semiconductor die 12, this surface therefore faces
semiconductor die 12.
[0062] For the cross sections that are shown in FIGS. 3a through
3c, that is a typical flip-chip BGA (FC-BGA) package, the IC chip
12 is electrically connected with package substrate 10 by solder
bumps 11. The underfill 13 (FIG. 3a) is applied, which fills the
gap between chip 12 and the substrate 10 and is cured at
temperature above room temperature to increase the bump-joint
reliability.
[0063] In order to meet demands of thermal performance of a high
performance IC package, the stiffener 23 (FIG. 3b) and heat
spreader 25 (FIG. 3b) are attached as shown in cross section in
FIG. 3b. The stiffener 23 is a plain metal plate with a proper
opening in the center to allow chip placement and to provide
support for the heat spreader attachment. The heat spreader 25 is a
plain metal plate, FIG. 3c, and provides heat dissipation for the
die 12. The disadvantages of the implementation of the heat
spreader as shown in FIGS. 3a and 3b is that thermal and mechanical
stresses are increased in the die 12, in solder bump 11 points of
contact and in the points of contact of contact balls 26. These
stresses have a negative effect on the package integrity and
degrade bump-joint reliability. The invention addresses these
problems.
[0064] Referring now specifically to FIGS. 4a through 4d, FIG. 4a
shows in cross section the package of the invention with heat
spreader 40 in which grooves 42 have been provided. The grooves
divide the heat spreader 40 into a number of sections, determined
by the number of grooves that are provided in a surface of heat
spreader 40. For the example of heat spreader 40 that is shown in
top view in FIG. 4c, two grooves 42 are provided dividing the heat
spreader into four sections. For the example of heat spreader 44
that is show in top view in FIG. 4d, four grooves 46 are provided
dividing the heat spreader into nine sections. This diving of the
heat spreader results in the separate sections of the heat spreader
functioning in almost independent manner whereby the typical
stresses that occur in the surface of the heat spreader are now
diverted to the (regions of) the grooves. In concentrating thermal
and mechanical stresses from across the surface of the heat
spreader to the regions of the grooves of the heat spreader, these
stresses are greatly reduced in the surface of the semiconductor
die 12, the solder bumps 11 and the contact balls 26. This
placement of the stress in the regions of the grooves results in
enhanced reliability performance of the semiconductor die 12 and
the underlying substrate 10 on which the die is mounted. In
addition, thermal and mechanical stress will be reduced on points
of electrical contact that are used to interconnect die 12 such as
the solder bumps 11 and the contact balls 26. Since the number of
grooves that is provided in the surface of the heat spreader is
limited, no significant amount of material of the heat sink is
removed which results in little or no negative impact on the
thermal performance of the package.
[0065] Grooves 42 and 46 can be created using methods of etching,
machining or punching of the surface of the heat spreader.
[0066] To summarize the heat shield of the invention:
[0067] the heat spreader of the semiconductor device package is
provided with grooves in the surface that faces the semiconductor
die to which the heat spreader is attached
[0068] the location of the grooves that are provided in a surface
of the heat spreader is selected such that an optimum level of
stress concentration is provided in the regions of the grooves,
thus providing stress relieve across the surface of the heat
spreader
[0069] the heat spreader of the invention provides a method for
concentrating thermal and mechanical stress into well defined
regions of the heat spreader; thermal and mechanical stress in
prior art heat spreaders is typically present uniformly distributed
across the largest surface of a heat spreader and as such exerts
stress across the largest surface of the die to which the heat
spreader is attached, and
[0070] the heat spreader of the invention can be provided with one
or more grooves, preferably two or four perpendicularly
intersecting grooves that divide the surface of the heat spreader
in which the grooves have been provided in equal segments.
[0071] Although the invention has been described and illustrated
with reference to specific illustrative embodiments thereof, it is
not intended that the invention be limited to those illustrative
embodiments. Those skilled in the art will recognize that
variations and modifications can be made without departing from the
spirit of the invention. It is therefore intended to include within
the invention all such variations and modifications which fall
within the scope of the appended claims and equivalents
thereof.
* * * * *