U.S. patent application number 10/283128 was filed with the patent office on 2003-09-18 for semiconductor device with sti and its manufacture.
This patent application is currently assigned to FUJITSU LIMITED. Invention is credited to Iriyama, Yasunori, Ohta, Hiroyuki.
Application Number | 20030173641 10/283128 |
Document ID | / |
Family ID | 28035335 |
Filed Date | 2003-09-18 |
United States Patent
Application |
20030173641 |
Kind Code |
A1 |
Ohta, Hiroyuki ; et
al. |
September 18, 2003 |
Semiconductor device with STI and its manufacture
Abstract
A semiconductor device includes: a silicon substrate with
semiconductor elements; an isolation trench formed in the silicon
substrate for isolating active regions in the silicon substrate,
the isolation trench having a trapezoidal cross sectional shape
having a width gradually narrowing with a depth from the surface of
the silicon substrate; a first liner insulating film formed on the
surface of the trench and made of a silicon oxide film or a silicon
oxynitride film having a thickness of 1 to 5 nm; a second liner
insulating film formed on the first liner insulating film and made
of a silicon nitride film having a thickness of 2 to 8 nm; and an
isolation region burying the trench defined by the second liner
insulating film.
Inventors: |
Ohta, Hiroyuki; (Kawasaki,
JP) ; Iriyama, Yasunori; (Kawasaki, JP) |
Correspondence
Address: |
ARMSTRONG,WESTERMAN & HATTORI, LLP
1725 K STREET, NW
SUITE 1000
WASHINGTON
DC
20006
US
|
Assignee: |
FUJITSU LIMITED
Kawasaki
JP
|
Family ID: |
28035335 |
Appl. No.: |
10/283128 |
Filed: |
October 30, 2002 |
Current U.S.
Class: |
257/510 ;
257/E21.546; 257/E21.628 |
Current CPC
Class: |
H01L 21/76224 20130101;
H01L 21/823481 20130101 |
Class at
Publication: |
257/510 |
International
Class: |
H01L 029/00 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 18, 2002 |
JP |
2002-074871 |
Claims
What we claim are:
1. A semiconductor device comprising: a silicon substrate with
semiconductor elements; an isolation trench formed in said silicon
substrate for isolating active regions in said silicon substrate,
said isolation trench having a trapezoidal cross sectional shape
having a width gradually narrowing with a depth from a surface of
said silicon substrate; a first liner insulating film formed on a
surface of said trench and made of a silicon oxide film or a
silicon oxynitride film having a thickness of 1 to 5 nm; a second
liner insulating film formed on said first liner insulating film
and made of a silicon nitride film having a thickness of 2 to 8 nm;
and an isolation region burying said trench defined by said second
liner insulating film.
2. A semiconductor device according to claim 1, wherein an upper
end of said second liner insulating film is retracted by less than
about 10 nm from the surface of said silicon substrate.
3. A semiconductor device according to claim 1, wherein said first
and second liner insulating films extend from side walls of said
trench to an upper surface of the silicon substrate.
4. A semiconductor device according to claim 3, wherein said
isolation region includes a portion extending on said second liner
insulating layer above the upper surface of said silicon
substrate.
5. A semiconductor device according to claim 4, wherein said second
liner insulating film includes a portion extending on side walls of
said extending portion of said isolation region.
6. A semiconductor device according to claim 1, wherein said second
liner insulating film has a tensile stress of 1 GPa or larger.
7. A semiconductor device comprising: a silicon substrate with
semiconductor elements; an isolation trench formed in said silicon
substrate for isolating active regions in said silicon substrate,
said isolation trench having generally a trapezoidal cross
sectional shape having a width gradually narrowing with a depth
from a surface of said silicon substrate and having a gradually
broadening upper portion, said isolation trench defining the active
regions with rounded shoulders; a liner insulating film formed on a
surface of said trench and made of a silicon nitride film having a
thickness of 2 to 8 nm; and an isolation region burying said trench
defined by said liner insulating film.
8. A semiconductor device according to claim 7, wherein a cross
sectional shape of the shoulder of the active region is
approximately a segment of a circle.
9. A semiconductor device according to claim 7, wherein said liner
insulating film applies a tensile stress of 1 GPa or larger to the
active region.
10. A semiconductor device according claim 7, further comprising an
underlying liner layer of silicon oxide between the surface of said
trench and said line insulating film.
11. A method of manufacturing a semiconductor device, comprising
steps of: (a) forming a polishing stopper layer on a surface of a
silicon substrate, said stopper layer including a lower silicon
oxide film and an upper silicon nitride film; (b) etching said
stopper layer and the silicon substrate by using a mask to form a
trench; (c) forming a first liner insulating film on a surface of
the silicon substrate exposed in said trench, said first liner
insulating film being a silicon oxide film or a silicon oxynitride
film having a thickness of 1 to 5 nm; (d) forming a second liner
insulating film on said first liner insulating film, said second
liner insulating film being made of a silicon nitride film having a
thickness of 2 to 8 nm; (e) depositing an isolation layer on said
silicon substrate, said isolation layer burying said trench defined
by said second liner insulating film; (f) polishing and removing an
unnecessary portion of said isolation layer by using said stopper
layer as a polishing stopper; and (g) etching said stopper
layer.
12. A method according to claim 11, further comprising between said
steps (b) and (c) a step of: (h) side-etching the silicon oxide
film of said stopper layer to form retracted portions of the
silicon oxide film.
13. A method according to claim 12, wherein thicknesses of the
silicon oxide film of said stopper layer and said first and second
liner insulating films are set to such values that said retracted
portions are not buried by the first and second liner insulating
films.
14. A method according to claim 11, further comprising between said
steps (b) and (c) a step of: (i) etching the silicon nitride film
of said stopper layer to form retracted portions of the silicon
nitride film and partially expose partial upper surfaces of the
underlying silicon oxide film.
15. A method according to claim 11, wherein said stopper layer
includes, from lower position, a silicon oxide film, an amorphous
silicon film and a silicon nitride film and the method further
comprises between said steps (b) and (c) a step of: (j)
side-etching the amorphous silicon film to form retracted portions
of the amorphous silicon film.
16. A method according to claim 11, wherein said step (d) forms a
silicon nitride film having a tensile stress of 1 GPa or
larger.
17. A method according to claim 11, wherein said step (g) includes
a step of etching the silicon nitride film of said stopper layer by
hot phosphoric acid.
18. A method according to claim 11, wherein said step (g) includes
a step of etching the silicon oxide film of said stopper layer by
dilute hydrofluoric acid or buffered hydrofluoric acid.
19. A method of manufacturing a semiconductor device, comprising
steps of: (a) forming a polishing stopper layer on a surface of a
silicon substrate, said stopper layer including a lower silicon
oxide film and an upper silicon nitride film; (b) etching said
stopper layer and the silicon substrate by using a mask to form a
trench in an isolation region defining active regions; (c)
side-etching the silicon oxide film of said stopper layer to
retract side walls of the silicon oxide film; (d) etching silicon
to round a shoulder of the active region exposed by the retracted
side wall; (e) forming a liner insulating film on the surface of
the silicon substrate, said liner insulating film being made of a
silicon nitride film having a thickness of 2 to 8 nm; (f)
depositing an isolation layer on said silicon substrate, said
isolation layer burying said trench defined by said liner
insulating film; (g) polishing and removing an unnecessary portion
of said isolation layer by using said stopper layer as a polishing
stopper; and (h) etching said stopper layer.
20. A method according to claim 19, wherein said step (e) forms a
silicon nitride film having a tensile stress of 1 GPa or
larger.
21. A method according to claim 19, wherein said step (h) includes
a step of etching the silicon nitride film by hot phosphoric acid.
Description
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is based on Japanese Patent Application No.
2002-074871, filed on Mar. 18, 2002, the entire contents of which
are incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] A) Field of the Invention
[0003] The present invention relates to a semiconductor device and
its manufacture method, and more particularly to a semiconductor
device having shallow trench isolation (STI) and its manufacture
method.
[0004] B) Description of the Related Art
[0005] Local oxidation of silicon (LOCOS) is known as one method
for the element isolation of a semiconductor device.
[0006] According to LOCOS technique, a silicon oxide film is formed
on a silicon substrate as a buffer layer, thereafter a silicon
nitride film as an oxidation prevention film is formed, the silicon
nitride film is patterned and then the surface of the silicon
substrate is thermally oxidized.
[0007] While the silicon substrate is thermally oxidized, oxidizing
species such as oxygen and moisture invade the buffer silicon oxide
film. As a result, the silicon substrate surface under the silicon
nitride film is oxidized and silicon oxide regions having a shape
called a bird's beak are formed. These bird's beak regions cannot
be used substantially as an element forming region (active region)
so that the area of the active region is reduced.
[0008] If the surface of a silicon substrate is thermally oxidized
by using a silicon nitride film pattern having openings of various
sizes, the thickness of a silicon oxide film formed on the silicon
substrate surface in an area corresponding to an opening of a
smaller size is thinner than that of a silicon oxide film formed in
an area corresponding to an opening of a lager size. This
phenomenon is called thinning.
[0009] The area not used as the active region in the whole area of
a semiconductor substrate increases because of bird's beaks and
thinning which occur more often as semiconductor devices are made
finer. Namely, since a ratio of the active region to the whole
substrate area is substantially lowered, high integration of
semiconductor devices is hindered.
[0010] Trench isolation (TI) technique is know as the technique of
forming active regions by which a trench is formed in the surface
layer of a semiconductor substrate and insulating material or
polysilicon is filled in the trench. This method has been used
bipolar transistor LSIs which require a deep isolation region.
[0011] Application of trench isolation technique to MOS transistor
LSIs is prevailing because of no bird's beak and thinning.
Isolation for a MOS transistor LSI does not require as deep
isolation as that of a bipolar transistor LSI and can be realized
by a relatively shallow trench of about 0.1 to 1.0 .mu.m. This is
called a shallow trench isolation (STI) structure.
[0012] With reference to FIGS. 9A to 9H, an STI process will be
described.
[0013] As shown in FIG. 9A, on the surface of a silicon substrate
1, a silicon oxide film 2 having a thickness of, e.g., 10 nm is
formed by thermal oxidation. On this silicon oxide film 2, a
silicon nitride film 3 having a thickness of e.g., 100 to 150 nm is
formed by chemical vapor deposition (CVD). The silicon oxide layer
2 functions as a buffer layer for relaxing a stress between the
silicon substrate 1 and silicon nitride film 3. The silicon nitride
film 3 is functions also as a stopper layer during a later
polishing process.
[0014] A resist pattern 4 is formed on the silicon nitride film 3.
An opening defined by the resist pattern 4 defines an area in which
the active region is formed. The region of the silicon substrate
under the resist pattern becomes an active region where device
elements are formed.
[0015] By using the resist pattern 4 as an etching mask, the
silicon nitride film 3 exposed in the opening and the underlying
silicon oxide film 2 and silicon substrate 1 are etched to a depth
of, e.g., about 0.5 .mu.m by reactive ion etching (RIE) to form a
trench 6. Thereafter, the resist pattern 4 is removed.
[0016] As shown in FIG. 9B, the silicon substrate surface exposed
in the trench 6 is thermally oxidized to form a silicon oxide film
7 having a thickness of, e.g., 10 nm.
[0017] As shown in FIG. 9C, burying the trench, a silicon oxide
layer 9 is deposited over the silicon substrate, for example, by
high density plasma (HDP) CVD. In order to make dense the silicon
oxide film 9 as the isolation region, the silicon substrate is
annealed, for example, in a nitrogen atmosphere at 900 to
1100.degree. C.
[0018] As shown in FIG. 9D, by using the silicon nitride film 3 as
a stopper, the silicon oxide layer 9 is etched downward by chemical
mechanical polishing (CMP) or reactive ion etching (RIE). The
silicon oxide film 9 is left only in the trench defined by the
silicon nitride film 3. At this stage, annealing may be performed
for making silicon oxide dense.
[0019] As shown in FIG. 9E, the silicon nitride film 3 is removed
by using hot phosphoric acid. Next, the buffer silicon oxide film 2
on the surface of the silicon substrate 1 is removed by using
dilute hydrofluoric acid. At this time, the silicon oxide film 9
buried in the trench is also etched.
[0020] As shown in FIG. 9F, the surface of the silicon substrate 1
is thermally oxidized to form a sacrificial silicon oxide film 22
on the silicon substrate 1 surface. Impurity ions of a
predetermined conductivity type are implanted into the surface
layer of the silicon substrate 1 via the sacrificial silicon oxide
film, and activated to form wells 10 of the predetermined
conductivity type in the silicon substrate 1.
[0021] The sacrificial silicon oxide film 22 is thereafter removed
by using dilute hydrofluoric acid. While the sacrificial silicon
oxide film is removed, the silicon oxide layer 9 is also etched by
the dilute hydrofluoric acid. By a plurality of hydrofluoric acid
processes, the silicon oxide layer 9 buried in the trench is etched
so that a dug divot or indent is formed along the side of the
active region.
[0022] As shown in FIG. 9G, the surface of the exposed silicon
substrate is thermally oxidized to form a silicon oxide film 11
having a desired thickness which film is used as the gate
insulating film. A polysilicon layer 12 is deposited over the
silicon substrate 1, and patterned to form a gate electrode.
Impurity ions of the conductivity type opposite to that of the
wells 10 are implanted and activated to form source/drain regions.
If necessary, side wall spacers are formed on the side walls of the
gate electrode, and impurity ions are again implanted and activated
to form high impurity concentration source/drain regions.
[0023] FIG. 9H shows the characteristics of drain current relative
to gate voltage of a transistor manufactured as above. The abscissa
represents gate voltage and the ordinate represents drain current.
A curve r shows the characteristic of a normal transistor. A curve
h shows the characteristics of a transistor formed by the
above-described processes. As seen from the curve h, the drain
current starts flowing at a lower gate voltage. This analysis
results in that a parasitic transistor turning on at a low
threshold voltage is added.
[0024] If the shoulder S of the isolation region 9 is etched and
divots or recesses are formed as shown in FIG. 9G, the shoulder of
the active region of the silicon substrate is surrounded by the
gate electrode not only from the upper surface of the active region
but also from the side thereof. As voltage is applied to the gate
electrode having such a shape, the shoulder of the active region
undergoes an electric field concentration so that a transistor
having a lower threshold voltage is formed. This parasitic
transistor forms the hump characteristics indicated by the curve h
shown in FIG. 9H.
[0025] As seen from the curve h, the drain current at a higher gate
voltage is lower than that of the curve r. As heat treatment is
performed in order to make dense the silicon oxide buried in the
trench, the silicon oxide layer 9 contracts so that the active
region surrounded by the silicon oxide film 9 receives a
compression stress.
[0026] As the compression stress is applied, the mobility of
electron/hole in the active region of the silicon substrate 1 may
lower, which reduces the saturated drain current. As the element is
made finer and the area of the active region is made small, the
influence of the compression stress increases.
[0027] In IEDM 1988, pp. 92-95, B. Davari et al. have proposed to
implant ions into the shoulder of an active region in order to
suppress the hump characteristics.
[0028] Another method has been proposed to round the shoulder of an
active region through thermal oxidation in order to suppress the
hump characteristics. Since the shoulder is rounded and the
electric field concentration is relaxed, the influence of a
parasitic transistor can be mitigated.
[0029] In IEDM 1992, pp. 57-60, Pierre C. Fazan et al. have
proposed to form insulating side wall spacers on the side walls of
an isolation silicon oxide film protruding from an upper surface of
a silicon substrate to thereby bury divots.
[0030] Although STI is suitable for the microfine structure of
semiconductor devices, there occur problems specific to STI. New
techniques capable of solving the problems specific to STI have
been desired to date.
SUMMARY OF THE INVENTION
[0031] It is an object of this invention to provide a semiconductor
device with STI capable of presenting good transistor
characteristics. It is another object of the invention to provide a
method of manufacturing a semiconductor device having good
transistor characteristics.
[0032] According to one aspect of the present invention, there is
provided a semiconductor device comprising: a silicon substrate
with semiconductor elements; an isolation trench formed in the
silicon substrate for separating active regions in the silicon
substrate, the isolation trench having a trapezoidal cross
sectional shape having a width gradually narrowing with a depth
from a surface of the silicon substrate; a first liner insulating
film formed on a surface of the trench and made of a silicon oxide
film or a silicon oxynitride film having a thickness of 1 to 5 nm;
a second liner insulating film formed on the first liner insulating
film and made of a silicon nitride film having a thickness of 2 to
8 nm; and an isolation region burying the trench defined by the
second liner insulating film.
[0033] According to another aspect of the present invention, there
is provided a method of manufacturing a semiconductor device,
comprising steps of: (a) forming a polishing stopper layer on a
surface of a silicon substrate, the stopper layer including a
silicon oxide film and a silicon nitride film; (b) etching the
stopper layer and the silicon substrate by using a mask to form a
trench; (c) forming a first liner insulating film on a surface of
the silicon substrate exposed in the trench, the first liner
insulating film being a silicon oxide film or a silicon oxynitride
film having a thickness of 1 to 5 nm; (d) forming a second liner
insulating film on the first liner insulating film, the second
liner insulating film being made of a silicon nitride film having a
thickness of 2 to 8 nm; (e)-depositing an isolation layer on the
silicon substrate, the isolation layer burying the trench defined
by the second liner insulating film; (f) polishing and removing an
unnecessary portion of the isolation layer by using the stopper
layer as a polishing stopper; and (g) etching the stopper
layer.
[0034] As above, it is possible to provide a transistor device with
STI and relaxed electric field concentration on the shoulders of an
active region, and its manufacture method.
[0035] Since a silicon nitride film is left at least on the side
walls of a trench, a tensile stress is applied to the channel
region of the active region so that a reduction in the mobility can
be relaxed.
[0036] The formation of a hump and the reverse narrow channel
effects can be suppressed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0037] FIGS. 1A to 1H are cross sectional views illustrating a
method of manufacturing a semiconductor device according to an
embodiment of the invention.
[0038] FIGS. 2A and 2B are a plan view and a cross sectional view
showing a semiconductor device manufactured by the embodiment
method illustrated in FIGS. 1A to 1H.
[0039] FIGS. 3A and 3B are graphs showing the characteristics of a
semiconductor device manufactured by the embodiment method
illustrated in FIGS. 1A to 1H, as compared to the characteristics
of a semiconductor device of prior art.
[0040] FIGS. 4A and 4B are a graph showing the effects of a silicon
nitride film left on the side walls of a trench and a graph showing
the dependency of a saturated drain current upon a source/drain
width.
[0041] FIGS. 5A to 5D are cross sectional views illustrating a
method of manufacturing a semiconductor device according to another
embodiment of the invention.
[0042] FIGS. 6A to 6D are cross sectional views illustrating a
method of manufacturing a semiconductor device according to a
further embodiment of the invention.
[0043] FIGS. 7A to 7H are cross sectional views illustrating a
method of manufacturing a semiconductor device according to still
another embodiment of the invention.
[0044] FIGS. 8A to 8K are cross sectional views illustrating a
method of manufacturing a semiconductor device according to still
another embodiment of the invention.
[0045] FIGS. 9A to 9H are cross sectional views illustrating a
method of manufacturing a semiconductor device according to prior
art and a graph showing the characteristics of a transistor
manufactured by this method.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0046] Embodiments of the invention will be described with
reference to the accompanying drawings.
[0047] FIGS. 1A to 1H are schematic cross sectional views
illustrating main processes of a method of manufacturing a
semiconductor device according to an embodiment of the
invention.
[0048] As shown in FIG. 1A, the surface of a silicon substrate 1 is
thermally oxidized to form a silicon oxide film 2 having a
thickness of 9 to 21 nm, e.g., 10 nm. On the silicon oxide film 2,
a silicon nitride film 3 having a thickness of 100 to 150 nm is
formed by low pressure (LP) chemical vapor deposition (CVD). For
example, LPCVD is performed at a temperature of 700.degree. C. by
using SiCl.sub.2H.sub.2 and NH.sub.3 as source gas.
[0049] A resist film is coated on the silicon nitride film 3,
exposed and developed to form a resist pattern 4. The resist
pattern 4 has an opening or openings for defining an isolation
region or regions and active regions (element regions) each
surrounded by the isolation region. The width of an opening 5a is,
for example, 0.2 to 1 .mu.m.
[0050] By using the resist pattern 4 as an etching mask, the
silicon nitride film 3, silicon oxide film 2 and silicon substrate
1 are etched. The silicon substrate 1 is etched by a depth of 0.5
.mu.m to form a trench 6. For example, the silicon nitride film and
silicon oxide film are etched by using mixture gas of
CF.sub.4+CHF.sub.3+Ar as etchant, and the silicon substrate 1 is
etched by using mixture gas of HBr+O.sub.2 or Cl.sub.2+O.sub.2 as
etchant.
[0051] With these etching conditions, the side walls of the trench
6 have slanted surfaces. With these slanted surfaces, electric
field concentration upon the shoulder of the active region can be
relaxed. The resist pattern 4 is thereafter removed.
[0052] As shown in FIG. 1B, the silicon substrate surface exposed
in the trench 6 is thermally oxidized to form a silicon oxide film
7 having a thickness of 1 to 5 nm. The whole silicon surface
exposed in the trench 6 is covered with the silicon oxide film
7.
[0053] As shown in FIG. 1C, a silicon nitride film 8 is formed by
LPCVD, covering the surfaces of the silicon oxide film 7 and
silicon nitride film 3. The thickness of the silicon nitride film 8
is 2 to 8 nm. This thickness of 2 to 8 nm of the silicon nitride
film 8 makes it difficult for hot phosphoric acid to be used for
etching silicon nitride to penetrate into this thin film 8.
[0054] LPCVD is performed at a temperature of about 650.degree. C.
by using mixture gas of SiCl.sub.2H.sub.2+NH.sub.3 as source gas.
The silicon nitride film formed by such thermal CVD has a tensile
stress of 1 GPa or larger. The direction of this stress is opposite
to that of the stress in a buried silicon layer after heat
treatment for making it dense to be described later. The thickness
of 1 to 5 nm of the silicon oxide film 7 makes it difficult for
dilute hydrofluoric acid to be used for etching silicon oxide to
penetrate into this thin film 7.
[0055] As shown in FIG. 1D, a silicon oxide layer 9 is deposited
over the substrate with the silicon nitride film 8, for example, by
high density plasma (HDP) CVD, the silicon oxide layer 9 burying
the trench. If the trench has a depth of 0.5 .mu.m, the thickness
of the silicon layer 9 is set to about 0.6 to 1 .mu.m in the flat
area.
[0056] The silicon oxide layer is formed by using mixture gas of
SiH.sub.4 and oxygen or TEOS and ozone as source gas. After the
silicon oxide layer 9 is grown, annealing at about 1000.degree. C.
is performed to make the silicon oxide layer 9 dense. The film
quality of the silicon oxide layer 9 in the trench after the
annealing is approximately similar to that of the thermally
oxidized film. Although the dense silicon oxide layer has a
compression stress, the directions of this compression stress and
the tensile stress of the silicon nitride film are opposite so that
both the stresses are cancelled out. The mobility can therefore be
prevented from being lowered by the compression stress.
[0057] As shown in FIG. 1E, an unnecessary region of the silicon
oxide layer 9 at a position higher than the silicon nitride films 3
and 8 is removed by performing chemical mechanical polishing (CMP).
CMP is performed by holding the silicon substrate between upper and
lower rotating surface plates which are controlled to have, for
example, a revolution speed of 20 rpm, a pressure of 5 psi
therebetween and a back pressure of 5 psi. As polishing agent,
slurry mainly containing colloidal silica or cerium oxide slurry is
used.
[0058] Under such polishing conditions, an etching rate of the
silicon nitride film 3 is small so that the silicon nitride film 3
functions as a polishing stopper. In the state after the polishing,
the silicon oxide layer 9 is approximately flush with the silicon
nitride film 3, and the silicon oxide layer 9 is left only in the
opening defined by the silicon nitride film 3. In this example,
although the silicon oxide layer 9 at a position higher than the
silicon nitride film 3 is removed by CMP, it may be removed by RIE
using mixture gas of CF.sub.4+CHF.sub.3.
[0059] As shown in FIG. 1F, the silicon nitride film 3 is etched by
hot phosphoric acid. At this time, the silicon nitride film 8 on
the side wall of the silicon nitride film 3 is also etched. As the
silicon nitride film 3 is removed, the upper surface of the silicon
nitride film 8 between the silicon oxide film 7 on the silicon
substrate 1 and the buried silicon oxide layer 9 is exposed.
[0060] Since the thickness of the silicon nitride film 8 is set as
thin as 2 to 8 nm, hot phosphoric acid having a relatively high
viscosity is hard to penetrate into this thin film so that the
silicon nitride film 8 between the silicon oxide film 7 and silicon
oxide layer 9 is hardly etched.
[0061] As the silicon nitride film 3 and the silicon nitride film 8
on the side wall of the silicon nitride film 3 are removed by hot
phosphoric acid, the upper portion of the silicon oxide layer 9
protrudes from the surface of the silicon substrate 1 as shown in
FIG. 1F.
[0062] Thereafter, the silicon oxide film 2 on the surface of the
silicon substrate 1 is removed by dilute hydrofluoric acid. At this
time, the protruded silicon oxide layer 9 is also etched
slightly.
[0063] The upper surface of the silicon oxide film 7 formed on the
trench surface is also exposed. Since the thickness of the silicon
oxide film 7 is set as thin as 1 to 5 nm, dilute hydrofluoric acid
is hard to enter this thin film so that the silicon oxide film 7 is
hardly etched.
[0064] As shown in FIG. 1G, the surface of the silicon substrate 1
is thermally oxidized to grow a sacrificial oxide film 22.
[0065] By using the sacrificial oxide film 22 as a through oxide
film, ions are implanted into the surface layer of the silicon
substrate 1. Implanted impurity ions are activated to form wells 10
having a predetermined conductivity type. For example, n- and
p-type wells are formed independently by ion implantation using
resist masks. After the well 10 is formed, the sacrificial oxide
film is removed by dilute hydrofluoric acid.
[0066] A plurality of hydrofluoric acid etching processes etch the
projected portion of the silicon oxide layer 9 and divots are
formed along the side of the shoulder of the active region.
However, the silicon nitride film 8 and silicon oxide film 7 are
hardly etched and they cover the side of the active region.
[0067] If buffered hydrofluoric acid mixed with NH.sub.4H having a
viscosity higher than dilute hydrofluoric acid is used, it is
possible to suppress etching the silicon oxide film 7 more
reliably.
[0068] As shown in FIG. 1H, the sacrificial oxide film is removed
and the exposed surface of the silicon substrate 1 is thermally
oxidized to form a gate insulating oxide film 11 having a thickness
of, e.g., 2 nm. Prior to forming the gate insulating oxide film 11,
dilute hydrofluoric acid etching is performed to such an extent
that a thermally oxidized film would be etched by 20 nm. A
polysilicon layer 12 is formed over the substrate surface and
patterned to form a gate electrode. Thereafter, impurity ions of a
conductivity type opposite to that of the well 10 are implanted to
form source/drain regions on both sides of the gate electrode. If
necessary, side wall spacers are formed on the side walls of the
gate electrode, and impurity ions are implanted and activated to
form high impurity concentration source/drain regions.
[0069] FIG. 2A is a plan view showing the layout of active regions
AR defined by an isolation region 9 and a gate electrode 12 formed
on the surface of a silicon substrate. FIGS. 1A to 1H are the cross
sectional views taken along line B-B' in FIG. 2A. Each active
region AR is surrounded by the isolation region 9. A MOS inverter
is constituted of two active regions.
[0070] The plan view of FIG. 2A shows the state before side wall
spacers are formed. After the side wall spacers are formed,
impurity ions having a conductivity type opposite to that of the
wells are implanted to form high impurity concentration
source/drain regions.
[0071] FIG. 2B is a cross sectional view taken along a line A-A'
shown in FIG. 2A. As shown in FIG. 2B, the side wall spacers SW are
formed on the side walls of the gate electrode, and the
source/drain regions S/D are formed on both sides of the gate
electrode. A silicide film 13 is formed on the upper surfaces of
the gate electrode 12 and source/drain regions S/D. A silicon oxide
film 7 and a silicon nitride film 8 are made very thin so that
etchant cannot enter these films and upper surfaces thereof are
left scarcely etched.
[0072] Since the upper surface of the silicon nitride film 8 is
positioned not lower than the surface of the silicon substrate, the
tensile stress of the silicon nitride film 8 is applied effectively
to the channel region.
[0073] FIG. 3A shows the characteristics of a n-type MOS transistor
formed by the processes described previously. The characteristics
of the MOS transistor having a gate length of 0.1 .mu.m and a gate
width of 1 .mu.m were measured. A curve p shows the characteristics
of a transistor of conventional techniques, and a curve s shows the
characteristics of a transistor of an embodiment. It was confirmed
that a saturated drain current increased and the mobility to be
otherwise lowered by a compression stress was maintained by the
tensile stress of the nitride film. The saturated drain current was
improved by 5%. The existence of a parasitic MOS transistor was not
confirmed and the absence of a hump was confirmed. The reverse
narrow channel effect was also studied.
[0074] FIG. 3B is a graph showing the measurement results. A curve
p shows the characteristics of a transistor of conventional
techniques, and a curve s shows the characteristics of a transistor
of an embodiment. According to the conventional techniques, as the
gate width is made narrow, the threshold voltage gradually lowers,
which indicates the existence of the reverse short channel effect.
In contrast, it can be seen from the curve s of the embodiment that
even if the gate width is made narrow, the threshold voltage
scarcely lowers and that the reverse narrow channel effect can be
suppressed. This may be ascribed to that there is less contribution
of a parasitic MOS transistor.
[0075] A tensile stress in a channel region relative to an
indent-or depression amount of an upper surface of a liner silicon
nitride film formed on the inner surface of a trench was simulated
by changing the indent position of the upper surface of the silicon
nitride film from the surface of the semiconductor substrate.
[0076] FIG. 4A is a graph showing how the tensile stress in the
channel region of an active region changes with the depression
amount of a side wall silicon nitride film from a silicon substrate
surface. The depression amount is 0 when the surface of the silicon
nitride film is flush with the surface of the semiconductor
substrate, and it increases as the silicon nitride film is
depressed from the semiconductor substrate surface. The tensile
stress in the channel region reduces as the depression amount of
the silicon nitride film increases. If the silicon nitride film is
depressed by about 30 nm or more, it can be considered that the
effects of the silicon nitride film disappear nearly.
[0077] In other words, the tensile stress can be effectively
applied to the channel region in the active region by limiting the
depression amount of the silicon nitride film from the surface of
the semiconductor substrate. The tensile stress can be applied
effectively to the channel region by setting the depression amount
to about 10 nm or smaller.
[0078] A change in the saturated drain current relative to the
width (SD width) of a source/drain region along the source/drain
direction was also measured.
[0079] FIG. 4B is a graph showing a change in the saturated drain
current relative to the SD width. According to conventional
techniques, as the SD width becomes narrow, the saturated drain
current Ids lowers. According to the embodiment, even if the SD
width becomes narrow, the saturated drain current Ids is maintained
almost constant.
[0080] In this embodiment, the liner silicon nitride film is formed
from the bottom surface to side wall of the trench. The liner
silicon nitride film 5 may be formed extending to the upper surface
of the active region.
[0081] FIGS. 5A to 5D are cross sectional views illustrating main
processes of a method of manufacturing a semiconductor device
according to another embodiment of the invention.
[0082] After processes similar to those described with reference to
FIG. 1A are performed, a silicon nitride film 3, a silicon oxide
film 2 and a semiconductor substrate 1 are etched by using a resist
pattern as an etching mask to form a trench 6 in the semiconductor
substrate.
[0083] As shown in FIG. 5A, the silicon oxide film 2 is side-etched
by dilute hydrofluoric acid solution to retract the silicon oxide
film 2 by about 10 nm from the side walls of the silicon nitride
film 3. The resist pattern is removed either before or after this
side etching.
[0084] As shown in FIG. 5B, similar to the above-described
embodiment, the substrate surface exposed in the trench and in the
retracted space of the silicon oxide film 2 is thermally oxidized
to form a silicon oxide film 7 having a thickness of 1 to 5 nm.
Thereafter, similar to the process in FIG. 1C, a silicon nitride
film 8 having a thickness of 2 to 8 nm is formed over the whole
surface of the substrate by CVD.
[0085] The thickness of the silicon oxide film 2 is set to such a
value that the retracted space of the silicon oxide film 2 is not
completely filled with the silicon nitride film 8. For example,
assuming that the thickness of the silicon oxide film 2 is 15 nm, a
twofold of a total thickness of the silicon oxide film 7 and
silicon nitride film 8 is set thinner than 15 nm.
[0086] As shown in FIG. 5B, a silicon oxide layer 9 is deposited,
for example, by HDP-CVD, the trench being buried with the silicon
oxide layer 9. Thereafter, similar to the process in FIG. 1F, an
unnecessary portion of the silicon oxide layer 9 at the position
higher than the silicon nitride films 3 and 8 is removed by CMP.
Annealing is performed in order to make the silicon oxide layer 9
dense.
[0087] As shown in FIG. 5C, the silicon nitride film 3 and the
silicon nitride film 8 in contact with the former film 8 are etched
by hot phosphoric acid. In this case, a portion of the silicon
nitride film 8 between the silicon oxide film 2 and silicon oxide
layer 9 is hardly etched because the thickness of the silicon
nitride film 8 is as thin as 2 to 8 nm. As a result, a lamination
of the silicon oxide film 7 and silicon nitride film 8 is left on
the shoulder of the active region of the silicon substrate 1.
Thereafter, similar to the previously described embodiment, the
silicon oxide film 2 is removed and a sacrificial oxide film is
grown to thereafter perform ion implantation and activation.
[0088] As shown in FIG. 5D, after the sacrificial film is removed
and a gate oxide film 11 is formed, a polysilicon layer 12 is
deposited and patterned to form a gate electrode.
[0089] In this embodiment, the lamination layer of the silicon
oxide film 7 and silicon nitride film 8 is left on the shoulder of
the active region. Therefore, the tensile stress applied to the
channel region becomes large as shown in FIG. 4A. The polysilicon
gate electrode 12 formed on the lamination layer faces the shoulder
of the active region via the insulating lamination layer thicker
than the gate insulating film. Therefore, the electric field
concentration can be relaxed.
[0090] A method of leaving the lamination layer of the silicon
oxide film and silicon nitride film on the shoulder of the active
region is not limited to the above embodiment.
[0091] FIGS. 6A to 6D are cross sectional views illustrating main
processes of a method of manufacturing a semiconductor device
according to a further embodiment of the invention.
[0092] As shown in FIG. 6A, after a trench is etched, the trench
surface in the semiconductor substrate 1 is thermally oxidized to
form a silicon oxide film 7 having a thickness of 1 to 5 nm. Next,
the silicon nitride film 3 is etched, for example, by about 10 nm
by hot phosphoric acid. Since the silicon oxide films 2 and 7 are
not etched, only the silicon nitride film 3 is etched so that the
silicon nitride film 3 is retracted, for example, by about 10 nm
from the side walls of the silicon oxide layer 7. After the side
walls of the silicon nitride film 3 are retracted, a silicon
nitride film 8 having a thickness of 2 to 8 nm is formed.
[0093] As shown in FIG. 6B, a silicon oxide layer 9 is deposited on
the surface of the semiconductor substrate, for example, by
HDP-CVD, the trench being buried with the silicon oxide layer 9.
The shoulder of the active region of the substrate 1 is covered
with portions of the silicon oxide films 2 and 7 and silicon
nitride film 8 on which the silicon oxide layer 9 is deposited.
[0094] CMP is then performed to remove an unnecessary portion of
the silicon oxide layer 9 at the position higher than the surface
of the silicon nitride film 3.
[0095] As shown in FIG. 6C, the silicon nitride film 3 and the
silicon nitride film 8 in contact with the former film 3 are etched
by hot phosphoric acid. In this case, a portion of the silicon
nitride film 8 between the silicon oxide films 2 and 7 and silicon
oxide layer 9 is hardly etched because the hot phosphoric acid does
not penetrate into the portion of the silicon nitride film.
[0096] Thereafter, similar to the previously described embodiment,
the silicon oxide film 2 is removed and a sacrificial oxide film is
grown to thereafter perform ion implantation and activation and
then remove the sacrificial oxide film.
[0097] As shown in FIG. 6D, a gate oxide film 11 is formed on the
exposed surface of the active region. Although the silicon oxide
layer 9 has divots etched along the side of the shoulder of the
active region, the shoulder is maintained covered with the silicon
oxide films 2 and 7 and silicon nitride film 8. A polysilicon layer
is deposited and patterned to form a gate electrode. Similar to the
embodiment shown in FIGS. 5A to 5D, since the shoulder of the
active region is covered with the lamination layer of the silicon
oxide films and silicon nitride film, a large tensile stress is
applied to the channel region so that an electric field
concentration is relaxed when a voltage is applied to the gate
electrode.
[0098] In the embodiments described above, the surface of a trench
is covered with a liner insulating film made of a lamination layer
of a silicon oxide film and a silicon nitride film. The liner
insulating film may be made of a single film.
[0099] FIGS. 7A to 7H are cross sectional views illustrating main
processes of a method of manufacturing a semiconductor device
according to still another embodiment of the invention.
[0100] As shown in FIG. 7A, after a trench is etched, a silicon
oxide film 2 is side-etched to retract the side walls of the
silicon oxide film 2 by about 10 nm from the side walls of a
silicon nitride film 3. This process is similar to the process in
FIG. 5A. The condition of limiting the thickness of the silicon
oxide film 2 is, however, different.
[0101] As shown in FIG. 7B, the shoulder of the active region and
the bottom corners of the trench are rounded, for example, by
chemical dry etching. This dry etching removes the surface layer of
the trench, and the layer damaged by trench etching, if any, is
removed. The shoulder of the active region is rounded to a circular
cross sectional shape having a radius of curvature approximately
equal to the retraction amount of the silicon oxide film 2. The
silicon surface after dry etching is a clean surface with fewer
defects.
[0102] As shown in FIG. 7C, a silicon nitride film 8 having a
thickness of 2 to 8 nm is formed on the surface of the
semiconductor substrate by CVD. If the thickness of the silicon
oxide film 2 is set greater than a twofold of the thickness of the
silicon nitride film 8, it is possible to prevent the retracted
space from being buried with the silicon nitride film 8. For
example, assuming that the thickness of the silicon oxide film 2 is
15 nm, the thickness of the silicon nitride film 8 is set to 5
nm.
[0103] As shown in FIG. 7D, after the silicon nitride film 8 is
formed, a silicon oxide layer 9 is deposited to bury the
trench.
[0104] As shown in FIG. 7E, the silicon oxide layer 9 is polished
by CMP using the silicon nitride film 9 as a polishing stopper.
After the surface of the silicon oxide film 9 is planarized,
annealing is performed, for example, for 30 minutes at 1000.degree.
C. in an N.sub.2 atmosphere in order to make the buried silicon
oxide film dense.
[0105] As shown in FIG. 7F, the silicon nitride film 3 is etched by
hot phosphoric acid. Portions of the silicon nitride film 8 between
the silicon substrate 1 and silicon oxide layer 9 and between the
silicon oxide film 2 and silicon oxide layer 9 are left unetched
because the hot phosphoric acid cannot penetrate into the portions
of the silicon nitride film 8.
[0106] As shown in FIG. 7G, the silicon oxide film 2 is removed, a
sacrificial film is grown, and ion implantation and activation is
performed. After the sacrificial film is removed, a gate oxide film
11 is formed by thermal oxidation. Although the upper portion of
the silicon oxide layer 9 is etched by the dilute hydrofluoric acid
process of removing the silicon oxide film, the silicon nitride
film 8 covering the shoulder of the active region is left
unetched.
[0107] As shown in FIG. 7H, a polysilicon layer 12 is deposited
covering the gate oxide film 11, and patterned to form a gate
electrode. Since the shoulder of the active region is rounded, the
degree of an electric field concentration can be mitigated when a
voltage is applied to the gate electrode.
[0108] In the embodiments described above, a silicon oxide film and
a silicon nitride film are formed on the surface of a silicon
substrate, and the silicon nitride film is used as the CMP stopper.
A lamination layer having a different structure may be formed on a
semiconductor substrate.
[0109] FIGS. 8A to 8K are cross sectional views illustrating main
processes of a method of manufacturing a semiconductor device
according to still another embodiment of the invention.
[0110] As shown in FIG. 8A, a silicon oxide film 2 similar to those
of the above-described embodiments is formed on the surface of a
semiconductor substrate 1. On this silicon oxide film 2, an
amorphous silicon film 2a is formed. On this amorphous silicon film
2a, a silicon nitride film 3 similar to those of the
above-described embodiments is formed. A photoresist layer is
coated on the surface of the silicon nitride film 3, and exposed
and developed to form a resist pattern 4.
[0111] As shown in FIG. 8B, by using the resist pattern 4 as an
etching mask, the silicon nitride film 3, amorphous silicon film 2a
and silicon oxide film 2 are etched and then the silicon substrate
is etched to form a trench 6.
[0112] As shown in FIG. 8C, the amorphous silicon film 2a is
selectively etched. For example, isotropic etching in a liquid
phase is performed by using HF+HNO.sub.3+H.sub.2O or
HF+NH.sub.4OH+H.sub.2O.sub.2+H.sub.2O to retract the side walls of
the amorphous silicon film 2a. During this etching, the silicon
substrate 1 is scarcely etched because of a difference of an
etching selection ratio between the amorphous silicon film and
crystal silicon.
[0113] As shown in FIG. 8D, the exposed silicon surface is
oxidized. A silicon oxide film 7a is formed on the amorphous
silicon film 7 and a silicon oxide film 7 is formed on the silicon
substrate. Instead of oxidizing the silicon surface, it may by
oxynitridized. The thickness of the silicon oxide film or silicon
oxynitride film is set to such a value that etchant for etching
silicon oxide in a later process is hard to penetrate into the
film. The silicon oxynitride film has a smaller etching rate than
the silicon oxide film so that the detraction amount by etching can
be reduced.
[0114] As shown in FIG. 8E, a silicon nitride film 8 is formed on
the whole surface of the substrate to a thickness of, e.g., 5 nm by
CVD. The thickness of the silicon nitride film 8 is set to such as
value that hot phosphoric acid etchant does not penetrate into the
silicon nitride film 8.
[0115] As shown in FIG. 8F, a silicon oxide layer 9 is deposited
burying the trench. As shown, the shoulder of the active region is
covered with a lamination layer of the silicon oxide film 7 and
silicon nitride film 8, and the silicon oxide layer 9 covers the
lamination layer.
[0116] As shown in FIG. 8G, CMP is performed to remove an
unnecessary portion of the silicon oxide layer 9 at the position
higher than the silicon nitride film 3. The state shown in FIG. 8G
shows the silicon nitride film 3 partially removed. CMP is
performed to the extent that the silicon nitride film 3 appears and
is not removed completely.
[0117] As shown in FIG. 8H, the silicon nitride film is removed by
hot phosphoric acid. With this etching, the exposed silicon nitride
film 3 and the silicon nitride film 8 in contact with the former
film are etched. However, since the thickness of the silicon
nitride film 8 is selected to such an extent that the hot
phosphoric acid does not penetrate into the silicon nitride film 8,
the retraction amount of the silicon nitride film 8 from the upper
surface thereof is limited.
[0118] As shown in FIG. 8I, the amorphous silicon film 2a is
removed by NH.sub.3+H.sub.2O+isopropyl alcohol (IPA).
[0119] As shown in FIG. 8J, the silicon oxide films 2 and 7a are
removed. This etching slightly etches the surface of the silicon
oxide layer 9. The nitride film 8, when projected, may be removed
since it is very thin. Thereafter, a sacrificial film is formed and
ion implantation and activation is performed to form wells 10.
After the sacrificial film is removed, a gate oxide film is formed
on the exposed surface of the active region.
[0120] As shown in FIG. 8K, a polysilicon film is formed covering
the gate insulating film 11, and patterned to form a gate electrode
12. The shoulder of the active region is maintained covered with
the silicon oxide film 7 and silicon nitride film 8. Depending upon
the process conditions, a portion of the silicon oxide layer 9 is
left on the silicon nitride film 8. Since the gate electrode 12 is
formed on this structure, an electric field concentration upon the
shoulder of the active region can be relaxed when a voltage is
applied to the gate electrode. A large tensile stress is applied to
the channel region.
[0121] The present invention has been described in connection with
the preferred embodiments. The invention is not limited only to the
above embodiments. It is apparent that various modifications,
improvements, combinations, and the like can be made by those
skilled in the art.
* * * * *