U.S. patent application number 10/370733 was filed with the patent office on 2003-08-21 for semiconductor device and method for fabricating the same.
This patent application is currently assigned to MATSUSHITA ELECTRONICS CORPORATION. Invention is credited to Moriwaki, Masaru, Yamada, Takayuki, Yamamoto, Kazuhiko.
Application Number | 20030155621 10/370733 |
Document ID | / |
Family ID | 18614530 |
Filed Date | 2003-08-21 |
United States Patent
Application |
20030155621 |
Kind Code |
A1 |
Moriwaki, Masaru ; et
al. |
August 21, 2003 |
Semiconductor device and method for fabricating the same
Abstract
After an insulating film serving as a gate insulating film is
formed on a semiconductor substrate, a titanium nitride film is
deposited by chemical vapor deposition on the insulating film.
Then, a tungsten film is deposited by sputtering on the titanium
nitride film. Subsequently, a multilayer film composed of the
tungsten film and the titanium nitride film is patterned to form a
gate electrode composed of the multilayer film.
Inventors: |
Moriwaki, Masaru; (Osaka,
JP) ; Yamada, Takayuki; (Osaka, JP) ;
Yamamoto, Kazuhiko; (Osaka, JP) |
Correspondence
Address: |
NIXON PEABODY, LLP
8180 GREENSBORO DRIVE
SUITE 800
MCLEAN
VA
22102
US
|
Assignee: |
MATSUSHITA ELECTRONICS
CORPORATION
Osaka
JP
|
Family ID: |
18614530 |
Appl. No.: |
10/370733 |
Filed: |
February 24, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10370733 |
Feb 24, 2003 |
|
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|
09759451 |
Jan 16, 2001 |
|
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6548389 |
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Current U.S.
Class: |
257/412 ;
257/306; 257/311; 257/E21.204; 257/E27.016 |
Current CPC
Class: |
H01L 27/0629 20130101;
H01L 21/28088 20130101 |
Class at
Publication: |
257/412 ;
257/306; 257/311 |
International
Class: |
H01L 029/76; H01L
031/062 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 3, 2000 |
JP |
2000-100306 |
Claims
What is claimed is:
1. A semiconductor device comprising: a multilayer gate electrode
comprised of a lower-layer gate electrode composed of a titanium
nitride film and formed on a gate insulating film provided on a
semiconductor substrate, and an upper-layer gate electrode composed
of a tungsten film an formed on the lower-layer gate electrode; and
a capacitor comprised of a lower electrode composed of the titanium
nitride film, a capacitor insulating film formed on the lower
electrode, and an upper electrode composed of the tungsten film and
formed on the capacitor insulating film.
2. The device of claim 1, wherein the lower-layer gate electrode
and the lower electrode are deposited by chemical vapor
deposition.
3. The device of claim 1, wherein the upper-layer gate electrode
and the upper electrode are deposited by sputtering.
4. A semiconductor device comprising: a multilayer gate electrode
comprised of a lower-layer gate electrode composed of a titanium
nitride film and formed on a gate insulating film provided on a
semiconductor substrate, and an upper-layer gate electrode composed
of a tungsten film and formed on the lower-layer gate electrode;
and a resistor composed of the titanium nitride film.
5. The device of claim 4, wherein the lower-layer gate electrode
and the resistor are deposited by chemical vapor deposition.
6. The device of claim 4, wherein the upper-layer gate electrode is
deposited by sputtering.
7. A semiconductor device comprising: a multilayer gate electrode
comprised of a lower-layer gate electrode composed of a titanium
nitride film deposited by chemical vapor deposition on a
semiconductor substrate and of an upper-layer gate electrode
composed of a tungsten film deposited by sputtering on the titanium
nitride film; and a capacitor comprised of a lower electrode
composed of the titanium nitride film, of a capacitor insulating
film formed on the lower electrode, and of an upper electrode
composed of the tungsten film formed on the capacitor insulating
film.
8. A semiconductor device comprising: a multilayer gate electrode
comprised of a lower-layer gate electrode composed of a titanium
nitride film deposited by chemical vapor deposition on a
semiconductor substrate and of an upper-layer gate electrode
composed of a tungsten film deposited by sputtering on the titanium
nitride film; and a resistor composed of the titanium nitride film.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates to a semiconductor device
having a gate electrode composed of a multilayer film comprising a
lower-layer titanium nitride film and an upper-layer tungsten film
and a method for fabricating the same.
[0002] With the recent advancement of technology for providing a
higher-speed semiconductor integrated circuit with a higher
integration density, a MOSFET has been miniaturized
increasingly.
[0003] However, if a gate insulating film for a conventional gate
electrode composed of a polycrystalline silicon film is thinned
more and more with the miniaturization of the MOSFET, the driving
force of the MOSFET lowers markedly due to the depletion of the
gate electrode.
[0004] To circumvent the problem, attention has been focused
recently on a metal gate process which uses, as a gate electrode, a
metal film free from the depletion of the gate electrode. The metal
gate process is effective in reducing a delay in the gate electrode
since a materiel composing the gate electrode of the metal gate has
a low resistance value.
[0005] As one of structures of the gate electrode, there has been
used a multilayer structure comprised of a lower-layer titanium
nitride film (TiN) film having a thickness of about 10 to 20 nm and
an upper-layer tungsten (W) film having a thickness of about 50 to
100 nm.
[0006] As conventional methods for forming a multilayer film
comprising a lower-layer titanium nitride film and an upper-layer
tungsten film, there have been known a first method wherein a
tungsten film is deposited by CVD using WF.sub.6 gas on a titanium
nitride film deposited by sputtering, a second method wherein a
tungsten film is deposited by sputtering on a titanium nitride film
also deposited by sputtering, and a third method wherein a tungsten
film is deposited by CVD using WF.sub.6 gas on a titanium nitride
film deposited by chemical vapor deposition (CVD).
[0007] In accordance with the first or second method wherein the
titanium nitride film is deposited by sputtering, however, an
insulating film formed under the titanium nitride film to serve as
a gate insulating film is physically damaged by sputtering
particles so that the reliability of the gate insulating film is
lowered.
[0008] In accordance with the third method wherein the tungsten
film is deposited by CVD using WF.sub.6 gas on the titanium nitride
film deposited by CVD, the problem that the gate insulating film is
physically damaged by the sputtering particles can be circumvented
but the problem is encountered that the reliability of the gate
insulating film is lowered by fluorine contained in the tungsten
film. According to the report made by H. Yang (IEDM Tech Dig.
(1997) pp. 459-462), the problem is encountered if a tungsten film
is deposited by CVD using WF.sub.6 that a large amount of fluorine
remains in the tungsten film and fluorine contained in the tungsten
film penetrates the titanium nitride film to be diffused into the
gate insulating film in a heat treatment process performed after
the deposition of the tungsten film, which lowers the reliability
of the gate insulating film.
SUMMARY OF THE INVENTION
[0009] In view of the foregoing, it is therefore an object of the
present invention to provide a method for forming a gate electrode
composed of a multilayer film comprising a lower-layer titanium
nitride film and an upper layer tungsten film without lowering the
reliability of a gate insulating film.
[0010] To attain the object, a method for fabricating a
semiconductor device according to the present invention comprises
the steps of: forming a first insulating film serving as a gate
insulating film on a semiconductor substrate; depositing a titanium
nitride film by chemical vapor deposition on the first insulating
film; depositing a tungsten film by sputtering on the titanium
nitride film; and patterning a multilayer film comprising the
tungsten film and the titanium nitride film to forma gate electrode
composed of the multilayer film.
[0011] In accordance with the method for fabricating a
semiconductor device according to the present invention, the
titanium nitride film is deposited by CVD on the first insulating
film as the gate insulating film, so that the first insulating film
is prevented from being physically damaged and the reliability of
the gate insulating film composed of the first insulating film is
improved.
[0012] Since the tungsten film is deposited by sputtering, there
can be prevented the degradation of the gate insulating film
resulting from fluorine contained in such a tungsten film as
deposited by CVD using WF.sub.6 gas.
[0013] Since the tungsten film is deposited by sputtering,
moreover, the degree of roughness of the surface of the tungsten
film is reduced. This reduces the amount of overetching performed
in forming the gate electrode by patterning the multilayer film
comprising the tungsten film and the titanium nitride film and
prevents penetration through the gate insulating film caused by
overetching.
[0014] In accordance with the method for fabricating a
semiconductor device according to the present invention, therefore,
the gate electrode with a low resistance value can be formed
without lowering the reliability of the gate insulating film so
that a high-performance and high-reliability MOSFET is
fabricated.
[0015] In the method for fabricating a semiconductor device
according to the present invention, the step of depositing the
titanium nitride film preferably includes the step of performing a
heat treatment with respect to the titanium nitride film in an
ammonia atmosphere.
[0016] The arrangement lowers the concentration of a residual
impurity which is present in the titanium nitride film and thereby
prevents an increase in gate leakage current and the peeling of the
titanium nitride film off the surface of the gate insulating film
even if a heat treatment is performed at about 1000.degree. C. with
respect to the titanium nitride film in the subsequent step.
[0017] In this case, the step of performing the heat treatment with
respect to the titanium nitride film is preferably performed in a
chamber in which the titanium nitride film has been deposited.
[0018] The arrangement lowers the concentration of the residual
impurity which is present in the titanium nitride film without
increasing process steps.
[0019] In the method for fabricating a semiconductor device
according to the present invention, the step of depositing the
titanium nitride film preferably includes the step of performing a
heat treatment with respect to the titanium nitride film at a
temperature not less than a temperature at which the titanium
nitride film is deposited.
[0020] The arrangement lowers the concentration of a residual
impurity which is present in the titanium nitride film and thereby
prevents an increase in gate leakage current and the peeling of the
titanium nitride film off the surface of the gate insulating film
even if a heat treatment is performed at about 1000.degree. C. with
respect to the titanium nitride film in the subsequent step.
[0021] In this case, the heat treatment is preferably performed in
an ammonia atmosphere.
[0022] The arrangement further lowers the concentration of the
residual impurity which is present in the titanium nitride
film.
[0023] In the method for fabricating a semiconductor device
according to the present invention, the step of depositing the
titanium nitride film is preferably performed at a temperature not
less than 600.degree. C.
[0024] The arrangement lowers the concentration of the residual
impurity which is present in the titanium nitride film and thereby
prevents an increase in gate leakage current and the peeling of the
titanium nitride film off the surface of the gate insulating film
even if a heat treatment is performed at about 1000.degree. C. with
respect to the titanium nitride film in the subsequent step.
[0025] Preferably, the method for fabricating a semiconductor
device according to the present invention further comprises,
between the step of depositing the titanium nitride film and the
step of depositing the tungsten film, the step of: forming a second
insulating film on the titanium nitride film and patterning the
second insulating film to form a capacitor insulating film, wherein
the step of patterning the multilayer film to form the gate
electrode includes the step of: forming an upper electrode of a
capacitor composed of the tungsten film and a lower electrode of
the capacitor composed of the titanium nitride film.
[0026] The arrangement allows formation of the semiconductor device
comprising the capacitor with reduced variations in the
characteristics of the electrode and reduced degradation of RF
properties without increasing the number of process steps.
[0027] Preferably, the method for fabricating a semiconductor
device according to the present invention further comprises,
between the step of depositing the titanium nitride film and the
step of depositing the tungsten film, the step of: forming a second
insulating film on the titanium nitride film and patterning the
second insulating film to form a hard mask composed of the second
insulating film above the isolation region, wherein the step of
patterning the multilayer film to form the gate electrode includes
the step of: patterning the titanium nitride film by using the hard
mask to form a resistor composed of the titanium nitride film.
[0028] The arrangement allows formation of the semiconductor device
comprising the resistor with a high sheet resistance value without
increasing the number of process steps.
[0029] In this case, it is preferred that a thickness of the second
insulating film is approximately equal to or less than a height of
a portion of the isolation region protruding from the semiconductor
substrate.
[0030] In the arrangement, the thickness of the tungsten film
remaining on each of the side surfaces of the hard mask overlying
the titanium nitride film is approximately equal to or less than
the thickness of the tungsten film remaining on the portion of the
titanium nitride film overlying the stepped portion of the
isolation region. Accordingly, the tungsten film remaining on each
of the side surfaces of the hard mask overlying the titanium
nitride film is removed by overetching for removing the tungsten
film remaining on the portion of the titanium nitride film
overlying the stepped portion of the isolation region, so that
variations in the characteristics of the resistor are
prevented.
[0031] A first semiconductor device according to the present
invention comprises: a multilayer gate electrode comprised of a
lower-layer gate electrode composed of a titanium nitride film
deposited by chemical vapor deposition on a semiconductor substrate
and of an upper-layer gate electrode composed of a tungsten film
deposited by sputtering on the titanium nitride film; and a
capacitor comprised of a lower electrode composed of the titanium
nitride film, of a capacitor insulating film formed on the lower
electrode, and of an upper electrode composed of the tungsten film
formed on the capacitor insulating film.
[0032] The first semiconductor device according to the present
invention implements a semiconductor device comprising a reliable
gate electrode and a capacitor with reduced variations in the
characteristics of the electrode and reduced degradation of RF
characteristics.
[0033] A second semiconductor device according to the present
invention comprises: a multilayer gate electrode comprised of a
lower-layer gate electrode composed of a titanium nitride film
deposited by chemical vapor deposition on a semiconductor substrate
and of an upper-layer gate electrode composed of a tungsten film
deposited by sputtering on the titanium nitride film; and a
resistor composed of the titanium nitride film.
[0034] The second semiconductor device according to the present
invention implements a semiconductor device comprising a reliable
gate electrode and a resistor with a high sheet resistance
value.
BRIEF DESCRIPTION OF THE DRAWINGS
[0035] FIGS. 1(a) to (c) are cross-sectional views illustrating the
individual process steps of methods for fabricating semiconductor
devices according to EMBODIMENTS 1 to 4;
[0036] FIG. 2(a) is a cross-sectional view showing a crystal
structure of a tungsten film deposited by CVD on a titanium nitride
film and FIG. 2(b) is a cross-sectional view showing a crystal
structure of a tungsten film deposited by sputtering on a titanium
nitride film;
[0037] FIG. 3 is a cross-sectional view for illustrating a problem
encountered when a heat treatment at about 1000.degree. C. is
performed with respect to a multilayer film consisting of a
lower-layer titanium nitride film and an upper-layer tungsten
film;
[0038] FIG. 4 is a cross-sectional view for illustrating the
effects of the method for fabricating a semiconductor device
according to EMBODIMENT 2;
[0039] FIG. 5 shows the relationship between a depth measured from
a surface of each of the titanium nitride films obtained according
to EMBODIMENTS 1 and 2 and the chlorine concentration in each of
the titanium nitride films;
[0040] FIG. 6 is a cross-sectional view for illustrating the
effects of the method for fabricating a semiconductor device
according to EMBODIMENT 3;
[0041] FIG. 7 shows the relationship between a depth measured from
a surface of each of the titanium nitride films obtained according
to EMBODIMENTS 1 and 4 and the chlorine concentration in each of
the titanium nitride films;
[0042] FIG. 8 shows the relationship between the film deposition
temperature for a titanium nitride film and the chlorine
concentration in the titanium nitride film in EMBODIMENT 4;
[0043] FIG. 9 shows the residual chlorine concentration in each of
the titanium nitride films obtained according to EMBODIMENTS 1 and
4 and a gate leakage current value in a MOS capacitor when a heat
treatment is performed with respect to each of the titanium nitride
films;
[0044] FIG. 10 shows the relationship between the heat treatment
temperature for each of the titanium nitride films obtained
according to EMBODIMENTS 1 and 4 and a gate leakage current value
in the MOS capacitor;
[0045] FIGS. 11(a) to (c) are cross-sectional views illustrating
the individual process steps of a method for fabricating a
semiconductor device according to EMBODIMENT 5;
[0046] FIGS. 12(a) to (c) are cross-sectional views illustrating
the individual process steps of the method for fabricating a
semiconductor device according to EMBODIMENT 5;
[0047] FIGS. 13(a) to (c) are cross-sectional views illustrating
the individual process steps of a method for fabricating a
semiconductor device according to EMBODIMENT 6;
[0048] FIGS. 14(a) to (c) are cross-sectional views illustrating
the individual process steps of the method for fabricating a
semiconductor device according to EMBODIMENT 6;
[0049] FIGS. 15(a) and (b) are cross-sectional views illustrating
the individual process steps of the method for fabricating a
semiconductor device according to EMBODIMENT 6; and
[0050] FIGS. 16(a) to (c) are cross-sectional views illustrating
the characteristics of the individual process steps of the method
for fabricating a semiconductor device according to EMBODIMENT
6.
DETAILED DESCRIPTION OF THE INVENTION
[0051] Embodiment 1
[0052] A method for fabricating a semiconductor device having an
n-type MOSFET as EMBODIMENT 1 of the present invention will be
described with reference to FIGS. 1(a) to (c).
[0053] First, as shown in FIG. 1(a), an isolation region 11 is
formed by a well-known method in a surface portion of a
semiconductor substrate 10 composed of, e.g., a p-type silicon
substrate. Then, a silicon oxynitride film 12 with a thickness of
about 2 nm as a gate insulating film is formed on the semiconductor
substrate 10.
[0054] Next, a titanium nitride film 13 with a thickness of about
10 to 20 nm is deposited on the silicon oxynitride film 12 by CVD
which is performed at a film deposition temperature of about
490.degree. C. by using TiCl.sub.4 and NH.sub.3 as source gas.
Subsequently, a tungsten film 14 with a thickness of about 100 nm
is deposited by sputtering on the titanium nitride film 13.
[0055] Next, as shown in FIG. 1(b), the multilayer film comprising
the tungsten film 14 and the titanium nitride film 13 and the
silicon oxynitride film 12 are patterned to form a gate electrode
15 composed of the multilayer film comprising the tungsten film 14
and the titanium nitride film 13 and forma gate insulating film 16
composed of the silicon oxynitride film 12. Then, an n-type
impurity such as arsenic (As) is ion implanted into the
semiconductor substrate 10 by using the gate electrode 15 as a mask
with an implant energy of about 8 keV, whereby a lightly doped
n-type impurity layer is formed. Subsequently, a silicon nitride
film with a thickness of about 50 nm is formed over the entire
surface of the semiconductor substrate 10 and then subjected to
anisotropical etching, thereby forming sidewalls 17 composed of the
silicon nitride film on the side surfaces of the gate electrode 15.
Thereafter, an n-type impurity such as arsenic is ion implanted
into the semiconductor substrate 10 by using the gate electrode 15
and the sidewalls 17 as a mask with an implant energy of about 40
keV, whereby a heavily doped n-type impurity layer is formed and
impurity diffused layers 18 each composed of the lightly doped
n-type impurity layer and the heavily doped n-type impurity layer
and serving as a source or drain region are formed.
[0056] Next, as shown in FIG. 1(c), an interlayer insulating film
19 composed of, e.g., a silicon oxide film is deposited over the
entire surface of the semiconductor substrate 10. Then, contact
holes are formed in the interlayer insulating film 19.
Subsequently, a conductive film having a barrier layer is deposited
to fill in the contact holes and then patterned to form contacts 20
and wiring layers 21.
[0057] Since EMBODIMENT 1 deposits the titanium nitride film 13 by
CVD on the silicon oxynitride film 12 as the gate insulating film
16, the silicon oxynitride film is prevented from being physically
damaged so that the reliability of the gate insulating film 16
composed of the silicon oxynitride film 12 is improved.
[0058] Since the titanium nitride film 13 is deposited by CVD at a
low temperature of about 490.degree. C., the rate at which the
titanium nitride film 13 is deposited becomes lower. As a
consequence, the titanium nitride film 13 with a smaller thickness
can be deposited with excellent controllability.
[0059] Since the tungsten film 14 is deposited by sputtering, there
can be prevented the degradation of the gate insulating film 16
resulting from fluorine contained in the tungsten film 14 more
positively than in the case where a tungsten film is deposited by
CVD using WF.sub.6 gas.
[0060] Since the gate electrode 15 is composed of the multilayer
film comprising the thin titanium nitride film 13 having a
thickness of about 10 to 20 nm and the thick tungsten film 14
having a low resistance value and a thickness of about 100 nm, the
gate electrode 15 can be reduced in resistance.
[0061] FIGS. 2(a) and (b) show the crystal structures of the
tungsten films 14 each deposited on the titanium nitride film 13,
of which FIG. 2(a) shows the tungsten film 14 deposited by CVD and
FIG. 2(b) shows the tungsten film 14 formed by sputtering. As can
be seen from the comparison between FIGS. 2(a) and (b), the degree
of surface roughness resulting from crystal grains is smaller at
the tungsten film 14 deposited by sputtering than at the tungsten
film 14 deposited by CVD.
[0062] If the tungsten film 14 is deposited by sputtering as in
EMBODIMENT 1, the amount of overetching performed in forming the
gate electrode 15 by pattering the multilayer film comprising the
tungsten film 14 and the titanium nitride film 13 can be reduced,
so that penetration through the gate insulating film 16 caused by
overetching is suppressed.
[0063] Embodiment 2
[0064] A method for fabricating a semiconductor device having an
n-type MOSFET as EMBODIMENT 2 of the present invention will be
described with reference to FIGS. 1(a) to (c).
[0065] First, as shown in FIG. 1(a), an isolation region 11 is
formed in a surface portion of a semiconductor substrate 10
composed of, e.g., a p-type silicon substrate, similarly to
EMBODIMENT 1. Then, a silicon oxynitride film 12 with a thickness
of about 2 nm as a gate insulating film is formed on the
semiconductor substrate 10.
[0066] Next, a gas mixture of TiCl.sub.4 and NH.sub.3 as source gas
is introduced into a chamber which is held at a temperature of
about 490.degree. C. and a titanium nitride film 13 with a
thickness of about 10 to 20 nm is deposited by CVD on the silicon
oxynitride film 12. Thereafter, the atmosphere within the chamber
is changed to NH.sub.3 while the semiconductor substrate 10 is held
continuously in the chamber and the temperature within the chamber
is held at a temperature not less than the film deposition
temperature (490.degree. C.) for the titanium nitride film 13. The
semiconductor substrate 10 is held under these conditions for about
3 to 10 minutes.
[0067] Next, a tungsten film 14 with a thickness of about 100 nm is
deposited by sputtering on the titanium nitride film 13, similarly
to EMBODIMENT 1. Then, as shown in FIG. 1(b), a multilayer film
comprising the tungsten film 14 and the titanium nitride film 13
and the silicon oxynitride film 12 are patterned to form a gate
electrode 15 and a gate insulating film 16.
[0068] Next, sidewalls 17 are formed on the side surfaces of the
gate electrode 15 and impurity diffused layers 18 each serving as a
source or drain region are formed in the semiconductor substrate
10, similarly to EMBODIMENT 1. Thereafter, an interlayer insulating
film 19, contacts 20, and a wiring layer 21 are formed, as shown in
FIG. 1(c).
[0069] The present inventors noticed that, when the titanium
nitride film 13 was formed by CVD using the source gas composed of
the gas mixture of TiCl.sub.4 and NH.sub.3, a gate leakage current
was increased by the heat treatment performed subsequently, e.g., a
heat treatment at about 1000.degree. C. for activating the impurity
diffusion layers 18 each serving as the source or drain region.
[0070] Then, the present inventors examined the reason that the
leakage current was increased by the heat treatment performed at
about 1000.degree. C. after the deposition of the titanium nitride
film 13 and found the following cause of the increased leakage
current.
[0071] When the titanium nitride film 13 was deposited by CVD using
the source gas composed of the gas mixture of TiCl.sub.4 and
NH.sub.3, the reaction of
6TiCl.sub.4+8NH.sub.3.fwdarw.6TiN+24HCl+N.sub.2 occurred to deposit
the titanium nitride film 13, so that chlorine remained in the
titanium nitride film 13. Consequently, when the heat treatment at
about 1000.degree. C. was performed with respect to the titanium
nitride film 13, chlorine remaining in the titanium nitride film 13
was diffused into the gate insulating film 16 in the heat treatment
process, whereby the gate leakage current was increased.
[0072] If the thickness of the gate insulating film 16 was
increased, the gate leakage current was increased against
expectations.
[0073] FIG. 3 shows a cross-sectional structure when the heat
treatment at about 1000.degree. C. was performed after the tungsten
film 14 was thus deposited on the titanium nitride film 13. As
shown in FIG. 3, the outward diffusion path of the residual
chlorine evaporated from the titanium nitride film 13 is closed so
that the residual chlorine resides between the silicon oxynitride
film 12 as the gate insulating film and the titanium nitride film
13. As a result, the titanium nitride film 13 peels off the surface
of the gate insulating film. The phenomenon is particularly marked
when the titanium nitride film 13 is deposited at a low temperature
for the improved quality of the titanium nitride film 13.
[0074] As a method for reducing the residual chlorine in the
titanium nitride film 13, Japanese Patent Publication No. 2803556
discloses a method wherein a plasma is applied to the titanium
nitride film 13. In accordance with the method, however, the gate
insulating film 16 is damaged by the applied plasma and the
reliability of the gate insulating film 16 may be lowered
thereby.
[0075] EMBODIMENT 2 is for preventing an increase in gate leakage
current and the peeling of the titanium nitride film 13 off the
surface of the gate insulating film without degrading the gate
insulating film 16 even if a heat treatment is performed at about
1000.degree. C. with respect to the titanium nitride film 13. As
stated previously, the atmosphere within the chamber is changed to
NH.sub.3 while the semiconductor substrate 10 is held continuously
in the chamber in which the titanium nitride film 13 has been
deposited and the temperature within the chamber is maintained at a
temperature not less than the film deposition temperature for the
titanium nitride film 13.
[0076] If the titanium nitride film 13 is thus held in the NH.sub.3
atmosphere at a temperature not less than the film deposition
temperature, unreacted TiCl.sub.4 and NH.sub.3 which are present in
the titanium nitride film 13 react to generate HCl, as shown in
FIG. 4. Since the generated HCl evaporates, the residual chlorine
in the titanium nitride film 13 is reduced.
[0077] FIG. 5 shows the relationship between a depth measured from
a surface of the titanium nitride film 13 and the chlorine
concentration in the nitride film 13 measured by using XPS. In FIG.
5, the broken line represents EMBODIMENT 1 (the case in which a
heat treatment is not performed with respect to the titanium
nitride film 13 deposited at 490.degree. C.) and the solid line
represents EMBODIMENT 2 (the case in which the heat treatment is
performed in the ammonia atmosphere with respect to the titanium
nitride film 13 deposited at 490.degree. C.).
[0078] As can be seen from FIG. 5, if the heat treatment is
performed in the ammonia atmosphere with respect to the titanium
nitride film 13 as in EMBODIMENT 2, the concentration of chlorine
in the titanium nitride film 13 can be reduced significantly to
about 2 at %.
[0079] Thus, EMBODIMENT 2 not only achieves the effects achieved by
EMBODIMENT 1 but also reduces the residual chlorine in the titanium
nitride film 13 by reducing the residual chlorine in the titanium
nitride film 13 and thereby prevents the peeling of the titanium
nitride film 13 off the surface of the gate insulating film.
[0080] Since EMBODIMENT 2 enables the deposition of the titanium
nitride film 13 and the removal of the residual chlorine by using a
single chamber and merely changing the gas introduced into the
chamber, the residual chlorine can be removed while an increase in
process steps is suppressed.
[0081] Although EMBODIMENT 2 has used the gas mixture of TiCl.sub.4
and NH.sub.3 as the source gas for depositing the titanium nitride
film 13, it is also possible to deposit the titanium nitride film
13 by using a gas mixture of TiI.sub.4 and NH.sub.3 or a gas
mixture of TiBr.sub.4 and NH.sub.3 instead. In this case also,
iodine (I) or bromine (Br) remaining in the titanium nitride film
13 can be reduced by holding the titanium nitride film 13 in the
NH.sub.3 atmosphere at a temperature not less than the film
deposition temperature.
[0082] Embodiment 3
[0083] A method for fabricating a semiconductor device having an
n-type MOSFET as EMBODIMENT 3 of the present invention will be
described with reference to FIGS. 1(a) to (c).
[0084] First, as shown in FIG. 1(a), an isolation region 11 is
formed in a surface portion of a semiconductor substrate 10
composed of, e.g., a p-type silicon substrate, similarly to
EMBODIMENT 1. Then, a silicon oxynitride film 12 with a thickness
of about 2 nm as a gate insulating film is formed on the
semiconductor substrate 10.
[0085] Next, a titanium nitride film 13 with a thickness of about
10 nm is deposited on the silicon oxynitride film 12 by CVD which
is performed at a temperature of about 490.degree. C. by using a
gas mixture of TiCl.sub.4 and NH.sub.3 as source gas. Thereafter,
rapid thermal annealing is performed for about 10 to 60 seconds in
an NH.sub.3 atmosphere at a temperature of 600 to 900.degree. C.
with respect to the titanium nitride film 13.
[0086] Next, a tungsten film 14 with a thickness of about 100 nm is
deposited by sputtering on the titanium nitride film 13, similarly
to EMBODIMENT 1. Then, as shown in FIG. 1(b), a multilayer film
comprising the tungsten film 14 and the titanium nitride film 13
and the silicon oxynitride film 12 are patterned to form a gate
electrode 15 and a gate insulating film 16.
[0087] Next, sidewalls 17 are formed on the side surfaces of the
gate electrode 15 and impurity diffused layers 18 each serving as a
source or drain region are formed in the semiconductor substrate
10, similarly to EMBODIMENT 1. Then, an interlayer insulating film
19, contacts 20, and a wiring layer 21 are formed, as shown in FIG.
1(c).
[0088] If the rapid thermal annealing is performed in the NH.sub.3
atmosphere with respect to the titanium nitride film 13 as in
EMBODIMENT 3, Cl which is present in the titanium nitride film 13
evaporates, as shown in FIG. 6, so that residual chlorine in the
titanium nitride film 13 is reduced. Since the heat treatment is
performed in the NH.sub.3 atmosphere, a phenomenon occurs in which
unreacted TiCl.sub.4 and NH.sub.3 which are present in the titanium
nitride film 13 react to generate HCl and the generated HCl
evaporates.
[0089] Thus, EMBODIMENT 3 not only achieves the effects achieved by
EMBODIMENT 1 but also reduces a gate leakage current by reducing
the residual chlorine in the titanium nitride film 13 and thereby
prevents the peeling of the titanium nitride film 13 off the
surface the gate insulating film.
[0090] Since EMBODIMENT 3 evaporates the residual chlorine by the
rapid thermal annealing, a long-time heat treatment is not
performed with respect to the semiconductor substrate 10. This
suppresses damage caused by the heat treatment to the semiconductor
device.
[0091] Although EMBODIMENT 3 has performed the rapid thermal
annealing in the ammonia gas atmosphere, it is also possible to
perform rapid thermal annealing in a nitrogen gas atmosphere, a gas
mixture atmosphere of nitrogen gas and hydrogen gas, an argon gas
atmosphere, or vacuum.
[0092] Although EMBODIMENT 3 has used the gas mixture of TiCl.sub.4
and NH.sub.3 as the source gas for depositing the titanium nitride
film 13, it is also possible to deposit the titanium nitride film
13 by using a gas mixture of TiI.sub.4 and NH.sub.3 or a gas
mixture of TiBr.sub.4 and NH.sub.3. In this case also, iodine or
bromine which is present in the titanium nitride film 13 can be
reduced by performing rapid thermal annealing with respect to the
titanium nitride film 13.
[0093] Embodiment 4
[0094] A method for fabricating a semiconductor device having an
n-type MOSFET as EMBODIMENT 4 of the present invention will be
described with reference to FIGS. 1(a) to (c).
[0095] First, as shown in FIG. 1(a), an isolation region 11 is
formed in a surface portion of a semiconductor substrate 10
composed of, e.g., a p-type silicon substrate, similarly to
EMBODIMENT 1. Then, a silicon oxynitride film 12 with a thickness
of about 2 nm as a gate insulating film is formed on the
semiconductor substrate 10.
[0096] Next, a titanium nitride film 13 with a thickness of about
10 nm is deposited on the silicon oxynitride film 12 by CVD which
is performed at about 650.degree. C. by using a gas mixture of
TiCl.sub.4 and NH.sub.3 as source gas.
[0097] Next, a tungsten film 14 with a thickness of about 100 nm is
deposited by sputtering on the titanium nitride film 13, similarly
to EMBODIMENT 1. Then, as shown in FIG. 1(b), a multilayer film
comprising the tungsten film 14 and the titanium nitride film 13
and the silicon oxynitride film 12 are patterned to form a gate
electrode 15 and a gate insulating film 16.
[0098] Next, sidewalls 17 are formed on the side surfaces of the
gate electrode 15 and impurity diffused layers 18 each serving as a
source or drain region are formed in the semiconductor substrate
10, similarly to EMBODIMENT 1. Then, an interlayer insulating film
19, contacts 20, and a wiring layer 21 are formed, as shown in FIG.
1(c).
[0099] Since EMBODIMENT 4 forms the titanium nitride film at a high
temperature, the concentration of residual chlorine in the titanium
nitride film can be reduced.
[0100] FIG. 7 shows the relationship between a depth measured from
a surface of the titanium nitride film 13 and the chlorine
concentration in the titanium nitride film 13 measured by using
XPS. In FIG. 7, the broken line represents EMBODIMENT 1 (the case
in which a heat treatment is not performed with respect to the
titanium nitride film 13 deposited at 490.degree. C.) and the solid
line represents EMBODIMENT 4 (the case in which the heat treatment
is not performed with respect to the titanium nitride film 13
deposited at 650.degree. C.). In FIG. 7, a portion indicated by the
dot-dash line results from the surface contamination of the
titanium nitride film 13 and a portion indicated by the
two-dot-dash line shows a measurement error.
[0101] As can be seen from FIG. 7, if the titanium nitride film 13
is deposited at a temperature of 650.degree. C. as in EMBODIMENT 4,
the chlorine concentration in the titanium nitride film 13 can be
reduced significantly to about 2 at %.
[0102] FIG. 8 shows the relationship between the film-deposition
temperature for the titanium nitride film 13 and the chlorine
concentration. In FIG. 8, .largecircle. represents the chlorine
concentration in the film before the heat treatment and
.circle-solid. represents the chlorine concentration in the film
after the heat treatment. As can be seen from FIG. 8, the chlorine
concentration before and after the heat treatment is lower as the
film deposition temperature is higher.
[0103] FIG. 9 shows the respective concentrations of residual
chlorine in the titanium nitride films 13 deposited on the gate
insulating films 16 with a thickness of 3.5 nm at the film
deposition temperatures of 650.degree. C. (EMBODIMENT 4) and
490.degree. C. (EMBODIMENT 1) by CVD using source gas composed of a
gas mixture of TiCl.sub.4 and NH.sub.3 and respective gate leakage
current values in MOS capacitors when a heat treatment was
performed at 1000.degree. C. for 10 seconds with respect to the
titanium nitride films 13.
[0104] As can be seen from FIG. 9, the amount of residual chlorine
after the heat treatment is smaller as the film deposition
temperature is higher and the gate leakage current is reduced
thereby. This indicates that, according to EMBODIMENT 4, the gate
leakage current can be reduced even if the heat treatment at about
1000.degree. C. for activating the impurity diffused layers 18 each
serving as the source or drain region is performed.
[0105] FIG. 10 shows the relationship between the heat treatment
temperatures for the titanium nitride films 13 deposited on the
gate insulating film 16 with a thickness of 2.4 nm at the film
deposition temperatures of 650.degree. C. (EMBODIMENT 4) and
490.degree. C. (EMBODIMENT 1) by CVD using source gas composed of
TiCl.sub.4 and NH.sub.3 and gate leakage current values in MOS
capacitors.
[0106] As can be seen from FIG. 10, a gate leakage current value
hardly changes even if the heat treatment is performed with respect
to the titanium nitride film 13.
[0107] EMBODIMENT 4 not only achieves the effects achieved by
EMBODIMENT 1 but also reduces the gate leakage current by reducing
the residual chlorine in the titanium nitride film 13 and thereby
prevents the peeling of the titanium nitride film 13 off the
surface of the gate insulating film.
[0108] Since EMBODIMENT 4 deposits the titanium nitride film 13 at
a high temperature, the rate at which the film is deposited becomes
higher than the rate at which the film is formed at a lower
temperature. This makes it difficult to form the titanium nitride
film 13 with a smaller thickness but it is possible to form the
titanium nitride film 13 with a thickness of about 20 nm.
[0109] Although EMBODIMENT 4 has used the gas mixture of TiCl.sub.4
and NH.sub.3 as the source gas for depositing the titanium nitride
film 13, it is also possible to deposit the titanium nitride film
13 by using a gas mixture of TiI.sub.4 and NH.sub.3 or a gas
mixture of TiBr.sub.4 and NH.sub.3. In this case also, iodine or
bromine which is present in the titanium nitride film 13 can be
reduced.
[0110] Embodiment 5
[0111] A method for fabricating a semiconductor device having an
n-type MOSFET and a capacitor as EMBODIMENT 5 of the present
invention will be described with reference to FIGS. 11(a) to (c)
and FIGS. 12(a) to (c).
[0112] First, as shown in FIG. 11(a), an isolation region 31 is
formed by a well-known method in a surface portion of a
semiconductor substrate 30 composed of, e.g., a p-type silicon
substrate. Then, a silicon oxynitride film 32 with a thickness of
about 2 nm as a gate insulating film is formed on the semiconductor
substrate 30.
[0113] Next, a titanium nitride film 33 having a thickness of about
10 to 20 nm and serving as a lower-layer gate electrode and a lower
electrode of a capacitor is deposited on the silicon oxynitride
film 32 by CVD which is performed at a temperature of about
490.degree. C. by using TiCl.sub.4 and NH.sub.3 as source gas.
Then, a silicon oxide film 34 having a thickness of about 5 to 10
nm and serving as a capacitor insulating film is formed on the
titanium nitride film 33.
[0114] Next, as shown in FIG. 11(b), a first resist pattern 35 is
formed on the silicon oxide film 34. Then, the silicon oxide film
34 is etched by using, e.g., a dilute hydrofluoric acid solution
and the first resist pattern 35 as a mask, whereby a capacitor
insulating film 34B composed of the silicon oxide film 34 is
formed.
[0115] Next, after the first resist pattern 35 is removed, a
tungsten film 36 having a thickness of about 100 nm and serving as
an upper-layer gate electrode and an upper electrode of the
capacitor is deposited by sputtering on the titanium nitride film
33 and the capacitor insulating film 34B, as shown in FIG. 11(c).
Then, a silicon nitride film 37 having a thickness of about 100 nm
and serving as a hard mask is formed on the tungsten film 36.
[0116] Next, as shown in FIG. 12(a), a second resist pattern 38 is
formed on the silicon nitride film 37. Then, the silicon nitride
film 37 is etched by using the second resist pattern 38 as a mask,
whereby a hard mask 37A composed of the silicon nitride film 37 is
formed, as shown in FIG. 12(b).
[0117] Next, the second resist pattern 38 is removed and then the
tungsten film 36, the titanium nitride film 33, and the silicon
oxynitride film 32 are patterned by using the hard mask 37A,
whereby an upper-layer gate electrode 36A and an upper electrode
36B of the capacitor each composed of the tungsten film 36, a
lower-layer gate electrode 33A and a lower electrode 33B of the
capacitor each composed of the titanium nitride film 33, and a gate
insulating film 32A and a patterned insulating film 32B each
composed of the silicon oxynitride film 32 are formed. As a result,
there are formed a gate electrode 39 composed of the upper-layer
gate electrode 36A and the lower-layer gate electrode 33A and a
capacitor 40 composed of the upper electrode 36B, the capacitor
insulating film 34B, and the lower electrode 33B.
[0118] Next, sidewalls 41 are formed by a well-known method on the
respective side surfaces of the gate electrode 39 and the capacitor
40, while impurity diffused layers 42 each serving as a source or
drain are formed in the semiconductor substrate 30, as shown in
FIG. 12(c).
[0119] Next, an interlayer insulating film 43 is formed entirely
over the gate electrode 39 and the capacitor 40 and then contact
holes are formed in the interlayer insulating film 43.
Subsequently, a metal film is deposited on the interlayer
insulating film 43 to fill in the contact holes and patterned to
form contacts and metal wiring 44.
[0120] Thus, since the tungsten film 36.serving as the upper-layer
gate electrode 36A is patterned to form the upper electrode 36B and
the titanium nitride film 33 serving as the lower-layer gate
electrode 33A is patterned to form the lower electrode 33B
according to EMBODIMENT 5, the effect of forming the capacitor
without increasing the number of process steps is achieved in
addition to the effects achieved by EMBODIMENT 1.
[0121] Moreover, since the upper electrode 36B is composed of the
tungsten film 36 and the lower electrode 33B is composed of the
titanium nitride film 33, variations in the characteristics of the
electrode and the degradation of RF characteristics as caused by a
heat treatment during the fabrication process in an electrode
composed of a polysilicon film doped with a conductive impurity do
not occur. In other words, EMBODIMENT 5 achieves not only a
reduction in process steps but also an improvement in the
characteristics of the capacitor.
[0122] Embodiment 6
[0123] A method for fabricating a semiconductor device having an
n-type MOSFET and a resistor as EMBODIMENT 6 of the present
invention will be described with reference to FIGS. 13(a) to (c),
FIGS. 14(a) to (c), FIGS. 15(a) and (b), and FIGS. 16(a) to
(c).
[0124] First, as shown in FIG. 13(a), an isolation region 51 is
formed by a well-known method in a surface portion of a
semiconductor substrate 50 composed of, e.g., a p-type silicon
substrate. Then, a silicon oxynitride film 52 with a thickness of
about 2 nm as a gate insulating film is formed on the semiconductor
substrate 50.
[0125] Next, a titanium nitride film 53 having a thickness of about
10 to 20 nm and serving as a lower-layer gate electrode and a
resistor is deposited on the silicon oxynitride film 52 by CVD
which is performed at a temperature of about 490.degree. C. by
using TiCl.sub.4 and NH.sub.3 as source gas. Then, a silicon oxide
film 54 serving as a first hard mask 54A (see FIG. 13(b)) for
forming a resistor having a thickness of about 20 to 50 nm is
formed on the titanium nitride film 53. As shown in FIG. 16(a), the
silicon oxide film 54 is formed to have a thickness t.sub.1
approximately equal to the height t.sub.2 Of that portion of the
isolation region 51 protruding from the semiconductor substrate 50.
The reason for this will be described later.
[0126] Next, as shown in FIG. 13(b), a first resist pattern 55 is
formed on the silicon oxide film 54. Then, the silicon oxide film
54 is etched by using, e.g., a dilute hydrofluoric acid solution
and the first resist pattern 55 as a mask, whereby a first hard
mask 54A composed of the silicon oxide film 54 is formed.
[0127] Next, after the first resist pattern 55 is removed, a
tungsten film 56 having a thickness of about 100 nm and serving as
an upper-layer gate electrode is deposited by sputtering on the
titanium nitride film 53 and the first hard mask 54A, as shown in
FIG. 13(c). Then, a silicon nitride film 57 having a thickness of
about 100 nm and serving as a second hard mask for forming a gate
electrode is formed on the tungsten film 56.
[0128] Next, as shown in FIG. 14(a), a second resist pattern 58 is
formed on the silicon nitride film 57. Then, the silicon nitride
film 57 is etched by using the second resist pattern 58 as a mask,
whereby a second hard mask 57A composed of the silicon nitride film
57 is formed, as shown in FIG. 14(b). In this case, it is preferred
to use etching gas having a selectivity to the tungsten film 56,
such as etching gas containing a gas mixture of CHF.sub.3 and
O.sub.2 as a main component, and perform sufficient overetching so
as not to leave an etching residue 64 composed of the silicon
nitride film 57 on the stepped portion of the tungsten film 56, as
shown in FIG. 16(b).
[0129] Next, after the second resist pattern 58 is removed, the
tungsten film 56 is etched by using etching gas containing
chlorine-based gas and the second hard mask 57A, whereby an
upper-layer gate electrode 56A composed of the tungsten film 56 is
formed, as shown in FIG. 14(c). Although the first hard mask 54A
composed of the silicon oxide film 54 is exposed in the etching
step, there is no possibility that the first hard mask 54A
disappears because of the high etching selectivity of the tungsten
film 56 to the silicon oxide film 54.
[0130] As stated previously, the thickness t.sub.1 of the silicon
oxide film 54 is approximately equal to the height t.sub.2 of the
portion of the isolation region 51 protruding from the
semiconductor substrate 50. Accordingly, the thickness of the first
tungsten film 65a remaining on each of the side surfaces of the
first hard mask 54A overlying the titanium nitride film 53 is
approximately equal to the thickness of the second tungsten film
65b remaining on the portion of the titanium nitride film 53
corresponding to the stepped portion of the isolation region 51, as
shown in FIG. 16(c). Consequently, the first tungsten film 65a is
removed by overetching for completely removing the second tungsten
film 65b. The thickness t.sub.1 of the silicon oxide film 54 is
sufficient if it is equal to or less than the height of the stepped
portion t.sub.2 of the isolation region 51 protruding from the
semiconductor substrate 50.
[0131] Next, the titanium nitride film 53 and the silicon
oxynitride film 52 are patterned by using the first and second hard
masks 54A and 57A, whereby a lower-layer gate electrode 53A and a
resistor 53B each composed of the titanium nitride film 53 are
formed and a gate insulating film 52A and a patterned insulating
film 52B each composed of the silicon oxynitride film 52 are
formed, as shown in FIG. 15(a).
[0132] Next, as shown in FIG. 15(b), sidewalls 60 are formed by a
well-known method on the side surfaces of a gate electrode 59
composed of the upper-layer gate electrode 56A and the lower-layer
gate electrode 53A and impurity diffused layers 61 each serving as
a source or drain are formed in the semiconductor substrate 50.
[0133] Next, an interlayer insulating film 62 is formed entirely
over the gate electrode 59 and the resistor 53B and then contact
holes are formed in the interlayer insulating film 62.
Subsequently, a metal film is deposited on the interlayer
insulating film 62 to fill in the contact hole and patterned to
form contacts and metal wiring 63.
[0134] Thus, since the resistor 53B has been formed by patterning
the titanium nitride film 53 serving as the lower-layer gate
electrode 53A according to EMBODIMENT 6, the effect of forming the
resistor 53B without increasing the number of process steps is
achieved in addition to the effects achieved by EMBODIMENT 1.
[0135] Although the titanium nitride film 53 serving as the
resistor 53B is a conductive material, it has a high resistivity of
150 to 250 .mu..OMEGA..multidot.cm and a small thickness of 10 to
20 nm so that a sufficiently high sheet resistance value of about
200 .OMEGA./.quadrature. is achievable.
[0136] Since the resistor 53B is composed of the titanium nitride
film 53, variations in the characteristics of the resistor and the
degradation of RF characteristics as caused by a heat treatment
during the fabrication process in a resistor composed of a
polysilicon film doped with a conductive impurity do not occur. In
other words, EMBODIMENT 6 not only reduces the number of process
steps but also improves the characteristics of the resistor
53B.
* * * * *