U.S. patent application number 10/304863 was filed with the patent office on 2003-08-21 for memory device.
This patent application is currently assigned to Coatue Corporation. Invention is credited to Krieger, Juri H., Yudanov, Nikolai.
Application Number | 20030155602 10/304863 |
Document ID | / |
Family ID | 46281638 |
Filed Date | 2003-08-21 |
United States Patent
Application |
20030155602 |
Kind Code |
A1 |
Krieger, Juri H. ; et
al. |
August 21, 2003 |
Memory device
Abstract
A memory storage and retrieval device, comprising: (a) an
electrically conductive first electrode; (b) an electrically
conductive second electrode; and (c) a layer stack intermediate the
first and second electrodes, comprising: (d) at least one active
layer comprising at least one polymer with variable electrical
conductivity; and (e) at least one passive layer comprised of a
material for varying the electrical conductivity of the at least
one active layer upon application of an electrical potential
difference between the first and second electrodes.
Inventors: |
Krieger, Juri H.;
(Brookline, MA) ; Yudanov, Nikolai; (Brookline,
MA) |
Correspondence
Address: |
WOLF GREENFIELD & SACKS, PC
FEDERAL RESERVE PLAZA
600 ATLANTIC AVENUE
BOSTON
MA
02210-2211
US
|
Assignee: |
Coatue Corporation
Woburn
MA
|
Family ID: |
46281638 |
Appl. No.: |
10/304863 |
Filed: |
November 27, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10304863 |
Nov 27, 2002 |
|
|
|
PCT/RU01/00334 |
Aug 13, 2001 |
|
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Current U.S.
Class: |
257/306 ;
257/310 |
Current CPC
Class: |
G11C 11/5664 20130101;
G11C 13/0016 20130101; G11C 13/0069 20130101; G11C 2213/35
20130101; G11C 2213/56 20130101; H01L 45/085 20130101; H01L 51/0062
20130101; H01L 45/1616 20130101; G11C 13/0064 20130101; G11C 13/04
20130101; H01L 51/0035 20130101; G11C 13/0009 20130101; G11C
13/0014 20130101; G11C 2213/71 20130101; H01L 45/1608 20130101;
H01L 51/0042 20130101; H01L 51/0077 20130101; H01L 51/0595
20130101; H01L 45/1233 20130101; G11C 2213/11 20130101; H01L
51/0034 20130101; G11C 2213/15 20130101; H01L 27/28 20130101; G11C
11/34 20130101; H01L 51/0036 20130101; H01L 51/0078 20130101; H01L
51/0094 20130101; G11C 2213/77 20130101; G11C 2213/34 20130101;
B82Y 10/00 20130101; H01L 45/14 20130101; H01L 45/08 20130101; H01L
51/0051 20130101; H01L 27/285 20130101; H01L 51/0037 20130101; H01L
51/0041 20130101 |
Class at
Publication: |
257/306 ;
257/310 |
International
Class: |
H01L 029/76; H01L
031/119 |
Claims
What is claimed is:
1. A memory storage and retrieval device, comprising: (a) an
electrically conductive first electrode; (b) an electrically
conductive second electrode; and (c) a layer stack intermediate
said first and second electrodes, said layer stack comprising: (d)
at least one active layer comprising at least one polymer material
with variable electrical conductivity; and (e) at least one passive
layer comprised of a material for varying said electrical
conductivity of said at least one active layer upon application of
an electrical potential difference between said first and second
electrodes.
2. The memory storage and retrieval device according to claim 1,
wherein: said electrical conductivity of said at least one active
layer is reversibly varied upon introduction of charged species
thereinto and removal of said charged species therefrom; and said
at least one passive layer is comprised of a said material for
reversibly donating said charged species to and accepting said
charged species from said active layer.
3. The memory storage and retrieval device according to claim 2,
wherein: said charged species comprise ions or a combination of
ions and electrons.
4. The memory storage and retrieval device according to claim 3,
wherein: said ions are selected from the group consisting of: metal
ions, metal-containing ions, non-metal ions, and
non-metal-containing ions.
5. The memory storage and retrieval device according to claim 2,
wherein: said layer stack comprises a pair of active layers in
mutual contact.
6. The memory storage and retrieval device according to claim 2,
wherein said layer stack further comprises: (f) at least one
barrier layer comprised of a material which impedes spontaneous
movement of said charged species when said electrical potential
difference is not applied between said first and said second
electrodes.
7. The memory storage and retrieval device according to claim 6,
wherein: said at least one barrier layer is positioned within said
stack intermediate said active layer and said passive layer.
8. The memory storage and retrieval device according to claim 6,
wherein: said layer stack comprises first and second active layers,
and said at least one barrier layer is positioned within said stack
intermediate said first and second active layers.
9. The memory storage and retrieval device according to claim 8,
wherein: said layer stack comprises first and second passive layers
in respective contact with said first and second electrically
conductive electrodes.
10. The memory storage and retrieval device according to claim 2,
wherein: each of said first and second electrically conductive
electrodes comprises at least one electrically conductive material
selected from the group consisting of metals, metal alloys, metal
nitrides, oxides, sulfides, carbon, and polymers.
11. The memory storage and retrieval device according to claim 10,
wherein: each of said first and second electrically conductive
electrodes comprises at least one material selected from the group
consisting of aluminum (Al), silver (Ag), copper (Cu), titanium
(Ti), tungsten (W), their alloys and nitrides, amorphous carbon,
transparent oxides, transparent sulfides, and organic polymers.
12. The memory storage and retrieval device according to claim 11,
wherein: each of said first and second electrically conductive
electrodes is from about 1,000 to about 8,000 .ANG. thick.
13. The memory storage and retrieval device according to claim 12,
wherein: each of said first and second electrically conductive
electrodes is about 3,000 to about 5,000 .ANG. thick.
14. The memory storage and retrieval device according to claim 2,
wherein: said at least one active layer comprises at least one
polymer with a relatively lower intrinsic electrical conductivity
when free of said charged species and a relatively higher
electrical conductivity when doped with said charged species.
15. The memory storage and retrieval device according to claim 14,
wherein: said at least one active layer comprises at least one
electrically conductive polyacetylene polymer.
16. The memory storage and retrieval device according to claim 15,
wherein: said polyacetylene polymer is selected from the group
consisting of polydiphenylacetylene,
poly(t-butyl)diphenylacetylene,
poly(trifluoromethyl)diphenylacetylene,
polybis(trifluoromethyl)acetylene- ,
polybis(tbutyldiphenyl)acetylene,
poly(trimethylsilyl)diphenylacetylene,
poly(carbazole)diphenylacetylene, polydiacetylene,
polyphenylacetylene, polypyridineacetylene,
polymethoxyphenylacetylene, polymethylphenylacetylene,
poly(t-butyl)phenylacetylene, polynitrophenylacetylene,
poly(trifluoromethyl)phenylacetylene,
poly(trimethylsilyl)pheylacetylene, and derivatives of the
foregoing containing ion trapping molecular groups selected from
the group consisting of crown ethers, cyclic analogues of crown
ethers, carboxyls, diimines, sulfonics, phosphonics and
carbodithioics.
17. The memory storage and retrieval device according to claim 14,
wherein: said at least one polymer is selected from the group
consisting of polyaniline, polythiophene, polypyrrole, polysilane,
polystyrene, polyfuran, polyindole, polyazulene, polyphenylene,
polypyridine, polybipyridine, polyphthalocyanine,
poly(ethylenedioxythiophene) and derivatives of the foregoing
containing ion trapping molecular groups selected from the group
consisting of crown ethers, cyclic analogues of crown ethers,
carboxyls, diimines, sulfonics, phosphonics and carbodithioics.
18. The memory storage and retrieval device according to claim 14,
wherein: said at least one active layer comprises a plurality of
channels or pores extending therethrough for facilitating movement
of said charged species therein.
19. The memory storage and retrieval device according to claim 14,
wherein: said at least one active layer is from about 50 to about
3,000 .ANG. thick.
20. The memory storage and retrieval device according to claim 19,
wherein: said at least one active layer is about 500 to about 700
.ANG. thick.
21. The memory storage and retrieval device according to claim 2,
wherein: said at least one passive layer comprises at least one
super-ionic conductor material or intercalation compound.
22. The memory storage and retrieval device according to claim 21,
wherein: said at least one super-ionic conductor material or
intercalation compound reversibly donates and accepts charged
species.
23. The memory storage and retrieval device according to claim 22,
wherein: said at least one super-ionic conductor material or
intercalation compound reversibly donates and accepts charged
species in the form of ions or a combination of ions and electrons,
said ions selected from the group consisting of silver (Ag), copper
(Cu), gold (Au), lithium (Li), sodium (Na), potassium (K), zinc
(Zn), magnesium (Mg), other metal or metal-containing ions,
hydrogen (H), oxygen (O), fluorine (F), and other
halogen-containing ions.
24. The memory storage and retrieval device according to claim 23,
wherein: said at least one super-ionic conductor material or
intercalation compound is selected from the group consisting of
AgI, AgBr, Ag.sub.2S, Ag.sub.2Se, Ag.sub.2-xTe, RbAg.sub.4I.sub.5,
CuI, CuBr, Cu.sub.2-xS, Cu.sub.2-xSe, Cu.sub.2-xTe,
Ag.sub.xCu.sub.2-xS, Cu.sub.3HgI.sub.4, Cu.sub.3HgI.sub.4, AuI,
Au.sub.2S, Au.sub.2Se, Au.sub.2S.sub.3, Na.sub.xCu.sub.ySe.sub.2,
Li.sub.3N, LiNiO.sub.2, Li.sub.xTiS.sub.2, Li.sub.xMoSe.sub.2,
Li.sub.xTaS.sub.2, Li.sub.xVSe.sub.2, Li.sub.xHfSe.sub.2,
Li.sub.xWO.sub.3, Cu.sub.xWO.sub.3, Na.sub.xWO.sub.3,
H.sub.xWO.sub.3, H.sub.xPd, Na--Al.sub.2O.sub.3,
(AgI).sub.x(Ag.sub.2O.sub.nB.sub.2O.sub.3).sub.1-x,
Ag.sub.2CdI.sub.4, Cu.sub.xPb.sub.1-xBr.sub.2-x,
Li.sub.3M.sub.2(PO.sub.4- ).sub.3-- where M=Fe, Sc, or Cr,
K.sub.3Nb.sub.3B.sub.2O.sub.12,
K.sub.1-xTi.sub.1-xNb.sub.xOPO.sub.4, SrZr.sub.1-xYb.sub.xO.sub.3,
Sr.sub.1-x/2Ti.sub.1-x, Nb.sub.xO.sub.3-, --Mg.sub.3Bi.sub.2,
Cs.sub.5H.sub.3(SO.sub.4).sub.x.H.sub.2O,
M.sub.3H(XO.sub.4).sub.2-- where M=Rb, Cs, or NH.sub.4 and X=Se or
S, NaZr.sub.2(PO.sub.4).sub.3,
Na.sub.4.5FeP.sub.2O.sub.8(OF).sub.1-x, ZrO.sub.2-x, CeO.sub.2-x,
CaF.sub.2, and BaF.sub.2.
25. The memory storage and retrieval device according to claim 21,
wherein: said at least one passive layer is from about 20 to about
300 .ANG. thick.
26. The memory storage and retrieval device according to claim 25,
wherein: said at least one passive layer is about 100 to about 150
.ANG. thick.
27. The memory storage and retrieval device according to claim 6,
wherein: said at least one barrier layer comprises at least one
material selected from the group consisting of SiO.sub.x,
AlO.sub.x, NbO.sub.x, TiO.sub.x, CrO.sub.x, VO.sub.x, TaO.sub.x,
CuO.sub.x, MgO.sub.x, WO.sub.x, AlN.sub.x, Al, Pt, Nb, Be, Zn, Ti,
W, Fe, Ni, and Pd.
28. The memory storage and retrieval device according to claim 6,
wherein: said at least one barrier layer is from about 20 to about
300 .ANG. thick.
29. The memory storage and retrieval device according to claim 28,
wherein: said at least one barrier layer is about 50 .ANG.
thick.
30. The memory storage and retrieval device according to claim 2,
wherein: said at least one active layer and said at least one
passive layer are each comprised of the same material, whereby said
stack effectively comprises a single layer.
31. The memory storage and retrieval device according to claim 30,
wherein: said single layer comprises a composite material
comprising a porous dielectric containing at least one polymer with
variable conductivity.
32. The memory storage and retrieval device according to claim 31,
wherein: said porous dielectric is selected from the group
consisting of Si, amorphous Si, silicon dioxide (SiO.sub.2),
aluminum oxide (Al.sub.2O.sub.3), copper oxide (Cu.sub.2O),
titanium dioxide (TiO.sub.2), boron nitride (BN), vanadium oxide
(V.sub.2O.sub.3), carbon tri-nitride (CN.sub.3), and ferroelectric
materials.
33. The memory storage and retrieval device according to claim 30,
wherein: said single active layer comprises at least one polymer
with variable conductivity and doped with a charged species or
electrolyte clusters.
34. The memory storage and retrieval device according to claim 30,
wherein said single layer stack further comprises: at least one
barrier layer positioned within the stack interior and comprised of
a material which impedes spontaneous movement of the charged
species when an electrical potential difference is not applied
between said first and said second electrodes.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a Continuation-in-Part of PCT
application PCT/RU01/00334 filed Aug. 13, 2001.
RELATED APPLICATIONS
[0002] This application contains subject matter related to the
subject matter disclosed in copending U.S. patent application Ser.
No. 10/238,880, filed on Sep. 11, 2002, entitled "Memory
Device".
FIELD OF THE INVENTION
[0003] The present invention relates to novel memory devices. The
invention is useful in the development, manufacture, and use of a
variety of devices and/or technologies, including, inter alia,
memory devices for electronic computers, associative memory
systems, circuit elements with programmable resistance for creating
synapses for neuronal nets, direct access data banks, and new types
of video/audio equipment.
BACKGROUND OF THE INVENTION
[0004] Modern electronic computers employ several different types
of memory devices for various purposes and functions requiring
different performance/operating characteristics, e.g., read/write
and storage/retrieval speeds. The multiplicity of different
requirements for the various memory devices substantially
complicates the operation of computer systems, increases start-up
times, and complicates data storage.
[0005] As a consequence of the above-mentioned drawbacks and
disadvantages associated with current memory device technology, a
high priority task of the microelectronics industry is
creation/development of a universal memory device/system having
high read/write speeds, high storage density, and long term data
retention characteristics.
[0006] A number of electronic memory or switching devices have been
proposed or developed which include a bi-stable element that can be
controllably alternated between high impedance and low impedance
states by application of an electrical input, e.g., a voltage equal
to or greater than a threshold voltage. Memory and switching
devices utilizing such threshold-type behavior have been
demonstrated with both organic and inorganic thin film
semiconductor materials, including amorphous silicon, chalcogenides
such as arsenic trisulphide-silver (As.sub.2S.sub.3--Ag), organic
materials, and heterostructures such as SrZrO.sub.3(0.2%
Cr)/SrRuO.sub.3. See, for example: U.S. Pat. Nos. 5,761,115;
5,896,312; 5,914,893; 5,670,818; 5,770,885; and 6,150,705; U.S.
Patent Application Publication No. 2001/0054709, Russian Patent No.
2,071,126; S. R. Ovshinsky, Phys. Rev. Lett., 36, 1469 (1976); J.
H. Krieger, et al., J. Struct. Chem., 34, 966 (1993); J. H.
Krieger, et al., Synthetic Metals, 122, 199 (2001); R. S. Potember,
et al., Appl. Phys. Lett., 34 (6), 405 (1979); Y. Machida, et al.,
Jap. J. Appl. Phys., Part 1, 28 (2), 297 (1989); A. Beck, et al.,
Appl. Phys. Lett., 77, 139 (2000); and C. Rossel et al., J. Appl.
Phys. (2001), in press.
[0007] U.S. Pat. No. 6,055,180 to Gudeson, et al. discloses an
electrically addressable, passive storage device for registration,
storage, and/or processing of data, comprising a functional medium
in the form of a continuous or patterned structure capable of
undergoing a physical or chemical change of state. The functional
medium comprises individually addressable cells each of which
represents a registered or detected value or is assigned a
predetermined logical value. Each cell is sandwiched between an
anode and cathode (electrode means) which contact the functional
medium of the cell for electrical coupling therethrough, with the
functional medium having a non-linear impedance characteristic,
whereby the cell can be directly supplied with energy for effecting
a change in the physical or chemical state in the cell.
[0008] A disadvantage/drawback of the storage device of U.S. Pat.
No. 6,055,180, however, is that writing of information can occur
only once, and reading of the stored information is performed
optically, thereby increasing the size and complexity of the device
and its use, at the same time reducing reliability of reading of
the information due to the difficulty in accurately positioning the
optical beam. In addition, an alternate writing method utilizing
thermal breakdown caused by application of a high voltage is also
disadvantageous in that writing of information can only occur once,
and high voltages, hence high electrical fields, are required.
[0009] JP 62-260401 discloses a memory cell with a three-layer
structure comprised of a pair of electrodes with a high temperature
compound (i.e., molecule) sandwiched therebetween, which memory
cell operates on a principle relying upon a change of electrical
resistance of the compound upon application of an external electric
field. Since the conductivity of the compound can be controllably
altered between two very different levels, information in bit form
can be stored therein.
[0010] U.S. Pat. No. 5,761,116 to Kozicki et al. discloses a
"programmable metallization cell" comprised of a "fast ion
conductor", such as a film or layer of a chalcogenide doped with a
metal ion, e.g., silver or copper, and a pair of electrodes, i.e.,
an anode (e.g., of silver) and a cathode (e.g., of aluminum),
spaced apart at a set distance on the surface of the doped
chalcogenide. The silver or copper ions can be caused to move
through the chalcogenide film or layer under the influence of an
electric field. Thus, when a voltage is applied between the anode
and the cathode, a non-volatile metal dendrite ("nano-wire") grows
on the surface of the chalcogenide film or layer ("fast ion
conductor") from the cathode to the anode, significantly reducing
the electrical resistance between the anode and cathode. The growth
rate of the dendrite is a function of the applied voltage and the
interval of its application. Dendrite growth may be terminated by
removing the applied voltage and the dendrite may be retracted
towards the cathode by reversing the polarity of the applied
voltage.
[0011] U.S. Pat. No. 5,670,818 to Forouhi et al. discloses a
read-only memory device in the form of an electrically programmable
antifuse comprised of a layer of amorphous silicon between metal
conductors. Under application of a high voltage, a portion of the
amorphous silicon layer undergoes a phase change and atoms from the
metal conductors migrate into the silicon layer, resulting in
formation of a thin conducting filament ("nano-wire") composed of a
complex mixture of silicon and metal.
[0012] The principal shortcomings of the above-described memory
devices relying upon nano-wire formation are related to the low
operational speeds caused by the extended interval required for
effecting substantial change in the electrical resistance between
the electrodes/conductors and to the high voltage required, e.g.,
.about.60 V. Such drawbacks significantly limit practical use of
the cells in current high speed electronic devices.
[0013] U.S. Pat. No. 4,652,894 to Potember et al. discloses a
current-controlled, bi-stable threshold or memory switch, comprised
of a layer of a polycrystalline metal-organic semiconductor
material sandwiched between a pair of metallic electrodes, wherein
the layer of metal-organic semiconductor material is an electron
acceptor for providing fast switching at low voltages between high
and low impedance states.
[0014] Practical implementation of the threshold memory switch of
U.S. Pat. No. 4,652,894 is limited, however, principally due to the
use of low temperature metal-organic semiconductor compounds which
are not sufficiently mechanically robust, and more importantly, are
insufficiently resistant to chemical degradation when subjected to
the elevated temperatures commonly associated with modern
semiconductor manufacturing processing, i.e., greater than about
150.degree. C. and as high as about 400.degree. C. In addition, the
physical characteristics of the metal-organic semiconductor
materials cause poor repeatability of the read/write/erase cycle,
and storage is limited to only 1 bit of formation, thereby
prohibiting use in high information density
applications/devices.
[0015] U.S. Patent Application Publication No. 2001/0054709 to
Heath et al. discloses the fabrication of electronic devices
comprised of two crossed nanowires sandwiching an electrically
addressable molecular species. The devices are used to produce
crossbar switch arrays, logic devices, memory devices and
communication and signal routing devices.
[0016] In view of the above, there exists a clear need for memory
devices which are free of the above-described shortcomings,
drawbacks, and disadvantages associated with memory devices of the
conventional art. The present invention, therefore, has as its
principal aim the development of a universal memory device/system
for high speed data storage and retrieval, with capability of long
term storage at high bit densities.
DISCLOSURE OF THE INVENTION
[0017] An advantage of the present invention is an improved memory
storage and retrieval device.
[0018] Another advantage of the present invention is an improved
memory storage and retrieval device not requiring formation of
conventional semiconductor junctions.
[0019] Yet another advantage of the present invention is an
improved memory storage and retrieval device which can be readily
fabricated from a variety of materials.
[0020] Still another advantage of the present invention is an
improved memory storage and retrieval device having very high read
and write speeds, long term data retention, and high data storage
density.
[0021] Additional advantages and other features of the present
invention will be set forth in the description which follows and in
part will become apparent to those having ordinary skill in the art
upon examination of the following or may be learned from the
practice of the present invention. The advantages of the present
invention may be realized and obtained as particularly pointed out
in the appended claims.
[0022] According to an aspect of the present invention, the
foregoing and other advantages are obtained in part by a memory
storage and retrieval device, comprising:
[0023] (a) an electrically conductive first electrode;
[0024] (b) an electrically conductive second electrode; and
[0025] (c) a layer stack intermediate the first and second
electrodes, the layer stack comprising:
[0026] (d) at least one active layer comprising a polymer material
with variable electrical conductivity; and
[0027] (e) at least one passive layer comprised of a material for
varying the electrical conductivity of the at least one active
layer upon application of an electrical potential difference
between the first and second electrodes.
[0028] In accordance with embodiments of the present invention, the
electrical conductivity of the at least one active layer is
reversibly varied upon introduction and removal of charged species;
and the at least one passive layer is comprised of a material for
reversibly donating the charged species to and accepting the
charged species from the active layer.
[0029] According to preferred embodiments of the invention, the
charged species comprise ions or a combination of ions and
electrons, the ions selected from the group consisting of: metal
ions, metal-containing ions, non-metal ions, and
non-metal-containing ions.
[0030] Embodiments of the present invention include those wherein
the layer stack comprises a pair of active layers in mutual
contact; and the layer stack may further comprise:
[0031] (f) at least one barrier layer comprised of a material which
impedes spontaneous movement of the charged species when the
electrical potential difference is not applied between the first
and second electrodes.
[0032] Further embodiments of the present invention include those
wherein the at least one barrier layer is positioned within the
stack intermediate the active layer and the passive layer;
embodiments wherein the layer stack comprises first and second
active layers and the at least one barrier layer is positioned
within the stack intermediate the first and second active layers;
and embodiments wherein the layer stack comprises first and second
passive layers in respective contact with the first and second
electrically conductive electrodes.
[0033] According to still further embodiments of the present
invention, the at least one active layer and the at least one
passive layer are each comprised of the same material, whereby the
stack effectively comprises a single layer. The single layer
comprises a composite material comprising a porous dielectric
containing at least one polymer with variable conductivity, and the
porous dielectric is selected from the group consisting of Si,
amorphous Si, silicon dioxide (SiO.sub.2), aluminum oxide
(Al.sub.2O.sub.3), copper oxide (Cu.sub.2O), titanium dioxide
(TiO.sub.2), boron nitride (BN), vanadium oxide (V.sub.2O.sub.3),
carbon tri-nitride (CN.sub.3), and ferroelectric materials,
including barium-strontium titanate ((Ba,Sr)TiO.sub.3).
[0034] Embodiments of the present invention include those wherein
the single layer stack comprises at least one barrier layer
positioned within the stack interior comprised of a material which
impedes spontaneous movement of the charged species when an
electrical potential difference is not applied between said first
and said second electrodes.
[0035] According to still further embodiments of the present
invention, the single layer comprises at least one polymer with
variable conductivity and doped with a charged species or
electrolyte clusters.
[0036] In accordance with embodiments of the present invention,
each of the first and second electrically conductive electrodes
comprises at least one electrically conductive material selected
from the group consisting of metals, metal alloys, metal nitrides,
oxides, sulfides, carbon, and polymers; and according to particular
embodiments of the invention, each of the first and second
electrically conductive electrodes comprises at least one material
selected from the group consisting of aluminum (Al), silver (Ag),
copper (Cu), titanium (Ti), tungsten (W), their alloys and
nitrides, amorphous carbon, transparent oxides, including
indium-tin-oxide (ITO), transparent sulfides, and conductive
organic polymers, each of the first and second electrically
conductive electrodes being from about 1000 to about 8,000 .ANG.
thick, preferably about 3,000 to about 5,000 .ANG. thick.
[0037] According to embodiments of the present invention, the at
least one active layer comprises at least one material with a
relatively lower intrinsic electrical conductivity when free of a
charged species, and a relatively higher electrical conductivity
when doped with a charged species. A suitable material for the
active layer includes at least one polymer with variable electrical
conductivity, which one or more polymers with variable electrical
conductivity further include a plurality of channels or pores
extending therethrough for facilitating movement of charged species
therein.
[0038] Examples of polymers with variable electrical conductivity
include polyacetylene polymers. Suitable polyacetylene polymers
include those selected from the group consisting of
polydiphenylacetylene, poly(tbutyl)diphenylacetylene,
poly(trifluoromethyl)diphenylacetylene,
polybistrifluoromethyl)acetylene,
polybis(t-butyldiphenyl)acetylene, poly(trimethylsilyl)
diphenylacetylene, poly(carbazole)diphenylacetylene,
polydiacetylene, polyphenylacetylene, polypyridineacetylene,
polymethoxyphenylacetylene, polymethylphenylacetylene,
poly(t-butyl)phenylacetylene, polynitrophenylacetylene,
poly(trifluoromethyl) phenylacetylene,
poly(trimethylsilyl)pheylacetylene- , and derivatives of the
foregoing containing ion trapping molecular groups selected from
the group consisting of crown ethers, cyclic analogues of crown
ethers, carboxyls, diimines, sulfonics, phosphonics and
carbodithioics.
[0039] Other suitable polymers include those selected from the
group consisting of polyaniline, polythiophene, polypyrrole,
polysilane, polystyrene, polyfuran, polyindole, polyazulene,
polyphenylene, polypyridine, polybipyridine, polyphthalocyanine,
poly(ethylenedioxythiop- hene) and derivatives of the foregoing
with ion trapping molecular groups selected from the group
consisting of crown ethers, cyclic analogues of crown ethers,
carboxyls, diimines, sulfonics, phosphonics and carbodithioics.
[0040] Preferred polymers are those with high thermal stability,
e.g., thermally stabile at about 400.degree. C. and higher.
[0041] It is also desirable to use a composite material comprised
of a porous dielectric containing at least one polymer with
variable conductivity. Examples of usable porous dielectric
materials include those selected from the group consisting of Si,
amorphous Si, silicon dioxide (SiO.sub.2), aluminum oxide
(Al.sub.2O.sub.3), copper oxide (Cu.sub.2O), titanium dioxide
(TiO.sub.2), boron nitride (BN), vanadium oxide (V.sub.2O.sub.3),
carbon tri-nitride (CN.sub.3), and ferroelectric materials,
including barium-strontium titanate ((Ba,Sr)TiO.sub.3).
[0042] The at least one active layer is from about 50 to about
3,000 .ANG. thick, preferably about 500 to about 700 .ANG.
thick.
[0043] In accordance with embodiments of the present invention, the
at least one passive layer comprises at least one super-ionic
conductor material or intercalation compound, wherein the at least
one super-ionic conductor material or intercalation compound
reversibly donates and accepts charged species; e.g., ions or a
combination of ions and electrons, the ions selected from the group
consisting of silver (Ag), copper (Cu), gold (Au), lithium (Li),
sodium (Na), potassium (K), zinc (Zn), magnesium (Mg), other metal
or metal-containing ions, hydrogen (H), oxygen (0), fluorine (F),
and other halogen-containing ions; and the at least one super-ionic
conductor material or intercalation compound is selected from the
group consisting of AgI, AgBr, Ag.sub.2S, Ag.sub.2Se, Ag.sub.2-xTe,
RbAg.sub.4I.sub.5, CuI, CuBr, Cu.sub.2-xS, Cu.sub.2-xSe,
Cu.sub.2-xTe, Ag.sub.xCu.sub.2-xS, Cu.sub.3HgI.sub.4,
Cu.sub.3HgI.sub.4, AuI, Au.sub.2S, Au.sub.2Se, Au.sub.2S.sub.3,
Na.sub.xCu.sub.ySe.sub.2, Li.sub.3N, LiNiO.sub.2,
Li.sub.xTiS.sub.2, Li.sub.xMoSe.sub.2, Li.sub.xTaS.sub.2,
Li.sub.xVSe.sub.2, Li.sub.xHfSe.sub.2, Li.sub.xWO.sub.3,
Cu.sub.xWO.sub.3, Na.sub.xWO.sub.3, H.sub.xWO.sub.3, H.sub.xPd,
Na--Al.sub.2O.sub.3, (AgI).sub.x(Ag.sub.2O.sub.nB.sub.2O.sub.3-
).sub.1-x, Ag.sub.2CdI.sub.4, Cu.sub.xPb.sub.1-xBr.sub.2-x,
Li.sub.3M.sub.2(PO.sub.4).sub.3-- where M=Fe, Sc, or Cr,
K.sub.3Nb.sub.3B.sub.2O.sub.12,
K.sub.1-xTi.sub.1-xNb.sub.xOPO.sub.4, SrZr.sub.1-xYb.sub.xO.sub.3,
Sr.sub.1-x/2Ti.sub.1-x, Nb.sub.xO.sub.3-, --Mg.sub.3Bi.sub.2,
Cs.sub.5H.sub.3(SO.sub.4).sub.x-H.sub.2O,
M.sub.3H(XO.sub.4).sub.2-- where M=Rb, Cs, or NH.sub.4 and X=Se or
S, NaZr.sub.2(PO.sub.4).sub.3,
Na.sub.4.5FeP.sub.2O.sub.8(OF).sub.1-x, ZrO.sub.2-x, CeO.sub.2-x,
CaF.sub.2, and BaF.sub.2. The passive layer is from about 20 to
about 300 .ANG. thick, preferably about 100 to about 150 .ANG.
thick.
[0044] According to embodiments of the present invention, the at
least one barrier layer comprises at least one material selected
from the group consisting of at least one material selected from
the group consisting of SiO.sub.x, AlO.sub.x, NbO.sub.x, TiO.sub.x,
CrO.sub.x, VO.sub.x, TaO.sub.x, CuO.sub.x, MgO.sub.x, WO.sub.x,
AlN.sub.x, Al, Pt, Nb, Be, Zn, Ti, W, Fe, Ni, and Pd. The barrier
layer is from about 20 to about 300 .ANG. thick, preferably about
50 .ANG. thick.
[0045] Additional advantages and aspects of the present invention
will become readily apparent to those skilled in the art from the
following description, wherein embodiments of the present invention
are shown and described, simply by way of illustration of the best
mode contemplated for practicing the present invention. As will be
described, the present invention is capable of other and different
embodiments, and its several details are susceptible of
modification in various obvious respects, all without departing
from the spirit of the present invention. Accordingly, the drawings
and description are to be regarded as illustrative in nature, and
not as limitative.
BRIEF DESCRIPTION OF THE DRAWINGS
[0046] The following detailed description of the embodiments of the
present invention can best be understood when read in conjunction
with the following drawings, in which similar reference numerals
are employed throughout to designate similar features, and in which
the various features are not necessarily drawn to scale but rather
are drawn as to best illustrate the pertinent features,
wherein:
[0047] FIGS. 1(A)-1(B), show, in schematic, partially cut-away
perspective view, an example of a two-layer memory device 10
according to the invention for illustrating the principle of
conductivity modulation;
[0048] FIG. 2 is a current (I)-voltage (V) plot for illustrating
operation of memory devices according to the invention;
[0049] FIG. 3 is a plot of voltage (V) and current (I) vs. time (in
nsec.) during switching of memory devices according to the
invention from a high resistance "off" state (corresponding to a
logical 0) to a low resistance "on" state (corresponding to a
logical 1); and
[0050] FIGS. 4-11 illustrate in simplified, schematic
cross-sectional view, various memory device constructions according
to the invention, each comprising a layer stack between a pair of
vertically spaced apart first and second electrodes.
DESCRIPTION OF THE INVENTION
[0051] The present invention is based upon the discovery by the
inventor that: (1) polymeric materials exist, or can be prepared,
which can be made to exhibit reversible change, i.e., modulation,
of their electrical conductivity upon application and subsequent
removal of an electrical field; and (2) useful devices, in
particular memory devices, can be fabricated wherein the phenomenon
of reversible conductivity change or modulation exhibited by such
polymeric materials forms the basis for operation of the
devices.
[0052] Specifically, there exists polymers with relatively low
intrinsic electrical conductivity, which are potentially useful as
an active layer of a memory device, which materials can be formed
into layers exhibiting a substantial increase in conductivity
(i.e., conductivity modulation) when doped with charged species of
various types, for example ions or a combination of ions and
electrons, which are introduced thereinto under the influence of an
applied electrical field of a first polarity, and which layers
reversibly exhibit a substantial decrease in electrical
conductivity when the charged species are caused to be at least
partially withdrawn therefrom by application of an electrical field
of a second, opposite polarity. Thus, active layers according to
the present invention are susceptible to conductivity modulation by
means of reversible doping/withdrawal of charged species, e.g.,
ions or a combination of ions and electrons, under the influence of
applied electric fields of appropriate polarity.
[0053] Examples of polymers with variable electrical conductivity
include polyacetylene polymers characterized by conjugated
unsaturated bonds which facilitate electron movement. Suitable
polyacetylene polymers include those selected from the group
consisting of polydiphenylacetylene,
poly(t-butyl)diphenylacetylene,
poly(trifluoromethyl)diphenylacetylene,
polybis(trifluoromethyl)acetylene- ,
polybis(t-butyldiphenyl)acetylene, poly(trimethylsilyl)
diphenylacetylene, poly(carbazole)diphenylacetylene,
polydiacetylene, polyphenylacetylene, polypyridineacetylene,
polymethoxyphenylacetylene, polymethylphenylacetylene,
poly(t-butyl)phenylacetylene, polynitrophenylacetylene,
poly(trifluoromethyl) phenylacetylene,
poly(trimethylsilyl)pheylacetylene, and derivatives of the
foregoing with ion trapping molecular groups selected from the
group consisting of crown ethers, cyclic analogues of crown ethers,
carboxyls, diimines, sulfonics, phosphonics and carbodithioics.
[0054] Other suitable polymers include those selected from the
group consisting of polyaniline, polythiophene, polypyrrole,
polysilane, polystyrene, polyfuran, polyindole, polyazulene,
polyphenylene, polypyridine, polybipyridine, polyphthalocyanine,
poly(ethylenedioxythiop- hene) and derivatives of the foregoing
with ion trapping molecular groups selected from the group
consisting of crown ethers, cyclic analogues of crown ethers,
carboxyls, diimines, sulfonics, phosphonics and carbodithioics.
[0055] Preferred polymers are those with high thermal stability,
e.g., thermally stabile at about 400.degree. C. and higher.
[0056] It is also desirable to use a composite material comprising
a porous dielectric containing one or more polymers with variable
conductivity. Examples of porous dielectric materials include those
selected from the group consisting of Si, amorphous Si, silicon
dioxide (SiO.sub.2), aluminum oxide (Al.sub.2O.sub.3), copper oxide
(Cu.sub.2O), titanium dioxide (TiO.sub.2), boron nitride (BN),
vanadium oxide (V.sub.2O.sub.3), carbon tri-nitride (CN.sub.3), and
ferroelectric materials, including barium-strontium titanate
((Ba,Sr)TiO.sub.3).
[0057] The at least one active layer is from about 50 to about
3,000 .ANG. thick, preferably about 500 to about 700 .ANG.
thick.
[0058] A key feature of the present invention is the presence of an
additional layer of material, termed a passive layer, for
reversibly functioning as a source of the charged species, e.g.,
ions or ions+electrons, which are introduced (injected) into the
active layer during application of the first polarity electrical
field and as an acceptor (sink) of the charged species which are
removed (withdrawn) from the active layer during application of the
second, opposite polarity electrical field. According to the
invention, reversible charged species donor/acceptor materials
suitable for use as the passive layer include, for example,
compounds with mobile ions, including super-ionic conductors and
intercalation compounds, e.g., AgI, AgBr, Ag.sub.2S, Ag.sub.2Se,
Ag.sub.2-xTe, RbAg.sub.4I.sub.5, CuI, CuBr, Cu.sub.2-xS,
Cu.sub.2-xSe, Cu.sub.2-xTe, Ag.sub.xCu.sub.2-xS, Cu.sub.3HgI.sub.4,
Cu.sub.3HgI.sub.4, AuI, Au.sub.2S, Au.sub.2Se, Au.sub.2S.sub.3,
Na.sub.xCu.sub.ySe.sub.2, Li.sub.3N, LiNiO.sub.2, LiTiS.sub.2,
Li.sub.xMoSe.sub.2, Li.sub.xTaS.sub.2, Li.sub.xVSe.sub.2,
Li.sub.xHfSe.sub.2, Li.sub.xWO.sub.3, Cu.sub.xWO.sub.3,
Na.sub.xWO.sub.3, H.sub.xWO.sub.3, H.sub.xPd, Na--Al.sub.2O.sub.3,
(AgI).sub.x(Ag.sub.2O.sub.nB.sub.2O.sub.3- ).sub.1-x,
Ag.sub.2CdI.sub.4, Cu.sub.xPb.sub.1-xBr.sub.2-x,
Li.sub.3M.sub.2(PO.sub.4).sub.3-- where M=Fe, Sc, or Cr,
K.sub.3Nb.sub.3B.sub.2O.sub.12,
K.sub.1-xTi.sub.1-xNb.sub.xOPO.sub.4, SrZr.sub.1-xYb.sub.xO.sub.3,
Sr.sub.1-x/2Ti.sub.1-x, Nb.sub.xO.sub.3-, --Mg.sub.3Bi.sub.2,
Cs.sub.5H.sub.3(SO.sub.4).sub.x-H.sub.2O,
M.sub.3H(XO.sub.4).sub.2-- where M=Rb, Cs, or NH.sub.4 and X=Se or
S, NaZr.sub.2(PO.sub.4).sub.3,
Na.sub.4.5FeP.sub.2O.sub.8(OF).sub.1-x, ZrO.sub.2-x, CeO.sub.2-x,
CaF.sub.2, and BaF.sub.2, which materials reversibly donate/accept
silver (Ag), copper (Cu), gold (Au), lithium (Li), sodium (Na),
potassium (K), zinc (Zn), magnesium (Mg), other metal or
metal-containing ions, hydrogen (H), oxygen (O), fluorine (F), and
other halogen-containing ions.
[0059] In certain embodiments of the memory device fabricated
according to the invention present invention, the at least one
active layer and the at least one passive layer are each comprised
of the same material, whereby the stack effectively comprises a
single layer. The single layer comprises a composite material
comprising a porous dielectric containing at least one polymer with
variable conductivity. The porous dielectric is selected from the
group consisting of Si, amorphous Si, silicon dioxide (SiO.sub.2),
aluminum oxide (Al.sub.2O.sub.3), copper oxide (Cu.sub.2O),
titanium dioxide (TiO.sub.2), boron nitride (BN), vanadium oxide
(V.sub.2O.sub.3), carbon tri-nitride (CN.sub.3), and ferroelectric
materials, including barium-strontium titanate ((Ba,Sr) TiO.sub.3).
The single layer stack may further comprise a barrier layer
positioned within the stack interior and comprised of a material
which impedes spontaneous movement of the charged species when an
electrical potential difference is not applied between said first
and said second electrodes.
[0060] In certain embodiments of the memory device fabricated
according to the invention present invention, the stack effectively
comprises a single layer containing at least one polymer with
variable conductivity and which is doped with a charged species or
electrolyte clusters.
[0061] Materials usable as the passive layer are characterized by
the ease, i.e. rapidity, with which they donate and accept charged
species, e.g., ions or ions+electrons, under the influence of a
relatively weak electric field, i.e., within the range of electric
fields used in typical semiconductor devices such as flash
memories. Thus, application of a first polarity electric field to a
layer stack comprised of at least one active layer and at least one
passive layer will draw charged species such as ions or
ions+electrons, from the latter into the former, and application of
a second, opposite polarity electric field will "pull" at least
some of the ions or ions+electrons out of the former layer and
return them to the latter layer. Further, the donation and
acceptance of the charged species is reversible and can be
modulated for extremely long time periods and for millions of
cycles.
[0062] According to the invention, the performance of memory cells
or devices is a function of the conductivity modulation
characteristics of the polymeric material of the active layer.
Thus, the ease with which charged species such as ions are
reversibly donated to the active layer (i.e., doped therein) and
withdrawn therefrom determines the ease with which "programming"
and "erasing" of the memory device occurs. Since this feature
necessitates facile movement of the charged species, e.g., ions or
ions+electrons, into and out from the active layer, the ions or
ions+electrons will travel freely in the polymeric material, and
thus have a tendency to return to their initial state or location
under the influence of internal electrical fields (as during
absence of the externally applied electrical field). Therefore,
according to the invention, in order to improve the data retention
characteristics of the memory devices, the interval during which
relaxation occurs is controlled, i.e., the interval when the
previously injected mobile ions or ions+electrons are partially
displaced or move out of the active layer and return to the passive
layer and the conductivity therefore decreases, is controlled. Such
control may, for example, be achieved by providing at least one
barrier layer for impeding motion of the charged species in the
absence of an applied electrical field. Therefore, for a material
to be useful as a barrier layer, it must have the property of not
permitting easy travel therethrough of charged species such as ions
or ions+electrons, or a property of not attracting, or even
repelling, ions or ions+electrons. Thus, the barrier layer limits
spontaneous movement of the charged species (i.e., movement in the
absence of an externally applied electric field) between the active
layer and the passive layer, thereby increasing the data retention
time of the memory device. Suitable materials for use as the
barrier layer according to the invention include of SiO.sub.x,
AlO.sub.x, NbO.sub.x, TiO.sub.x, CrO.sub.x, VO.sub.x, TaO.sub.x,
CuO.sub.x, MgO.sub.x, WO.sub.x, AlN.sub.x, Al, Pt, Nb, Be, Zn, Ti,
W, Fe, Ni, and Pd.
[0063] According to the invention, a layer stack is formed which
comprises at least one active layer and at least one passive layer,
and optionally including at least one barrier layer. The layer
stack is sandwiched between a pair of electrically conductive
electrodes which serve as electrical connections for supplying the
requisite externally applied electrical fields. Suitable
electrically conductive materials for use as electrodes include
metals, metal alloys, metal nitrides, oxides, sulfides, carbon, and
polymers, including for example: aluminum (Al), silver (Ag), copper
(Cu), titanium (Ti), tungsten (W), their alloys and nitrides,
amorphous carbon, transparent oxides, including indium-tin-oxide
(ITO), transparent sulfides, and organic polymers. The work
functions of the particular materials utilized for the electrodes
determines the ease with which electrons and/or holes are injected
into the device under the influence of the applied electric field,
and in turn, affects the memory function of the device, i.e., the
speed at which the device can be programmed, read, and erased, as
well as the amount of electrical power required to perform these
functions. In addition, one of the electrodes may, in some
instances, serve as a reactant material for forming the passive
layer of the device.
[0064] Referring now to FIGS. 1(A)-1(B), shown therein, in
schematic, partially cut-away perspective view, is an example of a
two-layer memory device 10 according to the invention for
illustrating the principle of conductivity modulation. As
illustrated, memory device 10 comprises an upper electrode 1 and a
lower electrode 2 with a layer stack interposed therebetween,
comprised of an upper, active layer 3 (bounded on opposite
vertically extending sides by encapsulation layer 9) in contact
with upper electrode 1 and a lower, passive layer 5 in contact with
lower electrode 2. Passive layer 5 is a source (i.e., donor) and
acceptor of a charged species, illustratively positively charged
ions 6 (typically metal ions) and active layer 3 is a poorly
electrically conducting material (e.g., an insulator) including a
plurality of micro-channels or pores 7 extending generally
vertically between passive layer 5 and upper electrode 1 for
facilitating injection and transport of ions 6 in the active layer
3. Thus, FIG. 1(A) illustrates the condition of memory device 10
when in the high resistance, low conductivity "off" state, i.e., no
applied electric field, with ions 6 essentially confined to passive
layer 5 and the micro-channels or pores 7 substantially devoid of
ions 6; whereas FIG. 1(B) illustrates the condition of memory
device 10 when in the low resistance, high conductivity "on" state,
i.e., after application of an electric field of polarity and
strength sufficient to cause ions 6 from the passive layer 5 to be
injected (donated) into the micro-channels or pores 7 of the active
layer 3 to form electrically conductive "nano-wires" 8. (In this
regard, it should be noted that some ions 6 may be present within
micro-channels or pores 7 when device 10 is in the "off" state;
however, the amount of ions is insufficient to establish
electrically conductive "nano-wires" 8).
[0065] Adverting to FIG. 2, shown therein is a current (I)-voltage
(V) plot for illustrating operation of memory devices according to
the invention. Starting at the origin of the plot (i.e., V and
I=0), the voltage (V) applied to a device in the "off" (insulating,
high resistance, or low conductivity) state is initially increased
along curve 1. When the applied voltage reaches the programming
threshold voltage V.sub.T, typically in the range 0.5-4 V, the
device quickly switches from the high resistance "off" state along
curve 2. During programming, ions from the passive layer are
mobilized by the applied electric field, injected into the active
layer, and arranged into conductive micro-channels (as shown in
FIG. 1(B)). The sharp decrease in resistance corresponds to the
point at which formation of the electrically conductive
micro-channels is complete, thereby providing a low resistance.
[0066] The memory device can be read at any voltage below the
threshold voltage V.sub.T, i.e., the "read region". Thus, a low
voltage may be utilized to probe the device and check its
resistance, wherein a low current indicates the device is in the
high resistance, "off" state, and a high current indicates the
device is in the low resistance, "on" state. The "read" operation
is non-destructive and does not disturb the state of the
device.
[0067] From the low resistance state, the applied voltage may be
reduced towards 0 V along curve 3. The slope of the I-V curve
indicates the memory device is in the low resistance state, since
the steeper the slope of the I-V curve, the lower the resistance.
The difference between the "on" and "off" states is termed the
"on/off ratio", which may be as high as 9 orders of magnitude for
the inventive devices, i.e., from several M to .about.100-200, but
typically is .about.4-6 orders of magnitude.
[0068] With the device in the low resistance "on" state, erase may
be performed by applying an increasingly negative voltage (along
curve 3) until the erase threshold voltage V.sub.E is reached, at
which point the device rapidly switches back to the high resistance
"off" state along curve 4. Erase threshold voltages V.sub.E are
typically in the same range as programming threshold voltages
V.sub.T, but can be tuned depending upon the choice of materials
for the active and passive layers, electrodes, and layer
thicknesses. In conceptual terms, an erase operation corresponds to
the removal of a minimum amount of charged species, e.g., ions from
the micro-channels or pores sufficient to interrupt continuity of
the conductive nano-wires. As a consequence, only a small number of
ions needs to be removed from the micro-channels or pores to
effectively sever the conductive wire and thereby increase the
resistance.
[0069] Referring to FIG. 3, which is a plot of voltage (V) and
current (I) vs. time (in nsec.) during switching of memory devices
according to the invention from a high resistance "off" state
(corresponding to a logical 0) to a low resistance "on" state
(corresponding to a logical 1), it is evident that switching times
are very fast, i.e., on the order of about 100 nsec., indicating
high operational speed.
[0070] A variety of device constructions comprising a layer stack
between a pair of vertically spaced apart first and second
electrodes are possible according to the invention, as illustrated
in simplified, schematic cross-sectional view in FIGS. 4-11,
wherein each of the various constituent layers is comprised of one
or more of the above-described materials indicated as suitable for
use as that constituent layer.
[0071] FIG. 4 shows a memory device 20 according to the invention,
comprising a single layer sandwiched between a pair of electrodes,
e.g., a composite active layer 3/5 comprised of a porous dielectric
containing a polymeric material, sandwiched between upper and lower
electrodes 1 and 2;
[0072] FIG. 5 shows a memory device 30 according to the invention,
comprising a layer stack sandwiched between upper and lower
electrodes 1 and 2, the layer stack including an upper, active
layer 3 and a lower, passive layer 5;
[0073] FIG. 6 shows a memory device 40 according to the invention,
comprising a layer stack sandwiched between upper and lower
electrodes 1 and 2, the layer stack including a pair of active
layers 3 including a first, upper active layer 3.sub.A and a
second, lower active layer 3.sub.B, and a lower, passive layer
5;
[0074] FIG. 7 shows a memory device 50 according to the invention,
comprising a layer stack sandwiched between upper and lower
electrodes 1 and 2, the layer stack including an upper, active
layer 3 and a lower, passive layer 5, with a barrier layer 4
inserted between the upper, active layer 3 and the lower, passive
layer 5;
[0075] FIG. 8 shows a memory device 60 according to the invention,
comprising a layer stack sandwiched between upper and lower
electrodes 1 and 2, the layer stack including a pair of active
layers 3 including a first, upper active layer 3.sub.A and a
second, lower active layer 3.sub.B, a barrier layer 4 inserted
between the first, upper active layer 3.sub.A and the second, lower
active layer 3.sub.B, and a lower passive layer 5;
[0076] FIG. 9 shows a memory device 70 according to the invention,
comprising a layer stack sandwiched between upper and lower
electrodes 1 and 2, the layer stack including a first, upper
passive layer 5.sub.A, a pair of active layers 3 including a first,
upper active layer 3.sub.A and a second, lower active layer
3.sub.B, a barrier layer 4 inserted between the first, upper active
layer 3.sub.A and the second, lower active layer 3.sub.B, and a
second, lower passive layer 5.sub.B;
[0077] FIG. 10 shows a memory device 80 according to the invention,
which is a variant of single layer embodiment of FIG. 4, with a
barrier layer 4 positioned within the stack interior 3/5; and
[0078] FIG. 11 shows a memory device 90 according to the invention,
comprising a single layer sandwiched between a pair of electrodes,
i.e., an active layer 3/5 comprised of a polymeric material doped
with a charged species or electrolyte clusters sandwiched between
upper and lower electrodes 1 and 2.
[0079] The thickness of each of the constituent layers of each of
the embodiments illustrated in FIGS. 4-11 are as follows:
[0080] first and second electrically conductive electrodes 1 and 2:
from about 1,000 to about 8,000 .ANG., with 3,000 to about 5,000
.ANG. presently preferred;
[0081] active layer 3 or active layers 3.sub.A and 3.sub.B: from
about 50 to about 3,000 .ANG. thick, with 500 to about 700 .ANG.
presently preferred;
[0082] passive layer 5 or passive layers 5.sub.A and 5.sub.B: from
about 20 to about 300 .ANG. thick, with 100 to about 150 .ANG.
presently preferred; and
[0083] barrier layer 4: from about 20 to about 300 .ANG. thick,
with 50 .ANG. presently preferred.
[0084] Each of the constituent layers may be prepared according to
conventional techniques and methodologies and, for brevity's sake,
details are not provided, except as noted below and in examples
1-17 described below:
[0085] the electrodes are formed via conventional thin film
deposition techniques, e.g., thermal evaporation, sputtering,
e-beam evaporation, etc.;
[0086] the passive layer may be formed by conventional thin film
deposition techniques such as thermal evaporation, CVD, spin
coating, or by first depositing a layer of a metal ultimately
included in the passive layer, e.g., by reacting an initially
formed Cu layer with a S, Se, or Te-containing gas or liquid to
form a layer of a reaction product, e.g., Cu.sub.2S or Cu.sub.2Se
in contact with the Cu layer;
[0087] porous active layers, such as porous polymeric materials,
may be formed according to well-known thin film deposition
techniques, such as thermal evaporation, spin coating, CVD, etc.
Preferable pore sizes are 10-100 .ANG., with 30 .ANG.
preferred.
[0088] According to embodiments of the present invention, the
polymer(s) of the active layer(s), may first be deposited as a
monomer precursor by way of chemical vapor deposition (CVD). An
example of forming one active layer by said process includes:
forming a polymeric film, such as a polydiphenylacetylene film,
over the surface of a passive layer, from a diphenylacetylene
monomer precursor. Similarly, an example of forming more than one
active layer by said process includes: forming a polymeric film,
such as a phthalocyanine film, on the surface of a first active
layer, from a tetracyanobenzene monomer precursor.
EXAMPLE 1
[0089] Ti/Li.sub.xTiS.sub.2/poly(t-butyl)diphenylacetylene/Al or Ti
or amorphous carbon (a-C) (as in FIG. 5)--A first or lower
conductive conductor is deposited on an upper surface of an
insulating layer. The first or lower conductor may be formed from
materials selected from: aluminum, silver, copper, titanium,
tungsten and their alloys and nitrides, conductive oxides, and
amorphous carbon (a-C). The first or lower conductor layer is about
3000 .ANG.-8000 .ANG. thick, with 5000 .ANG. A presently preferred.
The Li.sub.xTiS.sub.2 passive layer may be deposited by chemical
vapor deposition (CVD). The passive layer is about 50 .ANG.-300
.ANG. thick, with 100 .ANG. presently preferred. The intercalation
of lithium ions in TiS.sub.2 layer may be accomplished by means of
a solution of n-butyllithium in hexane. The active layer is
poly(t-butyl)diphenylacetylene, which may be deposited from
solution by spin-coating. The active layer is about 300 .ANG.-1000
.ANG. thick, with 500 .ANG. presently preferred. The second
conductor layer is deposited on the upper surface of the
poly(t-butyl)diphenylacetylene active layer, in a similar manner as
first conductor. The second conductor layer is about 3000
.ANG.-8000 .ANG. thick, with 5000 .ANG. presently preferred.
EXAMPLE 2
[0090] Ti/Polymer electrolyte+poly(t-butyl)diphenylacetylene/a-C
(as in FIG. 11)--A first or lower conductive conductor is deposited
on upper surface of insulating layer. The first or lower conductor
may be formed from titanium and is about 3000 .ANG.-8000 .ANG.
thick, with 5000 .ANG. presently preferred. The active layer is
mixture of a polymer electrolyte containing poly(propylene oxide)
with lithium salt (LiClO.sub.4) and poly(t-butyl)diphenylacetylene,
which may be deposited from solution by spin-coating. The active
layer is about 300 .ANG.-1000 .ANG. thick, with 500 .ANG. presently
preferred. The second conductor layer is amorphous carbon, which
can be deposited on the upper surface of the PhCCPh active layer by
magnetron co-sputtering. The second conductor layer is about 1000
.ANG.-5000 .ANG. thick, with 3000 .ANG. presently preferred.
EXAMPLE 3
[0091] Ti/Cu.sub.2-xS/polydiphenylacetylene/a-C (as in FIG. 5)--A
first or lower conductive conductor is deposited on an upper
surface of an insulating layer. The first or lower conductor may be
formed from titanium, and is about 3000 .ANG.-8000 .ANG. thick,
with 5000 .ANG. presently preferred. The passive layer is
Cu.sub.2-xS. The Cu.sub.2-xS passive layer is deposited on the
upper surface of the first or lower conductor. The copper layer is
about 100 .ANG.-300 .ANG. thick, with 150 .ANG. presently
preferred. This layer is deposited in a chamber with H.sub.2S gas
for 15 minutes at room temperature. Cu.sub.2-xS is produced by the
reaction between copper and H.sub.2S gas. The active layer is
polydiphenylacetylene, which may be deposited by way of CVD. A
polydiphenylacetylene film is formed on surface of Cu.sub.2-xS at
125.degree. C. from a diphenylacetylene monomer precursor. The
active layer is about 300 .ANG.-1000 .ANG. thick, with 500 .ANG.
presently preferred. The second conductor layer is amorphous carbon
which can be deposited on the upper surface of the
polydiphenylacetylene active layer, by magnetron co-sputtering. The
second conductor layer is about 1000 .ANG.-5000 .ANG. thick, with
3000 .ANG. presently preferred.
EXAMPLE 4
[0092] Ti/Ag.sub.2S/polydiphenylacetylene/a-C (as in FIG. 5)--The
memory cell was made using Ag.sub.2S as the passive layer, which is
deposited on the upper surface of the conductor layer. The passive
layer is about 50 .ANG.-300 .ANG. thick, with 100 .ANG. presently
preferred. The Ag.sub.2S passive layer may be deposited by way of
CVD or evaporation. The active layer is polydiphenylacetylene,
which may be deposited by way of CVD.
EXAMPLE 5
[0093] Ti/Li.sub.xWO.sub.3/poly(t-butyl)diphenylacetylene/Al or Ti
or a-C (as in FIG. 5)--The memory cell was made in the same manner
as Example 1 except that a Li.sub.xWO.sub.3 passive layer is
deposited on the upper surface of the first or lower conductor. The
Li.sub.xWO.sub.3 passive layer may be deposited with the following
process: The tungsten layer is deposited on the upper surface of
the first or lower conductor. The tungsten layer is about 100
.ANG.-300 .ANG. thick, with 150 .ANG. presently preferred. This
layer was deposited in a chamber with O.sub.2 gas for 20 minutes at
250.degree. C. After the reaction between tungsten and the oxygen
gas, WO.sub.3 is produced. The intercalation of lithium ions in
WO.sub.3 layer may be accomplished by means of a solution of
n-butyllithium in hexane. The passive layer is about 50 .ANG.-300
.ANG. thick, with 100 .ANG. presently preferred.
EXAMPLE 6
[0094] Ti/W/Cu.sub.xWO.sub.3/poly(t-butyl)diphenylacetylene/Al or
Ti or a-C (as in FIG. 7)--The memory cell was made using
Cu.sub.xWO.sub.3 as the passive layer. The Cu.sub.xWO.sub.3 passive
layer may be deposited with the following process: The tungsten
layer is deposited on upper surface of the first or lower
conductor, and is about 100 .ANG.-300 .ANG. thick, with 150 .ANG.
presently preferred. This layer was deposited in a chamber with
O.sub.2 gas for 20 minutes at 250.degree. C. WO.sub.3 is produced
by the reaction between the tungsten and oxygen. Next, CuI was
deposited on the WO.sub.3 layer from solution, by spin-coating.
After heating up to a 150.degree. C. temperature, Cu.sub.xWO.sub.3
is produced. Poly(t-butyl)diphenylacetylene serves as the active
layer.
EXAMPLE 7
[0095] Ti/W/H.sub.xWO.sub.3/polyaniline/Al or Ti or a-C or ITO (as
in FIG. 7)--A first or lower conductive conductor is deposited on
an upper surface of an insulating layer. The first or lower
conductor may be formed from titanium and is about 3000 .ANG.-8000
.ANG. thick, with 5000 .ANG. presently preferred. The WO.sub.3
passive layer may be deposited by the following process: The
tungsten layer is deposited on the upper surface of the first or
lower conductor, and is about 1000 .ANG.-300 .ANG. thick, with 150
.ANG. presently preferred. Next, the tungsten layer was deposited
in a chamber with O.sub.2 gas for 20 minutes at 250.degree. C. The
active layer is polyaniline, which may be deposited from solution
by spin-coating. The active layer is about 300 .ANG.-1000 .ANG.
thick, with 500 .ANG. presently preferred. The second conductor
layer is amorphous carbon, which can be deposited on the upper
surface of the polyaniline active layer by magnetron co-sputtering.
The second conductor layer is about 1000 .ANG.-5000 .ANG. thick,
with 3000 .ANG. presently preferred. Tungsten (W) serves as the
barrier layer.
EXAMPLE 8
[0096] Ti/polyaniline/Pd/polyaniline/a-C or Ti or ITO (as in FIG.
10)--A first or lower conductive conductor is deposited on an upper
surface of an insulating layer. The first or lower conductor may be
formed from titanium and is about 3000 .ANG.-8000 .ANG. thick, with
5000 .ANG. presently preferred. The lower active layer is
polyaniline, which may be deposited from solution by spin-coating
and is about 300 .ANG.-1000 .ANG. thick, with 500 .ANG. presently
preferred. The barrier layer is palladium, which may be deposited
by magnetron co-sputtering and is about 30 .ANG.-100 .ANG. thick
with 50 .ANG. presently preferred. The upper active layer is also
polyaniline with a preferred thickness of 500 .ANG.A. The second
conductor layer is amorphous carbon, which can be deposited on the
upper surface of the second polyaniline active layer by magnetron
co-sputtering. The second conductor layer is about 1000 .ANG.-5000
.ANG. thick, with 3000 .ANG. presently preferred.
EXAMPLE 9
[0097] Ti/Cu.sub.2-xS/SiO.sub.2+polydiphenylacetylene/a-C or ITO
(as in FIG. 5)--A first or lower conductive conductor is deposited
on an upper surface of an insulating layer. The first or lower
conductor may be formed from titanium and is about 3000 .ANG.-8000
.ANG. thick, with 5000 .ANG. presently preferred. A passive layer
is Cu.sub.2-xS. The Cu.sub.2-xS passive layer may be deposited by
CVD. The active layer is a composite containing porous silicon
oxide (SiO.sub.2) and polydiphenylacetylene. The active layer may
be deposited by using the following process: First, a film of
porous silicon oxide is deposited on the upper surface of passive
layer by way of CVD. Next, a film of polydiphenylacetylene is grown
in the pores of the silicon oxide from a diphenylacetylene monomer
precursor of at 125.degree. C. The active layer is about 300
.ANG.-1000 .ANG. thick, with 500 .ANG. presently preferred. The
second conductor layer is amorphous carbon, which can be deposited
on upper surface of active layer by magnetron co-sputtering. The
second conductor layer is about 1000 .ANG.-5000 .ANG. thick, with
3000 .ANG. presently preferred.
EXAMPLE 10
[0098] Ti/Cu.sub.2-xS/porous
ferroelectric+polydiphenylacetylene/a-C (as in FIG. 5)--The memory
cell was made in the same manner as Example 9 except that active
layer is composite of polydiphenylacetylene and porous
(Ba,Sr)TiO.sub.3 which can deposited by way of CVD. Cu.sub.2-xS
serves as the passive layer.
EXAMPLE 11
[0099] Ti/Cu.sub.2-xS/polydiphenylacetylene/polyphthalocyanine/a-C
(as in FIG. 6)--A first or lower conductive conductor is deposited
on an upper surface of an insulating layer. The first or lower
conductor may be formed from titanium and is about 3000 .ANG.-8000
.ANG. thick, with 5000 .ANG. presently preferred. The lower active
layer is polydiphenylacetylene, which may be deposited by CVD. A
polydiphenylacetylene film is formed on the surface of the
Cu.sub.2-xS passive layer at 125.degree. C. from a
diphenylacetylene monomer precursor. The upper active layer is
about 300 .ANG.-1000 .ANG. thick, with 500 .ANG. presently
preferred. The second active layer is polyphthalocyanine, having a
preferred thickness of 150 .ANG.. Polyphthalocyanine films are
formed on surface of the polydiphenylacetylene at 125.degree. C.
from a tetracyanobenzene monomer precursor. The second conductor
layer is amorphous carbon, which can be deposited on upper surface
of second polyphthalocyanine active layer by magnetron
co-sputtering. The second conductor layer is about 1000 .ANG.-5000
.ANG. thick, with 3000 .ANG. presently preferred.
EXAMPLE 12
[0100] Ti/Cu.sub.2-xS/polyphthalocyanine/a-C (as in FIG. 5)--The
memory cell was made using polyphthalocyanine as the active layer,
which may be deposited by CVD. A polyphthalocyanine film may be
formed on the surface of the Cu.sub.2-xS passive layer at
125.degree. C., from a monomer of tetracyanobenzene. The active
layer is about 500 .ANG.-3000 .ANG. thick, with 700 .ANG. presently
preferred. The second conductor layer is amorphous carbon, which
can be deposited on the upper surface of the active layer by
magnetron co-sputtering. The second conductor layer is about 1000
.ANG.-5000 .ANG. thick, with 3000 .ANG. presently preferred.
EXAMPLE 13
[0101] Ti/W/H.sub.xWO.sub.3/SiO.sub.2+polyaniline/Al or Ti or a-C
or ITO (as in FIG. 7)--This cell was fabricated in a similar manner
as Example 7, except that the active layer is a composite of
containing porous silicon oxide (SiO.sub.2) and polyaniline.
EXAMPLE 14
[0102] Ti/W/H.sub.xPd/SiO.sub.2+polyaniline/Al or Ti or a-C or ITO
(as in FIG. 7)--This cell was fabricated in a similar manner as
Example 13, except that the passive layer is palladium, which is
deposited by way of CVD or evaporation.
EXAMPLE 15
[0103] Ti/Cu.sub.2-xS/Cu.sub.2O+polydiphenylacetylene/a-C or ITO
(as in FIG. 5)--This cell was fabricated in a similar manner as
Example 9, except that the active layer is a composite of
containing porous copper oxide (Cu.sub.2O) and
polydiphenylacetylene.
EXAMPLE 16
[0104] Ti/W/H.sub.xWO.sub.3/Porous ferroelectric+polyaniline/Al or
Ti or a-C or ITO (as in FIG. 7)--This cell was fabricated in a
similar manner as Example 13, except that the active layer is a
composite of containing polyaniline and porous (Ba,Sr)TiO.sub.3
which can deposited by way of CVD.
EXAMPLE 17
[0105] Ti/SiO.sub.2+polyaniline/Pd/SiO.sub.2+polyaniline/a-C or TI
or ITO (as in FIG. 11)--This cell was fabricated in a similar
manner as Example 8, except that each active layer is a composite
containing porous silicon oxide (SiO.sub.2) and polyaniline. The
active layer is about 50 .ANG.-500 .ANG. thick, with 100 .ANG.
presently preferred.
EXAMPLE 18
[0106]
Ti/Li.sub.xWO.sub.3/poly(ethylenedioxythiophene)+poly(styrene
sulfonic acid)/Al or Ti or a-C or ITO (as in FIG. 7). This cell was
fabricated in a similar manner as Example 5, except that each
active layer is a composite containing poly(ethylenedioxythiophene)
and poly(styrene sulfonic acid).
[0107] The above-described illustrative, but non-limitative
examples of memory devices or cells fabricated according to the
inventive concept and methodology reflect the extreme flexibility
and versatility with regard to device structures and materials
selection afforded by the present invention. Inasmuch as the read,
write, and erase characteristics of the inventive devices are
readily amenable to variation by means of appropriate selection of
materials and layer thicknesses, the inventive devices are well
suited for use in a variety of applications currently employing
conventional semiconductor-based memory devices. Moreover, the
inventive memory devices are readily fabricated in cost-effective
manner utilizing conventional manufacturing technologies.
[0108] In the previous description, numerous specific details are
set forth, such as specific materials, structures, reactants,
processes, etc., in order to provide a better understanding of the
present invention. However, the present invention can be practiced
without resorting to the details specifically set forth. In other
instances, well-known processing materials, structures, and
techniques have not been described in detail in order not to
unnecessarily obscure the present invention.
[0109] Only the preferred embodiments of the present invention and
but a few examples of its versatility are shown and described in
the present invention. It is to be understood that the present
invention is capable of use in various other embodiments and is
susceptible of changes and/or modifications within the scope of the
inventive concept as expressed herein.
* * * * *