U.S. patent application number 10/378141 was filed with the patent office on 2003-08-07 for a method of forming a high reliability interposer for low cost high reliability applications.
Invention is credited to Fan, Zhineng, Le, Ai D., Li, Che-Yu.
Application Number | 20030146017 10/378141 |
Document ID | / |
Family ID | 26921665 |
Filed Date | 2003-08-07 |
United States Patent
Application |
20030146017 |
Kind Code |
A1 |
Fan, Zhineng ; et
al. |
August 7, 2003 |
A Method of Forming A HiGH RELIABILITY INTERPOSER FOR LOW COST HIGH
RELIABILITY APPLICATIONS
Abstract
The present invention features an interposer that provides a
high reliability interface between an LGA connector and a
motherboard. The novel interposer overcomes the limitations of
prior art interposers by including a stepped spacer for each solder
interconnection which prevents the relaxation of mechanical contact
force while ensuring the integrity of each solder interconnection.
The interposer provides noble metal plated contact pads on a first
surface to receive the contact members of an LGA connector, and
contact pads for BGA solder connections for attachment to a
motherboard. A description of the processes to manufacture the
interposer is also disclosed.
Inventors: |
Fan, Zhineng; (Santa Clara,
CA) ; Le, Ai D.; (Sunnyvale, CA) ; Li,
Che-Yu; (Ithaca, NY) |
Correspondence
Address: |
Mark Levy
SALZMAN & LEVY
Ste. 902
19 Chenango St.
Binghamton
NY
13901
US
|
Family ID: |
26921665 |
Appl. No.: |
10/378141 |
Filed: |
March 4, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10378141 |
Mar 4, 2003 |
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09866434 |
May 29, 2001 |
|
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60227689 |
Aug 24, 2000 |
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Current U.S.
Class: |
174/138G ;
257/E23.067 |
Current CPC
Class: |
H05K 7/1061 20130101;
H05K 1/112 20130101; H05K 3/325 20130101; H01R 12/7082 20130101;
H05K 2201/0314 20130101; H01L 2924/0002 20130101; H05K 2201/09845
20130101; H05K 2201/10378 20130101; H05K 2201/0394 20130101; H01L
23/49827 20130101; H05K 3/3436 20130101; H01L 2924/0002 20130101;
H01L 2924/00 20130101 |
Class at
Publication: |
174/138.00G |
International
Class: |
H01B 017/26 |
Claims
What is claimed is:
1. A low cost, high reliability interposer for use in electronic
packages, comprising: a) at least one dielectric layer having one
major surface and at least one edge; b) a plurality of conductive
pads, each having a first and second surface, spaced apart on said
major surface of said at least one dielectric layer, said first
surface of said conductive pads being plated with at least one
layer of metal, and at least a portion of said second surface of
said conductive pads being readily adaptable for connection to a
conductive member; c) a plurality of openings with a non-uniform
cross section, each one corresponding to and aligned with one of
said conductive pads; and d) a plurality of conductive members,
each one located within one of said openings and in electrical
contact with said portion of said second surface of said conductive
pads.
2. The interposer as recited in claim 1, wherein said at least one
dielectric layer comprises an insulative material.
3. The interposer as recited in claim 2, wherein said insulative
material is polyimide.
4. The interposer as recited in claim 2, wherein said insulative
material is a liquid crystal polymer.
5. The interposer as recited in claim 2, wherein said insulative
material is epoxy-glass-based.
6. The interposer as recited in claim 2, wherein said insulative
material has a coefficient of thermal expansion (CTE) that
substantially matches the CTE of the material to which it is to be
attached.
7. The interposer as recited in claim 1, wherein said conductive
pads comprise copper.
8. The interposer as recited in claim 1, wherein said first surface
of said conductive pads being plated with at least one layer of
metal is plated with nickel.
9. The interposer as recited in claim 8, wherein said first surface
of said conductive pads being plated with at least one layer of
metal is also plated with gold.
10. The interposer as recited in claim 1, wherein said plurality of
openings comprises a stepped cross section.
11. The interposer as recited in claim 1, wherein said plurality of
openings comprises a tapered cross section.
12. The interposer as recited in claim 1, wherein said conductive
members comprise solder.
13. The interposer as recited in claim 1, wherein said conductive
members are comprised of conductive paste.
14. The interposer as recited in claim 13, wherein said conductive
paste comprises solder paste.
15. The interposer as recited in claim 1, further comprises
alignment means to align said carrier to a structure adapted to
mate therewith.
16. The interposer as recited in claim 1, wherein said interposer
may be attached to a structure adapted to mate therewith by a
reflow process.
17. The interposer as recited in claim 16, wherein said reflow
process of said interposer to said structure is performed under
uniform pressure.
18. A method of forming a low cost, high reliability interposer for
use in electronic packages, said method comprising: a) forming a
first substructure comprising at least one first dielectric layer,
at least one metal layer, and at least one first opening abutting
said at least one metal layer; b) forming a second substructure
comprising at least one second dielectric layer and at least one
second opening; c) providing an adhesive layer intermediate said
first and second substructures; and d) aligning and laminating said
first and second substructures and said adhesive layer, at least
one of said first openings being aligned with at least one of said
second openings, thereby exposing a portion of said at least one
metal layer.
19. The method according to claim 18, wherein said step (a) forming
a first substructure comprises the substeps of: i) providing said
at least one first dielectric layer comprising first and second
sides; ii) forming said at least one first opening in said at least
one first dielectric layer; iii) providing an adhesive layer to
bond said at least one first dielectric layer to said at least one
metal layer; iv) laminating said adhesive layer and said at least
one metal layer to one side of said at least one first dielectric
layer; and v) masking, exposing and etching said at least one metal
layer as required to create predetermined metallic features.
20. The method according to claim 19, wherein said step (b) forming
a second substructure comprises the substeps of: i) providing said
at least one second dielectric layer; and ii) forming said at least
one second opening in said at least one second dielectric
layer.
21. The method according to claim 18, the steps further comprising:
e) introducing conductive material into said aligned openings and
in electrical contact with said exposed portion of said at least
one metal layer.
22. The method according to claim 21, wherein said conductive
material is solder paste.
23. The method according to claim 22, the steps further comprising
reflowing said solder paste.
24. The method according to claim 18, wherein the diameter of said
at least one second opening is equal to or greater the diameter of
said at least one first opening.
25. The method according to claim 19, wherein said at least one
first dielectric layer comprises an insulative material.
26. The method according to claim 25, wherein said insulative
material is epoxy-glass-based.
27. The method according to claim 26, wherein said insulative
material comprises FR4.
28. The method according to claim 20, wherein said at least one
second dielectric layer comprises an insulative material.
29. The method according to claim 28, wherein said insulative
material is epoxy-glass-based.
30. The method according to claim 29, wherein said insulative
material comprises FR4.
31. The method according to claim 18, wherein said openings are
provided in said first and said second substructures by a process
selected from the group consisting essentially of ablation,
etching, routing, drilling, and punching.
32. The method according to claim 19, wherein said at least one
metal layer comprises copper.
33. The method according to claim 19, wherein said at least one of
said predetermined metallic features comprises a contact pad.
34. The method according to claim 18, wherein said laminating
occurs at a temperature of approximately 185 degrees F. and a
pressure of approximately 20 pounds per square inch (PSI).
Description
RELATED PATENT APPLICATIONS
[0001] This application is a divisional application of Ser. No.
09/866,434, filed May 29, 2001. This application is also related to
copending U.S. patent application Ser. No. 09/457,776, filed Dec.
9, 1999 and copending U.S. patent application Ser. No. 09/645,860,
filed Aug. 24, 2000, both of which are hereby incorporated by
reference.
FIELD OF THE INVENTION
[0002] The present invention relates to electronic packaging
structures such as printed circuit boards, circuit modules, or the
like and, more particularly, to those structures requiring special
plating processes such as gold plating for electrical contact.
BACKGROUND OF THE INVENTION
[0003] The current trend in the design of high speed electronic
systems is to provide both high density and highly reliable
interconnections between various circuit devices, which form
important parts of these systems. The system may be a computer, a
telecommunications network device, a handheld "personal digital
assistant", medical equipment, or any other electronic equipment.
High reliability for such connections is essential due to potential
end product failure, should vital misconnections of these devices
occur. Further, to assure effective repair, upgrade, and/or
replacement of various system components (i.e., connectors, cards,
chips, boards, modules, etc.), it is also highly desirable that
such connections be separable and reconnectable in the field within
the final product. Also, with financial pressures on manufacturers
to be cost competitive, is also important that high-dollar-value
assemblies be reworkable to maximize yields and minimize the
dollar-value of material to be scrapped.
[0004] Historically, connectors on computer motherboards used for
allowing field-separable interconnection of semiconductor devices,
such as microprocessors and memory modules, were primarily
pin-grid-array (PGA) or spring loaded edge connector technology.
Such connector technologies allow field upgrade or replacement of
defective devices.
[0005] But as system density, input/output (I/O) array size and
performance have increased so dramatically, so have the stringent
specifications for interconnections. These demanding requirements,
especially when coupled with the requirement for
field-separability, have led to a wide variety of possible
connector solutions, the majority of them requiring that mating
pads on the motherboard be plated with a precious metal to ensure a
reliable and repeatable electrical contact. This additional
requirement adds cost to the motherboard so that such practice is
not widely implemented.
[0006] A land grid array (LGA) is an example of such a connection
in which the two primarily parallel circuit elements are connected.
Each element has a plurality of contact points or pads, arranged in
a linear or two-dimensional array. An array of interconnection
elements, known as an interposer, is placed between the two arrays
and provides the electrical connection between the contact points
or pads. While LGA interposers described in the prior art are
implemented in many different ways, the implementations of most
interest are those described in the referenced copending U.S.
patent applications.
[0007] Contact pads on motherboards commonly comprise copper and
have a barrier layer of nickel followed by a thin (e.g., 0.001
inch) layer of gold. This plating combination works well for ball
grid array (BGA) solder interconnections. It does not work as well,
however, for LGA connectors, where a thicker layer of gold is
required to ensure a reliable interconnection. Since a thicker gold
layer is more costly than a thinner layer, motherboard
manufacturers are reluctant to implement such a change.
[0008] One solution is proposed in the IBM Technical Disclosure
Bulletin, Volume 37, Number 02A, pp. 277 and 278, published in
February 1994. It describes an interposer that unfortunately falls
short in meeting the requirements of present-day systems. This
interposer is proposed to provide an array of electrical contact
pads on a first surface for connection to an LGA connector, and on
a second surface for BGA solder attachment to a motherboard.
However, during service the solder interconnections will creep,
thereby relaxing the contact force on individual contact members to
the point that the LGA connector loses electrical contact.
[0009] A solution to this shortcoming is to provide a spacer of
sufficient height to ensure that contact force is maintained at a
relatively high level to ensure reliable connections but not so
high as to prevent good BGA solder interconnections for all
contacts. The concern is that some of the solder interconnections
will not make electrical contact due to the non-planarity of the
mating surfaces.
[0010] It is believed that a high reliability interposer that
reduces the cost of a motherboard, while solving the solder creep
problem discussed above, constitutes a significant advancement in
the art.
[0011] It is, therefore, an object of the invention to enhance the
electrical interconnection art.
[0012] It is another object of the invention to provide an
interposer for high reliability that reduces the cost of a
motherboard.
[0013] It is an additional object of the invention to provide an
interposer that ensures the reliability of LGA connectors
especially at high temperatures.
SUMMARY OF THE INVENTION
[0014] In accordance with the present invention, there is provided
an interposer that functions as a high reliability interface
between an LGA connector and a motherboard. The novel interposer
overcomes the limitations of prior art interposers by including a
stepped spacer for each solder interconnection which prevents the
relaxation of mechanical contact force while ensuring the integrity
of each solder interconnection. The interposer provides noble metal
plated contact pads on a first surface to receive the contact
members of an LGA connector, and contact pads for BGA solder
connections for attachment to a motherboard. A description of the
processes to manufacture the interposer is also disclosed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] A complete understanding of the present invention may be
obtained by reference to the accompanying drawings, when taken in
conjunction with the detailed description thereof and in which:
[0016] FIG. 1 is a partial perspective view of an interposer in
accordance with the prior art;
[0017] FIG. 2 is a side view, in section and on an enlarged scale,
of a prior art interposer shown in FIG. 1, the interposer being
positioned for attachment to a circuit member and aligned with a
connector and another circuit member for eventually providing
interconnection therebetween;
[0018] FIGS. 3a and 3b are an enlarged side view of the interposer
of FIG. 1 before and with, respectively, the effects of creep of
the solder connections;
[0019] FIG. 4 is a partial perspective view of an electrical
connector in accordance with one embodiment of the present
invention;
[0020] FIG. 5 is a side view, in section and on an enlarged scale,
of the connector shown in FIG. 4; and
[0021] FIGS. 6a and 6b are an enlarged side view of the interposer
of FIG. 4 before and with, respectively, the effects of creep of
the solder connections.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0022] Generally speaking, the present invention features an
interposer that provides a high reliability interface between an
LGA connector and a motherboard. The novel interposer overcomes the
limitations of prior art interposers by including a stepped spacer
for each solder interconnection which prevents the relaxation of
mechanical contact force while ensuring the integrity of each
solder interconnection. The interposer provides noble metal plated
contact pads on a first surface to receive the contact members of
an LGA connector, and contact pads for BGA solder connections for
attachment to a motherboard. Improved manufacturability and
reliability are achieved with this invention.
[0023] Referring first to FIGS. 1 and 2, there are shown
perspective and side views, respectively, of an interposer 40 of
the prior art for providing a reworkable plurality of electrical
contact pads 46 for an electrical circuit member 34. Electrical
contact pads 46 preferably are plated with a noble metal such as
gold. When used in conjunction with a connector 10, a path for
electrically interconnecting a pair of electrical circuit members
24 and 34 is provided. Examples of circuit members suitable for
interconnection through interposer 40 include printed circuit
boards, circuit modules, etc. The term "printed circuit board" is
meant to include but not be limited to a multilayered circuit
structure including one or more conductive (i.e., signal, power
and/or ground) layers therein. Such printed circuit boards, also
known as printed wiring boards, are well known in the art and
further description is not believed necessary. The term "circuit
module" is meant to include a substrate or like member having
various electrical components (e.g., semiconductor chips,
conductive circuitry, conductive pins, etc.), which may form part
thereof. Such modules are also well known in the art and further
description is not believed necessary.
[0024] Interposer 40 includes a dielectric layer 42 having a
plurality of internal apertures or openings 44, each one
corresponding to and being aligned with a conductive pad 46. In one
example, dielectric layer 42 is composed of a material such Kapton
(a trademark of E. I. DuPont deNemours & Co., Wilmington, Del.)
or Upilex (a trademark of Ube Industries, Ltd., Japan) and is
0.010-inch thick. The openings 44 are typically cylindrical in
shape and are formed by a Kapton-etch process. Conductive pads 46
are composed of copper and covered by a plating layer 48, which in
this example is composed of a 200 micro-inch thick layer of nickel
covered by a 50 micro-inch thick layer of gold.
[0025] After alignment by methods well known in the art (e.g., pin
and hole, optical alignment, etc.), interposer 40 can be
electrically attached to flat conductive pads (e.g., copper
terminals) 38 located on an upper surface of electrical circuit
member 34 by a process appropriate for the particular composition
of the conductive members 50. For example, if the conductive
members 50 are solder, infrared or hot air reflow can be used to
attach the interposer 40 to the pads 38.
[0026] Referring now to FIGS. 3a and 3b, there is shown an enlarged
side view of interposer 40 of the prior art before and with,
respectively, the effects of creep of the solder connections.
Conductive members 50 (FIG. 3a) (e.g. solder connections) are
located in corresponding openings 44 and are in electrical contact
with corresponding conductive pads 46.
[0027] As stated hereinabove, because of the combination of
increased temperature of today's hotter-running semiconductors
along with the clamping forces of LGA connectors, conductive
members 52 (FIG. 3b) can flatten out due to creep, thereby relaxing
the contact force necessary to maintain electrical contact and
producing connector failures.
[0028] After alignment by methods well known in the art (e.g., pin
and hole, optical alignment, etc.), interposer 40 can be
electrically attached to flat conductive pads (e.g., copper
terminals) 38 located on an upper surface of electrical circuit
member 34 by a process appropriate for the particular composition
of the conductive members 50. For example, if the conductive
members 50 are solder, infrared or hot air reflow can be used to
attach the interposer 40 to the pads 38.
[0029] Referring now to FIGS. 4, and 5, there are shown perspective
and side views, respectively, of an interposer 60 of the present
invention for providing a reworkable plurality of electrical
contact pads 66 for an electrical circuit member 34. Electrical
contact pads 66 preferably are plated with a noble metal such as
gold. When used in conjunction with a connector 10, a path for
electrically interconnecting a pair of electrical circuit members
24 and 34 is provided. Examples of circuit members suitable for
interconnection through interposer 60 include printed circuit
boards, circuit modules, etc.
[0030] Interposer 60 includes a dielectric layer 62 having a
plurality of internal stepped apertures or openings 64, each one
corresponding to and aligned with a conductive pad 66. The stepped
aperture 64 provides the spacer of height (step height) necessary
to ensure the maintenance of the force on the connector contacts.
In one example, dielectric layer 62 is composed of KAPTON or UPILEX
material and is 0.010-inch thick. Other examples of suitable
material for dielectric layer 62 are liquid crystal polymer (LCP)
and epoxy-glass-based materials (i.e., FR4). Dielectric layer 62
has a coefficient of thermal expansion (CTE) that substantially
matches the CTE of the surrounding structures. Dielectric layer 62
may also be comprised of more than one layer of material to allow
the implementation of alternate methods of manufacture.
[0031] Conductive members 70 (e.g., solder connections) are
intended to be located in corresponding stepped openings 64 and are
in electrical contact with corresponding conductive pads 66. In one
example, the diameter of conductive member 70 is 0.026 inch at its
root and the height is 0.030 inch prior to attaching to the
motherboard 34. Conductive pads 66 are composed of copper and
covered by plating layer 68, which in this example is composed of a
200 micro-inch thick layer of nickel covered by a 50 micro-inch
thick layer of gold for good electrical contact. In one example,
the center-to-center distance of conductive pads 66 is 0.050 inch,
but could be reduced to about 0.040 inch or smaller if
required.
[0032] Referring now to FIGS. 6a and 6b, there is shown an enlarged
side view of interposer 60 of the present invention prior to and
including, respectively, the effects of creep of the solder
connections. The novel stepped openings 64 are again typically
cylindrical in shape. In one example, the upper portion 72 of
opening 64 that abuts conductive pad 66 is the same diameter as
prior art opening 44 (FIG. 2), while the lower portion 74 is larger
in diameter and acts as a reservoir to better contain the volume of
conductive material of each conductive member 76 (FIG. 6b). The
added height of the spacer ensures that the force on the connector
contacts is maintained but is not so excessive as to undermine the
integrity of the solder connections due to the non-planarity of the
circuit members 24 and 34 and the interposer 60. In one example,
the diameter of upper portion 72 of opening 64 is 0.026 inch and
the height is 0.010 inch, while the diameter of lower portion 74 is
0.035 inch and the height of the spacer is 0.010 inch.
[0033] While a stepped opening 64 has been chosen for purposes of
disclosure, it should be obvious that the principles taught by the
instant invention can be applied using openings of many different
shapes and sizes to accommodate specific design requirements.
[0034] Also, while the primary material for conductive members 70
and 76 has been chosen to be solder for purposes of disclosure, it
should be obvious that the principles taught by the instant
invention can be applied to other materials including conductive
adhesives.
[0035] After alignment by methods well known in the art (e.g., pin
and hole, optical alignment, etc.), interposer 60 can be
electrically attached to flat conductive pads (e.g., copper
terminals) 38 located on an upper surface of electrical circuit
member 34 by a process appropriate for the particular material of
conductive members 70. For example if the conductive members are
solder, infrared or hot air reflow would be possible options. A
pressure may be applied during reflow so that the shape of
conductive members 76 will be as shown in FIG. 6b.
[0036] It is possible that some conductive member/pad combinations
may be used for reasons other than for electrical interconnection
(e.g., mechanical or thermal benefits), which are well within the
scope of the invention. Furthermore it should be obvious to those
skilled in the art that the specific shape of conductive members 70
need not be truly spherical, and that many other shapes, including
but not limited to columns, may prove advantageous depending on
performance requirements, and assembly equipment and processes
available.
[0037] It should be clearly seen that interposer 60, once
conductive members 70 are properly attached to conductive pads 38
of electrical circuit member 34, provides an electrical path
interconnecting the circuitry of electrical circuit member 34
through opposing ends 20 and 18 of each contact member 16 of
connector 10 to conductive pads 28. Pads 28 are located on the
bottom, external surface of electrical circuit member 24, thereby
completing the path to electrical circuit member 24, which may
include a substrate 26 having a plurality of semiconductor elements
32 thereon. Conductive pads 28 and 38 understandably may provide
signal, power or ground connections, depending on the operational
requirements of the respective circuit member.
[0038] Each resilient contact member 16 of connector 10 is thus
compressed during engagement to form the appropriate
interconnection between corresponding pairs of conductive pads 28
and 66. This may be accomplished by many different retentive
methods including clamping means as well as many other methods well
known to those skilled in the art.
[0039] Although connector 10 may be of the type shown in the prior
art, it is preferably of a construction and composition as taught
in the referenced copending U.S. patent applications.
[0040] Alignment of the circuit members 24 and 34 relative to
interim connector 10 may be provided utilizing a pair of protruding
pins 30, which extends from one of the circuit members (e.g.,
module 24). These pins are aligned with and positioned within
corresponding openings 22 within carrier member 12 and openings 36
(shown in phantom lines) within the other circuit member 34. It
should be understood that other means of alignment are readily
possible, including the provision of pins extending from opposing
surfaces of carrier member 12 for inversion within corresponding
openings within the respective circuit members. To adjust for
tolerancing, one of the openings 22 within connector 10 may be of
an elongated configuration, forming a slot, for example.
[0041] Interposer 60 may be constructed in many different ways. For
the example where the dielectric layer is composed of two layers of
material, such as polyimide or FR4, a preferred method is to start
with a first dielectric layer and create the necessary openings in
it. The first dielectric layer is laminated to a copper layer. The
copper layer is masked off to allow precious metal plating of the
areas that will become the conductive pads and other features such
as alignment fiducials. Once the mask is removed, the excess copper
is etched away by appropriate etching means. Openings are created
in a second dielectric layer. A layer of adhesive is placed between
and aligned with the two dielectric layers for lamination of the
structure. In one case a temperature of 185 degrees F. and a
pressure of 20 pounds per square inch (PSI) were used. If all
layers are properly aligned, the stepped openings are formed and
are in alignment with contact pads. Once this operation is
complete, the overall structure is turned over and conductive
material such as solder paste is screened on into the appropriate
openings. The structure is sent through a reflow oven to form the
conductive members. The interposer is then ready for attachment to
an appropriate electronic packaging structure, such as a printed
circuit board.
[0042] For the example where the dielectric layer is composed of a
single layer of material, such as polyimide, FR4, or LCP, a
preferred method is to start with the dielectric layer and create
the necessary openings in it. The stepped openings may be created
in many different ways including a stepped drill, standard drilling
operations, routing, etching, or other methods well known in the
art. The dielectric layer is laminated to a copper layer. The
copper layer is masked off to allow precious metal plating of the
areas that will become the conductive pads and other features such
as alignment fiducials. Once the mask is removed, the excess copper
is etched away by appropriate etching means. If all layers are
properly aligned, the stepped openings are formed and are in
alignment with contact pads. Once this operation is complete, the
overall structure is turned over and conductive material such as
solder paste is screened on into the appropriate openings. The
structure is sent through a reflow oven to form the conductive
members. The interposer is then ready for attachment to an
appropriate electronic packaging structure, such as a printed
circuit board.
[0043] Since other modifications and changes varied to fit
particular operating requirements and environments will be apparent
to those skilled in the art, this invention is not considered
limited to the examples chosen for purposes of this disclosure, and
covers all changes and modifications which does not constitute
departures from the true spirit and scope of this invention.
[0044] Having thus described the invention, what is desired to be
protected by Letters Patent is presented in the subsequently
appended claims.
* * * * *