U.S. patent application number 09/982575 was filed with the patent office on 2003-07-24 for copper reflow process.
Invention is credited to Gardner, Donald S..
Application Number | 20030139033 09/982575 |
Document ID | / |
Family ID | 22639352 |
Filed Date | 2003-07-24 |
United States Patent
Application |
20030139033 |
Kind Code |
A1 |
Gardner, Donald S. |
July 24, 2003 |
COPPER REFLOW PROCESS
Abstract
A manufacturable method for forming a highly reliable electrical
interconnection. An electrical interconnection pattern is first
formed in a dielectric layer on a semiconductor substrate as
recessed regions in the dielectric layer. A conductive layer
primarily comprising copper is thereafter deposited over the
surface and in the recessed regions of the dielectric layer. The
conductive layer is then reflowed to fill the recessed regions of
the dielectric layer with substantially no void formation. This
reflow process may also be used to improve the step coverage of any
such copper layer deposited over the surface of a substrate to be
used in conjunction with alternate techniques for forming
electrical interconnections including photoresist patterning and
etch.
Inventors: |
Gardner, Donald S.;
(Mountain View, CA) |
Correspondence
Address: |
David J. Kaplan
BLAKELY, SOFOLOFF, TAYLOR & ZAFMAN
Seventh Floor
12400 Wilshire Boulevard
Los Angeles
CA
90025-1026
US
|
Family ID: |
22639352 |
Appl. No.: |
09/982575 |
Filed: |
October 17, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09982575 |
Oct 17, 2001 |
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08175200 |
Dec 28, 1993 |
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6475903 |
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Current U.S.
Class: |
438/632 ;
257/E21.588 |
Current CPC
Class: |
H01L 21/76882
20130101 |
Class at
Publication: |
438/632 |
International
Class: |
H01L 021/4763 |
Claims
It is claimed:
1. A method of forming an electrical conductor over a semiconductor
substrate, said method comprising the steps of: (a) forming a
recessed region in a first layer above said semiconductor
substrate; (b) forming a second layer above said first layer such
that at least a portion of said second layer is formed in said
recessed region, said second layer substantially comprising copper;
and (c) reflowing said second layer.
2. The method of claim 1 wherein at least a portion of said second
layer is deposited by a method selected from the group consisting
of sputtering, CVD, and evaporation.
3. The method of claim 1 wherein said second layer is formed and
said reflow is performed under high vacuum to extra high vacuum
conditions within the same vacuum system.
4. The method of claim 2 wherein said second layer is formed and
said reflow is performed under high vacuum to extra high vacuum
conditions within the same vacuum system.
5. The method of claim 1 further comprising the step of forming a
barrier layer between at least a portion of said first layer and at
least a portion of said second layer.
6. The method of claim 5 wherein said barrier layer comprises a
material selected from the group consisting essentially of oxide,
nitride, silicon oxynitride, silicon carbide, Mo, MoN, Ta, TaN, W,
WN, V, VN, Nb, NbN, Ti, TiN, and any combination thereof.
7. The method of claim 1 wherein said reflow is performed at a
temperature in the range of approximately 200.degree.
C.-800.degree. C.
8. The method of claim 2 wherein said reflow is performed at a
temperature in the range of approximately 200.degree.
C.-800.degree. C.
9. The method of claim 1 further comprising the step of etching at
least a portion of said second layer which exists substantially
outside said recessed region such that said second layer becomes
substantially isolated within said recessed region.
10. The method of claim 1 wherein said second layer comprises a
material selected from the group consisting essentially of
substantially pure copper, a vanadium alloy of copper, a niobium
alloy of copper, a palladium alloy of copper, and any combination
thereof.
11. The method of claim 1 wherein said second layer comprises
substantially pure copper to which elements are added in an amount
of between approximately 0.01 to 2 atomic percent to form an alloy
thereof.
12. The method of claim 1 wherein said recessed region is formed by
a process including dry etching a dielectric region of said first
layer, said dielectric region comprising a material selected from
the group consisting essentially of oxide, nitride, silicon
oxynitride, BSG, PSG, BPSG, silicon carbide, polyimide and any
combination thereof.
13. A method of forming an electrical conductor over a
semiconductor substrate, said method comprising the steps of: (a)
forming a recessed region in a first layer over said semiconductor
substrate, said first layer comprising a dielectric material; (b)
sputtering a second layer above said first layer such that at least
a portion of said second layer is deposited in said recessed
region, said second layer substantially comprising copper; and (c)
reflowing said second layer by exposing said second layer to a
temperature in the range of approximately 200.degree.
C.-800.degree. C. under high vacuum to extra high vacuum
conditions.
14. The method of claim 13 further comprising the step of forming a
barrier layer between at least a portion of said first layer and at
least a portion of said second layer.
15. The method of claim 14 wherein said barrier layer comprises a
material selected from the group consisting essentially of oxide,
nitride, silicon oxynitride, silicon carbide, Mo, MoN, Ta. TaN. W,
WN, V, VN, Nb, NbN, Ti, TiN, and any combination thereof.
16. The method of claim 13 wherein said second layer is deposited
and said reflow is performed under high vacuum to extra high vacuum
conditions within the same vacuum system.
17. The method of claim 13 wherein said reflow is performed at a
temperature below approximately 500.degree. C.
18. The method of claim 13 further comprising the step of
chemically-mechanically etching at least a portion of said second
layer which exists substantially outside said recessed region such
that said second layer becomes substantially isolated within said
recessed region.
19. The method of claim 14 further comprising the step of
chemically-mechanically etching at least a portion of said second
layer which exists substantially outside said recessed region such
that said second layer becomes substantially isolated within said
recessed region.
20. The method of claim 15 further comprising the step of etching
at least a portion of said second layer which exists substantially
outside said recessed region such that said second layer becomes
substantially isolated within said recessed region.
21. A method of forming an electrical conductor over a
semiconductor substrate, said method comprising the steps of: (a)
forming a first layer over said semiconductor substrate, said first
layer substantially comprising copper; (b) reflowing said first
layer; (c) patterning said first layer; and (d) etching said first
layer.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to semiconductor processing,
and more particularly to a method of forming copper
interconnections in a semiconductor device.
BACKGROUND OF THE INVENTION
[0002] As the demand for cheaper, faster, lower power consuming
microprocessors increases, so must the device packing density of
the integrated circuit. Very large scale integration (VLSI)
techniques have continually evolved to meet the increasing demand.
All aspects of the integrated circuit must be scaled down to fully
minimize the device dimensions of the integrated circuit. In
addition to minimizing transistor dimensions, one must minimize the
dimensions of the electrical interconnections which integrate the
semiconductor devices, such as transistors, together on a microchip
in order to form a complete circuit.
[0003] Currently, aluminum alloys are the most commonly used
conductive materials for electrical interconnections in a VLSI
integrated circuit. Aluminum and its alloys have been fully
characterized for use as electrical interconnections and much
technology has been developed to aid in the formation of aluminum
interconnections. While aluminum has very attractive features for
use as an electrical interconnection, such as low electrical
resistivity and strong adhesion to silicon dioxide (SiO.sub.2), as
VLSI dimensions reach into the deep-submicron Ultra Large Scale
Integration (ULSI) regime, the deficiencies of aluminum and its
allows become limiting factors in achieving superior performance.
For example, as the width of electrical interconnections becomes
narrower, the resistance of aluminum becomes non-negligible and
begins to contribute significantly to the resistance-capacitance
(RC) time delay of the circuit. Additionally, with decreasing
dimensions, design rules become increasingly restricted by aluminum
interconnection reliability concerns such as electromigration,
stress-induced void formation, hillock suppression, and current
density limitations.
[0004] For these reasons, the microelectronics industry has
recently migrated towards the investigation of more robust, more
conductive metals for use in interconnection technology such as
Copper (Cu). Cu is approximately 40% lower in resistivity than Al
and is much more resistant to reliability problems such as
electromigration. One of the main reasons why the use of Cu and its
alloys for interconnection applications has not been more
widespread is because a manufacturable dry-etch process has not yet
been demonstrated that can pattern Cu-based materials using
standard photolithographic techniques. To implement the use of Cu
as a microelectronic interconnection material, it has therefore
become necessary to develop alternate patterning techniques.
[0005] One technique is known as damascene. In damascene, a
dielectric layer is deposited onto a substrate, patterned, and
etched back such that the grooves, vias, or other recessed regions
etched into the dielectric layer represent the desired metal
interconnection pattern. A conductive material is then deposited
over the entire surface of the device, filling in the recessed
regions and blanketing the surface of the dielectric layer. Next,
the conductive material is etched back to a degree such that the
conductive material becomes electrically isolated within the
recessed regions etched out of the dielectric layer.
[0006] An inadequately filled recessed region in a damascene
process flow leads to the creation of a void or tunnel. Voids
significantly degrade semiconductor device yields thereby adding to
the total manufacturing cost. FIG. 1a shows a semiconductor
substrate 105 with dielectric layers 100 and 101 deposited on its
surface. A groove 102 has been created in dielectric layer 100.
FIG. 1b shows the semiconductor substrate of FIG. 1a after a
conductive layer 103 has been deposited on its surface. Note that
gap 104 has formed in the conductive layer 103.
[0007] As conductive material is deposited onto the substrate of
FIG. 1b, the conductive material may be deposited at a faster rate
on the top surface and along the walls nearer the top surface of
conductive layer 103 then at the bottom of gap 104. The reason for
this phenomenon is that as the walls of gap 104 close in, it
becomes increasingly more difficult for the conductive material to
travel to the bottom of the gap without "touching" and sticking to
the walls of gap 104. The amount of conductive material deposited
nearer the mouth of gap 104 is determined by how well the
conductive material sticks to the substrate upon contact with it.
If it sticks easily, as with sputter deposition, then less
conductive material will be deposited at the bottom of gap 104
compared to the amount of conductive material deposited nearer the
mouth of gap 104 thereby causing a bulging or cusping effect at the
mouth of gap 104 as can be seen in FIG. 1b. If the top surface of
the substrate is etched back at this point, gap 104 will remain
inside groove 102 leading to the problems described below as well
as limiting the current carrying capability of the electrical
interconnection. Therefore, it is necessary to continue depositing
conductive layer 103 in order to better fill groove 102 with
conductive material.
[0008] FIG. 1c shows the result of continued deposition of a
conductive material when the sticking coefficient is high. Note the
cusping of the walls at the mouth of gap 104. The result of this
cusping is that the bottom of the gap has been pinched-off from the
surface of the substrate. Thus, the gap has evolved into a tunnel
travelling along groove 102. Such a tunnel is known as a void. Gaps
and voids can cause significant problems in a semiconductor
manufacturing process and are considerable issues for sputtered and
evaporated films. One problem with gaps and voids is that they can
trap impurities which can harm the semiconductor device in
subsequent process steps. For instance. FIG. 1d shows the
semiconductor substrate of FIG. 1c after the surface of conductive
layer 103 has been etched back to isolate the portion of conductive
layer 103 residing within groove 102 of dielectric layer 100. The
isolated conductive layer 103 will become an electrical
interconnection of the device. Note that void 104 still exists
within the electrical interconnection 103. Even if the void hadn't
been created, an open gap would still exist within electrical
interconnection 103.
[0009] Assuming conductive layer 103 of FIG. 1c was etched back
using some sort of chemical etching process, the etchant chemicals
may become trapped within the gap or hollow void 104 and cause
additional etching or corrosion of electrical interconnection 103
even after the etchant has been removed from the surface of the
substrate. These trapped etchant chemicals may then contaminate the
semiconductor device which could degrade reliability. Trapped
etchant chemicals may also continue to etch the electrical
interconnection 103 resulting in the thinning of electrical
interconnection 103 or the creation of a electrical open, thereby
resulting in a failure. Interconnection thinning may lead to
reliability problems such as electromigration and current-carrying
limitations. Additionally, trapped contaminants may expand upon
subjecting the semiconductor substrate to subsequent high
temperature processing steps. Such expansion could cause
significant damage to adjoining surface features of the
semiconductor device. Finally, trapped contaminants may escape
during, for example, a subsequent process step thereby
contaminating all other semiconductor devices within the process
chamber.
[0010] Note that the potential for forming voids is greatly
increased by attempting to fill grooves of significantly varying
widths together on a single substrate at the same interconnection
level using deposition processes with relatively high sticking
coefficients. This is because these deposition processes are
typically optimized to fill a groove of a particular width. While
such optimization techniques may be suitably employed to fill
interconnections of this particular width on a semiconductor
substrate, the problem is that grooves of widths for which the
process has not been optimized run a much higher risk of void
formation. This makes interconnection technology dependent on
individual device layout. Such dependence degrades the
manufacturability of such processes.
[0011] It is currently more desirable to form copper
interconnections on a semiconductor substrate by Cu sputtering
rather than by CVD of Cu. One reason why Cu sputtering is more
desirable is that there is a significant cost associated with
performing CVD of Cu. Equipment necessary to form CVD Cu layers is
currently under development and not yet readily available for high
production manufacturing environments. Additionally, the materials
necessary to deposit CVD Cu layers are expensive, still under
investigation, and the films are not likely to be very pure.
Therefore, CVD of Cu is expensive and considerably adds to the
total manufacturing cost of a semiconductor device. Also, it is not
yet known if certain important alloys of Cu are capable of being
deposited using a CVD system. Furthermore, while some CVD
techniques which exhibit low sticking coefficients may be capable
of minimizing void formation, smooth continuous seams form along
the center of the CVD layers within the grooves. These seams may be
undesirable due to, for instance, their negative impact on the
grain size of the conductive layer and their susceptibility to
trapping impurities. Finally, CVD techniques which exhibit low
sticking coefficients also exhibit low deposition rates. Therefore,
in the interest of manufacturability, higher sticking coefficient
CVD processes are typically used to accelerate throughput time.
However, these higher sticking coefficient CVD processes exhibit
the same short-comings as the high sticking coefficient processes
discussed above.
[0012] Existing sputter deposition systems can easily and cheaply
deposit Cu layers and its alloys. However, sputter deposition
systems have exhibited significant limitations in their ability to
fill the recessed regions in damascene process flows as discussed
above. These limitations have precluded the applicability of
sputter deposition systems in a damascene process.
SUMMARY OF THE PRESENT INVENTION
[0013] A manufacturable method for forming a high performance,
highly reliable electrical interconnection for an advanced
semiconductor device is described. First, grooves are formed in a
dielectric layer on a semiconductor substrate. After a barrier
layer is formed on the surface of the dielectric layer, copper, or
an alloy thereof, is then sputtered over the entire surface of the
substrate such that open gaps are created in the copper layer
caused by the grooves in the underlying dielectric layer. Oxidation
of the copper layer is prevented by maintaining a vacuum during the
time between sputtering the copper layer and subjecting the copper
layer to a subsequent reflow process step. The reflow process
consists of exposing the copper layer to elevated temperatures
under high vacuum to extra high vacuum conditions. During the
reflow process, the grooves of the dielectric layer are
substantially filled with copper while gaps, voids, and seams are
substantially eliminated. The surface of the copper layer is then
chemically-mechanically polished back such that the copper remains
only in the grooves of the dielectric layer. These grooves
containing the copper then act as a layer of electrical
interconnections for the device.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] FIGS. 1a-d are illustrative of the prior art techniques
where:
[0015] FIG. 1a is an illustration of a cross-sectional view of a
semiconductor substrate after a recessed region has been
formed.
[0016] FIG. 1b is an illustration of a cross-sectional view of the
substrate of FIG. 1a after a conductive layer has been
deposited.
[0017] FIG. 1c is an illustration of a cross-sectional view of the
substrate of FIG. 1b after more conductive material has been
deposited.
[0018] FIG. 1d is an illustration of a cross-sectional view of the
substrate of FIG. 1c after the surface has been etched back.
[0019] FIGS. 2a-e are illustrative of an embodiment of the present
invention where:
[0020] FIG. 2a is an illustration of a cross-sectional view of a
semiconductor substrate.
[0021] FIG. 2b is an illustration of a cross-sectional view of the
substrate of FIG. 2a after a recessed region has been etched.
[0022] FIG. 2c is an illustration of a cross-sectional view of the
substrate of FIG. 2b after a conductive layer has been
deposited.
[0023] FIG. 2d is an illustration of a cross-sectional view of the
substrate of FIG. 2c after the conductive layer has been
reflowed.
[0024] FIG. 2e is an illustration of a cross-sectional view of the
substrate of FIG. 2d after the surface has been etched back.
[0025] FIG. 3a-e serve to further illustrate an embodiment of the
present invention where:
[0026] FIG. 3a is an illustration of a cross-sectional view of a
semiconductor substrate after a recessed region has been
formed.
[0027] FIG. 3b is an illustration of a cross-sectional view of the
substrate of FIG. 3a after a barrier layer has been deposited.
[0028] FIG. 3c is an illustration of a cross-sectional view of the
substrate of FIG. 3b after a conductive layer has been
deposited.
[0029] FIG. 3d is an illustration of a cross-sectional view of the
substrate of FIG. 3c after the conductive layer has been
reflowed.
[0030] FIG. 3e is an illustration of a cross-sectional view of the
substrate of FIG. 3d after the surface has been etched back.
DETAILED DESCRIPTION OF THE PRESENT INVENTION
[0031] A manufacturable method for forming a highly reliable,
electrical interconnection is described which is particularly well
suited for advanced VLSI and ULSI applications. In the following
description, numerous specific details such as layer thicknesses,
process sequences, times, temperatures, etc. are set forth in order
to provide a more thorough understanding of the present invention.
It will be obvious, however, to one skilled in the art, that the
present invention may be practiced without employing these specific
details. In other instances, well-known processes and processing
techniques have not been described in detail in order not to
unnecessarily obscure the present invention.
[0032] While diagrams representing a preferred embodiment of the
present invention are illustrated in FIGS. 2a-3e, these
illustrations are not intended to limit the invention. The specific
processes described herein are only meant to help clarify an
understanding of the present invention and to illustrate preferred
embodiments of how the present invention may be implemented in
order to form a preferred device. For the purposes of this
discussion, a semiconductor substrate is any substrate comprising
any material or materials used in the manufacture of a
semiconductor device. A substrate is a structure on which or to
which a processing step acts upon.
[0033] In a method consistent with the present invention, layer 205
of FIG. 2a is a semiconductor substrate which may include
semiconductor, dielectric, or conductive layers. Semiconductor
substrate 205 contains active devices which may be integrated by
the process of the present invention. Layer 201 of FIG. 2a is a
dielectric layer used to physically and electrically isolate the
subsequently deposited conductive layer 203 from the rest of the
semiconductor device. Layer 200 of FIG. 2a is another dielectric
layer which also serves to physically and electrically isolate the
subsequently deposited conductive layer 203 from the rest of the
semiconductor device. The electrical interconnection formed by the
process of the present invention may serve as, for instance, a
metal 1, metal 2, metal 3, or any other interconnection layer in a
multilevel interconnection device.
[0034] Examining FIG. 2a, dielectric layers 200 and 201 are formed
on the substrate 205. Dielectric layers 200 and 201 are typically
SiO.sub.2 (oxide), but may be silicon nitride (nitride), silicon
oxynitride, BSG, PSG, BPSG, silicon carbide, other organic
dielectrics such as polyimide, or any other dielectric material
which is compatible with a semiconductor manufacturing technology.
In an alternate embodiment of the present invention, dielectric
layers 200 and 201 may comprise a multilayer stack including
dielectric materials and, perhaps, other types of materials which
may exhibit semiconductive or even conductive properties. Also,
dielectric layer 200 may comprise the same material as dielectric
layer 201. In the latter case, dielectric layers 200 and 201 may be
formed as a single layer or multilayer stack onto semiconductor
substrate 205.
[0035] FIG. 2b shows the same region displayed in FIG. 2a after a
portion of dielectric layer 200 has been etched to form a recessed
region or groove 202 therein. Recessed region 202 may be only a
portion of a larger groove (running substantially perpendicular to
the page) in order to form a layer of electrical interconnections.
Groove 202 may be formed by any one of a plurality of well known
etch processes such as RIE, sputter etch, ion milling, or even wet
chemical etch. In one method, dielectric layer 201 is used as an
etch-stop for the dry etch of layer 200 to form groove 202. In
another method where dielectric layer 200 comprises the same
material as dielectric layer 201, a timed etch is appropriate. In
alternate embodiments of the present invention, FIG. 2b is not
formed as a result of etching groove 202 into layer 200 but rather
by selectively growing or depositing layer 200 about the groove
202. In an alternate embodiment of the present invention in which a
cross-level electrical shunt is to be formed, a recessed region may
be isolated to form a vertical via, plug, or contact, and the
region is recessed deep enough to make contact with an underlying
electrical interconnection layer. Via, plug, contact. electrical
interconnection layer, and any other structure with current
carrying capacity are herein generically termed electrically
conductive layers.
[0036] The width of groove 202 may be in the range of approximately
1.5 microns to well within the deep sub-micron regime of 0.25
microns and below. The aspect ratio of groove 202 (depth/width) may
be in the range of approximately 0.5 to four. In alternate
embodiments of the present invention, grooves of even higher aspect
ratios may be formed. Grooves with aspect ratios below 0.5 are
generally adequately filled by conventional deposition techniques
such as sputtering without the aid of the reflow process described
below, however, the reflow process additionally serves to improve
the step coverage and general film quality of these wide lines.
Since the reflow process does not substantially interfere with
these adequately filled wide grooves, the present invention is well
suited for simultaneously creating electrical interconnection
dimensions of vastly differing widths on a single substrate
surface. The depth of groove 202 (and hence the thickness of
dielectric layer 200) is approximately 500 nm. However, the depth
of groove 202 may be in the range of approximately 200 nm to 3000
nm. Where a recessed region needs to be very deep to accommodate,
for instance, a deep vertical via or contact, a recessed region may
be approximately 5000 nm. Typically, the walls of groove 202 are
substantially vertical to minimize lateral dimensions thereby
improving packing density.
[0037] FIG. 2c shows the same region displayed in FIG. 2b after a
conductive layer 203 has been deposited. The conductive layer 203
substantially comprises Cu as its primary element and may include
alloys thereof such as a vanadium alloy of Cu. a niobium alloy of
Cu, or a palladium alloy of Cu. In addition, conductive layer 203
may comprise other materials for use as, for example, barrier
layers (barrier layers are described below in more detail). In an
embodiment of the present invention in which conductive layer 203
comprises copper with an additive of vanadium, niobium, or
palladium, these additives comprise between approximately 0.01 and
2 atomic percent of the conductive material. Cu may be alloyed with
any number of dilute quantities of other elements. For example,
aluminum may be included in conductive layer 203 to prevent
corrosion of the layer. In order to reduce manufacturing costs
while improving semiconductor device quality, a preferred
embodiment of the present invention uses well known sputter
deposition processes to deposit the conductive layer 203. In
alternate embodiments of the present invention, CVD, evaporative,
or any combination of methods with substrate bias and/or with
techniques that ionize the atoms of conductive material may be used
to deposit at least a portion of the conductive layer 203.
[0038] Note gap 204 formed in conductive layer 203. In a preferred
embodiment of the present invention, conductive layer 203 is
deposited over the entire substrate to a thickness such that gap
204 remains open. For example, in an embodiment in which groove 204
is approximately 500 nm deep, conductive layer 203 may be deposited
to a thickness of approximately 1.6 microns without prematurely
closing gap 204 and forming a void. As discussed above, deposition
to a thickness beyond a certain point will cause the cusps at the
upper walls of the gap to meet thereby forming a void at the base
of the gap. In accordance with a preferred embodiment of the
present invention, gap 204 is completely sealed or filled by a
subsequent reflow step which eliminates any gaps, voids, or seams
in the conductive layer 203. Note that if a void is actually formed
upon deposition of conductive layer 203, the subsequent reflow step
may not be able to adequately seal the gap. The result of the
reflow step is shown in FIG. 2d.
[0039] A reflow step is a process step in which conductive layer
203 is exposed to an elevated temperature under vacuum for a period
of time necessary to cause conductive layer 203 to "smooth out" and
substantially seamlessly seal gap 204. The elevated temperatures of
the reflow step may be obtained by subjecting the substrate to
energy sources such as, for example, radiative, furnace, lamp,
microwave, or hot gas. For example, in one method consistent with
the present invention, a reflow step consisting of approximately
400.degree. C. for 30 minutes under a vacuum of approximately
3.times.10.sup.-9 torr would achieve the desired result. It has
been observed that depositing the conductive layer at low
temperatures (below approximately 150.degree. C.) improves the
subsequent reflow characteristics of the film. For example, gap 204
is more substantially sealed by a reflow process when conductive
layer 203 has been sputtered at a low temperature. By depositing
conductive layer 203 at higher temperatures, the reflow time may be
reduced due to simultaneous partial reflow and high temperature
deposition, however the groove 202 may not be completely filled
leading to void formation.
[0040] The driving force for the reduction in surface roughness of
the conductive layer 63 during the reflow step is believed to be
the minimization in surface free energy. This can be viewed at the
molecular level as the energy necessary to break the bonds in order
to create surface area. The more surface area that is created, the
higher the number of bonds that are broken. Therefore, more surface
area indicates more surface energy. There are several possible
mechanisms that may lead to surface smoothing such as viscous flow,
surface diffusion, volume diffusion, and evaporation-condensation
or transport through the vapor. Viscous flow is applicable for
amorphous materials (e.g. glass), and volume diffusion is important
at higher temperatures. For the present invention, it is believed
that surface diffusion and some volume diffusion are the two
mechanisms by which the reflow step works. It is important to note
that surface diffusion and evaporation-condensation would be
impeded by the formation of an oxide layer, so reflow should
preferably be done in a vacuum or pure inert atmosphere.
[0041] For this reason, a preferred embodiment of the present
invention maintains conductive layer 203 under very high to extra
high vacuum conditions between and during the deposition of at
least a portion of conductive layer 203 and the subsequent reflow
process step. In alternate embodiments of the present invention,
conductive layer 203 is kept under an inert atmosphere during the
critical time period between the deposition of conductive layer 203
and the reflow step. Still alternate embodiments of the present
invention keep conductive layer 203 under at least high vacuum
conditions, perhaps in addition to maintaining an inert ambient,
during this critical time period. To improve the manufacturability
of the present invention, the deposition and reflow process steps
may be performed within the same vacuum system without
significantly breaking the vacuum. Generally, high vacuum is
considered to be a pressure between approximately 1.times.10.sup.-3
torr and 1.times.10.sup.-6 torr, very high vacuum between
approximately 1.times.10.sup.-6 torr and 1.times.10.sup.-9 torr,
ultra high vacuum between approximately 1.times.10.sup.-9 torr and
1.times.10.sup.-12 torr, and extra high vacuum between
approximately 1.times.10.sup.-12 torr and 1.times.10.sup.-15 torr,.
An inert atmosphere for copper may include nitrogen or any of the
noble gases such as argon. In this manner, the potential for the
formation of an oxide layer on the surface of the conductive layer
63, which may inhibit the reflow process, is significantly reduced
or eliminated.
[0042] In a preferred embodiment of the reflow process step,
conductive layer 63 is exposed to a temperature below approximately
500.degree. C. However, the conductive layer 63 may be exposed to
temperatures in the range of approximately 200.degree.
C.-800.degree. C. with the range of approximately 300.degree.
C.-650.degree. C. being preferred. Various temperature ramping
schemes may be utilized in order to better control the reflow
process to promote complete sealing of the gap. Note that reflowing
too quickly may cause void formation. In general, the upper limit
on the temperature to which the conductive layer may be exposed
depends on the underlying substrate materials. For example, if an
aluminum layer is included in the underlying substrate, the reflow
temperature should be kept below the minimum temperature at which
the aluminum layer melts (660.degree. C.), its barrier layer is
consumed, junction spiking occurs, damaging hillocks are formed, or
any other damage to the device or severe degradation in its
reliability can result. It is also important to keep reflow
temperatures low so that, for example, any previously deposited
oxide layers don't themselves reflow. Because it may be necessary
to keep the reflow temperature low, it is fortunate, and indeed
surprising, that copper may be reflowed at temperatures below
approximately 673.degree. Kelvin (estimated actual surface
temperature), less than half of copper's melting point of
1356.degree. Kelvin. Note that all temperatures offered herein in
conjunction with the reflow process, unless otherwise noted, are
based on thermocouple measurements and do not necessarily reflect
actual substrate surface temperatures.
[0043] FIG. 2d illustrates the cross section of FIG. 2c after the
reflow step has been performed. Note how the reflow step has
completely sealed gap 204 of FIG. 2c. Contrasting this with gap 104
of FIG. 1b or the void of FIG. 1c, an advantage of the present
invention over the prior art can be seen. The groove 202 has been
more completely filled by conductive layer 203 during the reflow
step than groove 202 would have been filled by continued deposition
of a thicker conductive layer 203. Since the gap 204 of FIG. 2c has
been virtually eliminated, the problems associated with gaps,
voids, and seams, some of which have been discussed above, have
also been eliminated. The conductive layer 203 may now be etched
back to confine the conductive layer 203 to groove 202.
[0044] FIG. 2e shows the cross section of FIG. 2d after the
completion of an etch back process step. In a preferred embodiment
of the present invention, well known chemical-mechanical polishing
processes can be used to etch the conductive layer 203 from the
upper surfaces of dielectric layer 200. Thus, the portion of the
conductive layer 203 which exists substantially outside the groove
202 is removed thereby isolating conductive layer 203 to the groove
202. In a preferred embodiment of the present invention, an upper
portion of dielectric layer 200 is also removed as part of an
over-etch process to be sure most of the conductive layer 203 which
resides substantially outside the groove 202 has been removed. In
an alternate embodiment of the present invention, an alternate etch
process such as wet chemical etch, RE, back sputter, ion mill, or
mechanical polishing can be used to remove the portion of the
conductive layer 203 which resides substantially outside the groove
202. Note that etching techniques such as polishing additionally
serve to planarize the surface of the substrate.
[0045] FIGS. 3a-3e illustrate a more detailed description of a
preferred embodiment of the present invention already shown in
FIGS. 2a-2e in which a barrier layer is specifically illustrated as
part of the conductive layer. FIG. 3a is analogous to FIG. 2b and
displays a portion of substrate 306 above which dielectric layers
300 and 301 have been formed. Dielectric layer 300 has been etched,
selectively grown, or selectively deposited in order to create the
recessed region or groove 302 therein. See the discussion above for
a more detailed description of an embodiment by which the substrate
of FIG. 3a may be formed and suggested materials of which it may be
constructed.
[0046] FIG. 3b shows the same region displayed in FIG. 3a after a
barrier layer 303 has been formed. This barrier layer may serve one
or more of several functions. For example, the barrier layer may be
used to improve the adhesion between a subsequently formed layer
and another layer. This helps prevent, for example, delamination or
peeling from occurring during processing. Delamination may cause
significant yield or reliability problems. The barrier layer may
additionally serve to, for example, prevent materials contained
within a subsequently formed layer from contaminating other regions
of the semiconductor device, provide a more uniform layer onto
which a subsequent layer may be formed in order to better model a
process and reduce variability, improve the electrical contact
between a subsequently formed conductive layer and another
conductive layer, improve the wetting and agglomeration
characteristics of a subsequently formed layer, prevent substrate
damage by shielding against the radiation used for reflow, or
passivate an underlying or subsequently formed layer.
[0047] Note that in accordance with this embodiment of the present
invention, barrier layer 303 displayed in FIG. 3b has been
deposited along the walls of groove 302 (conformal coverage). In an
alternate embodiment of the present invention, barrier layer 303
may be deposited at the bottom of groove 302 and at the upper
surfaces of dielectric layer 300 but not substantially along the
walls of groove 302. Barrier layers constructed out of one or more
of the following materials may exhibit one or more of the desired
properties stated above: oxide, nitride, silicon oxynitride,
silicon carbide. Mo, MoN, Ta, TaN, W, WN, V, VN, Nb, NbN, Ti, and
TiN.
[0048] FIG. 3c shows the same region displayed in FIG. 3b after the
remaining portion of conductive layer 304 has been blanket
deposited creating gap 305. See the discussion above for a more
detailed description of an embodiment by which conductive layer 304
may be formed and suggested materials of which it may be
constructed. FIG. 3d illustrates the cross section of FIG. 3c after
a reflow step has been performed. Note that gap 305 shown in FIG.
3c has been sealed by the reflow process in FIG. 3d with
substantially no formation of a void or tunnel at the base of the
gap. See the discussion above for a more detailed description of
embodiments by which conductive layer 304 may be reflowed. FIG. 3e
shows the cross section of FIG. 3d after the completion of an etch
back process step in which conductive layer 304 and barrier layer
303 have been etched from the upper surface of dielectric layer
300. In an alternate embodiment of the present invention, at least
a portion of barrier layer 303 is left on the upper surface of
dielectric layer 300 after the completion of the etch back process.
Again, see above for a more detailed discussion of the etch back
process.
[0049] Where one desires to improve the step coverage of a
conductive layer, one might employ the reflow process taught by the
present invention in conjunction with a copper dry etch process.
For example, copper, or an alloy thereof, is deposited on a
semiconductor substrate. This copper layer is then subjected to a
reflow process consistent with the reflow process taught by the
present invention in order to improve the step coverage of the
copper layer. The copper layer is then patterned using, for
example, lithographic techniques, and then etched using, for
example, an RIE, sputter, or ion mill etching process. In such a
process, vias and interconnections may be formed from the same
copper layer.
[0050] Thus a novel electrical interconnection manufacturing
process has been described which improves the manufacturability,
quality, reliability, and performance of semiconductor devices.
This process is compatible with advanced VLSI and ULSI process
techniques.
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