U.S. patent application number 10/354088 was filed with the patent office on 2003-07-17 for layer structure having contact hole, fin-shaped capacitor using the layer structure, method of producing the fin-shaped capacitor, and dynamic random access memory having the fin-shaped capacitor.
This patent application is currently assigned to Fujitsu Limited. Invention is credited to Ema, Taiji.
Application Number | 20030134470 10/354088 |
Document ID | / |
Family ID | 27463125 |
Filed Date | 2003-07-17 |
United States Patent
Application |
20030134470 |
Kind Code |
A1 |
Ema, Taiji |
July 17, 2003 |
Layer structure having contact hole, fin-shaped capacitor using the
layer structure, method of producing the fin-shaped capacitor, and
dynamic random access memory having the fin-shaped capacitor
Abstract
A method of forming a structure having a contact hole includes
the steps of (a) forming an insulating layer on a first conductive
layer, (b) forming a second conductive layer on the insulating
layer, (c) forming an opening in the second conductive layer, (d)
forming a conductive sidewall around an inner wall of the first
conductive layer defining the opening, (e) selectively etching the
insulating layer in a state where the second conductive layer and
the conductive sidewall function as etching masks, so that the
contact hole having a width smaller than that of the opening and
defined by the conductive sidewall is formed, and the first
conductive layer is exposed through the contact hole, and (f)
removing the second conductive layer and the conductive
sidewall.
Inventors: |
Ema, Taiji; (Kawasaki-shi,
JP) |
Correspondence
Address: |
STAAS & HALSEY LLP
700 11TH STREET, NW
SUITE 500
WASHINGTON
DC
20001
US
|
Assignee: |
Fujitsu Limited
Kawasaki
JP
|
Family ID: |
27463125 |
Appl. No.: |
10/354088 |
Filed: |
January 30, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10354088 |
Jan 30, 2003 |
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09666842 |
Sep 21, 2000 |
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6528369 |
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09666842 |
Sep 21, 2000 |
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08453509 |
May 30, 1995 |
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6144058 |
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08453509 |
May 30, 1995 |
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08190573 |
Feb 2, 1994 |
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08190573 |
Feb 2, 1994 |
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07666069 |
Mar 7, 1991 |
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Current U.S.
Class: |
438/254 ;
257/E21.038; 257/E21.275; 257/E21.577; 257/E21.648;
257/E27.089 |
Current CPC
Class: |
H01L 27/10817 20130101;
H01L 27/10891 20130101; H01L 21/7687 20130101; H01L 21/31625
20130101; Y10S 148/014 20130101; H01L 27/10852 20130101; H01L
21/0337 20130101; H01L 21/0332 20130101; H01L 21/76802 20130101;
H01L 21/76843 20130101 |
Class at
Publication: |
438/254 |
International
Class: |
H01L 021/8242 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 8, 1990 |
JP |
2-54883 |
Sep 6, 1990 |
JP |
2-234585 |
Oct 23, 1990 |
JP |
2-283371 |
Oct 23, 1990 |
JP |
2-283370 |
Claims
What is claimed is:
1. A method of forming a structure having a contact hole comprising
the steps of: (a) forming an insulating layer on a first conductive
layer; (b) forming a second conductive layer on said insulating
layer; (c) forming an opening in said second conductive layer; (d)
forming a conductive sidewall around an inner wall of said first
conductive layer defining said opening; (e) selectively etching
said insulating layer in a state where said second conductive layer
and said conductive sidewall function as etching masks, so that
said contact hole having a width smaller than that of said opening
and defined by said conductive sidewall is formed, and said first
conductive layer is exposed through said contact hole; and (f)
removing said second conductive layer and said conductive
sidewall.
2. A method as claimed in claim 1, wherein said methd comprises,
between said step (e) and said step (f), the steps of: (e-1)
forming an etching resist on said first conductive layer exposed
through said contact hole, said second conductive layer and said
conductive sidewall; and (e-2) removing only a part of said etching
resist on said second conductive layer and said conductive sidewall
so that said first conductive layer exposed through said contact
hole is protected by said etching resist.
3. A method as claimed in claim 2, wherein said step (e-2)
comprises: projecting light onto said etching resist; and
developing said etching resist so that a part of said etching
resist is left on said first conductive layer exposed through said
contact hole.
4. A method as claimed in claim 1, wherein: said method further
comprises the step of forming an etching stopper layer on said
second conductive layer; and said etching stopper layer protects
said second conductive layer during said step (d), so that the
thickness of said second conductive layer can be prevented from
being reduced during said step (d).
5. A method as claimed in claim 1, wherein said method further
comprises the step of forming a third conductive layer on said
insulating layer and in contact with said first conductive layer
exposed through said contact hole.
6. A method as claimed in claim 1, wherein said first conductive
layer comprises polysilicon.
7. A method as claimed in claim 1, wherein: said second conductive
layer comprises polysilicon; and said conductive sidewall comprises
polysilicon.
8. A method as claimed in claim 1, wherein said method further
comprises the step of heating said insulating layer so that said
insulating layer is reflown and an edge portion of said insulating
layer defining an upper portion of said contact hole is gradually
curved.
9. A method of forming a structure having a contact hole comprising
the steps of: (a) forming an insulating layer on a first conductive
layer; (b) forming a second conductive layer on said insulating
layer; (c) forming an opening in said second conductive layer; (d)
forming a conductive sidewall around an inner wall of said first
conductive layer defining said opening; (e) selectively etching
said insulating layer in a state where said second conductive layer
and said conductive sidewall function as etching masks, so that
said contact hole having a width smaller than that of said opening
and defined by said conductive sidewall is formed on said
insulating layer and said first conductive layer is exposed through
said contact hole; (f) forming a barrier layer on said second
conductive layer, said conductive sidewall and said first
conductive layer exposed through said contact hole; and (g) forming
a third conductive layer on said barrier layer, said barrier layer
preventing said third conductive layer from reacting with said
second conductive layer and said conductive sidewall.
10. A method as claimed in claim 9, wherein: said barrier layer
comprises a bilayer structure having a titanium layer and a
titanium nitride layer; and said third conductive layer comprises
aluminum.
11. A method as claimed in claim 9, wherein: said second conductive
layer comprises polysilicon; and said conductive sidewall comprises
polysilicon.
12. A method of forming a structure having a contact hole
comprising the steps of: (a) forming an insulating layer on a first
conductive layer; (b) forming a second conductive layer on said
insulating layer; (c) forming an opening in said second conductive
layer; (d) forming a conductive sidewall around an inner wall of
said first conductive layer defining said opening; (e) selectively
etching said insulating layer in a state where said second
conductive layer and said conductive sidewall function as etching
masks, so that said contact hole having a width smaller than that
of said opening and defined by said conductive sidewall is formed,
and said first conductive layer is exposed through said contact
hole; and (f) forming a third conductive layer on said second
conductive layer, said conductive sidewall and said member exposed
through said contact hole, wherein: said second conductive layer
comprises polysilicon; said conductive sidewall comprises
polysilicon; and said third conductive layer comprises
tungsten.
13. A method as claimed in claim 12, wherein said contact hole is
filled with tungsten of said third conductive layer.
14. A method of forming a structure having a contact hole
comprising the steps of: (a) forming an insulating layer on a first
conductive layer; (b) forming a second conductive layer on said
insulating layer; (c) forming a first opening in said second
conductive layer; (d) selectively growing a third conductive layer
on said second conductive layer and an inner wall of said second
conductive layer defining said first opening, so that a second
opening defined by said third conductive layer and having a width
smaller than that of said first opening is formed; and (e)
selectively etching said insulating layer in a state where said
third conductive layer functions as an etching mask, so that said
contact hole having a width substantially identical to said second
opening defined by said third conductive layer is formed, and said
first conductive layer is exposed through said contact hole.
15. A method as claimed in claim 14, wherein: said second
conductive layer comprises polysilicon; and said third conductive
layer comprises polysilicon.
16. A method as claimed in claim 14, wherein said method further
comprises the steps of: forming a barrier layer on said third
conductive layer and said first conductive layer exposed through
said contact hole; and forming a fourth conductive layer on said
barrier layer, said barrier layer preventing said third conductive
layer from reacting with said fourth conductive layer.
17. A layer structure comprising: a first conductive layer; an
insulating layer formed on said first conductive layer and having a
contact hole, said first conductive layer being exposed through
said contact hole; a second conductive layer formed on said
insulating layer and having an opening having a width larger than
that of said contact hole; a conductive sidewall formed on said
insulating layer exposed through said opening and formed around an
inner wall of said second conductive layer defining said opening,
said conductive sidewall having a width substantially equal to that
of said contact hole; a barrier layer formed on said second
conductive layer, said conductive sidewall and said first
conductive layer exposed through said contact hole; and a third
conductive layer formed on said barrier layer, said barrier layer
preventing said third conductive layer from reacting with said
second conductive layer and said conductive sidewall.
18. A layer structure as claimed in claim 17, wherein: said third
conductive layer comprises aluminum; said first and second
conductive layers comprise polysilicon; and said conductive
sidewall comprises polysilicon.
19. A layer structure as claimed in claim 17, wherein said barrier
layer comprises a bilayer structure having a titanium layer and a
titanium nitride layer.
20. A layer structure comprising: a first conductive layer; an
insulating layer formed on said first conductive layer and having a
contact hole, said first conductive layer being exposed through
said contact hole; a second conductive layer formed on said
insulating layer and having a first opening having a width larger
than that of said contact hole; a third conductive layer formed on
said insulating layer exposed through said first opening and said
second conductive layer and formed around an inner wall of said
second conductive layer defining said first opening, said third
conductive layer defining a second opening having a width
substantially equal to that of said contact hole, said second
opening being continuously connected to said contact hole; a
barrier layer formed on said third conductive layer and said first
conductive layer exposed through said contact hole; and a fourth
conductive layer formed on said barrier layer, said barrier layer
preventing said fourth conductive layer from reacting with said
third conductive layer and said conductive sidewall.
21. A layer structure as claimed in claim 20, wherein: said fourth
conductive layer comprises aluminum; and said first, second and
third conductive layers comprise polysilicon.
22. A layer structure as claimed in claim 20, wherein said barrier
layer comprises a bilayer structure having a titanium layer and a
titanium nitride layer.
23. A layer structure comprising: a first conductive layer; an
insulating layer formed on said first conductive layer and having a
contact hole, said first conductive layer being exposed through
said contact hole; a second conductive layer formed on said
insulating layer and having an opening having a width larger than
that of said contact hole; a conductive sidewall formed on said
insulating layer exposed through said opening and formed around an
inner wall of said second conductive layer defining said opening,
said conductive sidewall having a width substantially equal to that
of said contact hole; and a third conductive layer formed on said
second conductive layer, said conductive sidewall and said first
conductive layer exposed through said contact hole, wherein said
third conductive layer comprises a material which causes no
reaction with said second conductive layer and said conductive
sidewall.
24. A layer structure as claimed in claim 23, wherein: said third
conductive layer comprises tungsten; said second conductive layer
comprises polysilicon; and said conductive sidewall comprises
polysilicon.
25. A dynamic random access memory comprising: a semiconductor
substrate having a first diffusion region and a second diffusion
region of a transfer transistor; a first insulating layer having a
first contact hole exposing said first diffusion region, and a
second contact hole exposing said second diffusion region; a word
line covered by said first insulating layer; a stacked capacitor
which is in contact with said first diffusion region through said
first contact hole; a bit line which is in contact with said second
diffusion region through said second contact hole; and a second
insulating layer covering said stacked capacitor, wherein: said
stacked capacitor comprises a storage electrode, a dielectric film
and a cell plate; said storage electrode which is in contact with
said first diffusion region through said first contact hole has a
first fin having a first portion, a second portion and a third
portion; said first portion has a first opening having a width
greater than that of said first contact hole; said second portion
serving as a sidewall is formed around an inner wall of said first
portion defining said first opening, so that a second opening has a
width substantially identical to that of said first contact hole;
and said third portion extends on said first and second portions,
substantially vertically extends in said first contact hole, and is
in contact with said first diffusion region.
26. A dynamic random access memory as claimed in claim 25, wherein:
said storage electrode comprises a second fin having a contact area
in which said second fin is in contact with said first fin; said
contact area is wider than said first contact hole; and said first
and second fins are spaced apart from each other.
27. A dynamic random access memory as claimed in claim 25, wherein
said first fin is spaced apart from said first insulating
layer.
28. A dynamic random access memory as claimed in claim 25, wherein
said first fin of said storage electrode is formed on said first
insulating layer.
29. A dynamic random access memory as claimed in claim 26, wherein
said first fin of said storage electrode is thicker than said third
portion thereof.
30. A dynamic random access memory as claimed in claim 25, wherein
said storage electrode having said first fin having said first,
second and third portions comprises polysilicon.
31. A dynamic random access memory comprising: a semiconductor
substrate having a first diffusion region and a second diffusion
region of a transfer transistor; a first insulating layer having a
first contact hole exposing said first diffusion region, and a
second contact hole exposing said second diffusion region; a word
line covered by said first insulating layer; a stacked capacitor
which is in contact with said first diffusion region through said
first contact hole; a bit line which is in contact with said second
diffusion region through said second contact hole; and a second
insulating layer covering said stacked capacitor, wherein: said
stacked capacitor comprises a storage electrode, a dielectric film
and a cell plate; and said storage electrode which is in contact
with said first diffusion region through said first contact hole
has a plurality of first fin-shaped portions located outside of
said first contact hole, a second portion connecting said first
fin-shaped portions to each other, and a third portion extending on
an uppermost one of said first fin-shaped portions and said second
portion, substantially vertically extending in said first contact
hole, and being in contact with said first diffusion region.
32. A dynamic random access memory as claimed in claim 31, wherein:
said second portion of said storage electrode is spaced apart from
said first insulating layer; and a lowermost one of said first
fin-shaped portions of said storage electrode is spaced apart from
said first insulating layer.
33. A dynamic random access memory as claimed in claim 31, wherein:
said second portion of said storage electrode is in contact with
said first insulating layer; and a lowermost one of said first
fin-shaped portions of said storage electrode is spaced apart from
said first insulating layer.
34. A dynamic random access memory as claimed in claim 33, wherein
said storage electrode has a substantially flat surface which
extends above said word line.
35. A dynamic random access memory as claimed in claim 31, wherein
said storage electrode comprises polysilicon.
36. A dynamic random access memory comprising: a semiconductor
substrate having a first diffusion region and a second diffusion
region of a transfer transistor; a first insulating layer having a
first contact hole exposing said first diffusion region, and a
second contact hole exposing said second diffusion region; a word
line covered by said first insulating layer; a stacked capacitor
which is in contact with said first diffusion region through said
first contact hole; a bit line which is in contact with said second
diffusion region through said second contact hole; and a second
insulating layer covering said stacked capacitor, wherein: said
stacked capacitor comprises a storage electrode, a dielectric film
and a cell plate; and said storage electrode which is in contact
with said first diffusion region through said first contact hole
has a plurality of first fin-shaped portions located outside of
said first contact hole, and a second portion connecting said first
fin-shaped portions to each other, and extending on an uppermost
one of said first fin-shaped portions, said second portion
substantially vertically extending in said first contact hole, and
being in contact with said first diffusion region.
37. A dynamic random access memory as claimed in claim 36, wherein
a lowermost one of said first fin-shaped portions is spaced apart
from said first insulating layer.
38. A dynamic random access memory device as claimed in claim 36,
wherein a lowermost one of said first fin-shaped portions is in
contact with said first insulating layer.
39. A dynamic random access memory as claimed in claim 36, wherein
said storage electrode comprises polysilicon.
40. A fin-shaped capacitor comprising: a storage electrode having
an exposed surface; a dielectric film formed around said exposed
surface of said storage electrode; and a cell plate covering said
storage electrode surrounded by said dielectric film, wherein: said
storage electrode is in contact with a diffusion region of a
semiconductor substrate through a contact hole formed in an
insulating layer formed on said semiconductor substrate; said
storage electrode has a first fin having a first portion, a second
portion and a third portion; said first portion has a first opening
having a width greater than that of said contact hole; said second
portion is formed around an inner wall of said first portion
defining said first opening, so that a second opening has a width
substantially identical to that of said contact hole; and said
third portion extends on said first and second portions,
substantially vertically extends in said contact hole, and is in
contact with said diffusion region in said semiconductor
substrate.
41. A fin-shaped capacitor as claimed in claim 40, wherein: said
storage electrode comprises a second fin having a contact area in
which said second fin is in contact with said first fin; said
contact area is wider than said contact hole; and said first and
second fins are spaced apart from each other.
42. A fin-shaped capacitor as claimed in claim 40, wherein said
first fin is spaced apart from said insulating layer.
43. A fin-shaped capacitor as claimed in claim 40, wherein said
first fin of said storage electrode is formed on said insulating
layer.
44. A fin-shaped capacitor as claimed in claim 41, wherein said
first fin of said storage electrode is thicker than said third
portion thereof.
45. A fin-shaped capacitor as claimed in claim 40, wherein said
storage electrode having said first fin having said first, second
and third portions comprises polysilicon.
46. A fin-shaped capacitor comprising: a storage electrode having
an exposed surface; a dielectric film formed around said exposed
surface of said storage electrode; and a cell plate covering said
storage electrode surrounded by said storage electrde, wherein:
said storage electrode is in contact with a diffusion region of a
semiconductor substrate through a contact hole formed in an
insulating layer formed on said semiconductor substrate; said
storage electrode has a plurality of first fin-shaped portions
located outside of said contact hole, a second portion connecting
said first fin-shaped portions to each other, and a third portion
extending on an uppermost one of said first fin-shaped portions and
said second portion, substantially vertically extending in said
contact hole, and being in contact with said diffusion region of
said semiconductor substrate.
47. A fin-shaped capacitor as claimed in claim 46, wherein: said
second portion of said storage electrode is spaced apart from said
insulating layer; and a lowermost one of said first fin-shaped
portions of said storage electrode is spaced apart from said
insulating layer.
48. A fin-shaped capacitor as claimed in claim 46, wherein: said
second portion of said storage electrode is in contact with said
insulating layer; and a lowermost one of said first fin-shaped
portions of said storage electrode is spaced apart from said
insulating layer.
49. A fin-shaped capacitor as claimed in claim 48, wherein said
insulating layer has a substantially flat surface on which said
second portion of said storage electrode is formed.
50. A fin-shaped capacitor as claimed in claim 46, wherein said
storage electrode comprises polysilicon.
51. A fin-shaped capacitor comprising: a storage electrode having
an exposed surface; a dielectric film formed around said exposed
surface of said storage electrode; and a cell plate covering said
storage electrode surrounded by said storage electrode, wherein:
said storage electrode is in contact with a diffusion region of a
semiconductor substrate through a contact hole formed in an
insulating layer formed on said semiconductor substrate; said
storage electrode has a plurality of first fin-shaped portions
located outside of said contact hole, and a second portion
connecting said fin-shaped portions to each other, and extending on
an uppermost one of said first fin-shaped portions, said second
portion substantially vertically extending in said contact hole,
and being in contact with said diffusion region in said
semiconductor substrate.
52. A fin-shaped capacitor as claimed in claim 51, wherein a
lowermost one of said first fin-shaped portions is spaced apart
from said insulating layer.
53. A fin-shaped capacitor device as claimed in claim 51, wherein a
lowermost one of said first fin-shaped portions is in contact with
said insulating layer.
54. A fin-shaped capacitor as claimed in claim 51, wherein said
storage electrode comprises polysilicon.
55. A method of producing a fin-shaped capacitor in a dynamic
random access memory comprising the steps of: (a) forming an
insulating layer on a semiconductor substrate having a diffusion
region; (b) forming a first conductive layer having a first opening
on said insulating layer; (c) forming a conductive sidewall around
an inner wall of said first conductive layer defining said first
opening, said conductive sidewall defining a second opening having
a width smaller than that of said first opening; (d) selectively
etching said insulating layer in a state where said first
conductive layer and said conductive sidewall function as etching
masks, so that said diffusion region is exposed through a contact
hole formed in said insulating layer and having a width
substantially identical to that of said second opening; (e) forming
a second conductive layer on said first conductive layer, said
conductive sidewall and said diffusion region exposed through said
contact hole; (f) patterning said first conductive layer and said
second conductive layer into a shape of a storage electrode of said
fin-shaped capacitor; (g) forming a dielectric film around an
exposed surface of said storage electrode; and (h) forming a cell
plate around said storage electrode covered by said dielectric
film.
56. A method as claimed in claim 55, wherein said step (a)
comprises the steps of: forming a first insulating layer directly
on said semiconductor substrate; and forming a second insulating
layer on said semiconductor substrate, said insulating layer having
said first and second insulating layers, and wherein said method
further comprises the step of isotropically etching said second
insulating layer, so that said storage electrode is spaced apart
from said first insulating layer.
57. A method of producing a fin-shaped capacitor in a dynamic
random access memory comprising the steps of: (a) forming a first
insulating layer on a semiconductor substrate having a diffusion
region; (b) forming a first conductive layer having a first opening
on said first insulating layer; (c) forming a conductive sidewall
around an inner wall of said first conductive layer defining said
first opening, said conductive sidewall defining a second opening
having a width smaller than that of said first opening; (d)
selectively etching said first insulating layer in a state where
said first conductive layer and said conductive sidewall function
as etching masks, so that said diffusion region is exposed through
a contact hole formed in said first insulating layer and having a
width substantially identical to that of said second opening; (e)
forming a second conductive layer on said first conductive layer,
said conductive sidewall and said diffusion region exposed through
said contact hole; (f) forming, on said second conductive layer, a
second insulating layer having a third opening having a width
substantially identical to that of said first opening; (g) forming
a third conductive layer on said second insulating layer and said
second conductive layer through said third opening; (h) patterning
said first and second conductive layers and said second insulating
layer into a shape of a storage electrode of said fin-shaped
capacitor; (i) isotropically etching said second insulating layer
so as to be removed; (j) forming a dielectric film around an
exposed surface of said storage electrode; and (k) forming a cell
plate around said storage electrode covered by said dielectric
film.
58. A method as claimed in claim 57, wherein said step (a)
comprises the steps of: forming a third insulating layer directly
on said semiconductor substrate; and forming a fourth insulating
layer on said third insulating layer; forming a fifth insulating
layer on said fourth insulating layer, said first insulating layer
has said third and fourth insulating layers, and wherein: said
fifth insulating layer is formed of a material identical to that of
said third insulating material; and said fifth insulating layer is
removed during said step (i), so that said storage electrode is
spaced apart from said fourth insulating layer.
59. A method as claimed in claim 57, wherein: said step (h)
comprises: forming a third insulating layer having a fourth opening
on said third conductive layer, said fourth opening being located
at a position different from that of said first opening; forming an
insulating sidewall around an inner surface of said fourth
insulating layer defining said fourth opening, said insulating
sidewall defining a fifth opening having a width smaller than that
of said fourth opening; and etching said first, second and third
conductive layers and said second and third insulating layers in a
state where said fourth insulating layer and said insulating
sidewall function as etching masks.
60. A method of producing a fin-shaped capacitor in a dynamic
random access memory comprising the steps of: (a) forming a first
insulating layer on a semiconductor substrate having a diffusion
region; (b) forming a plurality of stacked-layer structures, a
lowermost one of said stacked-layer structures being formed on said
first insulating layer, each of said stacked-layer structures
having a spacer layer and a first conductive layer; (c) forming a
first opening in said stacked-layer structures except said spacer
layer of said lowermost one of said stacked-layer structures; (d)
forming a conductive sidewall around an inner wall of said
stacked-layer structures defining said first opening, said
conductive sidewall defining a second opening having a width
smaller than that of said first opening; (e) selectively etching
said spacer layer of the lowermost one of said stacked-layer
structures and said first insulating layer in a state where said
first conductive layer of an uppermost one of said stacked layer
structures and said conductive sidewall function as masks, so that
said diffusion region is exposed through a contact hole formed in
said spacer layer of the lowermost one of said stacked-layer
structures and said first insulating layer; (f) forming a second
conductive layer on said first conductive layer of the uppermost
one of said stacked-layer structures, said conductive sidewall and
said diffusion region exposed through said contact hole; (g)
patterning said second conductive layer and said stacked-layer
structures except said spacer layer of the lowermost one of said
stacked-layer structures into a shape of a storage electrode of
said fin-shaped capacitor; (h) isotropically etching said spacer
layer of each of said stacked-layer structures so that said spacer
layer is removed; (i) forming a dielectric film around said storage
electrode; and (j) forming a cell plate around said storage
electrode covered by said dielectric film.
61. A method as claimed in claim 60, wherein: said method further
comprises, between said steps (b) and (c), the step of forming a
second insulating layer on said first conductive layer of the
uppermost one of said stacked-layer structures; and said second
insulating layer is removed during said step (e).
62. A method as claimed in claim 60, wherein said step (a)
comprises the steps of: forming a second insulating layer on said
semiconductor substrate; forming a third insulating layer on said
second insulating layer; heating said third insulating layer so
that said third insulating layer has a substantially flat surface;
and forming a fourth insulating layer on said substantially flat
surface of said third insulating layer, and wherein: said second,
third and fourth insulating layers form said first insulating
layer.
63. A method as claimed in claim 60, wherein: said first conductive
layer comprises polysilicon; and said spacer layer comprises
silicon oxide.
64. A method as claimed in claim 62, wherein: said second and
fourth insulating layers comprises silicon oxide; and said third
insulating layer comprises one of a spin-on-glass layer and a
phosphosilicate glass layer.
65. A method of producing a fin-shaped capacitor in a dynamic
random access memory comprising the steps of: (a) forming a first
insulating layer on a semiconductor substrate having a diffusion
region; (b) forming a plurality of stacked-layer structures, a
lowermost one of said stacked-layer structures being formed on said
first insulating layer, each of said stacked-layer structures
having a spacer layer and a first conductive layer; (c) forming a
first opening in said stacked-layer structures; (d) forming a
conductive sidewall around an inner wall of said stacked-layer
structures defining said first opening, said conductive sidewall
defining a second opening having a width smaller than that of said
first opening; (e) selectively etching said first insulating layer
in a state where said first conductive layer of an uppermost one of
said stacked layer structures and said conductive sidewall function
as masks, so that said diffusion region is exposed through a
contact hole formed in said first insulating layer; (f) forming a
second conductive layer on said first conductive layer of the
uppermost one of said stacked-layer structures, said conductive
sidewall and said diffusion region exposed through said contact
hole; (g) patterning said second conductive layer and said
stacked-layer structures into a shape of a storage electrode of
said fin-shaped capacitor; (h) isotropically etching said spacer
layer of each of said stacked-layer structures so that said spacer
layer is removed; (i) forming a dielectric film around said storage
electrode; and (j) forming a cell plate around said storage
electrode covered by said dielectric film.
66. A method as claimed in claim 65, wherein: said method further
comprises, between said steps (b) and (c), the step of forming a
second insulating layer on said first conductive layer of the
uppermost one of said stacked-layer structures; and said second
insulating layer is removed during said step (e).
67. A method as claimed in claim 65, wherein said step (a)
comprises the steps of: forming a second insulating layer on said
semiconductor substrate; forming a third insulating layer on said
second insulating layer; heating said third insulating layer so
that said third insulating layer has a substantially flat surface;
and forming a fourth insulating layer on said substantially flat
surface of said third insulating layer, and wherein: said second,
third and fourth insulating layers form said first insulating
layer.
68. A method as claimed in claim 65, wherein: said first conductive
layer comprises polysilicon; and said spacer layer comprises
silicon oxide.
69. A method as claimed in claim 67, wherein: said second and
fourth insulating layers comprise silicon oxide; and said third
insulating layer comprises one of a spin-on-glass layer and a
phosphosilicate glass layer.
70. A method of producing a fin-shaped capacitor in a dynamic
random access memory comprising the steps of: (a) forming a first
insulating layer on a semiconductor substrate having a diffusion
region; (b) forming a plurality of stacked-layer structures, a
lowermost one of said stacked-layer structures being formed on said
first insulating layer, each of said stacked-layer structures
having a spacer layer and a first conductive layer; (c) forming a
contact hole in said stacked-layer structures and said first
insulating layer so that said diffusion layer is exposed through
said contact hole; (d) forming a second conductive layer on said
first conductive layer of an uppermost one of said stacked-layer
structure and said diffusion layer exposed through said contact
hole, said second conductive layer substantially vertically
extending along an inner wall of said contact hole; (e) patterning
said second conductive layer and said stacked-layer structures into
a shape of a storage electrode of said fin-shaped capacitor; (f)
isotropically etching said spacer layer of each of said
stacked-layer structures so that said spacer layer is removed; (i)
forming a dielectric film around said storage electrode; and (j)
forming a cell plate around said storage electrode covered by said
dielectric film.
71. A method as claimed in claim 70, wherein said step (a)
comprises the steps of: forming a second insulating layer on said
semiconductor substrate; forming a third insulating layer on said
second insulating layer; heating said third insulating layer so
that said third insulating layer has a substantially flat surface;
and forming a fourth insulating layer on said substantially flat
surface of said third insulating layer, and wherein: said fourth
insulating layer is removed during said step (f).
72. A method as claimed in claim 71, wherein: said second and
fourth insulating layers comprises silicon oxide; said third
insulating layer comprises silicon nitride; and said first and
second conductive layers comprise polysilicon.
73. A method as claimed in claim 70, wherein: said step (c)
comprises: forming a third conductive layer on a top of said
stacked layer structures; forming a second insulating layer on said
third conductive layer; forming a photoresist film having a window
pattern on said second insulating layer; etching said second
insulating layer and said third conductive layer so that a first
window is formed in said third conductive layer and said second
insulating layer; removing said photoresist film; and forming a
conductive sidwall around an inner wall of said third conductor
layer defining said window, wherein said contact hole formed by
said step (c) having a size defined by said conductive sidewall.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention generally relates to a layer structure
having a contact hole suitable for dynamic random access memories
having fine contact holes, and a method of producing such a layer
structure. More particularly, the present invention is concerned
with a fin-shaped capacitor having such a layer structure, and a
method of forming such a fin-shaped capacitor. Furthermore, the
present invention is concerned with a dynamic random access memory
having such a fin-shaped capacitor.
[0002] Recently, there has been considerable activity as regards
the development of 64 Mbit dynamic random access memories (DRAM).
There are known DRAMs having three-dimensional stacked capacitor
cells capable of providing a storage capacity equal to or higher
than 64 Mbits (see Japanese Laid-Open Patent Application Nos.
1-137666, 1-147857 and 1-154549, U.S. Pat. No. 4,974,040 and T. Ema
et al., "3-DIMENSIONAL STACKED CAPACITOR CELL FOR 16M AND 64M
DRAMS", International Electron Devices Meetings, 592-IEDM 88, Dec.
11-14, 1988). In order to increase the integration density, it is
necessary to reduce the two-dimensional size of each memory cell
without reducing the capacitance of each stacked capacitor.
[0003] In order to fabricate 64 Mbit DRAMs, a feature scale
approximately equal to 0.3 [.mu.m] is required. However, the
conventional photolithography technique can realize a feature scale
approximately equal to a maximum of 0.5 [.mu.m]. 64 Mbit DRAMs can
be realized by reducing the size of each storage (stacked)
capacitor. For this purpose, it is necessary to reduce the size of
a contact window (opening) for a storage electrode which is a part
of the stacked capacitor. As described above, since the feature
scale realized by the conventional photolithography technique is
approximately 0.5 [.mu.m], it is impossible to form the contact
window having a size approximately equal to 0.3 [.mu.m]. It is also
necessary to reduce the size of a window (contact hole) provided
for connecting a word line formed of, for example, polysilicon, and
a low-resistance wiring line (word-line shunt layer) formed of Al
or Al alloy, directed to preventing the occurrence of a delay in
signal transmission in the word line.
[0004] Japanese Laid-Open Patent Application No. 63-119239
discloses a method for forming a fine pattern narrower than a
feature scale limit of the conventional photolithography technique.
The application teaches a process in which polysilicon, PSG or
SiO.sub.2 is grown on an SiO.sub.2 mask having a window through
which a substrate is partially exposed, and a grown film on the
mask and the exposed substrate surface is anisotropically etched,
so that a sidewall is formed on the substrate so that it is formed
around the entire inner wall of the window in the mask. The
distance between opposite surfaces of the sidewall in the window is
less than the feature scale limit. Thus, a surface area of the
substrate less than the feature scale limit is exposed through the
sidewall in the window. Then, the substrate is etched in such a way
that the combination of the sidewall and the mask function as an
etching mask, so that a hole is formed in the substrate.
[0005] The above-mentioned Patent Application discloses an
arrangement in which the mask is formed of SiO.sub.2 and a member
to be processed is formed of Si. Thus, the removal of the mask
material can be easily made. However, when a multilayer structure,
such as DRAMS, is produced, it is necessary to consider three
layers of a mask material, a material to be processed and a
underlying material which is located under the processed material
and which is exposed through a hole formed in the processed
material. In this case, it is necessary to prevent the exposed
portion of the underlaying material from be damaged during a
process in which the mask material is removed. Further, if the mask
material is left in the finalized products, it is necessary to have
no problem arising from the existence of the left mask material.
The above-mentioned Japanese Application does not suggest the above
matters.
[0006] Japanese Laid-Open Patent Application No. 60-224218
discloses the use of a sidewall directed to providing a window
(contact hole) smaller than the feature scale limit of the
conventional photolithography technique. The sidewall is formed of
Al and formed on an SiO.sub.2 layer and around an inner wall of a
window formed in a silicon nitride (Si.sub.3N.sub.4) layer also
formed on the SiO.sub.2 layer. The SiO.sub.2 layer is selectively
etched in such a way that the Al sidewall and the Si.sub.3N.sub.4
layer function as mask layers. However, it is very difficult to
form the Al sidewall in contact with the inner wall of the window
in the Si.sub.3N.sub.4 layer, since Al has a poor coverage
characteristic. Further, it is necessary to form the
Si.sub.3N.sub.4 layer which is sufficiently thick, because the
selective etching ratio of Si.sub.3N.sub.4 to SiO.sub.2 is
small.
[0007] Japanese Laid-Open Patent Application No. 63-116430 (which
corresponds to U.S. patent application Ser. No. 924,223 filed on
Oct. 28, 1986) teaches the use of a sidewall for forming a hole
smaller than the scale limit of the conventional photolithgraphy
technique. The just above application shows a lift-off process for
removing the mask material. However, the lift-off process has a
problem in that some of the mask material separated from the
substrate is re-adhered hereto. This frequently causes a pattern
fault in a subsequent process. The Japanese application of concern
does not disclose an effective step to process the mask material.
Further, the Japanese application shows a sidewall formed on the
side surface of a photosensitive material. It is necessary to form
the sidewall at a low temperature due to the thermal stability of
the photosensitive material. Thus, there is a great limitation
regarding the selection of mask materials. In addition, the
structure shown in the Japanese application of concern is limited
to a special application.
SUMMARY OF THE INVENTION
[0008] It is a general object of the present invention to provide
an improved layer structure having a contact hole, in which the
above-mentioned disadvantages are eliminated.
[0009] A more specific object of the present invention is to
provide a layer structure having a contact hole suitable for
DRAMs.
[0010] The above-mentioned objects of the present invention are
achieved by a method of forming a structure having a contact hole
comprising the steps of:
[0011] (a) forming an insulating layer on a first conductive
layer;
[0012] (b) forming a second conductive layer on the insulating
layer;
[0013] (c) forming an opening in the second conductive layer;
[0014] (d) forming a conductive sidewall around an inner wall of
the first conductive layer defining the opening;
[0015] (e) selectively etching the insulating layer in a state
where the second conductive layer and the conductive sidewall
function as etching masks, so that the contact hole having a width
smaller than that of the opening and defined by the conductive
sidewall is formed, and the first conductive layer is exposed
through the contact hole; and
[0016] (f) removing the second conductive layer and the conductive
sidewall.
[0017] The above-mentioned objects of the present invention are
also achieved by a method of forming a structure having a contact
hole comprising the steps of:
[0018] (a) forming an insulating layer on a first conductive
layer;
[0019] (b) forming a second conductive layer on the insulating
layer;
[0020] (c) forming an opening in the second conductive layer;
[0021] (d) forming a conductive sidewall around an inner wall of
the first conductive layer defining the opening;
[0022] (e) selectively etching the insulating layer in a state
where the second conductive layer and the conductive sidewall
function as etching masks, so that the contact hole having a width
smaller than that of the opening and defined by the conductive
sidewall is formed on the insulating layer and the first conductive
layer is exposed through the contact hole;
[0023] (f) forming a barrier layer on the second conductive layer,
the conductive sidewall and the first conductive layer exposed
through the contact hole; and
[0024] (g) forming a third conductive layer on the barrier layer,
the barrier layer preventing the third conductive layer from
reacting with the second conductive layer and the conductive
sidewall.
[0025] The above-mentioned objects of the present invention are
also achieved by a method of forming a structure having a contact
hole comprising the steps of:
[0026] (a) forming an insulating layer on a first conductive
layer;
[0027] (b) forming a second conductive layer on the insulating
layer;
[0028] (c) forming an opening in the second conductive layer;
[0029] (d) forming a conductive sidewall around an inner wall of
the first conductive layer defining the opening;
[0030] (e) selectively etching the insulating layer in a state
where the second conductive layer and the conductive sidewall
function as etching masks, so that the contact hole having a width
smaller than that of the opening and defined by the conductive
sidewall is formed, and the first conductive layer is exposed
through the contact hole; and
[0031] (f) forming a third conductive layer on the second
conductive layer, the conductive sidewall and the member exposed
through the contact hole,
[0032] wherein:
[0033] the second conductive layer comprises polysilicon;
[0034] the conductive sidewall comprises polysilicon; and
[0035] the third conductive layer comprises tungsten.
[0036] The aforementioned objects of the present inventoin are
achieved by a method of forming a structure having a contact hole
comprising the steps of:
[0037] (a) forming an insulating layer on a first conductive
layer;
[0038] (b) forming a second conductive layer on the insulating
layer;
[0039] (c) forming a first opening in the second conductive
layer;
[0040] (d) selectively growing a third conductive layer on the
second conductive layer and an inner wall of the second conductive
layer defining the first opening, so that a second opening defined
by the third conductive layer and having a width smaller than that
of the first opening is formed; and
[0041] (e) selectively etching the insulating layer in a state
where the third conductive layer functions as an etching mask, so
that the contact hole having a width substantially identical to the
second opening defined by the third conductive layer is formed, and
the first conductive layer is exposed through the contact hole.
[0042] Another object of the present invention is to provide a
layer structure having a contact hole as formed by the
above-mentioned methods.
[0043] This object of the present invention is achieved by a layer
structure comprising:
[0044] a first conductive layer;
[0045] an insulating layer formed on the first conductive layer and
having a contact hole, the first conductive layer being exposed
through the contact hole;
[0046] a second conductive layer formed on the insulating layer and
having an opening having a width larger than that of the contact
hole;
[0047] a conductive sidewall formed on the insulating layer exposed
through the opening and formed around an inner wall of the second
conductive layer defining the opening, the conductive sidewall
having a width substantially equal to that of the contact hole;
[0048] a barrier layer formed on the second conductive layer, the
conductive sidewall and the first conductive layer exposed through
the contact hole; and
[0049] a third conductive layer formed on the barrier layer, the
barrier layer preventing the third conductive layer from reacting
with the second conductive layer and the conductive sidewall.
[0050] The above-mentioned object of the present invention is
achieved by a layer structure comprising:
[0051] a first conductive layer;
[0052] an insulating layer formed on the first conductive layer and
having a contact hole, the first conductive layer being exposed
through the contact hole;
[0053] a second conductive layer formed on the insulating layer and
having a first opening having a width larger than that of the
contact hole;
[0054] a third conductive layer formed on the insulating layer
exposed through the first opening and the second conductive layer
and formed around an inner wall of the second conductive layer
defining the first opening, the third conductive layer defining a
second opening having a width substantially equal to that of the
contact hole, the second opening being continuously connected to
the contact hole;
[0055] a barrier layer formed on the third conductive layer and the
first conductive layer exposed through the contact hole; and
[0056] a fourth conductive layer formed on the barrier layer, the
barrier layer preventing the fourth conductive layer from reacting
with the third conductive layer and the conductive sidewall.
[0057] The above-mentioned object of the present invention is also
achieved by a layer structure comprising:
[0058] a first conductive layer;
[0059] an insulating layer formed on the first conductive layer and
having a contact hole, the first conductive layer being exposed
through the contact hole;
[0060] a second conductive layer formed on the insulating layer and
having an opening having a width larger than that of the contact
hole;
[0061] a conductive sidewall formed on the insulating layer exposed
through the opening and formed around an inner wall of the second
conductive layer defining the opening, the conductive sidewall
having a width substantially equal to that of the contact hole;
and
[0062] a third conductive layer formed on the second conductive
layer, the conductive sidewall and the first conductive layer
exposed through the contact hole,
[0063] wherein the third conductive layer comprises a material
which causes no reaction with the second conductive layer and the
conductive sidewall.
[0064] According to the present invention, there is also provided a
dynamic random access memory having any of the above-mentioned
structures.
[0065] According to the present invention, there is also provided a
fin-shaped capacitor and a method for producing such a fin-shaped
capacitor.
BRIEF DESCRIPTION OF THE DRAWINGS
[0066] Other objects, features and advantages of the present
invention will become more apparent from the following detailed
description when read in conjunction with the accompanying
drawings, in which:
[0067] FIG. 1A through FIG. 1H are cross-sectional views showing
steps of an improved method for producing a layer structure having
a contact hole according to a first preferred embodiment of the
present invention;
[0068] FIG. 2 is a cross-sectional view showing a second preferred
embodiment of the present invention;
[0069] FIGS. 3A through 3D are cross-sectional views showing a
third preferred embodiment of the present invention;
[0070] FIG. 4 is a cross-sectional view showing a fourth preferred
embodiment of the present invention;
[0071] FIG. 5 is a cross-sectional view showing a fifth preferred
embodiment of the present invention;
[0072] FIGS. 6A through 6N are cross-sectional views showing steps
of a DRAM production method according to a sixth preferred
embodiment of the present invention;
[0073] FIG. 7 is a plan view of a DRAM produced by the sixth
preferred embodiment of the present invention;
[0074] FIGS. 8A through 8E are cross-sectional views showing a
seventh preferred embodiment of the present invention;
[0075] FIGS. 9A and 9B are cross-sectional views showing a first
variation of the sixth preferred embodiment of the present
invention;
[0076] FIG. 10 is a cross-sectional view showing a second variation
of the sixth preferred embodiment of the present invention;
[0077] FIGS. 11A through 11J are cross-sectional views showing an
eighth preferred embodiment of the present invention;
[0078] FIGS. 12A through 12G are cross-sectional views showing a
ninth preferred embodiment of the present invention;
[0079] FIGS. 13A through 13F are cross-sectional views showing a
variation of the ninth preferred embodiment of the present
invention;
[0080] FIGS. 14A through 14G are cross-sectional views showing a
modification of the variation shown in FIGS. 13A through 13F;
and
[0081] FIGS. 15A through 15J are cross-sectional views showing a
tenth preferred embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0082] A description will now be given of a first preferred
embodiment of the present invention with reference to FIG. 1A
through FIG. 1H.
[0083] Referring to FIG. 1A, a conductive layer 2 formed of, for
example, polysilicon, is formed on a base 1 formed of an insulator,
such as SiO.sub.2. The polysilicon layer 2 is a word line of a
DRAM, for example. An insulating layer 3 formed of, for example,
BPSG (boron-phosphosilicate glass), is grown to, for example, 0.5
.mu.m on the entire surface by a CVD process. The BPSG layer 3 is
heated in a wet atmosphere at 850.degree. C. for 10 minutes, and
reflown, so that a substantially flat surface of the BPSG layer 3
can be formed. Then, a polysilicon layer 4 is grown to, for
example, 1000 angstrom by the CVD process. After that, a
photoresist film 5 is coated, and etched by the conventional
photolithography technique, so that the photoresist film 5
functions as an etching resist having a hole pattern can be formed.
Subsequently, the polysilicon layer 4 is selectively etched by an
RIE (reactive ion etching) process in which a CCl.sub.4/O.sub.2 gas
is used and the photoresist film 5 functions as an etching mask.
Thereby, a first opening 6 having a width (diameter) approximately
equal to 0.5 .mu.m is formed in the polysilicon layer 4.
[0084] As shown in FIG. 1B, a polysilicon layer 7 is grown to, for
example, 1500 angstroms on the entire surface including the first
opening 6 by CVD. Then, as shown in FIG. 1C, the polysilicon layer
7 is selectively etched by the RIE process using a
CCl.sub.4/O.sub.2 gas, so that a sidewall 8 is formed on an inner
wall (sidewall) of the first opening 6 formed in the polysilicon
layer 4. The sidewall 8 defines a second opening 9 having a width
approximately equal to 0.2 .mu.m.
[0085] As shown in FIG. 1D, the BPSG layer 3 is selectively etched
in an RIE process using a CHF.sub.3/He gas in which the polysilicon
layer 4 and the sidewall 8 function as masks. Thereby, a contact
hole 10 through which the polysilicon layer 2 is partially exposed
is formed in the BPSG layer 3.
[0086] As shown in FIG. 1E, a photoresist film 11 is formed on the
entire surface including the contact hole 10. Then, as shown in
FIG. 1F, the entire surface of the photoresist film 11 is exposed
and developed. During this process, a small amount of light enters
a bottom portion of the contact hole 10. Thus, a part of the
photoresist film 11 is left in the contact hole 10. The polysilicon
layer 4 and the sidewall 18 are dry-etched in a CF.sub.4/O.sub.2
plasma atmosphere in a state where the polysilicon layer 2 is
protected against dry etching due to the existence of the
photoresist film 11 in the contact hole 10. During the dry etching
process, the polysilicon layer 4 and the sidewall 8 are
isotropically etched. After that, the photoresist film 11 is
removed in an O.sub.2 plasma.
[0087] After that, an Al alloy (or Al) 12 is deposited on the upper
surface including the contact hole 10 by a sputtering process.
Then, the Al alloy layer 12 is etched, so that a desired Al (or Al
alloy) pattern is formed. Thereby, the polysilicon word line 2 is
connected to the Al alloy layer 12 via the contact hole 10. It will
be noted that the contact hole 10 has a width smaller than the
feature scale limit of the conventional photolithographic
technique. It will also be noted that the above-mentioned
production method is suitable for forming a contact hole for
connecting the word line and the word-line shunt layer which is
provided for preventing the occurrence of a delay in transmitting a
signal via the word line.
[0088] The BPSG layer 3 can be substituted for a stacked member in
which a PSG layer and an SiO.sub.2 layer are alternately stacked.
It is also possible to employ an alternative step instead of the
step shown in FIG. 1H. In the alternative step, after the
polysilicon layer 4 and the sidewall 8 are removed, the BPSG layer
3 is reflowed by heating the device in an N.sub.2 atmosphere at
850.degree. C. for 20 minutes, so that an upper edge of the contact
hole 10 is smoothly curved. The existence of such a smoothly curved
upper edge of the contact hole 10 improves the coverage of the Al
alloy layer 12.
[0089] A description will now be given of a second preferred
embodiment of the present invention with reference to FIG. 2. A
layer structure shown in FIG. 2 is the same as that shown in FIG.
1B except that an SiO.sub.2 layer 13 is formed on the polysilicon
layer 4. More specifically, the SiO.sub.2 film 13 is grown to, for
example, about 200 angstroms on the polysilicon layer 4 by CVD.
Then, the photoresist film 5 shown in FIG. 1A is formed on the
entire surface. After that, the first opening 6 is formed in the
SiO.sub.2 layer 13 and the polysilicon layer 4. Then, the
polysilicon layer 7 is formed on the photoresist film 5 and in the
first opening 6 in the same way as shown in FIG. 1B. Then, the
polysilicon layer 7 is anisotropically etched in the vertical
direction. The SiO.sub.2 layer 13 functions as an etching stopper
during the step shown in FIG. 1C, so that it is possible to prevent
a decrease in the thickness of the polysilicon layer 4. Further, it
becomes easy to detect the end of etching since the SiO.sub.2 layer
13 is exposed. It will be noted that the SiO.sub.2 layer 13 is
removed together with the BPSG layer 3 during the step shown in
FIG. 1E. Thus, it is not necessary to provide a special step to
remove the SiO.sub.2 layer 13.
[0090] A description will now be given of a third preferred
embodiment of the present invention with reference to FIGS. 3A
through 3C, in which those parts which are the same as those shown
in the previous figures are given the same reference numerals.
[0091] Referring to FIG. 3A, the BPSG layer 3 is grown to, for
example, 0.5 .mu.m on the entire surface including the polysilicon
layer (word line) 2 by CVD. Next, the polysilicon layer 4 is grown
to, for example, 1000 angstroms by CVD. Then, the photoresist film
5 is coated, and patterned by the conventional photolithography
technique, so that a hole pattern having a width approximately
equal to 0.5 .mu.m is formed in the photoresist film 5. After that,
the polysilicon layer 4 is selectively removed by an RIE process
using a CCl.sub.4/O.sub.2 gas in which the photoresist film 5
serves as a mask, so that the first opening 6 is formed in the
polysilicon layer 4.
[0092] As shown in FIG. 3B, a polysilicon layer 14 is selectively
grown on the upper surface of the polysilicon layer 4 and a side
surface thereof by a CVD process in which the device is maintained
at 650.degree. C. and an SiH.sub.4+HCl+H.sub.2 gas is used. The
polysilicon layer 14 defines a second opening 15 having a width
smaller than that of the first opening 6. It is easy to control the
thickness of the polysilicon layer 14, that is, easy to control the
width of the second opening 15.
[0093] Then, as shown in FIG. 3C, the BPSG layer 3 is removed via
the second opening 15 by an RIE process using a CHF.sub.3/He gas,
so that the contact hole 10 is formed and the polysilicon layer 2
is partially exposed through the contact hole 10. Finally, a
stakced layer 16 fomed of a Ti/TiN layer 16 is formed on the
polysilicon layer 14, and an Al alloy (or Al) layer 17 is formed on
the stacked layer 16, as shown in FIG. 3D. The stacked laye 16 will
be described in detail later.
[0094] A description will now be given of a fourth preferred
embodiment of the present invention with reference to FIG. 4, in
which those parts which are the same as those shown in the previous
figures are given the same reference numerals. In the step shown in
FIG. 1G, the polysilicon layer 4 and the sidewall 8 are removed, on
the other hand, according to the fourth embodiment of the present
invention, as shown in FIG. 4, the polysilicon layer 4 and the
sidewall 8 are not removed, but left on the BPSG layer 3. After the
layer structure shown in FIG. 1D is obtained, the stacked layer 16
is formed on the entire surface including the polysilicon layer 4,
the sidewall 8 and the exposed surface of the polysilicon layer 2
by CVD, for example. The stacked layer 16 consists of a Ti layer
having a thickness of 200 angstroms and a TiN layer having a
thickness of 1000 angstroms. Hereafter, the stacked layer 16 is
referred to as a Ti/TiN layer 16. After the Ti/TiN layer 16 is
formed, the Al alloy (or pure Al) 17 is deposited on the Ti/TiN
layer 16 by sputtering. After that, the polysilicon layer 4, the
Ti/TiN layer 16 and the Al alloy layer 17 are patterned by
etching.
[0095] It will be noted that if the Al alloy layer (or pure Al
layer) 17 is deposited directly on the polysilicon layer 4 and the
polysilicon sidewall 8, it will easily react to silicon in the
layer 4 and the sidewall 8 during a subsequent annealing process in
which a protection cover is formed, for example. The above reaction
increases the resistance of the Al alloy layer 17. The Ti/TiN layer
16 functions as a barrier layer which prevents the above-mentioned
reaction. The barrier layer 16 is not limited to the Ti/TiN
layer.
[0096] A description will now be given of a fifth preferred
embodiment of the present invention with reference to FIG. 5, in
which those parts which are the same as those shown in the previous
figures are given the same reference numerals. The fifth embodiment
shown in FIG. 5 has the left polysilicon layer 4 and the
polysilicon sidewall 8, and uses a W (tungsten) layer functioning
as a wiring line instead of the Al alloy (or pure Al) layer 17
shown in FIG. 4. The use of the W layer 18 does not need the
deposition of the Ti/TiN layer 16.
[0097] After the layer structure shown in FIG. 1D is obtained, the
W layer 18 is grown to, for example, 5000 angstroms on the entire
surface including the polysilicon layer 4, the polysilicon sidewall
8 and the exposed surface of the polysilicon layer 2 by CVD. The
contact hole 10 is filled with tungsten, so that the coverage of
the W layer 18 can be improved. It will be noted that it is easy to
fill the contact hole 10 with tungsten by CVD. It will be noted
that tungsten has a poor adhession to BPSG or SiO 2. On the other
hand, as shown in FIG. 5, the W layer 18 is formed on the
polysilicon layer 4 and the polysilicon sidewall 18. Thus, the
adhession problem can be solved.
[0098] A description will now be given of a sixth preferred
embodiment of the present invention with reference to FIG. 6A
through FIG. 6N. The sixth preferred embodiment of the present
invention provides a DRAM having a contact hole defined by a
sidewall.
[0099] Referring to FIG. 6A, an interlayer isolation insulating
layer 22 is grown to, for example, 4000 angstroms on a p-type
silicon substrate 21 by a selective thermal oxidation process (a
local-oxidation-of-silicon process: LOCOS), in which a silicon
nitride layer is used as an oxidation-resistant mask. Next, the
silicon nitride layer serving as the oxidation-resistant mask is
removed, so that active areas in the p-type silicon substrate 21
are exposed. Then, a gate insulating layer 23 having a thickness
equal to, for example, 100 angstroms is formed on the exposed
surfaces of the p-type silicon substrate 21 by a thermal oxidation
process. After that, a polysilicon layer is grown to, for example,
1000 angstroms by CVD. Then, the polysilicon layer is patterned by
a resist process and RIE process in the photolithography technique
in which a CCl.sub.4/O.sub.2 gas is used. Thereby, word lines WL
are formed. After that, As ions are introduced into the p-type
silicon substrate 21 by an ion implantation process in which the
word lines WL and the interlayer isolation insulating layer 2
function as masks. Thereby, an n.sup.+-type source region 24 and an
N.sup.+-type drain region 25 of a transfer transistor of a memory
cell are formed in the p-type silicon substrate 21. The dose of As
ions is equal to, for example, 1.times.10.sup.15 atoms/cm.sup.2.
During a subsequent thermal process, the source and drain regions
24 and 25 are heated. After that, an insulating layer 26 formed of
SiO.sub.2 is grown to, for example, 1000 angstroms by CVD.
[0100] As shown in FIG. 6B, the SiO.sub.2 insulating film 26 is
selectively etched in an RIE process in which a CHF.sub.3/H.sub.2
gas is used, so that a bit line contact hole 24A is formed in the
SiO.sub.2 insulating film 26. It will be noted that if a positional
error occurs in the bit line contact window 24A and thus the word
line WL is partially exposed, an exposed portion of the word line
WL can be compensated for, as will be described later. Thus, it is
sufficient to provide an alignment margin approximately equal to
0.1 .mu.m when the bit line contact window 24A is approximately 0.5
.mu.m in diameter. As will be indicated later, it is preferable to
remove a portion of the SiO.sub.2 insulating layer 26 in a scribe
area defined in a peripheral portion of a chip at the same time as
then the bit line contact hole 24A is formed.
[0101] As shown in FIG. 6C, an SiO.sub.2 insulating layer 41 is
grown to, for example, 1000 angstroms on the entire surface by
CVD.
[0102] After that, as shown in FIG. 6D, the SiO.sub.2 insulating
layer 41 is selectively etched by an anisotropic etching process,
such as, an RIE process using a CHF.sub.3/H.sub.2 gas. By this RIE
process, a sidewall SW1 having an about 0.1 .mu.m thickness is
formed so that it surrounds a vertical inner wall of the bit line
contact window 24A and a curved part of the SiO.sub.2 insulating
layer 26. The sidewall SW1 defines the width of the bit line
contact hole 24A, which is approximately equal to 0.3 .mu.m. It
will be noted that this dimension, 0.3 .mu.m, is considerably
smaller than the scale limit by the conventional photolithography
technique (approximately 0.5 .mu.m). The formation of the sidewall
SW1 contributes to reducing the alignment margin. Even if the word
line WL is partially exposed due to the positional error of the bit
line contact window 24A, the sidewall 24 will completely cover the
exposed surface of the word line WL.
[0103] The above-mentioned contact hole forming process is
distinguished from a known self-alignment contact formation method.
In the self-alignment contact formation method, an insulating layer
corresponding to the SiO.sub.2 insulating layer 26 and a
polysilicon layer provided for the word lines WL are patterned into
an identical shape. Then, sidewalls are formed around windows.
Thus, the windows are automatically defined by the sidewalls, so
that there is no need for any alignment margin. Normally, the
insulating film corresponding to the SiO.sub.2 insulating layer 26
is 2000 angstroms thick, and the underlying polysilicon layer
provided for forming the word lines WL is 1000 angstron's thick.
Thus, the sidewall is about 3000 angstrom high, and is a large step
portion formed on the surface of the substrate. On the other hand,
the process which has been described with reference to FIG. 6D does
not form such a great step surface portion. It should be noted that
the sidewall SW1 is also formed on a step portion on the surface of
the SiO insulating film, so that the slope of the curved surface
portion of the SiO.sub.2 insulating layer 26 can be reduced.
[0104] It is necessary to etch only the SiO.sub.2 insulating layer
41. As has been described previously, the scribe area on the
peripheral portion of the chip is exposed during the process shown
in FIG. 6B. Since the SiO.sub.2 layer 41 is formed on the scribe
area, etching is stopped when the scribe area which is a part of
the p-type silicon substrate 21 appears. This judgment of whether
or not the scribe area has appeared can be carried out by detecting
a change of a plasma emitting state during the RIE process, or by
detecting the film thickness of the scribe area by means of a laser
interference instrument.
[0105] Referring to FIG. 6E, a polysilicon layer is grown to, for
example, 500 angstroms on the entire surface by CVD. Then, As ions
are introduced into the polysilicon layer by an ion implantation
process in which the dose of As ions is equal to 1.times.10.sup.15
atoms/cm.sup.2. After that, a WSi.sub.2 film is formed to, for
example, 500 angstroms on the impurity doped polysilicon layer by
CVD. Then, the WSi.sub.2 layer and the impurity doped polysilicon
layer are patterned by an RIE process using a CCl.sub.4/O.sub.2
gas, so that a bit line BL having a two-layer structure is
formed.
[0106] As shown in FIG. 6F, an insulating layer 27 formed of
Si.sub.3N.sub.4, a spacer layer 28 formed of SiO.sub.2 and a
polysilicon layer 29' which forms a part of a storage electrode
(fin electrode) of a stacked capacitor are grown in this order by
CVD. The Si.sub.3N.sub.4 insulating layer 27, the SiO.sub.2 spacer
layer 28 and the polysilicon layer 29' are, for example, 1000, 500
and 1000 angstroms, respectively. It will be noted that the
polysilicon layer 29' plays the important role, as will be
described later.
[0107] As shown in FIG. 6G, the polysilicon layer 29' is
selectively etched by the resist process and RIE process using a
CCl.sub.4/O.sub.2 gas in the conventional photolithography
technique, so that an opening 29A having the same pattern as the
storage electrode contact window is formed in the polysilicon layer
29'. During the selective etching process, it is preferable to
remove a part of the polysilicon layer 29' on the scribe area in
the chip peripheral region. The opening 29A has a width
approximately equal to 0.5 .mu.m, which is the scale limit attained
by the conventional photolithography technique.
[0108] As shown in FIG. 6H, a polysilicon layer 32a is grown to,
for example, 1000 angstroms by CVD. Then, as shown in FIG. 6I, the
polysilicon layer is anisotropically etched by an RIE process using
a CCl.sub.4/O.sub.2 gas. Thereby, a sidewall 32 formed of
polysilicon around the inner surface of the opening 29A in the
polysilicon layer is left on the SiO.sub.2 spacer layer 28. The
sidewall 32 is approximately 0.1 .mu.m thick. As a result, the
opening 29A is reshaped into an opening 32A having a width of about
0.3 .mu.m. This dimension of the reshaped opening 29A is smaller
than the scale limit by the conventional photolithography
technique.
[0109] The polysilicon layer 29' and the polysilicon sidewall 32
function as masks when the underlying insulating layers are etched
to form the storage electrode contact window. It should be noted
that there is no special limitation on the formation of the
polysilicon layer 29' and the polysilicon sidewall 32, since they
are formed of polysilicon. It should also be noted that the
polysilicon layer 29' and the polysilicon sidewall 32 are not
removed during a subsequent process, and are utilized as parts of
the storage electrode of the stacked capacitor, as will be
described in detail later.
[0110] As shown in FIG. 6J, the SiO.sub.2 aaaspacer layer 28, the
Si.sub.3N.sub.4 insulating layer 27, the SiO.sub.2 insulating layer
26 and the SiO.sub.2 gate insulating layer 23 are selectively
etched by an RIE process in which a CHF.sub.3/H.sub.2 is used and
the polysilicon layer 29' and the polysilicon sidewall 32 function
as the etching masks. By the RIE process, a storage electrode
contact hole 25A is formed in the above-mentioned layers, so that
the n.sup.+-type drain region 25 is partially exposed.
[0111] As shown in FIG. 6K, a polysilicon layer 29" is grown to,
for example, 500 angstroms by CVD. A part of the polysilicon layer
29" completely covers the inner wall of the storage electrode
contact window 25A and the exposed surface of the n.sup.+-type
drain region 25. It is important to form the polysilicon layer 29"
in total contact with the Si.sub.3N.sub.4 insulating layer 27.
Then, As ions are introduced into the polysilicon layers 29" and
29' by an ion implantation process in which the dose of the As ions
is equal to, for example, 8.times.10.sup.15 atoms/cm.sup.2. By this
ion implantation process, each of the polysilicon layers 29" and
29' has a reduced resistance. It will be noted toat the layers
consisting of the polysilicon layers 29' and 29" and the sidewall
32 is thicker than the vertically extending portion of the
polysilicon layer 29".
[0112] Referring to FIG. 6L, a spacer layer 33 formed of SiO.sub.2
is grown to, for example, 500 angstroms on the entire surface by
CVD. After that, the SiO.sub.2 spacer layer 33 is selectively
etched by the resist process and RIE process using a
CHF.sub.3/H.sub.2 gas in the conventional photolithography
technique. By the RIE process, an opening 33A having a belt shape
is formed in the SiO.sub.2 spacer layer 33. It is sufficient to
form the opening 33A so that it is wider than the storage electrode
contact window 25A, because the opening 33A is used for stacking a
polysilicon layer (fin) on the integrated polysilicon layer
consisting of the layers 29" and 29' and the polisilicon sidewall
32.
[0113] Referring to FIG. 6M, a polysilicon layer is grown to, for
example, 1000 angstroms by CVD. After that, As ions are introduced
into the polysilicon layer by an ion implantation process in which
the dose of As ions is equal to, for example, 1.times.10.sup.15
atoms/cm.sup.2. Thereby, the resistance of the polysilicon layer is
reduced. After that, the above polysilicon layer, the SiO.sub.2
spacer layer 33, and the polysilicon layers 29" and 29' are
patterned into an electrode shape by the photoresist process and
RIE process using a gas of CCl.sub.4+O.sub.2 or CHF.sub.3+H.sub.2.
Thereafter, the SiO spacer layer 33 and the SiO.sub.2 spacer layer
28 are completely removed by an etching process in which the device
is placed in an HF etchant. Thereby, polysilicon fins 292 and 291
forming a storage electrode 25 of the stacked capacitor are formed.
The fin 292 has a bottom contact area wider than the contact hole
25A shown in FIG. 6J.
[0114] As has been described previously, the wall of the
Si.sub.3N.sub.4 insulating layer 27 which is a part of the storage
electrode contact window 25A completely makes contact with the
polysilicon layer 29', so that there is no possibility that the
SiO.sub.2 insulating layer 26 and the SiO.sub.2 interlayer
isolation insulating layer 22 are damaged.
[0115] After that, as shown in FIG. 6N, a dielectric film 36 around
an exposed surface of the storage electrode 29 is formed, and a
cell plate 37 (opposed electrode) is formed so that it covers the
entire surface. The dielectric film 36 is formed of, for example,
Si.sub.3N.sub.4. The stacked capacitor is made up of the storage
electrode 29, the dielectric film 36 and the cell plate 37. Then, a
PSG layer 38 is formed on the entire surface, and word-line shunt
layers 39 formed of, for example, an Al alloy, are formed on the
PSG layer 38. FIG. 7 is a plan view of the DRAM fabricated by the
above-mentioned production process. In FIG. 7, WL1 and WL2 indicate
word lines, and BL1 and BL2 indicate bit lines.
[0116] The word-line shunt layers 39 are connected to the
corresponding word lines WL via contact holes (not shown for the
sake of simplicity). It is preferable to form such contact holes by
the aforementioned first through fifth embodiments of the present
invention.
[0117] It can be seen from FIG. 6K that the lowermost polysilicon
fin 29.sub.1 has the sidewall 32, and the polysilicon layers 29'
and 29". The polysilicon layer 29" is thicker than the polysilicon
layer 29', and the largest thickness of the sidewall 32 is
approximately equal to the thickness of the polysilicon layer
29'.
[0118] A description will now be given of an eighth embodiment of
the present invention with reference to FIGS. 8A through 8E, in
which those parts which are the same as those shown in the previous
figures are given the same reference numerals. The eighth
embodiment of the present invention utilizes the steps which have
been described with reference to FIGS. 6A through 6L. After the
step related to FIG. 6L, a step shown in FIG. 8A is carried out. A
polysilicon layer is grown to, for example, 1000 angstroms on the
entire surface.
[0119] After that, as shown in FIG. 8B, an insulating layer 34
formed of SiO.sub.2 is grown to, for example, 2000 angstroms by
CVD. Then, the SiO.sub.2 insulating film 34 is patterned into the
shape of the storage electrode by the resist process and RIE
process using a CHF.sub.3/H.sub.2 gas in the photolithography
technique, so that openings are formed in the SiO.sub.2 insulating
film 34. Each of the openings is approximately 0.5 .mu.m wide,
which corresponds to the scale limit of the conventional
photolithography technique.
[0120] Then, an insulating layer 35 formed of SiO.sub.2 is grown
to, for example, 1000 angstroms on the entire surface by CVD.
Thereafter, the SiO.sub.2 insulating layer 35 is anisotropically
etched by an RIE process using a CHF.sub.3 and H.sub.2 gas.
Thereby, sidewalls 35 are formed around inner walls of the openings
in the SiO.sub.2 layer 34, and the rest thereof is removed. Each
sidewall 35 defines an opening 35A having a width approximately
equal to 0.3 .mu.m, which is smaller than the scale limit of the
conventional photolithography technique.
[0121] Then, as shown in FIG. 8C, the polysilicon layer 42, the
SiO.sub.2 spacer layer 33, and the polysilicon layers 29" and 29'
are patterned into the shape of the storage electrode by an RIE
process in which a CHF.sub.3/H.sub.2 gas is used and the SiO.sub.2
insulating layer 34 and the SiO.sub.2 sidewalls 15 function as
etching masks. It should be noted that the distance between
opposite portions of the polysilicon layer 42 is approximately 0.3
.mu.m. Similarly, the distance between opposite portions of the
polysilicon layer consisting of the polysilicon layer 29" and 29'
is also approximately 0.3 .mu.m. This means that the adjacent
storage electrodes are very close to each other, and thus the
surface area of each storage electrode is increased, so that each
stacked capacitor can have an increased capacitance.
[0122] It will be noted that during etching of the SiO.sub.2 spacer
layer 33, the SiO.sub.2 insulating layer 34 and the SiO.sub.2
sidewalls 35 serving as etching masks are also etched. From this
point of view, it is necessary for the layer 34 and the sidewalls
35 to have a sufficient thickness. Further, a special step to
remove the SiO.sub.2 insulating layer 34 and the SiO.sub.2
sidewalls 35 is not needed because the SiO.sub.2 insulating layer
34 and the sidewalls 35 are removed during a subsequent step in
which the device is placed in an HF etchant, as shown in FIG.
8D.
[0123] After that, a process identical to that which has been
described with reference to FIG. 6N is carried out. FIG. 8E shows a
DRAM fabricated according to the seventh preferred embodiment of
the present invention. A storage electrode 40 has two stacked
polysilicon fins 40.sub.1 and 40.sub.2. The polysilicon fin 401
corresponds to the patterned polysilicon layers 29" and 29' and the
polysilicon sidewall 32, and the polysilicon fin 402 corresponds to
the patterned polysilicon layer 42. It can be seen from FIG. 6N and
FIG. 8E that the adjacent stacked capacitors shown in FIG. 8E are
closer to each other than those shown in FIG. 6N.
[0124] A description will now be given of a first variation of the
aforementioned sixth preferred embodiment of the present invention,
with reference to FIGS. 9A and 9B, in which those parts which are
the same as those shown in the previous figures are given the same
reference numerals. The first variation has a storage electrode
having only the polysilicon fin 29.sub.1 which consists of the
polysilicon layers 29" and 29' and the polysilicon sidewall 32.
After the step which has been described with reference to FIG. 6K,
the polysilicon layer consisting of the polysilicon layers 29" and
29' and the polysilicon sidewall 32 is patterned into the shape of
the storage electrode. After that, the device is placed in an HF
etchant, so that the insulating layer 28 is completely removed, as
shown in FIG. 9A. Then, the process which has been described
previously with reference to FIG. 6N is carried out, so that a DRAM
shown in FIG. 9B can be obtained. It 1 is noted that the insulating
layer 27 can be formed of SiO.sub.2 or Si.sub.3N.sub.4. As shown in
FIG. 9B, the fin 29.sub.1 is thicker than a vertically extending
portion of the storage electrode.
[0125] FIG. 10 illustrates a second variation of the aforementioned
sixth preferred embodiment of the present invention. In FIG. 10,
those parts which are the same as those shown in the previous
figures are given the same reference numerals. The polysilicon fin
29.sub.1 consisting of the polysilicon layers 29" and 29' and the
polysilicon sidewall 32 is formed directly on the insulating layer
27 formed of SiO.sub.2 or Si.sub.3N.sub.4. The polysilicon layer
29' shown in FIG. 6F is grown on the insulating layer 27 without
forming the insulating layer 28. Then, the same steps as has been
described with reference to FIGS. 6G through 6K and FIG. 6N are
carried out. It is also possible to form the polysilicon fin
29.sub.2 on the polysilicon fin 29.sub.1 in the same way as has
been described with reference to FIGS. 6L and 6M.
[0126] A description will now be given of an eighth preferred
embodiment of the present invention with reference to FIGS. 11A
through 11J, in which those parts which are the same as shown shown
in the previous figures are given the same reference numerals. A
structure shown in FIG. 11B is the same as that shown in FIG. 6E.
Steps to obtain the structure shown in FIG. 11B are the same as
those which have been described with reference to FIGS. 6A through
6E.
[0127] As shown in FIG. 11C, the Si.sub.3N.sub.4 insulating layer
27, the SiO.sub.2 spacer layer 28, the impurity-doped polysilicon
layer 29', a spacer layer 45 formed of SiO.sub.2 and an
impurity-doped polysilicon layer 46' are formed in this order by
CVD. For example, each of these layers is 500 angstorms thick.
Then, the polysilicon layer 46', the SiO.sub.2 spacer layer 45 and
the polysilicon layer 29' are selectively etched by the resist
process and the RIE process, so that an opening 29A having a
thickness equal to, for example, 0.6 .mu.m is formed therein.
During the above RIE process, a CCl.sub.4/O.sub.2 gas is used for
the polysilicon layers 46' and 29', and a CHF.sub.3/He gas is used
for the SiO.sub.2 spacer layer 45.
[0128] As shown in FIG. 11D, a polysilicon layer 47' is grown to,
for example, 2000 angstorms on the entire surface by CVD. After
that, as shown in FIG. 11E, the polysilicon layer 47' is
anisotropically etched by an RIE process in which a
CCl.sub.4/O.sub.2 gas or an HBr/He gas is used. Thereby, a
polysilicon sidewall 47 is formed around an inner surface of the
opening 29A, and the remaining portion of the polysilicon layer 47'
is removed. The sidewall 47 defines a new opening 46A having a
width approximately equal to 0.2-0.3 .mu.m, which is smaller than
the width of the opening 29A shown in FIG. 11C.
[0129] After that, as shown in FIG. 11F, the SiO.sub.2 spacer layer
28, the Si.sub.3N.sub.4 insulating layer 27, the SiO.sub.2
insulating layer 26 and the SiO.sub.2 gate insulating layer 23 are
partially removed by an RIE process in which a CHF.sub.3/He gas is
used and the polysilicon layer 46' and the polysilicon sidewall 47
function as etching masks. By this RIE process, the surface of the
n.sup.+-type drain region 25 is partially exposed through a contact
hole 28A.
[0130] It should be noted that the width of the opening 46A is very
small and equal to about 0.2-0.3 .mu.m, and that the polysilicon
layer 46' and the polysilicon layer 47 functioning as the etching
masks form a part of the storage electrode without being removed.
Thus, it is not necessary to provide a special step to remove the
polysilicon layer 46' and the polysilicon sidewall 47 functioning
the etching masks.
[0131] As shown in FIG. 11G, a polysilicon layer 46" is grown to,
for example, 500 angstroms by CVD. During this step, the
polysilicon layers 46" and 46' as well as the polysilicon sidewall
47 are integrated.
[0132] Then, as shown in FIG. 11H, the polysilicon layers 46" and
46', the SiO.sub.2 spacer layer 45, and the polysilicon layer 29'
are patterned into the shape of the storage electrode in this order
by the resist process using a single mask and the RIE process in
the conventional photolithography process.
[0133] After that, as shown in FIG. 11I, the device shown in FIG.
11H is placed in an HF etchant, so that the exposed SiO.sub.2
insulating layers are isotropically etched, so that a storage
electrode 50 having two polysilicon fins 50.sub.1 and 50.sub.2 is
formed. The fin 50.sub.1 is formed of the patterned polysilicon
layer 29', and the fin 502 is formed of the patterned polysilicon
layers 46" and 46'. The fins 50.sub.1 and 50.sub.2 are connected by
the polysilicon sidewall 47. The polysilicon layer 46" which is a
part of the fin 50.sub.2 vertically extends from its portion on the
polysilicon layer 46' and makes contact with the n.sup.+-type drain
region 25. A vertical portion 50.sub.3 of the storage electrode 50
consists of the polysilicon sidewall 47 and the polysilicon layer
46". The vertical portion 50.sub.3, the polysilicon layer 46", and
the fin 50.sub.2 have mutually different thicknesses t.sub.1,
t.sub.2 and t.sub.3, respectively. The vertical portion 503 is
thicker than the polysilicon layer 46" and the fin 50.sub.2.
[0134] Finally, as shown in FIG. 11J, the dielectric film 36, the
cell plate 37, the PSG passivation layer 38 and the word-line shut
layers 39 are formed in the same way as has been described with
reference to FIG. 6N.
[0135] A description will now be given of a ninth preferred
embodiment of the present invention with reference to FIGS. 12A
through 12G, in which those parts which are the same as those shown
in the previous figures are given the same reference numerals.
[0136] Production steps shown in FIGS. 12A and 12B are carried out
in the same way as those shown in FIGS. 11A and 11B. After that, as
shown in FIG. 12C, the Si.sub.3N.sub.4 insulating layer 27, the
SiO.sub.2 spacer layer 28, the impurity-doped polysilicon layer
29', the SiO.sub.2 spacer layer 45 and the impurity-doped
polysilicon layer 46' are formed in this order by CVD. Each of
these layers is 500 angstroms thick, for example. Then, the
polysilicon layer 46', the SiO.sub.2 spacer layer 45, the
polysilicon layer 29' and the SiO.sub.2 spacer layer 28 are
selectively etched by the resist process and RIE process, so that
an opening 28A is formed therein. It will be noted that the
SiO.sub.2 layer 28 is etched as shown in FIG. 12C, while the
SiO.sub.2 layer 28 shown in FIG. 11C is not etched.
[0137] After that, as shown in FIG. 12D, a polysilicon layer 47' is
grown to, for example, 2000 angstorms by CVD. After that, as shown
in FIG. 12E, the polysilicon layer 47' is selectively etched by an
RIE process using a CCl.sub.4/O.sub.2 gas, so that a polysilicon
sidewall 47a is formed so that it surrounds the inner wall of the
opening 28A. The remaining portion of the polysilicon layer 47' is
completely removed. The polysilicon sidewall 47a defines a new
opening 46A narrower than the opening 28A.
[0138] Subsequently, as shown in FIG. 12F, the Si.sub.3N.sub.4
insulating layer 27, the SiO.sub.2 insulating layer 26 and the
SiO.sub.2 gate insulating layer 23 are selectively etched by an RIE
process in which a CHF.sub.3/He gas is used and the polysilicon
layer 46' and the sidewall 47a function as etching masks. By this
RIE process, the surface of the n.sup.+-type drain region 25 is
partially exposed through a through hole 27A having the same width
as the opening 46A. After that, the aforementioned production steps
are carried out, so that a DRAM shown in FIG. 12G can be
obtained.
[0139] The length of the sidewall 37a used in the ninth embodiment
of the present invention is greater than that of the sidewall 37
used in the eighth embodiment of the present invention. Thus, the
sidewall 47a functions as the mask more stably than the sidewall
47. On the other hand, the distance between the sidewall 37a and
the word line WL is closer than the corresponding distance obtained
in the eighth embodiment of the present invention. Thus, the
breakdown voltage of the DRAM shown in FIG. 12G is slightly smaller
than that of the DRAM shown in FIG. 11J.
[0140] A description will now be given of a variation of the ninth
preferred embodiment of the present invention with reference to
FIGS. 13A through 13F, in which those parts which are the same as
those shown in the previous figures are given the same reference
numerals. FIGS. 13A and 13B are the same as FIGS. 11A and 11B.
Then, as shown in FIG. 13C, the Si 3N4 insulating layer 27, the
SiO.sub.2 layer 28, the impurity-doped polysilicon layer 29', the
SiO.sub.2 spacer layer 45 and the impurity-doped polysilicon layer
46' are formed in this order by the aforementioned process. Then,
an SiO.sub.2 insulating layer 48 is grown to, for example, 200
angstroms by CVD.
[0141] Then, by using the resist process and the RIE process in the
photolithography process, the SiO.sub.2 layer 48, the polysilicon
layer 46', the SiO.sub.2 spacer layer 45, the polysilicon layer 29'
and the SiO.sub.2 spacer layer 28 are selectively removed, so that
the surface of the Si.sub.3N.sub.4 layer 27 is partially exposed
through the opening 28A.
[0142] Then, as shown in FIG. 13D, the polysilicon layer 47' is
grown to, for example, 2000 angstorms by CVD. After that, as shown
in FIG. 13E, the polysilicon layer 47' is selectively etched by
RIE, so that a widewall 42b is formed around an inner wall of the
opening 28A.
[0143] After that, as shown in FIG. 13F, the Si.sub.3N.sub.4 layer
27, the SiO.sub.2 layer 26 and the SiO.sub.2 gate insulating layer
23 are selectively etched via the opening defined by the sidewall
47b. The SiO.sub.2 layer 48 is removed at the same time as the
SiO.sub.2 insulating layer 26 is removed.
[0144] It will be noted that the SiO.sub.2 layer 48 functions to
protect the polysilicon layer 46' against the RIE process of
forming the sidewall 47b. Further, the SiO.sub.2 layer 48 functions
as the mask more stably during the time when the Si.sub.3N.sub.4
insulating layer 27 is being etched.
[0145] A description will now be given of a modification of the
variation shown in FIGS. 13A through 13F, with reference to FIGS.
14A through 14G, in which those parts which are the same as those
shown in the previous figures are given the same reference
numerals. FIGS. 14A and 14B are the same as FIGS. 11A and 11B,
respectively.
[0146] After forming the bit line BL, as shown in FIG. 14C, an SOG
(spin on glass) layer 49 is formed on the entire surface so that
the surface of the SOG layer 49 is substantially flat enough to
prevent the growth of residuum during a subsequent process. There
is a possibility that residuum may be formed on a rough surface
after the selective etching process. For example, in the variation
which has been described with reference to FIGS. 13A through 13F,
the SiO.sub.2 layer 48 may be partially left on a rough surface
portion of the polysilicon layer 46'. For the sake of simplicity,
FIG. 14C shows that the SOG layer 49 is completely flat. It can be
seen from FIG. 14C, the SOG layer 49 absorbs a roughness of the
surface shown in FIG. 14B. It is also possible to form a PSG reflow
layer instead of the SOG layer 49. After that, the layers 28, 29'
45, 46' and 48 are formed in the same way as has been described
previously. Then, these layers are selectively etched, so that the
opening 28A is formed, as shown in FIG. 14C.
[0147] Then, as shown in FIG. 14D, the polysilicon layer 47' is
grown to, for example, 2000 angstroms by CVD, and selectively
etched by the RIE process, so that a sidewall 47b is formed, as
shown in FIG. 14E. Thereafter, as shown in FIG. 14F, the
Si.sub.3N.sub.4 insulating layer 27, the SOG layer 49, the
sio.sub.2 layer 26 and the SiO.sub.2 layer 23 are selectively
etched, so that the n.sup.+-type drain region 25 is partially
exposed through the opening 27A. Finally, a DRAM shown in FIG. 14G
is fabricated by the aforementioned process which has been
described with reference to FIG. 6N.
[0148] A description will now be given of a tenth preferred
embodiment of the present invention with reference to FIGS. 15A
through 15J, in which those parts which are the same as those shown
in the previous figures are given the same reference numerals.
FIGS. 15A and 15B are the same as FIGS. 11A and 11B,
respectively.
[0149] Referring to FIG. 11C, after forming an Si.sub.3N.sub.4
layer 62 by CVD, three bilayer structures, each having an SiO.sub.2
insulating layer having a thickness of 500 angstroms and a
polysilicon layer having a thickness of 500 angstroms, are
successively grown by CVD. The first bilayer structure consists of
an SiO.sub.2 insulating layer 63 and a polysilicon layer 64. The
second bilayer structure consists of an SiO.sub.2 insulating layer
65 and a polysilicon layer 66. The third bilayer structure consists
of an SiO.sub.2 insulating layer 67 and a polysilicon layer 68.
After that, an SiO.sub.2 insulating layer 69 having a thickness of
100 angstroms, a polysilicon layer 70 having a thickness of 2000
angstorms and an SiO.sub.2 insulating layer 71 having a thickness
of 100 angstroms are successively grown in this order by CVD. Then,
a photoresist film 72 having a window pattern is placed on the
SiO.sub.2 insulating layer 71, and the SiO.sub.2 insulating layer
71 and the polysilicon layer 70 are etched, so that an opening 70A
is formed. The size of the opening 70A is approximately 0.5 .mu.m,
which is the scale limit in the conventional photolithography
technique.
[0150] Referring to FIG. 15D, the photoresist film 72 is removed,
and a polysilicon layer is grown to, for example, 1500 angstroms on
the entire surface. Then, the polysilicon layer is anisotropically
etched by an RIE process using an HBr/He gas, so that a polysilicon
sidewall 74 is formed around an inner wall of the opening 70A. The
polysilicon sidewall 74 defines a new opening 70B having a size
approximately equal to 0.2 .mu.m.
[0151] After that, as shown in FIG. 15E, the SiO.sub.2 insulating
layer 69 and the polysilicon layer 68 are anisotropically etched by
an RIE process in which the polysilicon layer 70 and the sidewall
74 function as etching masks. During the time when the SiO.sub.2
insulating layer 69 is being etched, the SiO.sub.2 insulating layer
71 is removed. Further, during the time when the polysilicon layer
68 is being etched, the polysilicon layer 70 decreases by
approximately 700 angstroms, so that a portion thereof having a
thickness of about 1300 angstroms is left. After that, the
SiO.sub.2 insulating layer 67 is removed in an RIE process using a
CHF.sub.3/H.sub.2 gas in which the polysilicon layer 70 and the
sidewall 74 function as etching masks. During this etching process,
there is little decrease in the thicknesses of the polysilicon
layer 70 and the sidewall 74 because the CHF.sub.3/H.sub.2 gas acts
to SiO.sub.2 greatly. After that, the polysilicon layer 66 and the
SiO.sub.2 insulating layer 65 are removed in the same way as has
been described above. During this etching process, each of the
polysilicon layer 70 and the sidewall 74 decreases by about 700
angstroms, so that they are approximately 600 angstroms thick.
[0152] As shown in FIG. 15F, the polysilicon layer 64 is removed by
RIE. During this RIE process, the polysilicon layer 70 and the
sidewall 74 are also removed. It will be noted that the SiO.sub.2
insulating layer 69 prevents the underlying polysilicon layer 68
from being etched even if over-etching is carried out. It is
preferable to carry out over-etching so that the polysilicon layer
70 and the sidewall 74 are completely removed.
[0153] Then, as shown in FIG. 15G, the SiO.sub.2 insulating layer
63 is removed in an etching process in which the polysilicon layer
68 functions as a mask. During this etching, the SiO insulating
layer 69 is 2 also removed. Subsequently, the Si 3N4 insulating
layer 62 is etched, and the SiO.sub.2 insulating layer 26 and
SiO.sub.2 gate insulating layer 23 are etched. Thereby, a window
formed in the layers 68 through 23 is formed, as shown in FIG.
15G.
[0154] Then, referring to FIG. 15H, a polysilicon layer 75 is grown
to, for example, 500 angstroms on the entire surface including the
window shown in FIG. 15G. After that, the polysilicon layers 75 and
68, the SiO.sub.2 insulating layer 67, the polysilicon layer 66,
the SiO.sub.2 insulating layer 65, and the polysilicon layer 64 are
patterned into the shape of the storage electrode. Thereby, a
device shown in FIG. 15H is formed.
[0155] After that, as shown in FIG. 15I, the device shown in FIG.
15H is placed in an HF etchant, so that the SiO.sub.2 insulating
layers 67, 65 and 63 are isotropically etched and completely
removed. By this step, a storage electrode 90 can be obtained. The
storage electrode 90 has a first polysilicon fin 90.sub.1 formed of
the patterned polysilicon layer 64, a second polysilicon fin
90.sub.2 formed of the patterned polysilicon layer 66, and a third
polysilicon fin 90.sub.3 having the patterned polysilicon layers 68
and 75, and a vertical connecting portion formed of the polysilicon
layer 75. The third polysilicon fin 90.sub.3 is thicker than the
first and second polysilicon fins 90.sub.1 and 90.sub.2.
[0156] After that, the aforementioned processes are carried out for
the device shown in FIG. 15I, so that a DRAM shown in FIG. 15J can
be formed. It is possible to apply the teachings shown in FIGS. 13A
through 13F to the tenth embodiment of the present invention. It is
also possible to form the lowermost fin9-.sub.1 directly on the
insulating layer 62. In this case, the insulating layer 62 can be
formed of SiO.sub.2.
[0157] The present invention is not limited to the specifically
disclosed embodiments, and variations and modifications may be made
without departing from the scope of the present invention.
* * * * *