U.S. patent application number 10/318065 was filed with the patent office on 2003-06-26 for semiconductor device and its manufacturing method capable of reducing low frequency noise.
This patent application is currently assigned to NEC CORPORATION. Invention is credited to Mizutani, Hiroshi.
Application Number | 20030116782 10/318065 |
Document ID | / |
Family ID | 18442020 |
Filed Date | 2003-06-26 |
United States Patent
Application |
20030116782 |
Kind Code |
A1 |
Mizutani, Hiroshi |
June 26, 2003 |
Semiconductor device and its manufacturing method capable of
reducing low frequency noise
Abstract
In a semiconductor device, a first semiconductor layer is formed
on a semiconductor substrate. A second semiconductor layer is
formed on a part of the first semiconductor layer, and a third
semiconductor layer is formed on a part of the second semiconductor
layer. A first electrode is formed on the third semiconductor
layer, and a second electrode is formed on the first semiconductor
layer in contact with the second semiconductor layer and apart from
the semiconductor layer, thus forming a diode.
Inventors: |
Mizutani, Hiroshi; (Tokyo,
JP) |
Correspondence
Address: |
SUGHRUE MION, PLLC
2100 Pennsylvania Avenue, NW
Washington
DC
20037-3213
US
|
Assignee: |
NEC CORPORATION
|
Family ID: |
18442020 |
Appl. No.: |
10/318065 |
Filed: |
December 13, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10318065 |
Dec 13, 2002 |
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09734685 |
Dec 13, 2000 |
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6525346 |
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Current U.S.
Class: |
257/183 ;
257/199; 257/E21.359; 257/E21.697; 257/E27.012; 257/E29.189;
257/E29.249; 257/E29.338; 438/167; 438/570; 438/572 |
Current CPC
Class: |
H01L 29/7783 20130101;
H01L 29/872 20130101; H01L 21/8252 20130101; H01L 29/7371 20130101;
H01L 29/66143 20130101; H01L 27/0605 20130101 |
Class at
Publication: |
257/183 ;
438/570; 438/572; 438/167; 257/199 |
International
Class: |
H01L 021/338; H01L
031/0328; H01L 021/28 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 14, 1999 |
JP |
355113/1999 |
Claims
1. A semiconductor device comprising: a semiconductor substrate; a
first semiconductor layer formed on said semiconductor substrate; a
second semiconductor layer formed on a part of said first
semiconductor layer; a third semiconductor layer formed on a part
of said second semiconductor layer; a first electrode formed on
said third semiconductor layer; and a second electrode formed on
said first semiconductor layer in contact with said second
semiconductor layer and apart from said third semiconductor layer;
thus forming a diode.
2. The semiconductor device as set forth in claim 1, wherein said
first and third semiconductor layers are of one conductivity type,
and said second semiconductor layer is undoped, so that said diode
is a Schottky barrier diode.
3. The semiconductor device as set forth in claim 1, wherein said
first, second and third semiconductor layers are of one
conductivity type, so that said diode is a Schottky barrier
diode.
4. The semiconductor device as set forth in claim 1, wherein said
first and third semiconductor layers have a different material from
that of said second semiconductor layer.
5. The semiconductor device as set forth in claim 1, wherein said
second electrode is buried in said first semiconductor layer.
6. The semiconductor device as set forth in claim 1, further
comprising: a fourth semiconductor layer formed on said second
semiconductor layer; and a fifth semiconductor layer formed on said
fourth semiconductor layer, said second and fifth semiconductor
layers being made of a material different from that of said first,
third and fourth semiconductor layers.
7. The semiconductor device as set forth in claim 1, further
comprising a fourth semiconductor layer formed on said third
semiconductor layer, said first and third semiconductor layers
being of a first conductivity type, said fourth semiconductor layer
being a second conductivity type opposite to said first
conductivity type, so that said diode is a tunnel diode.
8. The semiconductor device as set forth in claim 6, wherein said
second semiconductor layer is undoped.
9. The semiconductor device as set forth in claim 6, wherein said
second semiconductor layer is of said first conductivity type.
10. The semiconductor device as set forth in claim 1, further
comprising: a fourth semiconductor layer of an i-type conductivity
type formed on said third semiconductor layer; and a fifth
semiconductor layer formed on said fourth semiconductor layer, said
first and third semiconductor layers being of a first conductivity
type, said fifth semiconductor layer being of a second conductivity
type opposite to said first conductivity type, so that said diode
is a PIN diode.
11. The semiconductor device as set forth in claim 10, wherein said
second semiconductor layer is undoped.
12. The semiconductor device as set forth in claim 10, wherein said
second semiconductor layer is of said first conductivity type.
13. The semiconductor device as set forth in claim 1, further
comprising: an i-type channel layer between said semiconductor
substrate and said first semiconductor layer; and a charge supply
layer formed between said i-type channel layer and said first
semiconductor layer, said i-type channel layer, said charge supply
layer and said first semiconductor layer forming a heterojunction
field effect transistor separated from said diode.
14. The semiconductor device as set forth in claim 13, wherein said
diode and said field effect transistor are separated by an
isolation region therebetween in said i-type channel layer and said
charge supply layer.
15. The semiconductor device as set forth in claim 1, further
comprising; a semiconductor base layer having a conductivity type
opposite to that of said third semiconductor layer formed on said
third semiconductor layer; a semiconductor emitter layer having the
same conductivity type as that of said third semiconductor layer
formed on said semiconductor base layer; and a semiconductor
emitter cap layer having the same conductivity type as that of said
third semiconductor layer formed on said semiconductor emitter
layer; said first, second and third semiconductor layers, said
semiconductor base layer, said semiconductor emitter layer and said
semiconductor emitter cap layer forming a heterojunction bipolar
transistor separated from said diode.
16. The semiconductor device as set forth in claim 15, wherein said
diode and said bipolar transistor are separated by a groove formed
in said first semiconductor layer and said semiconductor
substrate.
17. A semiconductor device comprising: a semiconductor substrate; a
first semiconductor layer formed on said semiconductor substrate; a
second semiconductor layer formed on a part of said first
semiconductor layer; a first electrode formed on said second
semiconductor layer; and a second electrode buried in said first
semiconductor layer and apart from said second semiconductor layer,
thus forming a diode.
18. The semiconductor device as set forth in claim 17, wherein said
first and second semiconductor layers are of one conductivity type,
so that said diode is a Schottky barrier diode.
19. The semiconductor device as set forth in claim 17, further
comprising: a third semiconductor layer formed on said first
semiconductor layer; and a fourth semiconductor layer formed on
said third semiconductor layer, said second and fourth
semiconductor layers being made of a material different from that
of said first, second and third semiconductor layers.
20. The semiconductor device as set forth in claim 17, further
comprising a third semiconductor layer formed on said second
semiconductor layer, said first and second semiconductor layers
being of a first conductivity type, said third semiconductor layer
being a second conductivity type opposite to said first
conductivity type, so that said diode is a tunnel diode.
21. The semiconductor device as set forth in claim 17, further
comprising: a third semiconductor layer of an i-type conductivity
type second on said second semiconductor layer; and a fourth
semiconductor layer formed on said third semiconductor layer, said
first and second semiconductor layers being of a first conductivity
type, said fourth semiconductor layer being of a second
conductivity type opposite to said first conductivity type, so that
said diode is a PIN diode.
22. The semiconductor device as set forth in claim 17, further
comprising: an i-type channel layer between said semiconductor
substrate and said first semiconductor layer; and a charge supply
layer formed between said i-type channel layer and said first
semiconductor layer, said i-type channel layer, said charge supply
layer and said first semiconductor layer forming a heterojunction
field effect transistor separated from said diode.
23. The semiconductor device as set forth in claim 22, wherein said
diode and said field effect transistor are separated by an
isolation region therebetween in said i-type channel layer and said
charge supply layer.
24. The semiconductor device as set forth in claim 17, further
comprising: a semiconductor base layer having a conductivity type
opposite to that of said third semiconductor layer formed on said
second semiconductor layer; a semiconductor emitter layer having
the same conductivity type as that of said second semiconductor
layer formed on said semiconductor base layer; and a semiconductor
emitter cap layer having the same conductivity type as that of said
second semiconductor layer formed on said semiconductor emitter
layer, said first and second semiconductor layers, said
semiconductor base layer, said semiconductor emitter layer and said
semiconductor emitter cap layer forming a heterojunction bipolar
transistor separated from said diode.
25. The semiconductor device as set forth in claim 24, wherein said
diode and said bipolar transistor are separated by a groove formed
in said first semiconductor layer and said semiconductor
substrate.
26. A method for manufacturing a semiconductor device, comprising
the steps of: forming first, second and third semiconductor layers
on a semiconductor substrate by an epitaxial growing process;
patterning said third semiconductor layer by an etching process
using said second semiconductor layer as an etching stopper;
patterning said second semiconductor layer by an etching process
using said first semiconductor layer as an etching stopper, so that
said third semiconductor layer is formed on a part of said second
semiconductor layer; forming a first electrode on said third
semiconductor layer; and forming a second electrode on said first
semiconductor layer adjacent to said second semiconductor layer and
apart from said third semiconductor layer, thus completing a
diode.
27. The method as set forth in claim 26, wherein said first and
third semiconductor layers are of one conductivity type, and said
second semiconductor layer is undoped, so that said diode is a
Schottky barrier diode.
28. The method as set forth in claim 26, wherein said first, second
and third semiconductor layers are of one conductivity type, so
that said diode is a Schottky barrier diode.
29. The method as set forth in claim 26, wherein said first and
third semiconductor layers have a different material from that of
said second semiconductor layer.
30. The method as set forth in claim 27, further comprising a step
of partly etching said first semiconductor layer after said second
semiconductor layer is patterned and before said second electrode
is formed, so that said second electrode is buried in said first
semiconductor layer.
31. The method as set forth in claim 27, wherein said epitaxial
growing step further forms a fourth semiconductor layer and a fifth
semiconductor layer between said second and fourth semiconductor
layers, said second and fifth semiconductor layers being made of a
material different from that of said first, third and fourth
semiconductor layers.
32. The method as set forth in claim 27, wherein said epitaxial
growing step further forms a fourth semiconductor layer on said
third semiconductor layer, said first and third semiconductor
layers being of a first conductivity type, said fourth
semiconductor layer being a second conductivity type opposite to
said first conductivity type, so that said diode is a tunnel
diode.
33. The method as set forth in claim 31, wherein said second
semiconductor layer is undoped.
34. The method as set forth in claim 31, wherein said second
semiconductor layer is of said first conductivity type.
35. The method as set forth in claim 26, wherein said epitaxial
growing step further forms a fourth semiconductor layer of an
i-type conductivity type and a fifth semiconductor layer on said
fourth semiconductor layer, said first and third semiconductor
layers being of a first conductivity type, said fifth semiconductor
layer being of a second conductivity type opposite to said first
conductivity type, so that said diode is a PIN diode.
36. The method as set forth in claim 35, wherein said second
semiconductor layer is undoped.
37. The method as set forth in claim 35, wherein said second
semiconductor layer is of said first conductivity type.
38. The method as set forth in claim 26, wherein said epitaxial
growing step further forms an i-type channel layer and a charge
supply layer between said semiconductor substrate and said first
semiconductor layer, said i-type channel layer, said charge supply
layer and said first semiconductor layer forming a heterojunction
field effect transistor separated from said diode.
39. The method as set forth in claim 38, further comprising a step
of forming an isolation region in said i-type channel layer and
said charge supply layer, so that said diode and said field effect
transistor are separated by said isolation region.
40. The method as set forth in claim 26, wherein said epitaxial
growing step further forms a semiconductor base layer having a
conductivity type opposite to that of said third semiconductor
layer; a semiconductor emitter layer having the same conductivity
type as that of said third semiconductor layer, and a semiconductor
emitter cap layer having the same conductivity type as that of said
third semiconductor layer on said third semiconductor layer; said
first, second and third semiconductor layers, said semiconductor
base layer, said semiconductor emitter layer and said semiconductor
emitter cap layer forming a heterojunction bipolar transistor
separated from said diode.
41. The method as set forth in claim 40, further comprising a step
of forming a groove in said first semiconductor layer and said
semiconductor substrate, so that said diode and said bipolar
transistor are separated by said groove.
42. A method for manufacturing a semiconductor device, comprising
the steps of: forming first and second semiconductor layers on a
semiconductor substrate by an epitaxial growing process substrate;
patterning said second semiconductor layer so that said second
semiconductor layer is formed on a part of said first semiconductor
layer; partly etching said first semiconductor layer after said
second semiconductor layer is patterned; forming a first electrode
on said second semiconductor layer; and burying a second electrode
in said first semiconductor layer and apart from said second
semiconductor layer, thus forming a diode.
43. The method as set forth in claim 32, wherein said first and
second semiconductor layers are of one conductivity type, so that
said diode is a Schottky barrier diode.
44. The method as set forth in claim 42, wherein said epitaxial
growing step further forms a third semiconductor layer and a fourth
semiconductor layer between said first and third semiconductor
layers, said third semiconductor layer being made of a material
different from that of said first and second semiconductor
layers.
45. The method as set forth in claim 42, wherein said epitaxial
process further forms a third semiconductor layer on said second
semiconductor layer, said first and second semiconductor layers
being of a first conductivity type, said third semiconductor layer
being a second conductivity type opposite to said first
conductivity type, so that said diode is a tunnel diode.
46. The method as set forth in claim 42, wherein said epitaxial
growing step further forms a third semiconductor layer of an i-type
conductivity type and a fourth semiconductor layer on said second
semiconductor layer, said first and second semiconductor layers
being of a first conductivity type, said fourth semiconductor layer
being of a second conductivity type opposite to said first
conductivity type, so that said diode is a PIN diode.
47. The method as set forth in claim 42, wherein said epitaxial
growing step further forms an i-type channel layer and a charge
supply layer between said first semiconductor substrate and said
first semiconductor layer, said i-type channel layer, said charge
supply layer and said first semiconductor layer forming a field
effect transistor having hetero junctions separated from said
diode.
48. The method as set forth in claim 47, further comprising a step
of forming an isolation region in said i-type channel layer and
said charge supply layer, so that said diode and said field effect
transistor are separated by said isolation region.
49. The method as set forth in claim 42, wherein said epitaxial
growing step further forms a semiconductor base layer having a
conductivity type opposite to that of said third semiconductor
layer, a semiconductor emitter layer having the same conductivity
type as that of said second semiconductor layer, and a
semiconductor emitter cap layer having the same conductivity type
as that of said second semiconductor layer on said second
semiconductor layer, said first and second semiconductor layers,
said semiconductor base layer, said semiconductor emitter layer and
said semiconductor emitter cap layer forming a heterojunction
bipolar transistor separated from said diode.
50. The method as set forth in claim 49, further comprising a step
of forming a groove formed in said first semiconductor layer and
said semiconductor substrate, so that said diode and said bipolar
transistor are separated by said groove.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor device and
its manufacturing method, and more particularly, to a diode such as
a Schottky barrier diode (SBD), a tunnel diode and a PIN diode and
its manufacturing method.
[0003] 2. Description of the Related Art
[0004] A first prior art Schottky barrier diode is of a lateral
type which is constructed by a semi-insulating GaAs substrate, an
n.sup.--type GaAs contact layer formed on the GaAs substrate, an
n.sup.+-type GaAs layer formed on the n.sup.--type GaAs contact
layer, an anode electrode (Schottky electrode) formed on the
n.sup.--type GaAs contact layer, and a cathode electrode (ohmic
electrode) formed on the n.sup.+-type GaAs layer. This will be
explained later in detail.
[0005] In the above-described first prior art Schottky barrier
diode, however, since the path of the current adjacent to the
surface of the n.sup.--type GaAs contact layer is relatively long
and, is also very close thereto, the current is affected strongly
by a surface level of the n.sup.--type GaAs contact layer. As a
result, the low frequency noise characteristics such as 1/f noise
of the Schottky barrier diode remarkably deteriorates.
[0006] A second prior art Schottky barrier diode is of a vertical
type which is constructed by a semi-insulating GaAs substrate, an
n.sup.+-type GaAs contact layer formed on the GaAs substrate, an
n.sup.--type GaAs layer formed on the n.sup.+-type GaAs layer, an
anode electrode (Schottky electrode) formed on the n.sup.--type
GaAs layer 203, and a cathode electrode (ohmic electrode) formed on
the n.sup.+-type GaAs contact layer (see JP-A-8-255838). This also
will be explained later in detail.
[0007] Thus, in the above-described second prior art Schottky
barrier diode, the path of the current adjacent to the surface of
the n.sup.+-type GaAs contact layer is shortened, which would
improve the low frequency characteristics.
[0008] In the second prior art Schottky barrier diode, however,
since the path of the current adjacent to the surface of the
n.sup.--type GaAs contact layer is still close thereto, the current
is still affected strongly by the surface level of the n.sup.+-type
GaAs contact layer. As a result, the low frequency noise
characteristics of the Schottky barrier diode still
deteriorates.
SUMMARY OF THE INVENTION
[0009] It is an object of the present invention to provide a
semiconductor device such as a diode and its manufacturing method
capable of reducing the low frequency noise.
[0010] Another object is to provide such a semiconductor device
incorporating a heterojunction field effect transistor and a
heterojunction bipolar transistor and its manufacturing method.
[0011] According to the present invention, in a semiconductor
device, a first semiconductor layer is formed on a semiconductor
substrate. A second semiconductor layer is formed on a part of the
first semiconductor layer, and a third semiconductor layer is
formed on a part of the second semiconductor layer. A first
electrode is formed on the third semiconductor layer, and a second
electrode is formed on the first semiconductor layer in contact
with the second semiconductor layer and apart from said the
semiconductor layer, thus forming a diode.
[0012] Thus, the current path is distant from the surface level of
the second semiconductor layer, to improve the low frequency noise
characteristics.
[0013] Also, the cathode electrode is buried in the first
semiconductor layer so that the current path is further distant
from the surface level of the second semiconductor layer, to
further improve the low frequency noise characteristics.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The present invention will be more clearly understood from
the description set forth below, as compared with the prior art,
with reference to the accompanying drawings, wherein:
[0015] FIG. 1 is a cross-sectional view illustrating a first prior
art diode;
[0016] FIG. 2 is a cross-sectional view illustrating a second prior
art diode;
[0017] FIG. 3 is a cross-sectional view illustrating a
semiconductor device to which the diode of FIG. 2 is applied;
[0018] FIG. 4 is a cross-sectional view illustrating a first
embodiment of the diode according to the present invention;
[0019] FIGS. 5A through 5E are cross-sectional views for explaining
a method for manufacturing the diode of FIG. 4;
[0020] FIG. 6 is a cross-sectional view illustrating a second
embodiment of the diode according to the present invention;
[0021] FIGS. 7A through 7F are cross-sectional views for explaining
a method for manufacturing the diode of FIG. 6;
[0022] FIG. 8 is a cross-sectional view illustrating a third
embodiment of the diode according to the present invention;
[0023] FIGS. 9A through 9E are cross-sectional views for explaining
a method for manufacturing the diode of FIG. 8;
[0024] FIG. 10 is a cross-sectional view illustrating a fourth
embodiment of the diode according to the present invention;
[0025] FIGS. 11A through 11E are cross-sectional views for
explaining a method for manufacturing the diode of FIG. 10;
[0026] FIG. 12 is a cross-sectional view illustrating a fifth
embodiment of the diode according to the present invention;
[0027] FIGS. 13A through 13E are cross-sectional views for
explaining a method for manufacturing the diode of FIG. 12;
[0028] FIG. 14 is a cross-sectional view illustrating a sixth
embodiment of the diode according to the present invention;
[0029] FIGS. 16A through 15E are cross-sectional views for
explaining a method for manufacturing the diode of FIG. 14;
[0030] FIG. 16 is a cross-sectional view illustrating a
semiconductor device in which the Schottky barrier diode of FIG. 6
is combined with a high electron mobility transistor;
[0031] FIGS. 17A through 1711 are cross-sectional views for
explaining a method for manufacturing the semiconductor device of
FIG. 16;
[0032] FIG. 18 is a cross-sectional view illustrating a
semiconductor device in which the Schottky barrier diode of FIG. 6
is combined with a heterojunction bipolar transistor;
[0033] FIGS. 19A through 19I are cross-sectional views for
explaining a method for manufacturing the diode of FIG. 18;
[0034] FIG. 20 is a cross-sectional view illustrating a
semiconductor device in which the Schottky barrier diode of FIG. 6
is combined with a high electron mobility transistor and a
heterojunction bipolar transistor; and
[0035] FIG. 21 is a cross-sectional view illustrating an epitaxial
layer used in the manufacture of the semiconductor device of FIG.
20.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0036] Before the description of the preferred embodiments, prior
art diodes will be explained with reference to FIGS. 1, 2 and
3.
[0037] In FIG. 1, which illustrates a first prior art diode that
is, in this case, a Schottky barrier diode SBD, the Schottky
barrier diode SBD is of a lateral type which is constructed by a
semi-insulating GaAs substrate 101, an n.sup.--type GaAs contact
layer 102 formed on the GaAs substrate 101, an n.sup.+-type GaAs
layer 103 formed on the n.sup.--type GaAs contact layer 102, an
anode electrode 104 formed on the n.sup.--type GaAs contact layer
102, and a cathode electrode 105 formed on the n.sup.+-type GaAs
layer 103. Note that a Schottky barrier SB is generated of at an
interface between the anode electrode 104 and the n.sup.--type GaAs
contact layer 102.
[0038] In the Schottky barrier diode SBD of FIG. 1, when a forward
bias voltage is applied to the anode electrode 104 and the cathode
electrode 105, a current as indicated by an arrow I flows from the
anode electrode 104 to the n.sup.+-type GaAs layer 103 in parallel
with the surface of the n.sup.--type GaAs contact layer 102, and
then, the current I flows from the n.sup.+-type GaAs layer 103 to
the cathode electrode 105.
[0039] In the Schottky barrier diode SBD of FIG. 1, however, since
the path of the current I adjacent to the surface of the
n.sup.--type GaAs contact layer 102 is relatively long, and, is
also very close thereto, the current I is affected strongly by a
surface level SL of the n.sup.--type GaAs contact layer 102. As a
result, the low frequency noise characteristics of the Schottky
barrier diode SBD of FIG. 1 remarkably deteriorate.
[0040] In FIG. 2, which illustrates a second prior art diode that
is, in this case, a Schottky barrier diode SBD (see JP-A-8-255838),
the Shottky barrier diode SBD is of a vertical type which is
constructed by a semi-insulating GaAs substrate 201, an
n.sup.+-type GaAs contact layer 202 formed on the GaAs substrate
201, an n.sup.--type GaAs layer 203 formed on the n.sup.+type GaAs
layer 202, an anode electrode 204 formed on the n.sup.--type GaAs
layer 203, and a cathode electrode 205 formed on the n.sup.+-type
GaAs contact layer 202. Note that a Schottky barrier SB is
generated at an interface between the anode electrode 204 and the
n.sup.--type GaAs layer 203.
[0041] In the Schottky barrier diode SBD of FIG. 2, when a forward
bias voltage is applied to the anode electrode 204 and the cathode
electrode 205, a current as indicated by an arrow I flows from the
anode electrode 204 to the n.sup.--type GaAs layer 203
perpendicular to the surface of the n.sup.--type GaAs layer 203,
and then, the current I flows from the n.sup.--type GaAs layer 203
via the n.sup.+-type GaAs contact layer 202 to the cathode
electrode 205 in parallel with the surface of the n.sup.+-type GaAs
contact layer 202.
[0042] Thus, the path of the current I adjacent to the surface of
the n.sup.+-type GaAs contact layer 202 is shortened, which would
improve the low frequency characteristics.
[0043] In the Schottky barrier diode SBD of FIG. 2, however, since
the path of the current I adjacent to the surface of the
n.sup.--type GaAs contact layer 202 is still close thereto, the
current I is still affected strongly by a surface level SL of the
n.sup.+-type GaAs contact layer 202. As a result, the low frequency
noise characteristics of the Schottky barrier diode SBD of FIG. 2
still deteriorate.
[0044] In FIG. 3, which illustrates a semiconductor device to which
the Schottky barrier diode SBD of FIG. 2 is applied, a
heterojunction bipolar transistor HBT and a high electron mobility
transistor HEMT as well as the Schottky barrier diode SBD of FIG. 2
are formed in one chip.
[0045] The heterojunction bipolar transistor HBT is constructed by
an n.sup.+type GaAs sub collector layer 206, an n.sup.-type GaAs
collector layer 207, a p.sup.+-type GaAs base layer 208 an n-type
AlGaAs emitter layer 209, an n.sup.+-type GaAs emitter cap layer
210, collector electrodes 211, base electrodes 212 and a collector
electrode 213.
[0046] The Schottky barrier diode SBD and the heterojunction
bipolar HBT are isolated by a p-type element isolation region 214
formed within the n.sup.+-type GaAs layer 202 and the n.sup.+-type
GaAs layer 206 which are actually the same.
[0047] On the other hand, the high electron mobility transistor
HEMT is constructed by a superlattice buffer layer 215, an i-type
InGaAs channel layer 216, an n-type silicon planar doped layer 217,
an n-type AlGaAs layer donor layer 218, n.sup.+-type GaAs
source/drain layers 219, a T-shaped gate electrode 220, a source
electrode 221, and a drain electrode 222.
[0048] When forming the semiconductor device of FIG. 3, an
epitaxial layer for the layers 202, 203, 206, 207, 208, 209 and 210
is grown on the GaAs substrate 201 by a molecular beam epitaxy
(MBE) process. Then, an area of the epitaxial layer for the high
electron mobility transistor HEMT is etched by using a mask which
covers an area of the opitaxial layer for the hetro junction
bipolar transistor HBT and the Schottky barrier diode SBD. Then,
another epitaxial layer for the layers 215, 216, 217, 218 and 219
is regrown on the GaAs substrate 201. Finally, each layer of the
epitaxial layers is patterned, and then, each electrode is formed
to complete the semiconductor device of FIG. 3.
[0049] In the semiconductor device of FIG. 3, however, since an
epitaxial layer regrowing process is required, a deep trap level is
generated at an interface between the n.sup.--type GaAs contact
layer 202 and the GaAs substrate 201, which also deteriorates the
low frequency noise characteristics. Also, the epitaxial layer
regrowing process increases the manufacturing cost. Further, the
characteristics among wafers and among lots fluctuate, which would
decrease the manufacturing yield.
[0050] In FIG. 4, which illustrates a first embodiment of the diode
according to the present invention that is, in this case, a
Schottky barrier diode SBD, the Shottky barrier diode SBD is of a
vertical type which is constructed by a semi-insulating GaAs
substrate 1, an n.sup.+-type GaAs contact layer 2 formed on the
GaAs substrate 1, an undoped AlGaAs etching stopper layer 3 formed
on the n.sup.+-type GaAs contact layer 2, an n.sup.--type GaAs
layer 4 formed on the i-type AlGaAs etching stopper layer 3, an
anode electrode 5 formed on the n.sup.--type GaAs layer 4, and a
cathode electrode 6 formed on the n.sup.+-type GaAs contact layer
2. Note that a Schottky barrier SB is generated at an interface
between the anode electrode 5 and the n.sup.--type GaAs layer
4.
[0051] In the Schottky barrier diode SBD of FIG. 4, when a forward
bias voltage is applied to the anode electrode 5 and the cathode
electrode 6, a current as indicated by an arrow I flows from the
anode electrode 5 to the n.sup.--type GaAs layer 4 perpendicular to
the surface of the n.sup.--type GaAs layer 4, and then, the current
I flows from the n.sup.--type GaAs layer 4 via the i-type AlGaAs
etching stopper layer 3 and the n.sup.+-type GaAs contact layer 2
to the cathode electrode 6 in parallel with the surface of the
nt-type GaAs contact layer 2.
[0052] In the Schottky barrier diode SBD of FIG. 4, although the
path of the current I adjacent to the surface of the n.sup.+-type
GaAs contact layer 2 is still close thereto, there is no surface
level within the n.sup.+-type GaAs contact layer 2 due to the
presence of the i-type AlGaAs etching stopper layer 3. In this
case, a surface level SL may be generated in the i-type AlGaAs
etching stopper layer 3; however, the path of the current I is
distant from this surface level SL. Therefore, the current I is
hardly affected by the surface level SL of the i-type AlGaAs
etching stopper layer 3. As a result, the low frequency noise
characteristics of the Schottky barrier diode SBD of FIG. 4 can be
improved.
[0053] The method for manufacturing the Schottky barrier diode SBD
of FIG. 4 will be explained next with reference to FIGS. 5A through
5E.
[0054] First, referring to FIG. 5A, an n.sup.+-type GaAs contact
layer 2, an i-type AlGaAs etching stopper layer 3 and an
n.sup.--type GaAs layer 4 are grown on a semi-insulating GaAs
substrate 1 by an MBE process, a metal-organic chemical vapor
deposition (MOCVD) process or a vapor-phase epitaxy (VPE) process.
In this case, the i-type AlGaAs etching stopper layer 3 is about 50
.ANG. thick.
[0055] Next, referring to FIG. 5B; a photoresist pattern layer 11
is formed by a photolithography process. Then, the n.sup.--type
GaAs layer 4 is etched by a selective dry etching process using
BCl.sub.3 gas and the i-type AlGaAs etching stopper layer 3 as an
etching stopper. Then, the photoresist pattern layer 11 is
removed.
[0056] Next, referring to FIG. 5C, a photoresist pattern layer 12
is formed by a photolithography process. Then, the i-type AlGaAs
etching stopper layer 3 is etched by a wet etching process using
hydrogen peroxide water and the n.sup.+-type GaAs layer 2 as an
etching stopper. Then, the photoresist pattern layer 12 is
removed.
[0057] Next, referring to FIG. 5D, a silicon oxide layer 13 is
deposited by a CVD process.
[0058] Next, referring to FIG. 5E, a photoresist pattern layer 14
is formed by a photolithography process. Then, the silicon oxide
layer 13 is etched by a dry etching process using SF.sub.6 gas.
[0059] Finally, an anode electrode 5 and a cathode electrode 6 are
formed by a sputtering process and a lift-off process. Then, the
photoresist pattern layer 14 is removed, to obtain the Schottky
barrier diode SBD of FIG. 4. Note that the silicon oxide layer 13
is not shown in FIG. 4.
[0060] In the first embodiment, although the AlGaAs etching stopper
layer 3 is undoped, the AlGaAs etching stopper layer 3 can be
doped, i.e., of an n-type.
[0061] In FIG. 6, which illustrates a second embodiment of the
diode according to the present invention, the anode electrode 6 and
the cathode electrode 6 of FIG. 4 are buried in the n.sup.--type
GaAs layer 4 and the n.sup.+-type GaAs contact layer 2,
respectively, of FIG. 4.
[0062] In the Schottky barrier diode SBD of FIG. 6, the path of the
current I adjacent to the surface of the n.sup.+-type GaAs contact
layer 2 is distant therefrom, the path of the current I is further
distant from the surface level SL. Therefore, the current I is
hardly affected by the surface level SL of the i-type AlGaAs
etching stopper layer 3. As a result, the low frequency noise
characteristics of the Schottky barrier diode SBD of FIG. 6 can be
further improved.
[0063] The method for manufacturing the Schottky barrier diode SBD
of FIG. 6 will be explained next with reference to FIGS. 7A through
7F.
[0064] The manufacturing steps as illustrated in FIGS. 7A through
7E are the same as those as illustrated in FIGS. 5A through 5E,
respectively.
[0065] After the manufacturing step as illustrated in FIG. 7E, is
carried out, referring to FIG. 7F, the n.sup.+-type GaAs contact
layer 2 and the n.sup.--type GaAs layer 4 are etched by a wet
etching process using phosphoric acid. In this case, the etching
depth of the n.sup.+-type GaAs contact layer 2 and the n.sup.--type
GaAs layer 4 is about 100 .ANG.. Then, an anode electrode 5 and a
cathode electrode 6 are formed by a sputtering process and a
lift-off process. Then, the photoresist pattern layer 14 is
removed, to obtain the Schottky barrier diode SBD of FIG. 6. Note
that the silicon oxide layer 13 is not shown in FIG. 6.
[0066] Even in the second embodiment, although the AlGaAs etching
stopper layer 3 is undoped, the AlGaAs etching stopper layer 3 can
be doped, i.e., of an n-type.
[0067] In FIG. 8, which illustrates a third embodiment of the diode
according to the present invention, the i-type GaAs etching stopper
layer 3 of FIG. 6 is omitted.
[0068] In the Schottky barrier diode SBD of FIG. 8, the path of the
current I adjacent to the surface of the n.sup.+-type GaAs contact
layer 2 is distant therefrom, the path of the current I is distant
from the surface level SL within the n.sup.+-type GaAs contact
layer 2 Therefore, the current I is hardly affected by the surface
level SL of the n.sup.+-type GaAs layer 2.-As a result, the low
frequency noise characteristics of the Schottky barrier diode SBD
of FIG. 8 can be improved.
[0069] The method for manufacturing the Schottky barrier diode SBD
of FIG. 8 will be explained next with reference to FIGS. 9A through
9E.
[0070] First, referring to FIG. 9A, an n.sup.+-type GaAs contact
layer 2 and an n.sup.--type GaAs layer 4 are grown on a
semi-insulating GaAs substrate 1 by an MBE process, an MOCVD
process or a VPE process.
[0071] Next, referring to FIG. 9B, a photoresist pattern layer 11
is formed by a photolithography process. Then, the n.sup.--type
GaAs layer 4 is etched by a selective dry etching process using
BCl.sub.3 gas. Then, the photoresist pattern layer 11 is
removed.
[0072] Next, referring to FIG. 9C, a silicon oxide layer 13 is
deposited by a CVD process.
[0073] Next, referring to FIG. 9D, a photoresist pattern layer 14
is formed by a photolithography process. Then, the silicon oxide
layer 13 is etched by a dry etching process using SF.sub.6 gas.
[0074] Next, referring to FIG. 9E, the n.sup.+-type GaAs contact
layer 2 and the n.sup.--type GaAs layer 4 are etched by a wet
etching process using phosphoric acid. In this case, the etching
depth of the n.sup.+-type GaAs contact layer 2 and the n.sup.--type
GaAs layer 4 is about 100 .ANG.. Then, an anode electrode 5 and a
cathode electrode 6 are formed by a sputtering process and a
lift-off process. Then, the photoresist pattern layer 14 is
removed, to obtain the Schottky barrier diode SBD of FIG. 8. Note
that the silicon oxide layer 13 is not shown in FIG. 8.
[0075] In FIG. 10, which illustrates a fourth embodiment of the
diode according to the present invention that is, in this case, a
Schottky barrier diode SBD, an i-type GaAs layer 21 and an i-type
AlGaAs etching stopper layer 22 are added to the Schottky barrier
diode SBD of FIG. 4.
[0076] In the Schottky barrier diode SBD of FIG. 10, a surface
level SL may be generated in the i-type AlGaAs etching stopper
layer 22; however, the path of the current I is far away from this
surface level SL. Therefore, the current I is hardly affected by
the surface level SL of the i-type AlGaAs etching stopper layer 22.
As a result, the low frequency noise characteristics of the
Schottky barrier diode SBD of FIG. 10 can be further improved.
[0077] The method for manufacturing the Schottky barrier diode SBD
of FIG. 10 will be explained next with reference to FIGS. 11A
through 11E.
[0078] First, referring to FIG. 11A, an n.sup.+-type GaAs contact
layer 2, an i-type AlGaAs etching stopper layer 3, an i-type GaAs
layer 21, an i-type AlGaAs etching stopper layer 22 and an
n.sup.--type GaAs layer 4 are grown on a semi-insulating substrate
1 by an MBE process, an MOCVD process or a VPE process. In this
case, the i-type AlGaAs etching stopper layers 3 and 22 are about
50 .ANG. thick.
[0079] Next, referring to FIG. 11A, in the same way as in FIG. 5B,
a photoresist pattern layer 11 is formed by a photolithography
process. Then, the n.sup.--type GaAs layer 4 is etched by a 1
selective dry etching process using BCl.sub.3 gas and the i-type
AlGaAs etching stopper layer 22 as an etching stopper. Then, the
photoresist pattern layer 11 is removed.
[0080] Next, referring to FIG. 11C, a photoresist pattern layer 12
is formed by a photolithography process. Then, the i-type AlGaAs
etching stopper layer 22 is etched by a wet etching process using
hydrogen peroxide water and the i-type GaAs layer 21 as an etching
stopper. Then, the i-type GaAs layer 21 is etched by a 1 selective
dry etching process using BCl.sub.3 gas and the i-type AlGaAs
etching stopper layer 3 as an etching stopper. Then, the i-type
AlGaAs etching stopper layer 3 is etched by a wet etching process
using hydrogen peroxide water and the n.sup.+-type GaAs layer 3 as
an etching stopper. Then, the photoresist pattern layer 12 is
removed.
[0081] Next, referring to FIG. 11D, in the same way as in FIG. 5D,
a silicon oxide layer 13 is deposited by a CVD process.
[0082] Next, referring to FIG. 11E, in the same way as in FIG. 5E,
a photoresist pattern layer 14 is formed by a photolithography
process. Then, the silicon oxide layer 13 is etched by a dry
etching process using SF.sub.6 gas.
[0083] Finally, an anode electrode 5 and a cathode electrode 6 are
formed by a sputtering process and a lift-off process. Then, the
photoresist pattern layer 14 is removed, to obtain the Schottky
barrier diode SBD of FIG. 10. Note that the silicon oxide layer 13
is not shown in FIG. 10.
[0084] In the fourth embodiment, although the AlGaAs etching
stopper layers 3 and 22 are undoped, the AlGaAs etching stopper
layers 3 and 22 can be doped, i.e., of an n-type.
[0085] In the fourth embodiment, the cathode electrode 6 can be
buried in the n.sup.+-type GaAs contact layer 2 in the same way as
in the third embodiment, so as to further improve the low frequency
noise characteristics.
[0086] In FIG. 12, which illustrates a fifth embodiment of the
diode according to the present invention that is, in this case, a
tunnel diode TD, the tunnel diode TD is of a vertical type which is
constructed by a semi-insulating GaAs substrate 1, an n.sup.+-type
GaAs contact layer 2 formed on the GaAs substrate 1, an undoped
AlGaAs etching stopper layer 3 formed on the n.sup.+-type GaAs
contact layer 2, an n.sup.+-type GaAs layer 31 formed on the i-type
AlGaAs etching stopper layer 3, a p.sup.+-type GaAs layer 32 formed
on the n.sup.+-type GaAs layer 31, an anode electrode 5 formed on
the p.sup.+-type GaAs layer 32, and a cathode electrode 6 formed on
the n.sup.+-type GaAs contact layer 2.
[0087] In the tunnel diode TD of FIG. 12, when a forward bias
voltage is applied to the anode electrode 5 and the cathode
electrode 6, a current as indicated by an arrow I flows from the
anode electrode 5 via the p.sup.+-type GaAs layer 32 to the
n.sup.+-type GaAs layer 31 perpendicular to the-surface thereof,
and then, the current I flows from the n.sup.+-type GaAs layer 31
via the i-type AlGaAs etching stopper layer 3 and the n.sup.+-type
GaAs contact layer 2 to the cathode electrode 6 in parallel with
the surface of the n.sup.+-type GaAs contact layer 2.
[0088] Even in the tunnel diode TD of FIG. 12, although the path of
the current I adjacent to the surface of the n.sup.+-type GaAs
contact layer 2 is still close thereto, there is no surface level
within the n.sup.+-type GaAs contact layer 2 due to the presence of
the i-type AlGaAs etching stopper layer 3. In this case, a surface
level SL may be generated in the i-type AlGaAs etching stopper
layer 3; however, the path of the current I is distant from this
surface level SL. Therefore, the current I is hardly affected by
the surface level SL of the i-type AlGaAs etching stopper layer 3.
As a result, the low frequency noise characteristics of the tunnel
diode TD of FIG. 12 can be improved.
[0089] The method for manufacturing the tunnel diode TD of FIG. 12
will be explained next with reference to FIGS. 13A through 13E.
[0090] First, referring to FIG. 13A, an n.sup.+-type GaAs contact
layer 2, an i-type AlGaAs etching stopper layer 3, an n.sup.+-type
GaAs layer 31, a p.sup.+-type GaAs layer 32 and an n.sup.--type
GaAs layer 4 are grown on a semi-insulating substrate 1 by an MBE
process, an MOCVD process or a VPE process. In this case, the
i-type AlGaAs etching stopper layer 3 is about 50 .ANG. thick.
[0091] Next, referring to FIG. 13B, a photoresist pattern layer 11
is formed by a photolithography process. Then, the p.sup.+-type
GaAs layer 32 and the n.sup.+-type GaAs layer 31 are etched by a 1
selective dry etching process using BCl.sub.3 gas and the i-type
AlGaAs etching stopper layer 3 as an etching stopper. Then, the
photoresist pattern layer 11 is removed.
[0092] Next, referring to FIG. 13C, in the same way as in FIG. SC,
a photoresist pattern layer 12 is formed by a photolithography
process. Then, the i-type AlGaAs etching stopper layer 3 is etched
by a wet etching process using hydrogen peroxide water and the
nt-type GaAs layer 2 as an etching stopper. Then, the photoresist
pattern layer 12 is removed.
[0093] Next, referring to FIG. 13D, in the same way as in FIG. 5D,
a silicon oxide layer 13 is deposited by a CVD process.
[0094] Next, referring FIG. 13E in the same way as in to FIG. 5E, a
photoresist pattern layer 14 is formed by a photolithography
process. Then, the silicon oxide layer 13 is etched by a dry
etching process using SF.sub.6 gas.
[0095] Finally, an anode electrode 5 and a cathode electrode 6 are
formed by a sputtering process and a lift-off process. Then, the
photoresist pattern layer 14 is removed, to obtain the tunnel diode
TD of FIG. 12. Note that the silicon oxide layer 13 is not shown in
FIG. 12.
[0096] In the fifth embodiment, although the AlGaAs etching stopper
layer 3 is undoped, the AlGaAs etching stopper layer 3 can be
doped, i.e., of an n-type.
[0097] In the fourth embodiment, the cathode electrode 6 can be
buried in the n.sup.+-type GaAs contact layer 2 in the same way as
in the third embodiment, so as to further improve the low frequency
noise characteristics.
[0098] In FIG. 14, which illustrates a sixth embodiment of the
diode according to the present invention that is, in this case, a
PIN diode D, the PIN diode D is of a vertical type which is
constructed by a semi-insulating GaAs substrate 1, an n.sup.+-type
GaAs contact layer 2 formed an the GaAs substrate 1, an undoped
AlGaAs etching stopper layer 3 formed on the n.sup.+-type GaAs
contact layer 2, an n-type GaAs layer 41 formed on the i-type
AlGaAs etching stopper layer 3, an i-type GaAs layer 42 formed on
the n-type GaAs layer 41 a p-type GaAs layer 43 formed on the
i-type GaAs layer 42, an anode electrode 5 formed on the p-type
GaAs layer 43, and a cathode electrode 6 formed on the n.sup.+-type
GaAs contact layer 2.
[0099] In the PIN diode D of FIG. 14, when a forward bias voltage
is applied to the anode electrode 5 and the cathode electrode 6, a
current as indicated by an arrow I flows from the anode electrode 5
via the p-type GaAs layer 43 and the i-type GaAs layer 42 to the
n-type GaAs layer 41 perpendicular to the surface thereof, and
then, the current I flows from the n-type GaAs layer 41 via the
i-type AlGaAs etching stopper layer 3 and the n.sup.+-type GaAs
contact layer 2 to the cathode electrode 6 in parallel with the
surface of the n.sup.+-type GaAs contact layer 2.
[0100] Even in the PIN diode D of FIG. 14, although the path of the
current I adjacent to the surface of the n.sup.+-type GaAs contact
layer 2 is still close thereto, there is no surface level within
the n.sup.+-type GaAs contact layer 2 due to the presence of the
i-type AlGaAs etching stopper layer 3. In this case, a surface
level SL may be generated in the i-type AlGaAs etching stopper
layer 3; however, the path of the current I is distant from this
surface level SL. Therefore, the current I is hardly affected by
the surface level SL of the i-type AlGaAs etching stopper layer 3.
As a result, the low frequency noise characteristics of the PIN
diode D of FIG. 14 can be improved.
[0101] The method for manufacturing the tunnel diode D of FIG. 14
will be explained next with reference to FIGS. 15A through 15E.
[0102] First, referring to FIG. 15A, an n.sup.+-type GaAs contact
layer 2, an i-type AlGaAs etching stopper layer 3, an n-type GaAs
layer 41, an i-type GaAs layer 42 a p-type GaAs layer 43 and an
n.sup.--type GaAs layer 4 are grown on a semi-insulating substrate
1 by an MBE process, an MOCVD process or a VPE process. In this
case, the i-type AlGaAs etching stopper layer 3 is about 50 .ANG.
thick.
[0103] Next, referring to FIG. 15B, a photoresist pattern layer 11
is formed by a photolithography process. Then, the p-type GaAs
layer 43, the i-type GaAs layer 42 and the n-type GaAs layer 41 are
etched by a 1 selective dry etching process using BCl.sub.3 gas and
the i-type AlGaAs etching stopper layer 3 as an etching stopper.
Then, the photoresist pattern layer 11 is removed.
[0104] Next, referring to FIG. 15C, in the same way as in FIG. 5C,
a photoresist pattern layer 12 is formed by a photolithography
process. Then, the i-type AlGaAs etching stopper layer 3 is etched
by a wet etching process using hydrogen peroxide water and the
nt-type GaAs layer 2 as an etching stopper. Then, the photoresist
pattern layer 12 is removed.
[0105] Next, referring to FIG. 15D, in the same way as in FIG. 5D,
a silicon oxide layer 13 is deposited by a CVD process.
[0106] Next, referring FIG. 15E in the same way as in to FIG. 5E, a
photoresist pattern layer 14 is formed by a photolithography
process. Then, the silicon oxide layer 13 is etched by a dry
etching process using SF.sub.6 gas.
[0107] Finally, an anode electrode 5 and a cathode electrode 6 are
formed by a sputtering process and a lift-off process. Then, the
photoresist pattern layer 14 is removed, to obtain the PIN diode D
of FIG. 14. Note that the silicon oxide layer 13 is not shown in
FIG. 14.
[0108] In the sixth embodiment, although the AlGaAs etching stopper
layer 3 is undoped, the AlGaAs etching stopper layer 3 can be
doped, i.e., of an n-type.
[0109] In the sixth embodiment, the cathode electrode 6 can be
buried in the n.sup.+-type GaAs contact layer 2 in the same way as
in the third embodiment, so as to further improve the low frequency
noise characteristics.
[0110] FIG. 16 is a cross-sectional view illustrating a
semiconductor device in which the Schottky diode SBD of FIG. 6 is
combined with a high electron mobility transistor HEMT.
[0111] In FIG. 16, an i-type InGaAs channel layer 51 and an n-type
AlGaAs electron supply layer 52 are formed on the GaAs substrate 1
for the high electron mobility transistor HEMT. In this case, the
i-type InGaAs channel layer 51 and the n-type AlGaAs electron
supply layer 52 are meaningless for the Schottky barrier diode SBD.
Also, the Schottky barrier diode SBD and the high electron mobility
transistor HEMT are isolated from each other by a p.sup.+-type
isolation region 53. Further, a gate electrode 5(G) is made of the
same material as the anode electrode 5(A), and a source electrode
6(S) and a drain electrode 6(D) are made of the same material as
the cathode electrode 6(C).
[0112] The method for manufacturing the semiconductor device of
FIG. 16 will be explained next with reference to FIGS. 17A through
17H.
[0113] First, referring to FIG. 17A, an i-type InGaAs channel layer
51, an n-type AlGaAs electron supply layer 52, an n.sup.+-type GaAs
contact layer 2, an i-type AlGaAs etching stopper layer 3 and an
n.sup.--type GaAs layer 4 are grown on a semi-insulating GaAs
substrate 1 by an MBE process, a MOCVD process or a VPE process. In
this case, the i-type AlGaAs etching stopper layer 3 is about 50
.ANG. thick.
[0114] Next, referring to FIG. 17B, a photoresist pattern layer 11
is formed by a photolithography process. Then, the n.sup.--type
GaAs layer 4 is etched by a selective dry etching process using
BCl.sub.3 gas and the i-type AlGaAs etching stopper layer 3 as an
etching stopper. Then, the photoresist pattern layer 11 is
removed.
[0115] Next, referring to FIG. 17C, a photoresist pattern layer 54
is formed by a photolithography process. Then, boron ions are
implanted into the GaAs substrate 1 as well as the layers 51, 52, 2
and 3. As a result, a p.sup.+-type isolation region 53 is formed.
Then, the photoresist pattern 54 is removed.
[0116] Next, referring to FIG. 17D, a photoresist pattern layer 12
is formed by a photolithography process. Then, the i-type AlGaAs
etching stopper layer 3 is etched by a wet etching process using
hydrogen peroxide water and the n.sup.+-type GaAs layer 2 as an
etching stopper. Then, the photoresist pattern layer 12 is
removed.
[0117] Next, referring to FIG. 17E, a photoresist pattern layer 55
is formed by a photolithography process. Then, the n.sup.+-type
GaAs layer 2 is etched by a 1 selective dry etching process using
BCl.sub.3 gas and the n-type AlGaAs etching stopper layer 52 as an
etching stopper. Then, the photoresist pattern layer 55 is
removed.
[0118] Next, referring to FIG. 17F, a silicon oxide layer 13 is
deposited by a CVD process.
[0119] Next, referring to FIG. 17G, the silicon oxide layer 13 is
perforated by a photolithography and dry etching process using
SF.sub.6 gas to form openings for an anode electrode 5(A) and a
gate electrode 5(G). Then, the anode electrode 5(A) and the gate
electrode 5(G) are buried in the openings by a sputtering and
lift-off process.
[0120] Next, referring to FIG. 17H, the silicon oxide layer 13 is
perforated by a photolithography and dry etching process using
SF.sub.6 gas to form openings for a cathode electrode 6(C), a
source electrode 6(G), 6(S) and a drain electrode 6(D). Then, the
n.sup.+-type GaAs contact layer 2 is etched by a wet etching
process using phosphoric acid. In this case, the etching depth of
the n.sup.+-type GaAs contact layer 2 is about 100 .ANG.. Then, the
cathode electrode 6(C), the source electrode 6(C) and the drain
electrode 6(D) are buried in the openings by a sputtering and
lift-off process, to obtain the semiconductor device of FIG.
16.
[0121] In FIG. 16, although the AlGaAs etching stopper layer 3 is
undoped, the AlGaAs etching stopper layer 3 can be doped, i.e., of
an n-type. Also, the anode electrode 5(A) can be buried in the
n.sup.--type GaAs layer 4, and the gate electrode 5(G) can be
buried in the n-type AlGaAs layer 52.
[0122] FIG. 18 is a cross-sectional view illustrating a
semiconductor device in which the Schottky diode SBD of FIG. 6 is
combined with a heterojunction bipolar transistor HBT.
[0123] In FIG. 18, the InGaAs etching stopper layer 3 is of an
n-type. Also, the n.sup.+-type GaAs contact layer 2 of the
heterojunction bipolar transistor HBT serves as a collector contact
layer, and the n-type GaAs layer 3 and the n-type GaAs layer 4
serve as a collector layer.
[0124] Additionally, the heterojunction bipolar transistor HBT is
constructed by a p.sup.+-type GaAs base layer 61, an n-type AlGaAs
emitter layer 62 and a n.sup.+-type InGaAs emitter cap layer 63.
Further, reference numeral 6(C') designates a collector electrode,
65 designates a base electrode, and 66 designates an emitter
electrode. The collector electrode 6(C') are made of the same
material as the cathode electrode 6(C).
[0125] The method for manufacturing the semiconductor device of
FIG. 18 will be explained next with reference to FIGS. 19A through
19I.
[0126] First, referring to FIG. 19A, an n.sup.+-type GaAs contact
layer 2, an n-type AlGaAs etching stopper layer 3, an n.sup.--type
GaAs layer 4, a p.sup.+-type GaAs base layer 61, an n-type AlGaAs
emitter layer 62, and an n.sup.+-type InGaAs emitter cap layer 63
are grown on a semi-insulating GaAs substrate 1 by an MBE process,
a MOCVD process or a CVE process. In this case, the n-type AlGaAs
etching stopper layer 3 is about 50 .ANG. thick.
[0127] Next, referring to FIG. 19B, a photoresist pattern layer
(not shown) is formed by a photolithography process to cover an
emitter area. Then, the n.sup.+-type InGaAs emitter cap layer 63
and the n-AlGaAs emitter layer 62 are etched by a wet or dry
etching process using the photoresist pattern as a mask.
[0128] Next, referring to FIG. 19C, a photoresist pattern layer
(not shown) is formed by a photolithography process to cover a base
area and an anode area. Then, the p.sup.+-type GaAs layer 61 and
the n.sup.--GaAs layer 4 are etched by a selective dry etching
process using BCl.sub.3 gas and the photoresist pattern as a
mask.
[0129] Next, referring to FIG. 19D, a photoresist pattern layer
(not shown) is formed by a photolithography process to cover an
area adjacent to the anode area. Then, the n-type InGaAs etching
stopper layer 3 is etched by a wet etching process using hydrogen
peroxide water.
[0130] Next, referring to FIG. 19E, a photoresist pattern layer
(not shown) is formed by a photolithography process to cover an
area other than the anode area. Then, the p.sup.+-type GaAs layer
61 of the anode area is etched by a selective dry etching process
using BCl.sub.3 gas and the photoresist pattern layer as a
mask.
[0131] Next, referring to FIG. 19F, a photoresist patter layer (not
shown) is formed by a photolithography process to cover an area
where the Schottky barrier diode SBD and the heterojunction bipolar
transistor HBT will be formed. Then, the n.sup.+-type GaAs contact
layer 2 and the GaAs substrate 1 are etched by using the
photoresist pattern layer as a mask.
[0132] Next, referring to FIG. 19G, a silicon oxide layer 13 is
deposited by a CVD process.
[0133] Next, referring to FIG. 19H, the silicon oxide layer 13 is
perforated by a photolithography and dry etching process using
SF.sub.6 gas to form openings for an anode electrode 5(A), a base
electrode 65 and an emitter electrode 66. Then, the anode electrode
5(A), the base electrode 65 and the emitter electrode 66 are buried
in the openings by a sputtering and lift-off process.
[0134] Next, referring to FIG. 19I, the silicon oxide layer 13 is
perforated by a photolithography and dry etching process using
SF.sub.6 gas to form openings for a cathode electrode 6(C) and a
collector electrode 6(C'). Then, the n.sup.+-type GaAs contact
layer 2 is etched by a wet etching process using phosphoric acid.
In this case, the etching depth of the n.sup.+-type GaAs contact
layer 2 is about 100 .ANG.. Then, the cathode electrode 6(C) and
the collector electrode 6(C') are buried in the openings by a
sputtering and lift-off process, to obtain the semiconductor device
of FIG. 18.
[0135] In FIG. 18, the anode electrode 5(A) can be buried in the
n.sup.--type GaAs layer 4, the base electrode 65 can be buried in
the p.sup.+-type GaAs base layer 61, and the emitter electrode 66
can be buried in the n.sup.+-type InGaAs emitter cap layer 63.
[0136] FIG. 20 is a cross-sectional view illustrating a
semiconductor device in which the Schottky diode SBD of FIG. 6 is
combined with a high electron mobility transistor HEMT and a
heterojunction bipolar transistor HBT.
[0137] In FIG. 20, the semiconductor device of FIG. 16 and the
semiconductor device of FIG. 18 are combined altogether. In this
case, the i-type InGaAs channel layer 51 and the n-type AlGaAs
electron supply layer 52 are also formed in the heterojunction
bipolar transistor HBT, however, the i-type InGaAs channel layer 51
and the n-type AlGaAs electron supply layer 52 are meaningless for
the heterojunction bipolar transistor HBT.
[0138] In order to manufacture the semiconductor device of FIG. 20,
one eptaxial layer is grown on the GaAs substrate 1. That is, as
illustrated in FIG. 21, an i-type InGaAs channel layer 51, an
n-type AlGaAs electron supply layer 52, an n.sup.+-type GaAs
contact layer 2, an n-type AlGaAs etching stopper layer 3, an
n.sup.+-type GaAs layer 4, a p.sup.+-type GaAs base layer 61, an
n-type AlGaAs emitter layer 62, and an n.sup.+-type InGaAs emitter
cap layer 63 are grown on a semi-insulating GaAs substrate 1 by an
MBE process, a MOGVD process or a VPE process. In this case, the
n-type AlGaAs etching stopper layer 3 is about 50 .ANG. thick.
[0139] Other manufacturing steps of the semiconductor device of
FIG. 20 are similar to those of the semiconductor device of FIG.
18.
[0140] In FIGS. 16, 18 and 20, since an epitaxial growing process
is carried out only once, no deep trap level is generated, which
would improve the low frequency noise characteristics. Also, the
manufacturing cost would be decreased. Further, the characteristics
among wafers and among lots hardly fluctuate, which would increase
the manufacturing yield.
[0141] In FIG. 16, 18 and 20, although the Schottky barrier diode
of FIG. 6 is combined with a high electron mobility transistor HEMT
and/or a heterojunction bipolar transistor HBT, the Schottky
barrier diode SBD of FIGS. 4 and 7, the tunnel diode TD of FIG. 8
and the PIN diode of FIG. 10 can be combined with a high electron
mobility transistor HEMT and/or a heterojunction bipolar transistor
HBT.
[0142] As explained hereinabove, according to the present
invention, since the path of a current is distant from the surface
level which would generate low frequency noise, the low frequency
characteristics can be improved.
* * * * *