U.S. patent application number 10/096899 was filed with the patent office on 2003-06-12 for voltage level shifting circuit.
Invention is credited to Foroudi, Navid, Peirce, John N.M..
Application Number | 20030107426 10/096899 |
Document ID | / |
Family ID | 24128644 |
Filed Date | 2003-06-12 |
United States Patent
Application |
20030107426 |
Kind Code |
A1 |
Foroudi, Navid ; et
al. |
June 12, 2003 |
Voltage level shifting circuit
Abstract
An integrated level shifter circuit converts an input signal
having a first voltage potential to an output signal having a
second voltage potential. The level shifter circuit provides
circuit operation between the sections when the voltage potential
of the input logic signal is converted to the output logic signal
having lower voltage potential. For logic signals transmitted
between sections of an integrated circuit operating with different
supply voltages. The level shift circuit for each input includes
two transistors and a voltage divider circuit having two resistors
in series. The values of the resistors are selected to yield a
desired output voltage at a node between the two resistors. In
effect, the resistors lessen the a full 0.9 volt diode drop to
yield a level shift which is a fraction of a diode drop. A
capacitor in parallel with the resistor provides a path for AC
signals and increases both the speed and bandwidth of the level
shifter.
Inventors: |
Foroudi, Navid; (Ottawa,
CA) ; Peirce, John N.M.; (Ottawa, CA) |
Correspondence
Address: |
FREEDMAN & ASSOCIATES
117 CENTREPOINTE DRIVE
SUITE 350
NEPEAN, ONTARIO
K2G 5X3
CA
|
Family ID: |
24128644 |
Appl. No.: |
10/096899 |
Filed: |
March 14, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10096899 |
Mar 14, 2002 |
|
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09534083 |
Mar 24, 2000 |
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6433611 |
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Current U.S.
Class: |
327/333 |
Current CPC
Class: |
H03K 19/013 20130101;
H03K 19/01812 20130101; H03K 5/003 20130101 |
Class at
Publication: |
327/333 |
International
Class: |
H03L 005/00 |
Claims
What is claimed is:
1. A current-mode level shifting circuit comprising: a first and a
second input terminal; a first and a second transistor each having
a collector, a base and an emitter, the collectors of the two
transistors being coupled to a common voltage terminal, the base of
the first and second transistor being coupled to the first and
second input terminal respectively; the base of each of the first
and second transistor being coupled to a voltage divider circuit,
each voltage divider circuit comprising a first and a second
resistor in series between the respective base and emitter of
respective transistors, a node between each first and second
resistors in series being output nodes; a differential pair of
transistors; and, two load circuits comprising a resistive circuit
element in parallel with a circuit element for conducting current
without affecting a voltage drop thereacross in a substantial
manner, each load circuit coupled to a collector of the
differential pair for providing a substantially constant voltage
less than a circuit supply voltage at the respective collectors in
operation, wherein each voltage divider has a capacitor connected
in parallel with one of the first and second series resistors.
2. A load circuit for provision of current from a source to a
high-speed circuit comprising: a first port for communication with
the source; a second port for communication with the high-speed
circuit; a resistor electrically connected between the first and
second port providing a first path of current flow in a first mode
of operation of the load circuit; and, a diode electrically
connected between the first and second port, wherein the diode is
coupled in parallel to the resistor for providing a second path of
current flow from the source to the high speed circuit when the
diode is switched for conducting current.
3. A load circuit for provision of current from a source to a
high-speed circuit as defined in claim 2, wherein the high-speed
circuit is used for mobile wireless applications.
4. A load circuit for provision of current from a source to a
high-speed circuit as defined in claim 2, wherein in a first mode
of operation substantially all current is provided via the first
path of current flow.
5. A load circuit for provision of current from a source to a
high-speed circuit as defined in claim 2, wherein in a second mode
of operation current is provided via the first path and the second
path of current flow, a fixed current provided via the first path
of current flow.
6. A load circuit for provision of current from a source to a
high-speed circuit as defined in claim 2, wherein the diode
comprises a Schottky diode.
7. A load circuit for provision of current from a source to a
high-speed circuit as defined in claim 2, wherein the source
comprises a battery.
8. A method of provision of current from a source to a high-speed
circuit comprising the steps of: receiving the current from the
current source via a first port; transmitting the current in a
first mode of operation via a resistor to a second port connected
to the high-speed circuit when a voltage drop between the first and
the second port is less than a switching voltage of the diode; and,
transmitting the current in a second mode of operation via a
resistor and a diode connected in parallel thereto, to the second
port when a voltage drop between the first and the second port
exceeds a switching voltage of the diode.
Description
[0001] This application is a continuation-in-part of U.S. patent
application Ser. No. 09/534,083 filed Mar. 24, 2000.
FIELD OF THE INVENTION
[0002] This invention relates generally to voltage level shifting
and more particularly to introducing a variable common-mode DC
level offset for a wideband AC signal.
BACKGROUND OF THE INVENTION
[0003] Level shift circuits which are necessary in digital circuits
that belong to high-speed, differential logic families such as
emitter coupled logic (ECL) or current mode logic (CML) are well
known. U.S. Pat. No. 6,018,261 incorporated herein by reference,
describes a requirement for such a circuit.
[0004] Earlier prior art level shift circuits provide a wideband
solution for obtaining a fall diode voltage (Vbe) drop in the
common-mode direct current (DC) voltage level of alternating
current (AC) input signals. Typical circuits that require such a
level shift circuit are shown in FIGS. 1A and 1B and are described
in prior art U.S. Pat. No. 6,018,261. The emitter coupled logic
latch shown in FIG. 1A requires differential clock input signals
(CLK, CLKX) whose common-mode DC voltage must be shifted down from
the common-mode DC voltage of the differential data input signals
(D, DX) for proper circuit operation to occur. In particular, for
the latch shown in FIG. 1A, the base to collector junctions of
devices connected to the clock inputs CLK and CLKX would be forward
biased if the common-mode DC level of the differential clock input
signals were not shifted down from the common-mode DC level of the
data inputs D and DX. Thus, it becomes necessary to lower the
common-mode DC level of the clock input signals CLK and CLKX to a
low enough potential to avoid forward biasing the base to collector
junctions of the current steering transistors. A more complex
situation exists where three bias levels are required as shown in
FIG. 1B.
[0005] One typical circuit, which has been extensively used to
lower the common-mode DC level of an AC signal, is the emitter
follower circuit shown in prior art FIG. 2. This type of circuit
has been developed to lower the common-mode DC voltage level of the
clock input signals by an amount equal to a full base to emitter
voltage drop for a given bias current. Since the common-mode DC
level of the incoming clock signals at terminals INO and INOX is
approximately at the supply voltage, the emitter follower circuit
lowers the common-mode DC level of the clock signals at terminals
O1 and O1X by a full diode drop below the supply voltage. An
alternative configuration for obtaining a full diode drop level
shift without limiting the input signal's AC bandwidth is shown in
prior art FIG. 4. This approach uses the path through a high-speed
differential buffer to maintain high output signal bandwidth. In
this approach, a diode connected bipolar transistor Q4 having its
collector and base shorted is used to drop the differential
buffer's supply voltage by a full diode drop or by about 0.9 volts.
Thus, the common-mode DC level of the output signals appearing at
terminals CLK_OUT and CLK_OUTX is shifted down by a full diode drop
from the supply voltage.
[0006] The problem with the full diode drop level shift circuits
identified in FIG. 2 and FIG. 4 and described in U.S. Pat. No.
6,018,261 is that the present design environment for integrated
circuits requires circuit operation in the presence of supply
voltages as low as 1.8 volts DC for circuits with two DC bias
levels such as the latch in FIG. 1A. A similar requirement is for
circuits with three bias levels, such as the circuit in FIG. 1B, to
operate at 2.7 volts. In a contemporary, bipolar process, a base to
emitter diode voltage drop is approximately 0.9 volts for active
devices that are biased for high-speed operation. When the supply
voltage is lowered to 1.8 volts and the common-mode DC level of the
clock input signals is shifted down by 0.9 volts through the use of
the full diode drop level shift circuits illustrated in FIG. 2 or
FIG. 4, the resulting common-mode DC level of the signals appearing
at terminals CLK and CLKX of FIG. 1A is 0.9 volts below the 1.8
volt supply voltage, i.e. 0.9 volts. Again, since a base to emitter
voltage drop is around 0.9 volts, the DC voltage level present at
the emitters of devices Q2 and Q3 in FIG. 1A will be approximately
zero volts.
[0007] Thus, the collector to emitter voltage of the current
sinking transistor, Q1 in FIG. 1A, will also be approximately zero
volts. In the presence of the required bias voltage of around 0.9
volts at the base of transistor Q1, the base to collector voltage
of Q1 would be sufficiently high to forward bias this junction, and
Q1 would be in saturation and would not act as a current sink.
Therefore, it is not possible to operate digital circuits that
belong to high-speed, differential logic families such as emitter
coupled logic (ECL) or current mode logic (CML) with traditional
full diode drop level shift circuits when operating with supply
voltages as low as 1.8 volts.
[0008] FIG. 1A can be treated as an output circuit consisting of a
pair of resistors R1 and R2 with equal value resistance. One
terminal of each resistor is connected to a supply voltage (Vdd).
The remaining terminals OUT and OUTX of the resistors are driven by
a pair of linked bi-value currents I1 and I2. When I1 is at value
I, I2 is at value 0. Conversely, if I2 is at value I, I1 is at
value 0. In this way, a logic signal is defined between terminals
OUT and OUTX of the circuit. Logic HIGH is defined when the voltage
at terminal OUT is approximately equal to Vdd while the voltage at
OUTX is approximately equal to Vdd-Vlogic, where Vlogic is the
product of resistor value R and current value I. Logic LOW is
defined when the voltage at terminal OUTX is approximately equal to
Vdd while the voltage at OUT is approximately equal to Vdd-Vlogic.
Typically Vlogic is defined with value sufficiently large to steer
substantially all the current in a bipolar diffamp to one collector
of the amplifier but small compared to a silicon diode voltage. A
typical value is 200 millivolts (mV).
[0009] FIG. 1B is a typical input circuit illustrating logic with
three DC bias levels. The circuit consists of differential
amplifiers (devices Q11 through Q16) stacked to form an AND gate.
The output voltage is generated by drawing current through
differential load resistors R3 and R4. The circuit is biased by
source Q17 with fixed value I. Logic levels at the output are
defined in the same manner as in a transmitting circuit coupled at
the input ports thereof. As seen in the figure, output terminal AND
is at logic HIGH only when terminal A is at high potential compared
to AX, B is at high potential compared to BX and C is at high
potential compared to CX.
[0010] The need for level shifting the inputs to a receiving
circuit coupled to the output ports thereof is demonstrated by
studying the DC voltage constraints at the inputs to the receiving
circuit. If the transmitting circuit is coupled to terminals A and
AX, acceptable performance can be achieved. If it is assumed that
terminals A and AX are excited by a voltage between Vdd and
Vdd-Vlogic, application of similar voltages to terminals B and BX
results in saturation of devices Q13 and Q14. This results in slow
or incorrect circuit operation. Clearly, the DC level of the
voltages applied to terminals B and BX must be shifted down with
respect to the voltages applied at A and AX by at least Vsat, the
minimum voltage applied across a bipolar collector-emitter junction
to keep that device from saturating. Similarly, the voltages at
terminals C and CX must be below the voltages at B and BX by at
least Vsat. At the same time, the logic definitions of the signals
must be preserved. For these operations a level shift circuit is
required.
[0011] As discussed above, the problem with the full diode drop
level shift circuits identified in FIG. 2 and FIG. 4 is that the
present design environment for integrated circuits requires supply
voltages to be minimized. In a contemporary, small-geometry bipolar
process, a base to emitter diode voltage drop is approximately 0.9
volts for active devices at room temperature that are biased for
high speed operation. Using full diodes for level shifts and
assuming a Vsat of 0.4 volts, the minimum voltage Vdd applied
required for correct circuit operation in FIG. 1B is 3.1 volts at
room temperature. For a circuit such as FIG. 1A with only two
inputs a supply voltage of 2.2 volts is required. To meet industry
supply voltage standards, it is desirable to operate at voltages as
low as 2.7 volts with 3 levels of logic and 1.8 volts with 2 levels
of logic.
[0012] A solution to this problem is to create a level shift
circuit that produces a DC level shift that is a fraction of a
diode drop. In that way, three-level logic could be supported by
coupling a CML transmitting signal directly to the A inputs of a
receiving circuit, through the fractional diode level shifter to
the B inputs of the receiving circuit and through a full-diode
level shifter to the C inputs of the receiver. For two-level logic,
only the A and B connections would be required.
[0013] A fractional-diode level shift circuit would behave
optimally if the level shift voltage is set to 1/2 Vbe and
maintained at that value. This can be seen by returning again to
the receiving circuit in FIG. 1B. Assume that input pairs A, B and
C are driven by 0, F and 1 diode level shifts, respectively, where
F is a fraction between 0 and 1. If F is greater than 0.5, this
moves transistors Q15 and Q16 closer to or into saturation. If F is
less than 0.5, this moves transistors Q13 and Q14 closer to or into
saturation. Maximum immunity to device saturation on both Q13, Q14
and Q15, Q16 is achieved when F is at 0.5. Since diode voltage Vbe
is a function of temperature, the level shift voltage (F)(Vbe)
should track in proportion to Vbe with temperature for optimal
performance.
[0014] One way to avoid having to lower the clock input signal's
common-mode DC voltage by the full 0.9 volt diode drop is shown in
prior art FIG. 3. This circuit uses R1 and R2 to lower the
common-mode DC level of the input signal by an arbitrary fraction
of a base to emitter voltage drop. Resistors R1 and R2 form a
voltage divider which subdivides the voltage between the base and
emitter of Q1. Since the circuit produces a voltage drop that is
some fraction of a full base to emitter voltage drop, it is
referred to herein as a sub-Vbe level shifting circuit. When a 1.8
volt supply is used, dropping the voltage by 0.45 volts instead of
0.9 volts allows the latch in FIG. 1A to operate correctly.
[0015] An inherent problem with the circuit illustrated in FIG. 3
is a significant reduction in circuit speed and bandwidth due to
the presence of a large time constant directly in the signal path.
This occurs because resistors R1 and R2 must be made large enough
not to sink substantial current from previous stages. This large
resistance, together with the input capacitance of the transistors
in the next stage, forms a long time constant relative to the
period of the incoming signals. An example of this scenario might
be a contemporary IC process for which a minimum-sized NPN
transistor's base transit time is 9.9 pS and for which the maximum
transition frequency (Ft) has been found to occur at a collector
bias current of 200 .mu.A. In this situation and referring to FIG.
3, the base charging capacitance of Q1 would be approximately 75 fF
and would dominate the maximum useful frequency of the device.
Assuming that only 20 uA is to flow through R1 and R2 from the
previous stage, then the values selected for R1 and R2 each will be
about 33 KOhms. With this value of resistance attached to the base
terminal, the corner frequency would be only approximately 32 MHz
at the input of the sub-Vbe level shift circuit. This frequency
response is not adequate for the present high frequency design
environment around 3-4 GHz.
[0016] Therefore, the need exists for a circuit configuration for
application as a DC level offset for wideband AC signals.
Traditional full diode drop level shifting circuits do not work
with ECL and CML logic structures at low supply voltages. Thus, it
would be desirable to have a circuit, which would provide a
fraction of a diode voltage drop DC voltage offset from a supply
voltage or potential without limiting the bandwidth of the wideband
signals.
[0017] In an attempt to overcome the limitations of the prior art
circuit of FIG. 3, U.S. Pat. No. 6,018,261 provides a somewhat
complex solution to providing a circuit, which has a fraction of a
diode voltage drop DC voltage offset from a supply voltage and
which overcomes the significant reduction in circuit speed and
bandwidth.
[0018] Referring now to the prior art circuit of FIG. 5, a block
diagram illustrating an embodiment of the sub-Vdd voltage offset
circuit is shown generally at 100. This circuit 100 is generally
used for transmitting a lock signal from a transmitting circuit to
a receiving circuit. As is well known in the art, a "signal" may be
defined by referring to FIG. 1A discussed herein.
[0019] To illustrate its operation of the circuit of FIG. 5
disclosed in U.S. Pat. No. 6,018,261, an input voltage or bias 101
is applied to bias sub-Vbe reference 103 and to bias a comparator
circuit 105. The output of the sub-Vbe reference 103 is set to a
voltage which is less than the supply voltage (Vdd) by some
fraction of a diode voltage drop (Vbe). Typically, the supply
voltage Vdd is approximately 1.8 volts. P-channel MOSFET transistor
107 is connected to the output of the comparator circuit 105 and
sources current from supply voltage Vdd to a sub-Vdd reference
point 109 and comparator input 108 to close a feedback control
loop. Comparator 105 controls the gate to source voltage of
transistor 107 such that the voltage at the sub-Vdd reference point
109 is held at approximately the same voltage as the output voltage
of the sub-Vbe reference 103 over variations in load current drawn
through transistor 107. The sub-Vbe circuit 100 operates by
creating a voltage source whose output current and voltage appear
at sub-Vdd reference point 109 and whose voltage is an arbitrary
fraction of a diode voltage drop (Vbe) lower than the supply
voltage Vdd.
[0020] Although this circuit appears to perform its intended
function, it appears to be complex and costly to manufacture.
Furthermore it does not provide the ability to dispose the level
shifter at any desired location in a desired path within the
circuit topology since the level shifter in FIG. 5 is combined with
a gate.
[0021] It is an object of this invention to provide a voltage level
shift circuit that is inexpensive to implement using a conventional
integrated circuit process.
[0022] It is therefore an object of this invention to provide a
significant improvement to the circuit shown in FIG. 3, which
greatly lessens the inherent problems associated with speed and
bandwidth that were mentioned heretofore.
SUMMARY OF THE INVENTION
[0023] In accordance with the invention there is provided, a
voltage level shifting circuit for use with an alternating current
signal for providing a voltage offset up to a portion of a full
diode voltage drop below a supply voltage, comprising:
[0024] an input terminal for receiving the alternating current
signal;
[0025] a first and a second transistor connected in series, the
first transistor having a collector, a base and an emitter, the
base of the first transistor being connected to or serving as the
input terminal, the second transistor being electrically coupled
with the emitter of the first transistor, the base of the first
transistor being coupled to the second transistor via a first and a
second resistor in series forming a voltage divider network, the
first resistor connected to the base of the first transistor, a
node between the two resistors being an output terminal; and,
[0026] a capacitor connected in parallel with one of the
resistors.
[0027] In accordance with the invention a voltage level shifting
circuit is provided comprising:
[0028] a first transistor having a collector, a base and an
emitter, the collector for being coupled to a supply voltage, the
base serving an input for an input signal to be level shifted; a
voltage divider circuit coupled between the base and the emitter of
the first transistor and having a node therebetween serving as an
output node; and
[0029] a capacitor for reducing high frequency impedance in
parallel with a portion of the voltage divider circuit.
[0030] In accordance with the invention there is further provided,
a current-mode level shifting circuit comprising:
[0031] a first and a second input terminal;
[0032] a first and a second transistor each having a collector, a
base and an emitter, the collectors of the two transistors being
coupled to a common voltage terminal, the base of the first and
second transistor being coupled to the first and second input
terminal respectively; the base of each of the first and second
transistor being coupled to a voltage divider circuit, each voltage
divider circuit comprising a first and a second resistor in series
between the respective base and emitter of respective transistors,
a node between each first and second resistors in series being
output nodes; and,
[0033] each voltage divider having a capacitor connected in
parallel with one of the first and second series resistors.
[0034] In accordance with another aspect of the invention there is
provided, a load circuit for provision of current from a source to
a high-speed circuit comprising:
[0035] a first port for communication with the source;
[0036] a second port for communication with the high-speed
circuit;
[0037] a resistor electrically connected between the first and
second port providing a first path of current flow in a first mode
of operation of the load circuit; and,
[0038] a diode electrically connected between the first and second
port, wherein the diode is coupled in parallel to the resistor for
providing a second path of current flow from the source to the high
speed circuit when the diode is switched for conducting
current.
[0039] In accordance with the other aspect of the invention there
is further provided, a method of provision of current from a source
to a high-speed circuit comprising the steps of:
[0040] receiving the current from the current source via a first
port;
[0041] transmitting the current in a first mode of operation via a
resistor to a second port connected to the high-speed circuit;
and,
[0042] transmitting the current in a second mode of operation via a
diode, the diode being connected in parallel to the resistor, to
the second port if a voltage drop between the first and the second
port exceeds a switching voltage of the diode.
BRIEF DESCRIPTION OF THE DRAWINGS
[0043] Exemplary embodiments of the invention will now be described
in conjunction with the drawings in which:
[0044] FIG. 1A is a prior art schematic diagram showing an ECL or
CML latch used in transmitting and receiving circuits indicating
the need for level-shift circuits.
[0045] FIG. 1B is a prior art schematic diagram showing an AND gate
and indicating the need for level-shift circuits.
[0046] FIG. 2 is prior art schematic showing a traditional full
diode drop level shift circuit for differential AC signals.
[0047] FIG. 3 is prior art schematic showing a voltage level shift
circuit.
[0048] FIG. 4 is prior art schematic showing an alternative,
wideband full diode drop level shift topology.
[0049] FIG. 5 is a block diagram of a prior art circuit that is a
sub-Vbe voltage reference circuit, having a comparator, and current
sourcing transistor.
[0050] FIG. 6a is a is a schematic diagram of a sub-Vbe voltage
level shift circuit in accordance with the invention which greatly
improves upon the prior art circuit shown in FIG. 3.
[0051] FIG. 6b is a is a schematic diagram of the circuit of FIG.
6a with a load applied thereto.
[0052] FIG. 7a is a graph of two plots showing a 100 MHz input
signal and an output response of a prior art circuit absent
additional capacitors across one of the voltage divider
resistors.
[0053] FIG. 7b is a graph of two plots showing a 100 MHz input
signal and an output response of a prior art circuit having
capacitors across one of the voltage divider resistors as is taught
in accordance with this invention.
[0054] FIG. 8a is a graph of two plots showing an 800 MHz input
signal and an output response of a prior art circuit absent
additional capacitors across one of the voltage divider
resistors.
[0055] FIG. 8b is a graph of two plots showing an 800 MHz input
signal and an output response of a prior art circuit having
capacitors across one of the voltage divider resistors as is taught
in accordance with this invention;
[0056] FIG. 9 is a graph of a circuit in accordance with an aspect
of this invention wherein load circuits according to the invention
are used to provide a substantially constant voltage at collectors
of a differential pair of a CML latch that is approximately 0.3
volts below a supply voltage, while allowing current to pass;
[0057] FIG. 10a is a schematic diagram showing a load circuit
according to the invention;
[0058] FIG. 10b is a schematic diagram of the load circuit shown in
FIG. 10a in a first mode of operation;
[0059] FIG. 10c is a schematic diagram of the load circuit shown in
FIG. 10a in a second mode of operation; and,
[0060] FIG. 11 is a graphical diagram showing a characteristic of a
diode.
DETAILED DESCRIPTION
[0061] Referring once again to the prior art circuit of FIG. 3, and
for ease of explanation looking at only a portion of the circuit
including Q1 and Q2 and the voltage divider circuit consisting of
resistors R1 and R2 in series coupled between the base of Q1 and
the emitter of Q1, it is evident that the voltage at the output
terminal O1 is related to Vbe of Q1 and is scaled by the ratio of
R1 and R2, such that if R1=R2 the voltage at O1=V(IN0)-(Vbe/2).
Although this accomplishes the desired effect of providing less
than a full diode drop from input IN .O slashed. to output O1, as
was mentioned heretofore, the parasitic capacitance at the base of
the transistor in the following circuit which in combination of the
resistor R1 acts as a low-pass filter and severely limits the
performance of the circuit.
[0062] A preferred exemplary embodiment of the invention shown in
FIG. 6a, which illustrates a dual level shifter that can be used
with a CML circuit, that provides a solution which obviates much of
the problem induced by effect of the unwanted low-pass filter
formed by the RC circuit consisting of resistor R1 (FIG. 3) and the
parasitic capacitance at the input of the transistor in the
following stage. By the addition of capacitors C2 and C3 in this
example having a value of 200 femto-Farads across the resistors R2
and R3 respectively, each having a resistance of 46.3 K.OMEGA.,
effectively providing an alternative path for high frequency AC, a
high-pass filter is formed which offsets the limitations of the
unwanted low-pass filter. By providing the capacitor in parallel
with resistor R3, the emitter rather than the base of transistor Q4
is loaded, which is preferable since the impedance of the emitter
is lower than that of the base. Loading of the circuit is shown in
FIG. 6b, which was used for circuit evaluation through simulation.
Notwithstanding, if the previous stage to the voltage level shifter
has a very low output impedance, it may be preferable to provide
the capacitor C3 across the resistor R5 or capacitors across both
resistors.
[0063] FIG. 7a is a graph consisting of two simulated plots in the
form of an input waveform above and an output waveform below for a
100 MHz input signal applied to the circuit of FIG. 6b, absent the
capacitors C2 and C3. The differential input signals are applied to
the terminals inputn and inputp of the transistors Q2 and Q4
respectively. The output signals are measured at terminals op and
on.
[0064] Clearly, it can be seen that the output waveform is delayed
and its substantially square shape is significantly degraded after
it has effectively passed through a low-pass filter formed by the
resistor parasitic capacitance combination.
[0065] FIG. 7b is a graph consisting of two simulated plots in the
form of an input waveform above and an output waveform below for
the same 100 MHz input signal applied to the circuit of FIG. 6b, as
is shown in FIG. 7a with the capacitors C2 and C3 present. As with
FIG. 7a, the differential input signals are applied to the
terminals inputn and inputp of the transistors Q2 and Q4
respectively. The output signals measured are at terminals outputp
and outputn. It is immediately evident that by providing the
capacitors C2 and C3 in accordance with this invention, the output
response very closely tracks the input response. The delay between
input and output is negligible and the waveform substantially
retains its shape, from input to output.
[0066] This effect is more accentuated in FIG. 8a and FIG. 8b where
a higher frequency 800 MHz signal is applied. As a result of
increasing the frequency and not providing the capacitors C2 and
C3, the output response is substantially delayed in time and the
output waveform is significantly more distorted than the output
response of FIG. 7a, having little in common with the input signal
from which it was generated.
[0067] Notwithstanding the improvement in the performance of the
level shifter is indicated by viewing FIG. 8b wherein the
capacitors C2 and C3 are used.
[0068] Thus, in accordance with this invention an inexpensive
solution is possible. Providing capacitor C3 in parallel with the
second resistor R3, greatly enhances the performance of the circuit
of FIG. 6. Since this is a differential circuit having a
differential pair Q5 and Q6, a practical embodiment of this
particular circuit requires two level shifters each having an
additional capacitor C2 and C3 respectively. Selecting the values
of the capacitor depends in part on the values of the resistors R4,
R2 and R5, R3, and is dependent upon the inherent parasitic
capacitance of, for example transistors Q5 and Q6.
[0069] In a preferred embodiment of the invention the two resistors
of the voltage divider pair have a resistance ratio of 1:1+30%.
[0070] Turning now to FIG. 9, an alternative embodiment of the
invention is shown including a CML latch with a level shifter
circuit at its output. Q2 and Q2bar are a fraction of a diode drop
lower than Q and Qbar. Load circuits 100 provide a load at the
input end of the circuit and replace conventional load resistors
typically provided in conventional circuits.
[0071] The invention replaces conventional load resistors typically
provided in conventional circuits for varying the voltage source
voltage levels. An inherent problem with conventional load
resistors is a significant reduction in circuit speed, which is
exaggerated with increasing current supplied to the circuit. The
resistance R of the load resistor together with a parasitic
capacitance C, which is present in all electric circuits, produces
a time constant proportional to the product RC limiting operating
speed of the circuit. Another disadvantage of conventional load
resistors is the dependence of the voltage drop upon the current
that passes through the resistor. A current dependent variable
voltage swing can affect the operation of high-speed circuits. This
problem is enhanced at higher currents due to the proportionality
of the voltage swing to the product of the resistance R of the load
resistor and the current i.
[0072] Typically, there is a tradeoff in high-speed circuit design.
More current is used to generate higher speed circuits that draw
more power and are, therefore, less mobile. Less current is used in
slower circuits. Also, to increase speed of operation of the
circuit, the voltage swings used to represent on and off states are
reduced to limit any effects of RC time constants on the circuit.
Unfortunately, high current consumption is a limiting factor in
battery life of portable electronic devices and as such, is
generally not desirable. At a same time, electronics for wireless
applications, which are battery powered, increase in operating
speed over time.
[0073] Referring to FIG. 10 a load circuit 100 for provision of a
direct current to a high-speed circuit according to the invention
is shown. The load circuit 100 comprises a load resistor 102 and a
diode 104 in the form of a Schottky diode disposed in parallel
between the power supply and a powered circuit. Input port 106 of
the load circuit is connected to a DC power supply such as a
battery for providing a current from the battery to the circuit.
Output port 108 is electrically coupled to an input of the powered
circuit in the form of a high-speed battery powered circuit for
propagation of the current to the circuit. The two modes of
operation of the load circuit 100 will now be described with
reference to FIGS. 10b and 10c. FIG. 10b shows a first mode of
operation with current i1 flowing through resistor 102 as indicated
by arrows. This causes a voltage drop Vi1 proportional to the
product of resistance R of the resistor 102 and current i1.
Increasing current i1 increases the voltage drop accordingly. When
the voltage drop Vi1 equals a switching voltage of the diode 104
the diode acts to conduct current. The switching voltage is
approximately equal to a voltage drop of the diode Vdiode, which is
substantially a fixed value independent of the current provided
thereto, as indicated in the diagram shown in FIG. 11. For example,
Schottky diodes have a small fixed voltage drop of approximately
0.3 volts. After switching of the diode 104, in a second mode of
operation, a second path for the current is provided. With a near
fixed current i1max passing through the resistor R, the voltage
drop necessary to switch the diode into its conducting state is
provided. In contrast to typical load resistors the diode allows
the current to pass therethrough without an additional voltage drop
thereacross and, as such, limits the effects of the RC time
constant on the circuit operating speed. Also, R is easily selected
to result in a desired RC time constant without greatly affecting
circuit operation. In fact, the selection of R is an engineering
decision since the voltage drop i1max is somewhat identical
regardless of the value R and, as such, circuit operation is not
affected by those tradeoffs affecting the prior art.
[0074] Therefore, the load circuit according to the invention
substantially reduces the time constant and the voltage swing
compared to load resistors, which is highly advantageous for
high-speed circuits.
[0075] As is evident to a person of skill in the art, the load
circuit according to the invention can be easily adapted to the
needs of a high-speed circuit by choosing a suitable combination of
a resistor and a diode from a large variety of resistors and diodes
commonly available.
[0076] Of course numerous other embodiments may be envisaged
without departing from the spirit and scope of the invention.
* * * * *