U.S. patent application number 09/993719 was filed with the patent office on 2003-06-05 for modeling of phase synchronous circuits.
This patent application is currently assigned to INTEL CORPORATION. Invention is credited to Henry-Greard, Loic, Kam, Timothy, Kishinevsky, Michael.
Application Number | 20030106029 09/993719 |
Document ID | / |
Family ID | 25539851 |
Filed Date | 2003-06-05 |
United States Patent
Application |
20030106029 |
Kind Code |
A1 |
Kishinevsky, Michael ; et
al. |
June 5, 2003 |
MODELING OF PHASE SYNCHRONOUS CIRCUITS
Abstract
Embodiments of the present invention generate equations that
model a synchronous circuit that contains sequential elements,
which may include transparent elements, and a plurality of
multiple-phase clocks. Phase-related information is assigned to
nodes of the circuit. The phase-related information describes input
and output characteristics at nodes of the circuit as the
characteristics relate to clock phases. Equations are formed that
model signals at the circuit nodes based on the phase-related
information.
Inventors: |
Kishinevsky, Michael;
(Beaverton, OR) ; Kam, Timothy; (Portland, OR)
; Henry-Greard, Loic; (Portland, OR) |
Correspondence
Address: |
KENYON & KENYON
1500 K STREET, N.W., SUITE 700
WASHINGTON
DC
20005
US
|
Assignee: |
INTEL CORPORATION
|
Family ID: |
25539851 |
Appl. No.: |
09/993719 |
Filed: |
November 27, 2001 |
Current U.S.
Class: |
716/108 |
Current CPC
Class: |
G06F 30/33 20200101 |
Class at
Publication: |
716/4 ; 716/5;
716/6 |
International
Class: |
G06F 017/50 |
Claims
What is claimed is:
1. A method of modeling a circuit including at least one
multiple-phase clock and a plurality of sequential elements that
input and output signals, comprising: assigning clock phase
information to said signals based on a phase-related behavior of
said sequential elements; forming equations corresponding to said
circuit, wherein said equations represent said signals and
incorporate said clock phase information; and using said equations
to de-bug said circuit.
2. The method of claim 1, wherein said clock phase information is
based on phase-related input and output characteristics of emitters
of said signals and samplers of said signals.
3. The method of claim 1, wherein said clock phase information
specifies phases during which, respectively, said sequential
elements may register valid input signals and generate valid output
signals.
4. The method of claim 1, wherein said sequential elements include
transparent elements.
5. A method of deriving an equation corresponding to a sequential
element of a circuit including at least one multiple-phase clock,
comprising: assigning first phase-related information to an input
signal of said sequential element; assigning second phase-related
information to an output signal of said sequential element;
constructing an equation which computes a stable value of said
output signal based on said first and second phase-related
information; and using said equation to de-bug said circuit.
6. The method of claim 5, wherein said first phase-related and
second phase-related information describe an earliest valid time
for said input and output signal, respectively.
7. The method of claim 5, wherein said stable value is indexed by
an index representing phases of said clock, and said index is
modified by a modifier based on said first and second phase-related
information.
8. The method of claim 7, wherein said modifier has the form
.vertline.Ph.sub.i-Ph.sub.j.vertline./k, where Ph.sub.i and
Ph.sub.j correspond to said first and second phase information and
said clock has k phases.
9. The method of claim 8, wherein an equation of the form
y(i)=x(i-1+.vertline.Ph.sub.i-Ph.sub.j.vertline./k) models an
output signal of a flip-flop element of said circuit, where x is an
input signal to said flip-flop element and i is said index.
10. The method of claim 8, wherein an equation of the form
y(i)=x(i-.vertline.Ph.sub.i-Ph.sub.j.vertline./k) models an output
signal of a transparent element of said circuit, where x is an
input signal to said transparent element and i is said index.
11. A computer-usable medium tangibly embodying computer-executable
instructions, said instructions when executed implementing a
process for generating equations that model a circuit including at
least one multi-phase clock and a plurality of sequential elements
that input and output signals, comprising: (i) assigning first
phase-related information to said sequential elements and to
primary inputs and outputs of said circuit; and (ii) assigning
second phase-related information to said signals based on said
first phase-related information.
12. The computer-readable medium of claim 11, wherein said process
further comprises forming equations corresponding to said circuit,
said equations representing said signals and incorporating said
second phase-related information.
13. The computer-usable medium of claim 12, wherein said equations
compute a stable value indexed by an index representing phases of
said clock, and said index is modified by a modifier based on said
second phase-related information.
14. The computer-usable medium of claim 11, wherein (ii) further
comprises: for each of said signals, providing said first
phase-related information from its transitive fan-in and transitive
fan-out; and applying rules to said first phase-related information
to assign said second phase-related information.
15. The computer-usable medium of claim 14, wherein said rules
relate to phase-related input and output characteristics of said
transitive fan-in and transitive fan-out.
Description
TECHNICAL FIELD
[0001] The field of the present invention is that of circuit
modeling, and more specifically that of modeling of circuit designs
using phase synchronous equations.
BACKGROUND OF THE INVENTION
[0002] Logic design of, for example, integrated circuits typically
includes a design phase and a verification phase for determining
whether a design works as expected. Verification uses software
simulation to avoid the cost of first implementing a design in
hardware to verify it.
[0003] Designs to be verified can be represented in a hardware
description language (HDL) "model" that, through simulation, can
predict the behavior of a proposed design independently of its
physical implementation. The model may be expressed at varying
levels of abstraction: some levels may be highly abstract,
representing a circuit only in terms of its behavior, while other
levels may include more details of physical implementation. One
commonly utilized abstraction level is referred to as "register
transfer level," or RTL.
[0004] Writing models in HDL presents challenges. Accurate modeling
of designs may call for a significant level of implementation
detail, but too much implementation detail can introduce functional
bugs. Generally, the number of bugs in a model is proportional to
its size (i.e., the amount of code required to specify the model).
More abstract models tend to be smaller in size and may therefore
contain fewer bugs. Abstract models also allow for faster
simulation and better exploration of design space.
[0005] One known technique which has been applied in modeling logic
designs and which provides for a useful degree of abstraction and
conciseness, is the use of synchronous equations. For example, a
combinational AND gate with two inputs, "a" and "b", and output
"c", may be modeled as c(i)=a(i) b(i) (where the AND operation is
indicated by concatenation), where index i serves as a clock
counter, and a(i) corresponds to a stable value of signal a at
clock count i. As another example, a flip-flop with input x and
output y may be modeled as y(i)=x(i-1). Such synchronous equations
have been used to model, for example, iterative synchronous
algorithms used in DSP (digital signal processing) systems, in
control theory and CAD (computer-aided design) for control systems,
and in systolic computations as well as other types of
computations.
[0006] One drawback of using synchronous equations to model logic
designs, however, is that they are ill suited to model high-speed
circuits. High-speed circuits such as, for example,
high-performance microprocessors, require circuit designs that
produce very accurate clock phases, utilize transparent latches,
and support multiple clock methodologies. Standard synchronous
equations cannot model the behavior of circuits with transparent
components, multi-phase clocking, and multiple clocks.
[0007] An additional problem that arises in the coding of models of
logic designs is that typically clock phase information must be
manually coded for each signal in a design, which is a tedious,
error-prone and time-consuming process. This manual process must be
repeated if the clock phase information changes as a result of
design changes.
[0008] A method and system are needed to address the foregoing
concerns.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1 illustrates a process flow for generating phase
synchronous equations according to embodiments of the
invention;
[0010] FIG. 2A illustrates an example circuit that could be
processed according to embodiments of the invention;
[0011] FIG. 2B illustrates the example circuit of FIG. 2A with
phase labels assigned to sequential elements and primary I/O;
[0012] FIG. 2C illustrates the example circuit of FIGS. 2A and 2B
with phase labels further assigned to internal signals; and
[0013] FIG. 3 shows two different circuits that may be modeled by
the same set of phase synchronous equations according to
embodiments of the invention.
[0014] FIG. 4 illustrates a process flow according to one possible
application of embodiments of the invention.
DETAILED DESCRIPTION
[0015] Embodiments of the present invention comprise operations to
process an abstract representation of a synchronous circuit to
generate a set of phase synchronous equations corresponding
thereto. Generating the phase synchronous equations may be referred
to herein as "modeling" the circuit; similarly, the phase
synchronous equations may be referred to as a "model" of the
circuit.
[0016] A model of the circuit in the form of the phase synchronous
equations is advantageous because the model is abstract and
succinct, enabling more efficient verification of the corresponding
logic design. The equations can be used efficiently to compute
stable values of the system, given initial values, every next
phase. The values computed using the set of equations correspond to
the stable values at the outputs of the gates of the circuit.
[0017] Another advantage of the equations is that the model is
formal. "Formal" in this context means, for example, that certain
properties of the modeled system, or theorems regarding the
behavior of the system, can be proven using the equations.
[0018] As part of generating the phase synchronous equations,
embodiments of the invention may automatically generate clock phase
information for nodes of the circuit. This clock phase information
is referred to herein as "phase labels." The phase labels describe
phase-related behavior at nodes of the circuit.
[0019] The abstract representation of the synchronous circuit may
be, for example, in the form of digital data stored on a
computer-readable medium. Embodiments of the invention may take the
form of computer-executable instructions which, when executed by a
processor, process the data to generate the phase synchronous
equations.
[0020] A "netlist" is one possible form of an abstract
representation of a circuit such as could be processed according to
embodiments of the invention. A netlist may include a specification
of all logic gates in the circuit, all connections between the
gates, all primary inputs, and all primary outputs. A netlist is
typically coded in HDL as RTL-level description.
[0021] An example of a set of phase synchronous equations resulting
from application of a process according to embodiments of the
invention is shown below in Table 1.
1 TABLE 1 e(i) = F(b(i - 1), g(i - 0.5)) i .epsilon. {1, 2, . . .}
g(i) = F(a(i - 1), e(i - 0.5)) i .epsilon. {0.5, 1.5, . . .}
[0022] The equations shown in Table 1 model circuits shown in FIG.
3.
[0023] Referring now to FIG. 3, circuit 310 comprises a plurality
of sequential elements, including a rising-edge flip-flop and two
transparent latches, and a combinational element, i.e., a MUX
(multiplexer) controlled by the clock, mclk. The ellipse enclosing
the "F" symbol denotes an arbitrary function computed by one or a
plurality of gates. The circuit is driven by different clocks with
different frequencies: "fclk" and "mclk". The frequency of "fclk"
may be a multiple of (in this example, double) the frequency of
"mclk".
[0024] Circuit 320 comprises a plurality of transparent latches and
two arbitrary functions "F". Circuit 320 is driven by a single
clock, "mclk".
[0025] Circuits such as shown in FIG. 3, that is, circuits
including transparent latches, combinational elements, clocks of
different frequencies, and the like, are typically difficult to
understand. As outlined above, conventional modeling techniques are
primarily limited to handling synchronous circuits consisting of
single-edge, single-clock flip-flops and combinational logic.
Handling of transparent latches is at best limited to re-timing.
Multiple phases and multiple clocks are not supported. Similarly,
classic synchronous equations cannot model transparency, multiple
clocks, multiple clock phases, clock gating and clocked logic.
[0026] By contrast, processing of representations of the circuits
according to embodiments of the invention provides a formal model
in the form of equations which explain what the circuits are
computing even though they comprise transparent latches,
multiple-phase clocks and multiple clocks of different
frequencies.
[0027] For example, the equations shown in Table 1, which
correspond to both circuits 310 and 320, demonstrate that circuits
310 and 320 are equivalent. The equations shown in Table 1 compute
the same values, notwithstanding that circuits 310 and 320 comprise
differing elements, and notwithstanding that circuit 310 has two
clocks while circuit 320 has only one.
[0028] To generate phase synchronous equations as described in the
foregoing, a process comprising a sequence of operations may be
performed as illustrated in FIG. 1. Each operation will be
described in detail in the discussion that follows.
[0029] As shown in FIG. 1, an abstract representation 100 of a
synchronous circuit, for example a netlist, may be provided as
input to the process; the process may be implemented using
computer-executable instructions according to embodiments of the
invention. Hereinafter, for convenience, the abstract
representation 100 of the circuit is simply referred to as the
"circuit," it being understood that in actual implementation of the
process according to embodiments, the circuit would be represented
in some form of digital data suitable for being manipulated by
computer-executable instructions.
[0030] As one initial operation of the process, the circuit may be
processed to assign phase labels to each sequential element and
primary input and primary output of the circuit as shown in block
101. Sequential elements include flip-flops and transparent latches
of either polarity. As discussed in more detail below, the phase
labels describe the input and output characteristics of the
sequential elements and primary I/O as these characteristics relate
to clock phases.
[0031] In addition to sequential elements and primary inputs and
outputs, a circuit typically includes combinational elements (e.g.,
AND, OR and other Boolean logic gates, MUXes and the like). Nodes
of the circuit which may take on logic values corresponding to the
inputs and outputs of the sequential elements and combinational
elements are referred to herein as "signals."The primary inputs and
outputs are also "signals."
[0032] After phase labels have been assigned to the sequential
elements and primary I/O of the circuit as shown in block 101, the
phase labels may be "propagated" to the internal signals of the
circuit. In this context, "propagated" means that information about
behavior of "emitters" and "samplers" of each signal, as contained
in the phase labels of each emitter and sampler, is provided for
each signal to enable a determination of a phase behavior of each
signal.
[0033] An emitter may be either a primary input or an output of a
sequential element, and a sampler may be either a primary output or
an input of a sequential element. The propagated phase information
is used in a later operation to assign phase labels to each signal
according to a set of rules.
[0034] More particularly, "late phase" labels may be propagated
backwards (i.e., from the primary outputs in the direction of the
primary inputs of the circuit) as shown in block 102, and "early
phase" labels may be propagated forwards (i.e., from the primary
inputs in the direction of the primary outputs of the circuit) as
shown in block 103. The meaning of "late phase" and "early phase"
will be discussed below.
[0035] Next, an operation may be performed to reduce faster clocks
to slower clocks for multi-clock nodes, as shown in block 104. In
the case of circuits with multiple clocks with different
frequencies, this operation may be needed to determine the effect
of phases of one clock on phases of another clock. For example,
circuit 310 in FIG. 3 includes two clocks of different frequencies,
where clock "fclk" has a frequency which is a multiple (a double in
this case) of a frequency of clock "mclk." A clock reduction
operation could be executed in the case of a circuit such as
circuit 310 to determine how or whether events that occur during a
phase of "fclk" need to be considered during a phase of "mclk."
[0036] Using the phase information computed in the propagation
operations outlined above, phase labels may be assigned to the
internal signals of the circuit, as shown in block 105. A set of
rules, as described in greater detail hereinafter, may be applied,
using the propagated phase information to assign the phase labels.
As noted above, this automated phase labeling provides advantages
by offloading the task from designers.
[0037] With phase labels now assigned to sequential elements,
primary I/O, and internal signals of the circuits, the phase
synchronous equations may be generated, as shown in block 106. The
operation of generating the phase synchronous equations may utilize
a shift operator, as also described in more detail below.
[0038] An illustrative example of an application of the foregoing
operations follows.
[0039] FIG. 2A shows a circuit that might be modeled according to
embodiments of the present invention. The circuit comprises primary
inputs a and b coupled to a rising-edge flip-flop 200 and a
falling-edge flip-flop 210, respectively. Flip-flops 200 and 210
are both input to AND gate 220. AND gate 220, in turn, is coupled
to both active-high transparent latch 230 and active-low
transparent latch 240. "Transparent" in the foregoing context means
that when a clock input of the appropriate polarity is present, the
latch propagates the value of its input to its output, and when the
clock polarity changes, the latch retains its previous value.
Latches 230 and 240 are respectively coupled to primary outputs h
and k.
[0040] The primary inputs and outputs, the inputs and outputs of
each sequential element (i.e., in the example of FIG. 2A,
flip-flops 200 and 210 and latches 230 and 240) and each
combinational element (in the example of FIG. 2A, AND gate 220) are
"signals" as described above. Each signal is assigned an
identifier. In FIG. 2A, the signals are identified a, b, c, d, e,
f, g, h and k. Signals a and b, and h and k, are primary inputs and
outputs, respectively. Signals c and d are the outputs of
flip-flops 200 and 210, respectively, and inputs of AND gate 220.
Signal e is the output of AND gate 220. Signals f and g are the
inputs to latches 230 and 240, respectively.
[0041] In clock-driven digital systems, clock cycles may be
partitioned into multiple phases; thus, for example, phases of a
clock cycle with k clock phases may be denoted 0, 1, . . . , k-1.
In general, clock-driven digital systems may be driven by a single
clock or by multiple clocks. In the particular example shown in
FIG. 2A, the sequential elements (i.e., flip-flops 200, 210 and
transparent latches 230, 240) may be assumed to be clock-driven
(clock inputs are omitted from the figure for simplicity). Further,
for ease of understanding, it may be assumed that all sequential
elements, primary inputs and primary outputs run off the same
clock.
[0042] It is further assumed for ease of understanding that k=2;
i.e., that the circuit of FIG. 2A has a 2-phase clock cycle
constituted by a phase 0 followed by a phase 1. Let phase 0 be a
"clock-high" phase (a phase when the clock is high) and let phase 1
be a "clock-low" phase (a phase when the clock is low). Further,
let the clock-high phase be denoted "H" and let the clock-low phase
be denoted "L". H and L may be applied as phase labels.
[0043] As described above in connection with FIG. 3, as an initial
operation of generating phase synchronous equations, primary I/Os
and sequential elements of the circuit are assigned phase
labels.
[0044] For sequential elements, the phase labels describe the
"latest required input phase" and "earliest valid output phase" for
each sequential element. "Latest required input phase" refers to
the latest phase, during a clock cycle, that a signal can arrive at
the input of a sequential element and still be correctly registered
by the sequential element (i.e., stabilize at the correct logic
level). For example, for rising-edge flip-flop 200 of FIG. 2A, an
input signal should stabilize before the clock goes high, which
means that the input signal should arrive before the end of the L
phase of the clock.
[0045] "Earliest valid output phase" refers to the earliest phase,
during a clock cycle, that the sequential element can generate a
valid output signal (i.e., output a signal that stabilizes at the
correct logic level). Again using rising-edge flip-flop 200 as an
example, an output signal of the flip-flop can at earliest
stabilize shortly after the clock goes high, which will occur
during the H phase of the clock.
[0046] In view of the foregoing, FIG. 2B shows the circuit of FIG.
2A with phase labels assigned to the sequential elements. The phase
labels are assigned with the format "(latest required input phase,
earliest valid output phase)". Thus, rising-edge flip-flop 200 has
the phase labels (L, H) assigned to it, for the reasons described
above. For falling-edge flip-flop 210, naturally, the labels are
reversed. By applying the reasoning discussed above in connection
with flip-flop 200, it can be seen that transparent latches 230 and
240 should be assigned the phase labels (H, H) and (L, L),
respectively, as shown in FIG. 2B.
[0047] Signals of the circuit are also assigned phase labels. As
noted above, in FIG. 2A, signals are denoted by the letters a
through k. The signals correspond to primary inputs, primary
outputs, and conductors ("wires") within the circuit.
[0048] The phase labels assigned to the signals correspond to an
"early phase" and a "late phase". As used herein, "early phase"
refers to the earliest valid time for the signal, and "late phase"
refers to the latest possible arrival time for the signal. The
early phase label reflects the phase-related output characteristics
of emitters, while the late phase label reflects the phase-related
input characteristics of samplers. More particularly, the early
phase label specifies the earliest clock phase during which an
output of an emitter can become valid (stabilize at the correct
logic level), and the late phase label specifies the latest phase
during which a signal can arrive (stabilize at the correct logic
level) at the input of a sampler.
[0049] It should be noted that for sequential elements, the latest
required input phase corresponds to the late phase for signals, and
that the earliest valid output phase corresponds to the early phase
for signals.
[0050] For primary inputs, the early phase label is not known and
cannot be determined from the rest of the circuit, because emitters
for the primary inputs are in the environment of the circuit, which
is unknown. Thus, the early phase labels for primary inputs could
be assumed to be some default value, or could be supplied by a user
or determined from the environment circuit if it is given.
[0051] Symmetrically, late phase labels for the primary outputs
cannot be determined from the rest of the circuit, because samplers
of the primary outputs are in the environment, which is unknown.
Thus, as in the case of the primary inputs, this information could
be provided by a user. Alternatively, the assumption could be made
that samplers include both an element with a latest required input
phase of H and an element with a latest required input phase of L.
In the example illustrated in FIG. 2C, the "-" (dash or hyphen) in
the late phase label position of the primary outputs indicates that
this information is unknown, or that, potentially, samplers include
both an element with a latest required input phase of H and an
element with a latest required input phase of L.
[0052] FIG. 2B also shows phase labels assigned to the primary
I/O.
[0053] As discussed above, after phase labels have been assigned to
sequential elements and primary I/O, the operations of backward and
forward propagation of phase labels from sequential elements and
primary I/Os to internal signals may be performed. The propagation
operations provide the phase information regarding emitters and
samplers needed at each signal to assign phase labels.
[0054] For example, referring now to FIG. 2B, to perform backward
propagation of late phase labels, the latest required input phase
label of transparent latch 230, which has a value of H, would be
propagated to signals f, e, c and d. Similarly, the latest required
input phase label of transparent latch 240, which has a value of L,
would be propagated to signals f, e, c and d.
[0055] In the particular example of FIGS. 2A and 2B, there are no
signals between primary output h and transparent latch 230.
Similarly, there are no signals between primary output k and
transparent latch 240. Therefore, no backward propagation occurs
between primary output h and transparent latch 230, or between
primary output k and transparent latch 240. If there were signals
between these elements, the late phase labels of primary outputs h
and k would be propagated to the signals.
[0056] Again referring to FIG. 2B, to perform forward propagation
of early phase labels, the earliest valid output phase label of
flip-flop 200, which has a value of H, would be propagated to
signals c, e, f and g. Similarly, the earliest valid output phase
label of flip-flop 210, which has a value of L, would be propagated
to signals d, e, f and g. There are no signals between primary
input a and flip-flop 200, or between primary input b and flip-flop
210. Therefore, no forward propagation occurs between primary input
a and flip-flop 200, or between primary input b and flip-flop 210.
If there were signals between these elements, the early phase
labels of primary inputs a and b would be propagated to the
signals.
[0057] After backward and forward propagation, rules may be applied
to assign phase labels to internal signals. Rules for assigning
phase labels to signals are described in the following.
[0058] Phase labels for signals are denoted "(Ph.sub.1 (s),
Ph.sub.2(s))", where s is a signal (for example, a-k, referring to
FIG. 2A). Ph.sub.1 corresponds to the early phase label, and
Ph.sub.2 corresponds to the late phase label. For sequential
elements, the latest required input phase corresponds to Ph.sub.2,
and the earliest valid output phase corresponds to Ph.sub.1.
[0059] For a given signal to which phase labels are to be assigned,
the phase labels of the transitive fan-in of the signal are
analyzed. These phase labels were propagated to respective signals
during the forward propagation operation described above.
Transitive fan-in refers to all circuit elements "upstream" of a
point in a circuit; i.e., elements which may drive signals to that
point.
[0060] Each path of the transitive fan-in is traversed in the
direction of the primary inputs until a sequential element or
primary input is encountered, and then the traversal stops. If all
sequential elements and/or primary inputs first encountered in such
a traversal of the transitive fan-in of a given signal have been
assigned the same early phase label Ph.sub.1, then that early phase
label, Ph.sub.1, is assigned as the early phase label of the
signal. For example, if all first-encountered sequential elements
and/or primary inputs in the transitive fan-in of a given signal
have been assigned an early phase label of H, then H is assigned as
that signal's early phase label.
[0061] Similarly, the phase labels of the transitive fan-out of the
signal are analyzed. These phase labels were propagated to
respective signals during the backward propagation operation
described above. Transitive fan-out refers to all circuit elements
"downstream" of a point in a circuit; i.e., elements which may
receive signals driven from that point.
[0062] Each path of the transitive fan-out is traversed in the
direction of the primary outputs until a sequential element or
primary output is encountered, and then the traversal stops. If all
sequential elements and/or primary outputs first encountered in
such a traversal of the transitive fan-out of the signal have been
assigned the same late phase label Ph.sub.2, then that late phase
label, Ph.sub.2, is assigned as the late phase label of the signal.
For example, if all first-encountered sequential elements and/or
primary outputs in the transitive fan-out of a given signal have
been assigned a late phase label of L, then L is assigned as that
signal's late phase label.
[0063] The foregoing constitutes a special case of the application
of more general rules, described below, to the special case wherein
all elements in the transitive fan-in of a signal have the same
early phase label, and all elements in the transitive fan-out of
the signal have the same late phase label.
[0064] A more general rule, referred to herein as the "min" rule,
is as follows. If the first-encountered sequential elements and/or
primary inputs of the transitive fan-in of a given signal all have
the same early phase label Ph.sub.1, but the first-encountered
sequential elements and/or primary outputs of the transitive
fan-out of the signal have late phase labels that differ from each
other (i.e., Ph.sub.2 for each sequential element or primary output
is one of a set {Ph.sub.21, Ph.sub.22, . . . }, then Ph.sub.1 is
assigned as the signal's early phase label, and Ph.sub.2 for the
signal is selected from {Ph.sub.21, Ph.sub.22, . . . } such that
the phase difference between Ph.sub.1 and Ph.sub.2 is the narrowest
possible.
[0065] Another more general rule, referred to herein as the "max"
rule, is as follows. If the first-encountered sequential elements
and/or primary inputs of the transitive fan-in of a signal have
differing early phase labels {Ph.sub.11, Ph.sub.12, . . . } but the
first-encountered sequential elements and/or primary outputs of the
transitive fan-out of the signal have the same late phase label
Ph.sub.2, then Ph.sub.2 is assigned as the signal's late phase
label, and Ph.sub.1 for the signal is selected from {Ph.sub.11,
Ph.sub.12, . . . } such that the phase difference between Ph.sub.1
and Ph.sub.2 is the widest possible.
[0066] Finally, according to the "multiple" rule, if the
first-encountered sequential elements and/or primary inputs of the
transitive fan-in of a signal have differing early phase labels
{Ph.sub.11, Ph.sub.12, . . . } and the first-encountered sequential
elements and/or primary outputs of the transitive fan-out of the
signal have differing late phase labels {Ph.sub.21, Ph.sub.22, . .
. , Ph.sub.2k} then the signal is said to have k instances (one
instance per late phase label), as will be explained below,
time-multiplexed to a single wire. For each signal instance phase
labels are computed independently following the max rule explained
above. The signal is labeled with a set of phase labels, one per
signal instance. For example, signal e in FIG. 2C is labeled with
two pairs of labels {(H,L),(L,H). Pair (H,L) corresponds to a
signal instance e.sup.H and pair (L,H) corresponds to signal
instance e.sup.L.
[0067] FIG. 2C shows the circuit of FIG. 2A with phase labels
assigned to the signals. The phase labels for the signals are given
in the format "(early phase, late phase)". Thus, for example,
signal c, the output of flip-flop 200, is assigned the phase labels
(H, H). The assignment of the phase labels (H, H) to signal c is an
example of the application of the "min" rule. It can be seen that H
is the appropriate early phase label because the first-encountered
upstream sequential element, flip-flop 200, has an earliest valid
output phase H (or Ph.sub.1 value).
[0068] H is also the appropriate late phase label for signal c.
This may be understood by inspecting the transitive fan-out of
signal c. The first-encountered sequential elements in the
transitive fan-out of signal c are transparent latches 230 and 240.
As indicated by its phase label, for latch 230 the value of input
signal c (once it has been propagated through the AND gate 120)
should stabilize before the end of the H phase. For latch 240, the
value of input signal c need not stabilize until sometime during
the L phase. Thus, there are two different constraints on the
latest possible arrival time for signal c. In this case, the H
phase is the more stringent requirement, since signal c is emitted
during the H phase. Accordingly, the H phase is assigned as the
late phase label for signal c.
[0069] It may be observed, given the logic of the circuit of FIG.
2A, that signal e can change its value two times during one clock
cycle. Accordingly, signal e may be treated in a manner analogous
to a manner in which a time-multiplexed signal would be treated.
The signal e may be considered to correspond to a plurality of
signal "instances". Signal instances may be considered to be
independent signals which are time-multiplexed on the same wire.
The most common use for signal instances is modeling different
stable values per clock.
[0070] If a circuit being modeled uses multiple clocks, an
additional label is assigned that indicates which clock the phase
labels are associated with. If the circuit being modeled only
involves one clock, then the third label is not assigned.
[0071] The foregoing is a demonstration of at least one
advantageous aspect of embodiments of the invention, wherein the
task of assigning phase labels is fully automated, eliminating the
need for tedious manual calculation and coding of phase labels, and
enabling increased productivity.
[0072] As noted above, after phase labels are assigned, the process
according to the invention may construct phase synchronous
equations, based on information in the circuit and the information
derived during phase labeling.
[0073] The phase synchronous equations may be constructed based on
a phase shift operator. For a given clock with k clock phases as
described above, where 0 through k-1 are integers, and phase labels
Ph.sub.i, Ph.sub.j identify phases i, j, with 0.ltoreq.i,
j.ltoreq.k-1, the shift operator from clock phase Ph.sub.j to phase
Ph.sub.i is defined as:
Shift(Ph.sub.i,
Ph.sub.j)=.vertline.Ph.sub.i-Ph.sub.j.vertline./k
[0074] Based on the above formulation, for circuits utilizing a
single two-phase clock such as the circuit illustrated in FIGS.
2A-2C, the shift operator value is 0 if Ph.sub.i=Ph.sub.j, and 0.5
if Ph.sub.i.noteq.Ph.sub.j (recalling that H and L correspond to a
phase 0 and a phase 1, respectively). Accordingly, phase
synchronous equations derived for such circuits will contain either
a 0 or 0.5 shift operator value, as described in greater detail
below.
[0075] Each signal of a modeled circuit may be represented by a
general phase synchronous equation in which the output signal
transmitted by a circuit element is a function of a clocking index
i and the phase shift operator. For example, such an equation for a
flip-flop with input x and output y is
y(i)=x(i-1+Shift(Ph.sub.1(y), Ph.sub.1(x))) where the initial value
of y(i) is y(i.sub.0). The symbol i.sub.0 indicates the initial
value of the clock index. The shift operator in this equation
computes a phase shift between the early phase labels of the input
and output signals of a flip-flop.
[0076] The second phase label of signal s, Ph.sub.2(S) is used to
select the correct signal instance of s if multiple instances of s
exist. The correct instance of s should have Ph.sub.2(s)
corresponding to the latest possible arrival phase of a
flip-flop.
[0077] In the case of the circuit shown in FIGS. 2A-2C which
utilizes a two-phase clock, the clocking index i.di-elect cons.{0,
1, 2, . . . } for signal instances with an early phase label of H,
and the clocking index i.di-elect cons.{-0.5, 0.5, 1.5, . . . } for
signal instances with an early phase label of L. The initial clock
value i.sub.0=-0.5 for signal instances with an early phase label
of L, and i=0 would be the initial clock value for signal instances
with an early phase label of H.
[0078] Thus, for example, the output of falling edge flip-flop 210
may be represented by the equation d(i)=b(i-1), i.di-elect
cons.{0.5, 1.5, . . . }.
[0079] The general phase synchronous equation for a transparent
latch with input x and output y is y(i)=x(i-Shift(Ph.sub.1(x),
Ph.sub.1(y))) where the initial value of y(i) is y(i.sub.0). Thus,
for example, the output of active-high transparent latch 230 may be
represented by the equation h(i)=f(i-0.5), i.di-elect cons.{1, 2,
3, . . . }, as the phase shift is 0.5.
[0080] For a combinational gate with inputs x and z, output y, and
function f, a general equation is as follows:
y(i)=f(x(i+shift(Ph.sub.1(y- ), Ph.sub.1(x))),
z(i+shift(Ph.sub.1(y), Ph.sub.1(z)))). For example, for the output
signal e of AND gate 120, the following two equations express
behavior of two possible signal instances: e.sup.H(i)=c(i)d(i+0.5),
i.di-elect cons.{1, 2, 3, . . . }, corresponding to the signal
instance having an early phase label of H and a late phase label of
L, and e.sup.L(i)=c(i+0.5)d(i), i.di-elect cons.{-0.5, 0.5, 1.5, .
. . }, corresponding to the signal instance having an early phase
label of L and having a late phase label of H
[0081] Table 2, below, shows the phase synchronous equations that
would be derived for the circuit of FIGS. 2A-2C.
2 TABLE 2 c(i) = a(i - 1) i .epsilon. {1, 2, . . .} d(i) = b(i - 1)
i .epsilon. {0.5, 1.5, . . .} e.sup.H(i) = c(i)d(i + 0.5) i
.epsilon. {0, 1, . . .} e.sup.L(i) = c(i + 0.5)d(i) i .epsilon.
{-0.5, 0.5, . . .} f(i) = e.sup.L(i) i .epsilon. {-0.5, 0.5, . . .}
g(i) = e.sup.H(i) i .epsilon. {0, 1, . . .} h(i) = f(i - 0.5) i
.epsilon. {0, 1, . . .} k(i) = g(i - 0.5) i .epsilon. {0.5, 1.5, .
. .}
[0082] A model of a circuit in terms of phase synchronous equations
according to embodiments of the invention offers advantages, as
described above. The phase synchronous equations achieve an
abstract, concise formal model that avoids the occurrence of
functional bugs that typically occur in model specifications with a
high degree of implementation detail. The model is formal and can
be used in logic synthesis, simulation or verification.
[0083] Logic synthesis takes an initial description of a netlist
usually represented in HDL and produces another netlist optimized
for given design criteria such as delay, area, and power. Often the
initial netlist is in a more abstract form and has less structure
than the optimized netlist. For example, in case of combinational
logic the initial netlist may just have one large Boolean function
per the primary output. The netlist resulting from logic synthesis
typically has more structure (e.g., a large function may be split
into smaller gates) and may be optimized (e.g., gates from
different functions may be shared).
[0084] Embodiments of the present invention enable sequential logic
synthesis for circuits with transparent latches and
multi-clock/phase clocks since, among other reasons, as noted
above, a formal model enabling the application of formal methods of
reasoning about the model is generated.
[0085] Following logic synthesis, an optimized netlist may be
processed by simulation software to debug the logic design
represented in the netlist. In simulation, a test case comprising
various stimuli may be applied to the design. The application of
the test case typically produces, as output, results data
representing the response of the simulated design which is compared
to expected results, to determine whether the design functions as
expected. The design may subsequently be revised to improve
performance or de-bug errors.
[0086] Thus, for example, one possible application according to
embodiments of the invention is illustrated in FIG. 4. A model 400
comprising phase synchronous equations generated as described above
may be input to a logic synthesis process 401. The logic synthesis
process 401 may be followed by a simulation process 402. The
simulation process may be followed by a process of de-bugging the
logic design as shown in block 403.
[0087] Software comprising computer-executable instructions
according to embodiments of the present invention may be stored and
transported on a computer-usable medium such as diskette, magnetic
tape, disk or CD-ROM. The instructions may be downloaded to another
storage medium such as a ROM or RAM, from which they may be fetched
and executed by a processor to effect the advantageous features of
the invention.
[0088] Several embodiments of the present invention are
specifically illustrated and described herein. However, it will be
appreciated that modifications and variations of the present
invention are covered by the above teachings and within the purview
of the appended claims without departing from the spirit and
intended scope of the invention.
* * * * *