U.S. patent application number 09/991571 was filed with the patent office on 2003-05-22 for sense amplifier with independent write-back capability for ferroelectric random-access memories.
Invention is credited to Grace, James W., McAdams, Hugh P., Rickes, Jurgen T..
Application Number | 20030095456 09/991571 |
Document ID | / |
Family ID | 25537333 |
Filed Date | 2003-05-22 |
United States Patent
Application |
20030095456 |
Kind Code |
A1 |
Rickes, Jurgen T. ; et
al. |
May 22, 2003 |
SENSE AMPLIFIER WITH INDEPENDENT WRITE-BACK CAPABILITY FOR
FERROELECTRIC RANDOM-ACCESS MEMORIES
Abstract
A sensing circuit with independent write-back capability
includes a write back function block having a write-back output
signal, a sense amplifier that receives an input and a reference
signal. The sense amplifier generates an output signal and the
write back function block further receives this output signal. An
optional data buffer also receives the output signal.
Inventors: |
Rickes, Jurgen T.; (Los
Altos Hills, CA) ; McAdams, Hugh P.; (McKinney,
TX) ; Grace, James W.; (Los Altos Hills, CA) |
Correspondence
Address: |
AGILENT TECHNOLOGIES, INC.
Legal Department, DL429
Intellectual Property Administration
P.O. Box 7599
Loveland
CO
80537-0599
US
|
Family ID: |
25537333 |
Appl. No.: |
09/991571 |
Filed: |
November 16, 2001 |
Current U.S.
Class: |
365/205 |
Current CPC
Class: |
G11C 7/067 20130101;
G11C 7/062 20130101; G11C 11/22 20130101 |
Class at
Publication: |
365/205 |
International
Class: |
G11C 007/00 |
Claims
We claim:
1. A sensing circuit having independent write-back capability
comprising: a sense amplifier which compares an input to a
reference signal and generates an output signal; and a tri-statable
write-back block having an enable and an write-back output signal;
wherein the output signal of the sense amplifier is coupled to the
write back block.
2. The sensing circuit of claim 1 further including a data buffer
receiving the output signal of the sense amplifier.
3. The sensing circuit of claim 2, the sense amplifer including: a
p-channel transistor having a source connected to power and a first
drain; a first and a second leg, each leg connected to the drain of
the p-channel transistor and ground, each leg further including, a
first p-channel transistor having a source connected to the first
drain, a second p-channel transistor having a source connected to
the drain of the first p-channel transistor at a first node, two
n-channel transistors, connected in parallel, having their drains
connected to the drain of the second p-channel transistor at a
second node and their sources connected to ground, a third
n-channel transistor, serially connected to the gate of the first
p-channel transistor, and for each leg, the second node connects to
the gates of the second p-channel transistor and one of the two
n-channel transistors of the other leg; and a first n-channel
transistor, connected across the first nodes of the first and
second legs.
4. The data buffer of claim 2, including: a first n-channel
transistor, having a drain generating a data-out signal, having a
gate receiving a control signal; and a second n-channel transistor,
having a drain connected to the source of the first n-channel
transistor, a source connected to ground, and a gate receiving the
output signal of the sense amplifier.
5. The data buffer of claim 4, further including: a first p-channel
transistor, having a source connected to power, a gate receiving
the output signal of the sense amplifier and a drain; and a second
p-channel transistor, connected to the drain of the first p-channel
transistor and the drain of the first n-channel transistor, having
a gate connected to VDD.
6. The data buffer of claim 4, further including: a first p-channel
transistor, having a source connected to power, a gate receiving
the output signal of the sense amplifier and a drain; and a second
p-channel transistor, connected to the drain of the first p-channel
transistor and the drain of the first n-channel transistor, having
a gate connected to the complement of the gate control signal of
the first n-channel transistor.
7. The sensing circuit of claim 1, the write-back block including:
a first p-channel transistor having a source connected to power; a
second p-channel transistor having a source connected to the drain
of the first p-channel transistor; a first n-channel transistor,
having a drain connected to the drain of the second p-channel
transistor forming the write-back output signal which is connected
to the input signal; and a second n-channel transistor, having a
drain connected to the source of the first n-channel transistor,
having a source connected to ground; wherein the gates of the first
p-channel and second n-channel transistors receive the
complementary output signal (is there an antecedent here in claim
1?).
8. A method of sensing of differential data, consisting of:
receiving a differential input signal on an input and a reference
input; amplifying the differential input signal; buffering the
output signal; and writing-back the data to the input.
9. The method of sensing as defined in claim 8, wherein the steps
of writing-back and amplifying occur independently.
10. The method of sensing as defined in claim 8, for a single
reception of differential input data and the steps of amplifying
and buffering are repeated.
11. A sense amplifer comprising: a p-channel transistor having a
source connected to power and a first drain; a first and a second
leg, each leg connected to the drain of the p-channel transistor
and ground, each leg further including, a first p-channel
transistor having a source connected to the first drain, a second
p-channel transistor having a source connected to the drain of the
first p-channel transistor at a first node, two n-channel
transistors, connected in parallel, connected to the drain of the
second p-channel transistor at a second node and ground, a third
n-channel transistor, serially connected to the gate of the first
p-channel transistor, and for each leg, the second node connects to
the second p-channel transistor and one of the two n-channel
transistors of the other leg; and a first n-channel transistor,
connected across the first nodes of the first and second legs.
Description
BACKGROUND
[0001] The digital differential comparator, shown in FIG. 1, has
been used in Dynamic Random-Access memories (DRAMs), as well as
Static Random-Access memories (SRAMs). However, this circuit
usually finds application in the data path external to the memory
array itself, amplifying the data signal received from the memory
array and passing it on to the output buffer. Since this circuit
lacks any ability to write-back onto the input nodes, and since it
is somewhat more complex than the traditional latching sense
amplifier, shown in FIG. 2, it does not normally find use in the
memory array itself.
[0002] Ferroelectric memories are superior to EEPROMs and Flash
memories in terms of write-access time and overall power
consumption. They are used in applications where a non-volatile
memory is required with these features, e.g. digital cameras and
contact less smart cards. Contact less smart cards require
non-volatile memories with low power consumption as they use only
electromagnetic coupling to power up the electronic chips on the
card. Digital cameras require both low power consumption and fast
frequent writes in order to store and restore an entire image into
the memory in less than 0.1 seconds.
[0003] A typical read access of a ferroelectric memory consists of
a write access followed by sensing. To illustrate, a "0" is written
to the ferroelectric capacitor to discover the original data
content of the memory cell. If the original content of the memory
cell is a "1", writing a "0" reverses the direction of the
polarization within the ferroelectric capacitor. This induces a
large current spike on the sense wire. On the other hand, there is
no current spike on the sensing wire if the original content of the
ferroelectric capacitor was also a "0". Therefore, by sensing the
presence of a current spike on the sensing wire, the original data
of the accessed ferroelectric capacitor are determined.
[0004] The read operation as described is destructive since a "0"
is written to any memory cell that is accessed for a read. The
original data, however, are saved in the sense amplifier and can be
restored back into the accessed memory cell. In other words, a read
access is only complete after the second write that restores the
original data.
SUMMARY
[0005] A sensing circuit with independent write-back capability
includes a sense amplifier that receives an input and a reference
signal and a tri-statable write-back block receiving a write enable
signal and the sense amplifier's output signal. An optional data
buffer also receives the sense amplifier's output signal.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] FIG. 1 illustrates a digital differential comparator of the
prior art.
[0007] FIG. 2 illustrates as prior art latching sense
amplifier.
[0008] FIG. 3 illustrates a functional block diagram of the present
invention.
[0009] FIG. 4 illustrates the write-back function block shown in
FIG. 3.
[0010] FIG. 5 illustrates the sense amplifier shown in FIG. 4.
[0011] FIG. 6 illustrates the optional data buffer shown in FIG.
5.
DETAILED DESCRIPTION
[0012] The optimum number of cells per bit line of a ferroelectric
memory tends to be larger than that of a DRAM. Therefore, a
somewhat more complex sense amplifier can be more easily tolerated,
since there are fewer partitions of the memory array and the cell
efficiency tends to be higher. The higher bit line capacitance of
the FeRAM, due to the larger number of bits, means that use of a
prior latching sense amplifier (shown in FIG. 2) results in even
slower access time. Since an adequate voltage separation between
bit line and bit line bar must occur before they can be coupled to
the output data path, additional time is required to charge or
discharge the heavily loaded bit lines.
[0013] A functional block diagram 10 of the present invention is
shown in FIG. 3. The write-back function block 12 is enabled by
input signal WB. During operation, the sense amplifier compares the
voltage on the bit line (BL) to the voltage on the reference input
(REF). The sense amplifier's output signal (OUT) is received by the
write-back function block 12. An optional data buffer 16 also
receives the output signal. Thus, the heavily loaded bit line is
separated from the lightly loaded internal sensing nodes.
[0014] FIG. 4 illustrates the write-back function block 12 shown in
FIG. 3. Serially connected from power to ground are a first and
second p-channel transistor followed by a first and a second
n-channel transistor. The BL signal is connected to the node
between the second p-channel transistor and first n-channel
transistor. The gates of the first p-channel transistor and the
second n-channel transistor are tied together to node OUT bar which
is the complement of the sense amplifier's output signal OUT. The
gate of the second p-channel transistor receives a control signal
write-back bar (WBB) while the gate of the first n-channel
transistor receives a control signal write-back (WB).
[0015] FIG. 5 illustrates the sense amplifier 14 shown in FIG. 3. A
third p-channel transistor MP1 has its source connected to power
and its drain connected to the first and second leg. Each leg
includes two serially connected p-channel transistors (MP2, MP4;
MP3, MP5) followed by two parallel connected n-channel transistors
(MN3, MN1; MN2, MN4).
[0016] For the first leg, at the OUT bar port, the node between the
drain of the second p-channel transistor MP4 and the drains of the
two parallel connected n-channel transistors MN3, MN1 are connected
to the gate of the second p-channel transistor MP5 of the second
leg and the gate of the n-channel transistor MN2. For the second
leg, at the OUT port, the node between the drain of the second
p-channel transistor MP5 and the drains of the two parallel
connected n-channel transistors MN2, MN4 are connected to the gate
of the second p-channel transistor MP4 of the first leg and the
gate of the second n-channel transistor MN1.
[0017] FIG. 6 illustrates an alternate embodiment for the sense
amplifier shown in FIG. 3. In addition to the electrical
connectivity as described in FIG. 5, a fifth n-channel transistor
MN5 connects nodes N1 and N2 and is used for equalization. A sixth
n-channel transistor MN6 is serially connected to the gate of
p-channel transistor MP2. A seventh n-channel transistor MN7 is
serially connected to the gate of the p-channel transistor MP3. The
gates of n-channel transistors MN5, MN6, and MN7 are connected to
EN bar. N-channel transistors MN6 and MN7 are isolation
devices.
[0018] FIG. 7 illustrates the optional data buffer 16 shown in FIG.
3. A first and a second p-channel transistor are serially connected
between power and port DATA. The gate of the first p-channel
transistor receives signal OUT, while the gate of the second
p-channel transistor receives signal VDD. Two n-channel transistors
are serially connected between port DATA and ground. The gate of
the first n-channel transistor connects to OUT while the gate of
the second n-channel transistor receives signal YS.
[0019] In operation, the lack of write-back capability inherent in
the standalone sense amplifier is overcome by the addition of the
series p-channel and series n-channel transistors tied to BL, which
in a memory array would be the bit or data line. WB and WBB are
additional complementary control signals that are generated after
the sense amplifier has been activated by applying VSS to EN bar
and VDD to EN after OUT and OUT bar have been driven to their full
logic levels. Simultaneous with the write-back restore on the bit
line, data can be accessed via the YS signal and started on its
path to the chip's data output buffer, irrespective of the time
required to accomplish the write-back.
* * * * *