U.S. patent application number 10/298423 was filed with the patent office on 2003-05-22 for yokeless hidden hinge digital micromirror device.
Invention is credited to DiCarlo, Anthony, Huffman, James D., Knipe, Richard L., Mezenner, Rabah, Oden, Patrick I..
Application Number | 20030095318 10/298423 |
Document ID | / |
Family ID | 23297755 |
Filed Date | 2003-05-22 |
United States Patent
Application |
20030095318 |
Kind Code |
A1 |
DiCarlo, Anthony ; et
al. |
May 22, 2003 |
Yokeless hidden hinge digital micromirror device
Abstract
A micromirror array 110 fabricated on a semiconductor substrate
11. The array 110 is comprised of three operating layers 12, 13,
14. An addressing layer 12 is fabricated on the substrate. A hinge
layer 13 is spaced above the addressing layer 12 by an air gap. A
mirror layer 14 is spaced over the hinge layer 13 by a second air
gap. The hinge layer 13 has a hinge 13a under and attached to the
mirror 14a, the hinge 13a permitting the mirror 14a to tilt. The
hinge layer 13 further has spring tips 13c under the mirror 14a,
which are attached to the addressing layer 12. These spring tips
13c provide a stationary landing surface for the mirror 14a.
Inventors: |
DiCarlo, Anthony;
(Richardson, TX) ; Oden, Patrick I.; (McKinney,
TX) ; Knipe, Richard L.; (McKinney, TX) ;
Mezenner, Rabah; (Richardson, TX) ; Huffman, James
D.; (Cambridge, GB) |
Correspondence
Address: |
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, M/S 3999
DALLAS
TX
75265
|
Family ID: |
23297755 |
Appl. No.: |
10/298423 |
Filed: |
November 18, 2002 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
60332332 |
Nov 21, 2001 |
|
|
|
Current U.S.
Class: |
359/291 |
Current CPC
Class: |
B81B 3/0035 20130101;
G02B 26/0841 20130101; Y10T 428/22 20150115 |
Class at
Publication: |
359/291 |
International
Class: |
G02B 026/00 |
Claims
What is claimed is:
1. An array of digital micro pixel elements, comprising: a mirror
layer having a mirror associated with each pixel element; a hinge
layer spaced under the mirror layer, the hinge layer having a
torsion hinge under each mirror and attached to the mirror such
that the mirror may tilt above the hinge layer; and an address
layer spaced under the hinge layer, the address layer having
circuitry for controlling operation of the pixel elements; wherein
the hinge layer further has spring tips under each mirror and
mechanically connected to the address layer.
2. The array of claim 1, wherein the hinge layer has four spring
tips.
3. The array of claim 1, wherein each mirror is rectangular in
shape, wherein the hinge is under the diagonal axis of the mirror
such that the mirror tilts around the diagonal axis, and the spring
tips are located under the tilting corners of the mirror.
4. The array of claim 1, wherein the spring tips and the hinge are
fabricated from the same material.
5. The array of claim 1, wherein the spring tips are fabricated
from a metallic material.
6. The array of claim 1, wherein the spring tips extend from at
least one spring tip beam that is connected to the address layer
with one or more spring tip support vias.
7. The array of claim 6, wherein the hinge and the spring tip beams
form a continuous pattern of the hinge layer.
8. A micro pixel array, comprising: a substrate having electrical
components fabricated on the surface of the substrate; an array of
pixel elements, each element comprising a mirror, a hinge under the
mirror spaced under the mirror by an air gap and mechanically
connected to the mirror such that the mirror may tilt above the
hinge, an address layer spaced under the hinge and in electrical
connection with the electrical components of the substrate, and
spring tips mechanically connected to and spaced above the address
layer, such that the mirror may land on the spring tips.
9. The array of claim 8, wherein the hinge layer has four spring
tips.
10. The array of claim 8, wherein each mirror is rectangular in
shape, wherein the hinge is under the diagonal axis of the mirror
such that the mirror tilts around the diagonal axis, and the spring
tips are located under the tilting corners of the mirror.
11. The array of claim 8, wherein the spring tips and the hinge are
fabricated from the same material.
12. The array of claim 8, wherein the spring tips are fabricated
from a metallic material.
13. The array of claim 8, wherein the spring tips extend from at
least one spring tip beam that is connected to the address layer
with one or more spring tip support vias.
14. The array of claim 8, wherein each spring tip is connected to
the address layer with at least one spring tip via.
15. A method of forming a micromirror array, comprising the steps
of: forming control circuitry on a semiconductor substrate;
depositing a first spacer layer on the substrate; patterning the
first spacer layer to define hinge support vias and spring tip
support vias; depositing a hinge layer over the first spacer layer;
forming at least one hinge etch mask on the hinge layer; patterning
the hinge layer to form at least one hinge and at least two spring
tip beams, each spring tip beam having a spring tip extending from
an end of the spring tip beam; depositing a second spacer layer
over the hinge layer; patterning the second spacer layer to define
mirror support vias; depositing a metal mirror layer over the
second spacer layer; patterning the metal mirror layer to form an
array of micromirrors; and removing the first and the second spacer
layers.
16. The method of claim 15, further comprising the steps of
depositing an oxide layer over the hinge layer and of etching the
oxide layer such that inner surfaces of the hinge tip support vias
and spring tip support vias are coated with oxide.
17. The method of claim 16, wherein the etching is patterned
etching.
18. The method of claim 16, wherein the etching is blanket
etching.
19. The method of claim 15, wherein the hinge layer has four spring
tips.
20. The method of claim 15, wherein each mirror is rectangular in
shape, wherein the hinge is under the diagonal axis of the mirror
such that the mirror tilts around the diagonal axis, and the spring
tips are located under the tilting corners of the mirror.
21. A display system, comprising: a light source for producing a
light beam along a light path; and a micromirror device in the
light path for selectively reflecting portions of the light beam
along a second light path toward an image plane, the micromirror
device comprising: a substrate having electrical components
fabricated on the surface of the substrate; an array of mirror
elements, each element comprising a reflective mirror, a hinge
under the mirror spaced under the mirror by an air gap and
mechanically connected to the mirror such that the mirror may tilt
above the hinge, an address layer spaced under the hinge and in
electrical connection with the electrical components of the
substrate, and spring tips mechanically connected to and spaced
above the address layer, such that the mirror may land on the
spring tips.
22. The display system of claim 21, further comprising a projection
lens in the second light path for receiving the selectively
reflected light and focusing the selectively reflected light on the
image plane.
23. The display system of claim 21, further comprising a controller
for providing image data to the micromirror device.
Description
RELATED APPLICATION
[0001] This application is related to co-pending application Ser.
No. ______ (Atty Dkt No. TI-31710) filed entitled "Digital
Micromirror Device Having Mirror-Attached Spring Tips" now U.S.
Pat. No. ______.
TECHNICAL FIELD OF THE INVENTION
[0002] This invention relates to micro-electromechanical devices
and their fabrication, and more particularly to a digital
micromirror device having an improved design.
BACKGROUND OF THE INVENTION
[0003] A Digital Micromirror Device.TM. (DMD.TM.) is a type of
microelectromechanical systems (MEMS) device. Invented in 1987 at
Texas Instruments Incorporated, the DMD is a fast, reflective
digital light switch. It can be combined with image processing,
memory, a light source, and optics to form a digital light
processing system capable of projecting large, bright,
high-contrast color images.
[0004] The DMD is fabricated using CMOS-like processes over a CMOS
memory. It has an array of individually addressable mirror
elements, each having an aluminum mirror that can reflect light in
one of two directions depending on the state of an underlying
memory cell. With the memory cell in a first state, the mirror
rotates to +10 degrees. With the memory cell in a second state, the
mirror rotates to -10 degrees. By combining the DMD with a suitable
light source and projection optics, the mirror reflects incident
light either into or out of the pupil of the projection lens. Thus,
the first state of the mirror appears bright and the second state
of the mirror appears dark. Gray scale is achieved by binary
pulsewidth modulation of the incident light. Color is achieved by
using color filters, either stationary or rotating, in combination
with one, two, or three DMD chips.
[0005] DMD's may have a variety of designs, and the most popular
design in current use is a structure consisting of a mirror that is
rigidly connected to an underlying yoke. The yoke in turn is
connected by two thin, mechanically compliant torsion hinges to
support posts that are attached to the underlying substrate.
Electrostatic fields developed between the underlying memory cell
and the yoke and mirror cause rotation in the positive or negative
rotation direction.
[0006] The fabrication of the above-described DMD superstructure
begins with a completed CMOS memory circuit. Through the use of six
photomask layers, the superstructure is formed with alternating
layers of aluminum for the address electrode, hinge, yoke, and
mirror layers and hardened photoresist for sacrificial layers that
form air gaps.
SUMMARY OF THE INVENTION
[0007] One aspect of the invention is an array of digital
micromirror pixel elements. The array has a structure defined by
three layers spaced from each other with an air gap between each
layer. A mirror layer has a reflective mirror associated with each
pixel element. A hinge layer is spaced under the mirror layer, and
has a torsion hinge under each mirror and attached to the mirror
such that the mirror may tilt above the hinge layer. An address
layer is spaced under the hinge layer, and has circuitry for
controlling operation of the pixel elements. The hinge layer
further has spring tips under each mirror and mechanically
connected to the address layer.
[0008] As stated in the Background, conventional DMD designs have a
yoke under the mirror, at the hinge level. During operation, the
yoke rather than the mirror lands on an underlying landing surface.
The yoke has spring tips, used for landing. In the present
invention, there is no yoke and the mirror lands on spring tips
that are stationary under the mirror at the hinge level.
[0009] An advantage of the present invention is that the yoke
structure of prior DMD designs is eliminated. This greatly
simplifies the DMD structure, as well as its fabrication. Various
patterning and etching steps associated with the yoke are
eliminated. Fabrication of DMDs in accordance with the invention is
expected to significantly increase the current DMD yield.
[0010] Also, as compared to previous DMD designs using a yoke, the
mirror moves with reduced inertia. This permits faster mirror
transition times.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is an exploded view of a DMD pixel element in
accordance with the invention.
[0012] FIG. 2 is a cross sectional view of the layers of a DMD
wafer through deposition and etching of a first spacer layer.
[0013] FIG. 3 is a perspective view of the surface of the first
spacer layer.
[0014] FIG. 4 is a cross sectional view of the layers of a DMD
wafer through deposition of a hinge metal layer and oxide
layer.
[0015] FIG. 5 is a cross sectional view of the layers of a DMD
wafer through deposition and etching of a first spacer layer.
[0016] FIG. 6 is a cross sectional view of the layers of a DMD
wafer through deposition of a hinge patterning layer.
[0017] FIG. 7 is a perspective view of the surface of the hinge
layer after patterning.
[0018] FIG. 8 is a cross sectional view of the layers of a DMD
wafer through deposition of a second spacer layer.
[0019] FIG. 9 is a cross sectional view of the layers of a DMD
wafer through deposition of a mirror metal layer.
[0020] FIG. 10 is a cross sectional view of the layers of a DMD
wafer through deposition of a mirror patterning layer.
[0021] FIG. 11 is a top plan view of the mirror elements of a DMD
array.
[0022] FIG. 12 illustrates the three layers of an orthogonal
embodiment of the invention.
[0023] FIG. 13 is a schematic representation of a projection
display system having a DMD array in accordance with the
invention.
DETAILED DESCRIPTION OF THE INVENTION
[0024] FIG. 1 is an exploded view of a DMD pixel element 10 in
accordance with the invention. Pixel element 10 is one of an array
of such elements fabricated on a wafer, using semiconductor
fabrication techniques.
[0025] DMD pixel element 10 is a monolithically integrated MEMS
superstructure cell fabricated over a CMOS SRAM cell 11. Two
sacrificial layers (see FIGS. 2 and 10) have been removed by plasma
etching to produce air gaps between three metal layers of the
superstructure. For purposes of this description, the three metal
layers are "spaced" apart by being separated by these air gaps.
[0026] The uppermost metal layer 14 has a reflective mirror 14a.
The air gap under the mirror 14a frees the mirror 14a to rotate
about a compliant torsion hinge 13a, which is part of the second
metal layer 13. A third metal (M3) layer 12 has address electrodes
12a for the mirror 14a, the address electrodes 12a being connected
to SRAM cell 11. The M3 layer 12 further has a bias bus 12b, which
interconnects the mirrors 14a of all pixels to a bond pad at the
chip perimeter. An off-chip driver supplies the bias waveform
necessary for proper digital operation.
[0027] The DMD mirrors 14a are each 16 um square and made of
aluminum for maximum reflectivity. They are arrayed on 17 um
centers to form a matrix having a high fill factor (.about.90%).
The high fill factor produces high efficiency for light use at the
pixel level and a seamless (pixelation-free) projected image. The
hinge layer 13 under the mirrors 14a permits a close spacing of the
mirrors 14, and because of the underlying placement of the hinges,
an array of pixel elements 10 is referred to as a "hidden hinge"
type DMD architecture.
[0028] In operation, electrostatic fields are developed between the
mirror 14a and its address electrodes 12a, creating an
electrostatic torque. This torque works against the restoring
torque of the hinge 13a to produce mirror rotation in a positive or
negative direction. The mirror 14a rotates until it comes to rest
(or lands) against spring tips 13c, which are part of the hinge
layer 13. These spring tips 13c are attached to the addressing
layer 12, and thus provide a stationary but flexible landing
surface for the mirror 14a.
[0029] FIGS. 2-10 illustrate the DMD fabrication process. As
explained below, this process follows conventional DMD fabrication
up through deposition of a first spacer layer, S1.
[0030] FIG. 2 is a cross sectional view of the layers of a DMD
wafer through the deposition of the first spacer (S1) layer 21. The
fabrication of the DMD superstructure begins with a completed CMOS
memory circuit 11. Circuit 11 may be a conventional 5T or 6T SRAM
cell. A thick oxide is deposited over the CMOS surface and then
planarized, such as by using a chemical mechanical polish (CMP)
technique. The CMP step provides a completely flat substrate for
DMD superstructure fabrication.
[0031] Through the use of photomasking techniques, the M3 layer 12
is formed above the CMOS 11. This M3 layer 12 is formed with
aluminum for address and bus circuitry. The aluminum is
sputter-deposited and plasma-etched using plasma-deposited SiO2 as
the etch mask. M3 layer 12 may be etched in a pattern used for DMD
structures previously described in U.S. Pat. No. 6,028,690,
entitled "Reduced Micromirror Gaps for Improved Contrast Ratio, and
in U.S. Pat. No. 5,583,688, entitled "Multi-level Digital
Micromirror Device", both assigned to Texas Instruments
Incorporated. These patents are incorporated by reference
herein.
[0032] A spacer layer 21, identified as S1, is then deposited over
the M3 layer 11. Spacer layer 21 may be formed from hardened
photoresist. Later in the packaging flow, this spacer layer 21 is
plasma-ashed to form an air gap. A number of vias are then formed
in spacer layer 21, formed by conventional pattern and etching
techniques.
[0033] FIG. 3 is a perspective view of the surface of the first
spacer layer 21 after the vias have been formed. It illustrates
spring tip support vias 31, hinge support vias 32, and electrode
support vias 33.
[0034] FIGS. 4-6 illustrate fabrication of hinge layer 13. As
explained below, hinge layer 13 contains both hinge 13a, spring tip
beams 13b, and spring tips 13c extending from the spring tip beams
13b.
[0035] Referring to FIG. 4, the hinge layer 13 is formed by
deposition of the hinge metal layer 13 and an oxide layer 42. The
hinge metal is typically an aluminum alloy, such as AlTiO. An
example of a suitable thickness for hinge layer 13 is 840
angstroms. An example of a suitable thickness for oxide layer 42 is
5000 angstroms.
[0036] FIG. 5 illustrates a portion of the partially fabricated DMD
having a via 31, 32, or 33, and the result of a patterned etch
process. The etch leaves an oxide coating within the vias 31, 32,
or 33. The oxide at the bottom of the vias covers the thin metal at
the bottom of each via, thereby providing strengthening. A develop
rinse is then performed, or other cleanup to remove residue and
prevent surface contamination. As an alternative to a patterned
etch, a blanket etch could be used, which would tend to leave the
oxide on the via side walls. As an alternative to oxide layer 42, a
metal material rather than oxide could be deposited.
[0037] FIG. 6 illustrates the deposition and patterning of a hinge
patterning layer 61. The patterning layer 61 is etched with a hinge
etch mask in the pattern illustrated in FIG. 1. Then patterning
layer 61 is chemically removed. The patterned hinge layer 13 is
then descumed.
[0038] FIG. 7 is a perspective view of the surface of the patterned
hinge layer 13. The various vias 31, 32, 33 are shown, as well as a
hinge pad 71, upon which the mirror via 14a will end. Referring
again to FIG. 1, the vias, now filled with deposited oxide
material, form hollow support posts after the spacer layer 21 is
removed. Two spring tips 13c are located under each of the two
tilting corners of mirror 14a. In the embodiment of FIG. 7, the
hinge 13a and spring tips 13b form a continuous pattern with the
two spring tip beams 13b extending at an angle from each end of
hinge 13a, but other patterns are possible. For example, one or two
landing tips may be used, at a 45 degree or 90 degree angle
orientation to the hinge.
[0039] FIG. 8 illustrates the deposition of second spacer (S2)
layer 81. The mirror via 14a, illustrated in FIG. 1, is patterned
and etched. The spacer resist is then cured and the surface
descumed. A feature of the invention is that the gap between the
mirror layer 14 and the hinge layer 13 can be reduced, as compared
to conventional DMD designs. This reduces reflection off the hinge
level in the gap, resulting in better image quality.
[0040] FIG. 9 illustrates deposition of metal mirror layer 91, from
which mirror 14a is patterned. A typical thickness for mirror layer
91 is 3300 angstroms. The metal for mirror layer 91 is typically
aluminum or an alloy of aluminum.
[0041] FIG. 10 illustrates deposition of a mirror patterning layer
101, which is used to pattern mirror 14a. Mirror layer 14 is
patterned and etched, leaving the mirror 14 of FIG. 1.
[0042] The packaging flow begins with the wafers partially sawed
along the chip scribe lines to a depth that will allow the chips to
be easily broken apart later. Before separating the chips from one
another, each chip is tested for full electrical and optical
functionality by a high-speed automated wafer tester. The chips are
then separated from the wafer, and proceed to a plasma etcher that
is used to selectively strip the organic sacrificial layers, S1 and
S2, from under the mirror layer 14 and hinge layer 13. The chips
are then plasma-cleaned, relubricated, and hermetically sealed in a
package.
[0043] FIG. 11 is a top view of an array 110 of mirror elements 10.
DMD arrays often have more than a thousand rows and columns of
pixel elements 10. Packaged DMD chips are commercially available in
various array sizes. For example, SVGA (800.times.600) and SXGA
(1280.times.1024) arrays have been made. The diagonals of the
active area are 0.7 inches and 1.1 inches, respectively.
[0044] The above-described design is a "diagonal" design, in which
mirror 14 rotates around its diagonal. The same design can be
easily modified to concepts can be applied to an "orthogonal"
design, in which mirror 14 rotates around its flat sides.
[0045] FIG. 12 illustrates addressing layer 120, hinge layer 121,
and mirror layer 122 of an orthogonal DMD design. Three layers are
shown with solid, dotted, and dashed lines, respectively. As an in
the diagonal design described above, the hinge layer 121 has a
hinge 121a, spring tip beams 121b, and spring tips 121c. An
advantage of an orthogonal design is that a projection system using
such DMDs can have reduced optical path lengths and thus a more
compact size.
[0046] In operation, during landing, the torquing around the landed
spring tip 13b reduces back torquing from the non landing tip 13b.
This increases the tilt angle. A reset signal entering the bias
line should not be required to initiate a transition. Bias
potential and address voltages are expected to be sufficient to
operate pixel 10, assuming that the time bias off parameter is
sufficient for re-application of bias to achieve the desired
transition. Because the spring tips 13b are at a radius closer to
hinge 13a than is the case with conventional DMD designs, the
effects of any holding torque due to stiction is reduced. Also, for
purposes of the desired electrostatic operation, pixel 10 provides
greater torque for a given pixel-electrode potential difference.
This is due to having most of the active torque supplying areas of
the address in electrodes and mirror placed as far out radially as
possible. The hinge metal may be thicker due to increased
electrostatic efficiency.
[0047] FIG. 13 is a schematic view of an image projection system
1300 having an improved micromirror device 1302 in accordance with
the invention. Light from light source 1304 is focused on the
micromirror device 1302 by lens 1306. Although shown as a single
lens, lens 1306 is typically a group of lenses and mirrors which
together focus and direct light from the light source 1304 onto the
surface of the micromirror device 1302. Mirrors on the micromirror
device that are rotated to an off position reflect light to a light
trap 1308 while mirrors rotated to an on position reflect light to
projection lens 1310, which is shown as a single lens for
simplicity. Projection lens 1310 focuses the light modulated by the
micromirror device 1302 onto an image plane or screen 1312. Mirrors
in the exterior border region of micromirror device 1302 direct the
light impinging on the border region to the light trap 1308,
ensuring that the border region of the display 1314 is very dark
and creating a sharp contrast with the interior image portion 1316
of the image plane. Controller 1320 provides timing and control
signals for operating the pixel elements in the manner described
above and in the referenced patents.
[0048] Other Embodiments
[0049] Although the present invention has been described in detail,
it should be understood that various changes, substitutions, and
alterations can be made hereto without departing from the spirit
and scope of the invention as defined by the appended claims.
* * * * *