U.S. patent application number 10/003535 was filed with the patent office on 2003-05-08 for high frequency signal isolation in a semiconductor device.
Invention is credited to Banerjee, Suman Kumar, Du, Yang, Duvallet, Alain, Thoma, Rainer.
Application Number | 20030085432 10/003535 |
Document ID | / |
Family ID | 21706319 |
Filed Date | 2003-05-08 |
United States Patent
Application |
20030085432 |
Kind Code |
A1 |
Du, Yang ; et al. |
May 8, 2003 |
HIGH FREQUENCY SIGNAL ISOLATION IN A SEMICONDUCTOR DEVICE
Abstract
A semiconductor device (20) includes an isolated p-well (22)
formed in a substrate (21) by a buried n-well (25) and an n-well
ring (24). The n-well ring (24) extends from a surface of the
semiconductor device (20) to the buried n-well (25). The isolated
p-well (22) includes a plurality of n-well plugs (27) extending
from the surface of the semiconductor device (20) into the isolated
p-well (22) and contacting the buried n-well (25). The plurality of
n-well plugs (27) reduces an n-well resistance to provide better
noise isolation for high frequency signals.
Inventors: |
Du, Yang; (Austin, TX)
; Banerjee, Suman Kumar; (Mesa, AZ) ; Thoma,
Rainer; (Gilbert, AZ) ; Duvallet, Alain;
(Austin, TX) |
Correspondence
Address: |
MOTOROLA INC
AUSTIN INTELLECTUAL PROPERTY
LAW SECTION
7700 WEST PARMER LANE MD: TX32/PL02
AUSTIN
TX
78729
|
Family ID: |
21706319 |
Appl. No.: |
10/003535 |
Filed: |
November 2, 2001 |
Current U.S.
Class: |
257/394 ;
257/E21.544; 257/E21.642 |
Current CPC
Class: |
H01L 21/823878 20130101;
H01L 21/761 20130101 |
Class at
Publication: |
257/394 |
International
Class: |
H01L 029/76; H01L
029/94; H01L 031/062; H01L 031/113; H01L 031/119 |
Claims
What is claimed is:
1. A semiconductor device, comprising: a substrate; a buried n-well
within the substrate; and an n-well ring extending from a surface
of the semiconductor device to the buried n-well and contacting the
buried n-well, wherein the n-well ring and buried n-well form an
isolated p-well, the isolated p-well comprising: a plurality of
n-well plugs extending from the surface into the isolated p-well
and contacting the buried n-well.
2. The semiconductor device of claim 1, wherein the isolated p-well
comprises: a plurality of composite well ties, each composite well
tie comprising a n+ active region formed on top of each of the
plurality of n-well plugs for making electrical contact with the
plurality of n-well plugs.
3. The semiconductor device of claim 2, further comprising a p-plus
guard ring surrounding the top of each of the plurality of n-well
plugs.
4. The semiconductor device of claim 2, wherein each composite well
tie further comprises: an isolation portion between the n+ active
region and the p+ guard ring of each of the plurality of n-well
plugs.
5. The semiconductor device of claim 1, wherein each of the
plurality of n-well plugs are spaced apart from each other at a
distance of less than approximately 50 microns.
6. The semiconductor device of claim 1, wherein each of the
plurality of n-well plugs are substantially evenly spaced
apart.
7. The semiconductor device of claim 1, wherein each of the
plurality of n-well plugs have a length in a range of approximately
0.5 microns to 1.0 microns and a width in a range of approximately
0.5 microns to 1.0 microns.
8. The semiconductor device of claim 1, wherein at least a portion
of the plurality of n-well plugs form an n-well strip.
9. A semiconductor device, comprising: a p-type substrate; an
isolated p-well within the p-type substrate, defined by an n-well
ring and a buried n-well, wherein n-well ring and buried n-well
electrically isolate the isolated p-well from the p-type substrate;
a plurality of composite well ties within the isolated p-well, each
composite well tie comprising: a p-type portion extending into the
isolated p-well; and an n-type portion extending through a depth of
the isolated p-well and contacting the buried n-well.
10. The semiconductor device of claim 9, wherein each composite
well tie further comprises: an isolation portion between the p-type
portion and n-type portion, wherein the n-type portion is
electrically isolated from the p-type portion.
11. The semiconductor device of claim 10, wherein the isolation
portions comprise inter-well shallow trench isolations.
12. The semiconductor device of claim 11, wherein each composite
well tie further comprises: an intra-well shallow trench isolation
portion around the p-type portion.
13. The semiconductor device of claim 9, wherein each of the
plurality of composite well ties is spaced apart from each other at
a distance of less than approximately 50 microns.
14. The semiconductor device of claim 9, wherein each of the
plurality of composite well ties is substantially evenly spaced
apart.
15. The semiconductor device of claim 9, wherein the n-type
portions are doped with a concentration in a range of approximately
1 e17 atom/cm.sup.3 to 1 e19 atom/cm.sup.3, and the buried n-well
is doped with a concentration in a range of approximately 1 e17
atom/cm.sup.3 to 5 e19 atom/cm.sup.3.
16. The semiconductor device of claim 9, wherein at least a portion
of the plurality of composite well ties share an n-type portion
that extends from one composite well tie to another composite well
tie of the portion of composite well ties.
17. The semiconductor device of claim 9, wherein the isolated
p-well further comprises an active device having a bulk electrode
coupled to the p-type portion of at least one of the plurality of
composite well ties.
18. The semiconductor device of claim 9, wherein the n-well ring
comprises a trench isolation portion and a p-plus guard ring.
19. A semiconductor device, comprising: an isolated p-well defined
by an n-well ring and a buried n-well, wherein the n-well ring
extends along a depth of the isolated p-well and electrically
contacts the buried n-well; a plurality of p-well ties within the
isolated p-well; and a plurality of n-well plugs, wherein each of
the plurality of n-well plugs is within a corresponding p-well tie
at a predetermined spacing and extends through the depth of the
isolated p-well, electrically contacting the buried n-well.
20. The semiconductor device of claim 19, further comprising: an
isolation portion between each of the n-well plugs and the
corresponding p-well tie, wherein each of the n-well plugs is
electrically isolated from the corresponding p-well tie.
21. The semiconductor device of claim 19, wherein each of the
plurality of n-well plugs are spaced apart from each other at a
distance of less than approximately 50 microns.
Description
FIELD OF THE INVENTION
[0001] The present invention relates generally to semiconductor
devices, and more particularly, to high frequency signal isolation
in a semiconductor device.
BACKGROUND OF THE INVENTION
[0002] To reduce cost in integrated circuit design, it is desirable
to include as much functionality as possible on a single integrated
circuit. For example, in a low cost wireless communication system,
it is desirable to include the RF (radio frequency) circuits on the
same integrated circuit as the digital logic circuits. However,
noise generated by the digital logic circuits can be injected into
sensitive RF circuit blocks such as phase locked loops (PLL) and
low noise amplifier circuits. Conceptually, an ideal Faraday cage
prohibits external electromagnetic interference and provides
perfect signal isolation. In an integrated circuit, implanted wells
are used to reduce the effect of noise and to provide signal
isolation. In a CMOS twin well process with a p-type substrate, the
pn junction between n-well and p-type substrate provides some
signal isolation for PMOS. The NMOS signal isolation is
accomplished using a deep n+ implant (DNW) with an n-well to create
an isolated p-well (IPW) pocket, and is sometimes referred to as a
triple well process. Implanted wells as used to approximate a
Faraday cage in integrated circuits, reduce the effect of noise.
However, the use of implanted wells fails to provide adequate
signal isolation at higher RF frequencies.
[0003] FIG. 1 illustrates a top view of a prior art semiconductor
device 10. FIG. 2 illustrates a cross-sectional view of the prior
art semiconductor device 10 of FIG. 1. Semiconductor device 10 has
a p substrate 18. A deep n-well implant 16 together with a n-well
ring 15 creates an isolated p-well pocket 12. A plurality of p+
well ties 14 is implanted in the surface of the isolated p-well 12.
Electronic circuits are built into the surface of the isolated
p-well (not shown). The isolated p-well 12 functions to isolate the
circuits implemented in the well from circuits that are implemented
outside of the well. However, the deep n-well implant 16 has a
relatively high resistance that is undesirable for signal isolation
in the RF frequency range.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIG. 1 illustrates a top view of a prior art semiconductor
device.
[0005] FIG. 2 illustrates a cross-sectional view of the prior art
semiconductor device of FIG. 1.
[0006] FIG. 3 illustrates a top view of a semiconductor device in
accordance with the present invention.
[0007] FIG. 4 illustrates a cross-sectional view of the
semiconductor device of FIG. 3.
DETAILED DESCRIPTION
[0008] Generally, the present invention provides a semiconductor
device 20 having a substrate 21, a buried n-well 25, and an n-well
ring 24. The n-well ring 24 extends from a surface of the
semiconductor device 20 to the buried n-well 25. The n-well ring 24
and the buried n-well 25 form an isolated p-well 22. The isolated
p-well 22 includes a plurality of n-well plugs 27 extending from
the surface into the isolated p-well 22 and contacting the buried
n-well 25. The plurality of n-well plugs 27 reduces an n-well
resistance to provide better isolation for high frequency
signals.
[0009] FIG. 3 illustrates a top view of a portion of a
semiconductor device 20 in accordance with the present invention.
FIG. 4 illustrates a cross-sectional view of semiconductor device
20 of FIG. 3 along the line 4-4. Referring to both FIG. 3 and FIG.
4, semiconductor device 20 includes a substrate 21, deep n-well 25,
composite well ring 23, and composite well ties 34 and 44. An
isolated p well 22 is formed by deep n-well 25 and n-well ring 24.
Composite well ring 23 includes n-well ring 24, inter-well STI
(shallow trench isolation) 26, intra-well STI 30, n+ active 29, and
p+ active 28. Composite well tie 34 includes n-well plug 27, p+
active 36, inter-well STI 38, n+ active 40, and intra-well STI 42.
A plurality of composite well ties, similar to composite well tie
34, are spaced throughout isolated p-well 22. However, for the
purpose of illustration, only one other composite well tie,
composite well tie 44, is illustrated in FIGS. 3 and 4.
[0010] Deep n-well 25 is first implanted in substrate 21. Then,
n-well ring 24 is implanted over deep n-well 25 to construct
isolated p-well 22. Inter-well STI 26, intra-well STI 30, n+ active
29, and p+ active 28 are formed over n-well 24 and isolated p-well
22. Composite-well ties 34 and 44 are formed at the same time, and
with the same mask, as composite n-well ring 23. The n-well plug 27
is formed at the same time as n-well ring 24. The n-well plug 27 is
doped with a concentration in a range of approximately 1 e17
atom/cm.sup.3 to 1 e19 atom/cm.sup.3, and the buried n-well 25 is
doped with a concentration in a range of approximately 1 e17
atom/cm.sup.3 to 5 e19 atom/cm.sup.3 Then p+ active 36, inter-well
STI 38, n+ active 40, and intra-well STI 42 are formed over n-well
plug 27. The p+ active 36 forms a guard ring around the n-well
plugs to eliminate process sensitive leakage and to make the
composite n-well ties more robust.
[0011] Because of Ohm's parallel resistor law, more n-well ties in
the isolated p-well results in lower resistance. However, the
additional n-well ties reduce resistance at the cost of increased
surface area of the integrated circuit. In the illustrated
embodiment, the composite n-well ties are evenly spaced apart from
each other at a distance of less than approximately 50 microns.
Reducing n-well tie spacing, and thus increasing the number of
n-well ties, results in better signal isolation quality. Each of
the plurality of n-well plugs 34 have a length in a range of
approximately 0.5 microns to 1.0 microns and a width in a range of
approximately 0.5 microns to 1.0 microns. In other embodiments, the
composite n-well ties can be spaced further apart than 50 microns
and may be spaced in an uneven manner to accommodate circuit layout
or other concerns. Also, the n-well plugs may have different
lengths and widths. For example, in one embodiment, the n-well plug
may be rectangular in shape forming a strip.
[0012] Composite well ties 34 and 44 are used to make contact to
the deep n-well 25, and reduce the deep n-well resistance of buried
n-well 25 by providing a plurality of parallel conductive paths
though isolated p-well 22. Also, composite well ties 34 and 44 can
be implanted inside isolated p-well 22 using the same mask as
n-well ring 24. After p-well implantation, n+ active region 40 and
p+ active region 36 are formed to make ohmic contact to the well.
In the illustrated embodiment, both the composite well ring 23 and
composite well ties 34 and 44 have a similar structure to achieve
optimum signal isolation. As the frequency increases, a lumped well
resistance Rw determines the amount of signal isolation.
[0013] The lumped well resistance can be shown by the following
equation: Rw =Rnw*Rpw/(Rnw+Rpw), where Rnw is the deep n-well
resistance and Rpw is the isolated p-well resistance. At high
frequencies, the lumped well resistance functions as a shunt
resistor. Minimizing Rw improves noise isolation for frequencies up
to about 10 gigahertz (GHz).
[0014] Although the present invention has been described with
reference to a specific embodiment, further modifications and
improvements will occur to those skilled in the art. Therefore, it
is intended that this invention encompass all such variations and
modifications as fall within the scope of the appended claims.
* * * * *