U.S. patent application number 09/985023 was filed with the patent office on 2003-05-01 for creation of a polarizable layer in the buried oxide of silicon-on-insulator substrates for the fabrication of non-volatile memory.
Invention is credited to Hughes, Harold L., Lawrence, Reed K., McMarr, Patrick J..
Application Number | 20030082887 09/985023 |
Document ID | / |
Family ID | 25531119 |
Filed Date | 2003-05-01 |
United States Patent
Application |
20030082887 |
Kind Code |
A1 |
Hughes, Harold L. ; et
al. |
May 1, 2003 |
CREATION OF A POLARIZABLE LAYER IN THE BURIED OXIDE OF
SILICON-ON-INSULATOR SUBSTRATES FOR THE FABRICATION OF NON-VOLATILE
MEMORY
Abstract
This invention concerns a process of forming a polarizable layer
in a buried oxide layer of a silicon-on-insulator substrate for the
fabrication of non-volatile memory. This process comprises
implanting, through the active silicon layer, Si ions into the
buried oxide layer at an ion implantation energy selected so that
the implanted ion has its peak concentration between 5-50 nm from
the silicon/buried oxide interface. The implantation step can occur
while externally heating the silicon-on-insulator substrate at a
temperature between 25-300 degrees Celsius. After implantation, an
annealing step may be completed to repair any damage the
implantation may have created in the silicon-on-insulator
substrate.
Inventors: |
Hughes, Harold L.; (West
River, MD) ; McMarr, Patrick J.; (Alexandria, VA)
; Lawrence, Reed K.; (Leesburgh, VA) |
Correspondence
Address: |
NAVAL RESEARCH LABORATORY
ASSOCIATE COUNSEL (PATENTS)
CODE 1008.2
4555 OVERLOOK AVENUE, S.W.
WASHINGTON
DC
20375-5320
US
|
Family ID: |
25531119 |
Appl. No.: |
09/985023 |
Filed: |
November 1, 2001 |
Current U.S.
Class: |
438/404 ;
257/E21.561; 257/E21.662; 438/450 |
Current CPC
Class: |
H01L 27/112 20130101;
H01L 21/7624 20130101 |
Class at
Publication: |
438/404 ;
438/450 |
International
Class: |
H01L 021/76 |
Claims
We claim:
1. A process of forming a polarizable layer in a buried oxide layer
of a silicon-on-insulator substrate for the fabrication of
non-volatile memory, said process comprising: implanting, through
said active silicon layer, silicon ions into said buried oxide
layer at an ion implantation energy selected so that said implanted
ion has its peak concentration between 5-50 nm from the
silicon/buried oxide interface; and annealing said
silicon-on-insulator substrate.
2. The process of claim 1, wherein said implantation is conducted
at a temperature between 25 degrees Celsius and 300 degrees
Celsius.
3. The process of claim 1, wherein said step of implanting is
channeled through the top-silicon layer.
4. The process of claim 1, wherein said step of implanting is
carried out such as to supply a dose of ions of 1.times.10.sup.15
cm.sup.-2 to 1.times.10.sup.17 cm.sup.-2, depending on the
operating voltage of the MOS transistor fabricated on the
top-silicon.
5. The process of claim 1, wherein said step of annealing is
carried out in an inert atmosphere.
6. The process of claim 5, wherein said inert atmosphere is an
argon atmosphere.
7. The process of claim 5, wherein said step of annealing is
carried out at temperatures of 900 degrees Celsius to 1000 degrees
Celsius.
8. A silicon-on-insulator substrate for the fabrication of
non-volatile memory, said device comprising: a substrate; a buried
oxide layer within said substrate; and a polarizable layer within
said buried oxide layer.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates generally to
silicon-on-insulator structures, and more specifically to
processing a polarizable layer in the buried oxide of
silicon-on-insulator substrates for the fabrication of non-volatile
memory.
[0003] 2. Discussion of the Background
[0004] There are various types of commercial non-volatile memory
that have been fabricated on bulk silicon, but no commercial
non-volatile memories have been fabricated on SOI substrates that
utilize the buried oxide in their operation.
[0005] Two known techniques for forming the buried oxide layer in
SOI substrates are the implantation of oxygen ions in the
separation-by-implantation-of-oxygen process (SIMOX) and the method
of first growing a thermal oxide and then bonding. The difficulty
is that the buried oxide formed using either of these commercial
processes are non-polarizable.
[0006] The test for the polarizability of the buried oxide is (1)
the fabrication of point-contact transistors, (2) measurement of
the transistor characteristics, (3) application of a positive
voltage to the back-gate or drain above the operating voltage and
(4) remeasurement of the transistor characteristics. The procedure
is then repeated, where a negative voltage of the same magnitude is
applied to the back-gate or drain. Any significant reproducible
hysteresis in the transistor characteristics indicates that the
buried oxide has been polarized. These measurements were performed
on a wide range of commercially available SOI substrates, and
demonstrate that the buried oxides of these substrates are
non-polarizable.
[0007] In the SIMOX process, a thin layer of a monocrystalline
silicon substrate is separated from the bulk of the substrate by
implanting oxygen ions into the substrate to form a buried
dielectric layer. The SIMOX process provides a heterostructure in
which a buried silicon dioxide layer serves as a highly effective
insulator for surface layer electronic devices.
[0008] In the SIMOX process, oxygen ions are implanted into
silicon, after which the material is annealed to form the buried
silicon dioxide layer or BOX region. The annealing phase
redistributes the oxygen ions such that the silicon/silicon dioxide
boundaries become smoother and more abrupt, thus forming a sharp
and well-defined BOX region.
[0009] One important criterion for SIMOX wafers is the defect
density, which should be minimized in order to produce high quality
wafers. Defect density can be defined in terms of the departure
from perfect crystallinity in the silicon layer that is separated
from the bulk substrate by the buried oxide layer. In general, as
the oxygen ions are implanted into the wafer to produce the buried
SiO.sub.2 layer, atomic silicon is displaced. Additionally, excess
silicon atoms from the growing BOX region can alter the crystal
structure of the top silicon layer resulting in a variety of point
and extended defects, such as threading dislocations and stacking
faults, during the ion implantation and/or annealing processes.
These defects degrade the quality and reliability of devices, e.g.,
transistors, that are subsequently formed in the upper silicon
layer.
[0010] It is known that, in the SIMOX substrate, structure and
quality of the buried oxide layer formed under the top silicon
layer by implanting the oxygen ions into the single-crystal silicon
substrate depend on an ion implanting quantity (dose of ions), so
that the dose of oxygen ions as 10.sup.17-10.sup.18/cm.sup.2 is
required in order to form the buried oxide layer having the abrupt
interface. But, there is the disadvantage of producing crystal
defects in the top single-crystal silicon layer when the dose of
ions is increased, and observing the relation of a crystal
dislocation density and the dose of ions, when the dose of ions
reaches over 1.0.times.10.sup.18/cm.sup.2, the dislocation density
is increased and crystal quality of the top silicon layer where
device elements are formed is inferior. When the dose of ions is
controlled within the range between 0.5.times.10.sup.18/cm.sup.2
and less than 1.0.times.10.sup.18/cm.sup.2 in order not to produce
the crystal defect, a breakdown electric field of the buried oxide
layer is smaller and the breakdown voltage is decreased.
Consequently, as a condition capable of obtaining the high
breakdown electric field of the buried oxide layer and of achieving
the low dislocation density in the top silicon layer, at an
acceleration energy of 150-200 keV, for example, the ion
implantation has been practiced by setting the dose of ions at
around 0.4.times.10.sup.18/cm.sup.2 (J. Mater. Res., Vol. 8, No. 3,
1993 pp. 524-534).
[0011] At least one disadvantage is that the buried oxide layer is
non-polarizable. There exists a need for a method of creating a
polarizable layer in the buried oxide of silicon-on-insulator
substrates. The buried oxide of silicon-on-insulator substrates can
be used for the fabrication of non-volatile memory.
SUMMARY OF THE INVENTION
[0012] Accordingly, it is one object of the present invention to
provide a novel process for creating a polarizable buried oxide in
SOI substrates.
[0013] It is another object of this invention to provide a process
for creating a polarizable buried oxide in SOI substrates by the
implantation of ions.
[0014] It is another object of this invention to provide a process
for creating a polarizable buried oxide in SOI substrates by the
implantation of silicon ions into the buried oxide.
[0015] It is another object of this invention to provide a process
for creating a polarizable buried oxide in SOI substrates by the
channeling and implantation of ions such that damage effects to the
top silicon region are reduced.
[0016] These and other objects, which will become apparent during
the following detailed description, have been achieved by the
inventors' discovery that a polarizable buried oxide layer in a SOI
substrate may by prepared by:
[0017] externally heating the silicon-on-insulator substrate;
[0018] implanting ions into the buried oxide layer; and
[0019] annealing the silicon-on-insulator substrate.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0020] The present invention provides a process for forming a
polarizable layer in a buried oxide layer of a silicon-on-insulator
substrate for the fabrication of non-volatile memory, the process
comprising:
[0021] externally heating the silicon-on-insulator substrate;
[0022] implanting ions into the buried oxide layer; and
[0023] annealing the silicon-on-insulator substrate.
[0024] A typical SOI includes a silicon substrate, an active
silicon layer, and a buried oxide layer sandwiched between the
active silicon layer and the silicon substrate. Generally, the
buried oxide layer rests directly on and physically contacts the
silicon substrate. Also, the active silicon layer generally rests
on and physically contacts the buried oxide layer. The buried oxide
layer electrically isolates the active silicon layer from the
silicon substrate.
[0025] During the implantation stage, the dose of the implanted ion
should be as high as can be obtained without damaging the active Si
layer to such an extent that a subsequent anneal will not
essentially rectify the damage.
[0026] Channeling of the ions during the implantation stage may
minimize the damage to the active Si layer. Channeling, however, is
not required according to the present invention.
[0027] The depth of the implant is determined by the energy. The
implant energy required to obtain the desired implantation profile
in the buried oxide layer will vary depending upon the implanted
species, the thickness of the active Si layer and the angle of
implantation. Other factors, such as the density of the buried
oxide layer may also effect the required implantation energy. Thus,
the energy required to obtain the desired implantation profile in
the BOX is best determined empirically for each situation, using
the knowledge of those skilled in the art of ion implantation.
Typically, the peak implant concentration is 5 to 50 nm from the
silicon/buried oxide interface. Most typically, the peak implant
concentration is about 20 nm from the silicon/buried oxide
interface.
[0028] Typically, the step of externally heating the substrate is
carried out at temperatures of 25 degrees Celsius to 300 degrees
Celsius.
[0029] Typically, the step of implanting is carried out such as to
supply a dose of ions of 1.times.10.sup.15 cm.sup.-2 to
1.times.10.sup.17 cm.sup.-2, depending on the operating voltage of
the MOS transistor fabricated on the top-silicon.
[0030] Typically, the step of annealing is carried out at
temperatures of 900 degrees Celsius to 1000 degrees Celsius.
Annealing removes residual damage in the active Si layer and
stabilizes the Si-implanted buried oxide layer. At temperatures
below about 800 degrees Celsius, no significant annealing occurs.
At high temperatures, either the Si active layer melts or
contamination becomes a greater concern. Generally, annealing is
performed for about 1-5 hours. If the annealing time is overly
long, the Si in the substrate may begin to reduce the BOX layer.
Generally, the post-implantation anneal is performed either in
vacuo or under an atmosphere that is non-reactive with the SOI
structure.
EXAMPLE
[0031] Following initial electrical characterization of SIMOX
substrates, the substrates were implanted with silicon ions at
doses of 5.times.10.sup.15 and 1.times.10.sup.16 ions/cm.sup.2 at
130 keV. The SIMOX substrates selected for implantation had a top
silicon thickness of .about.1500 .ANG. and a buried oxide thickness
of .about.1700 .ANG.. For this system, at 130 keV, TRIM and SILVACO
simulations showed that the majority of the silicon ions would be
implanted into the buried oxide. SIMS analysis confirmed that
.about.90% of the ions were implanted in the top 600 .ANG. of the
buried oxide. The temperature of the SIMOX substrates during
implantation was 200 degrees C. The ions were channeled to minimize
damage in the top silicon of the substrate. To determine if the
electrical properties of the substrates were degraded by the high
dose implantations, SIS structures were fabricated on the implanted
substrates and PCT transistor measurements performed. There was a
small change in the subthreshold swing, which corresponds to a
back-channel interface state density of .about.3.times.10.sup.11
cm.sup.-2 eV.sup.-1. The magnitudes of the currents above the
subthreshold region are essentially identical for the implanted and
unimplanted substrates, indicating that the implantation process
does not seriously impact carrier mobility.
[0032] Obviously, many modifications and variations of the present
invention are possible in light of the above teachings. It is
therefore to be understood that, within the scope of the appended
claims, the invention may be practiced otherwise than as
specifically described.
* * * * *