U.S. patent application number 10/262789 was filed with the patent office on 2003-05-01 for semiconductor device, semiconductor package, electronic device, and method for establishing information processing environment.
This patent application is currently assigned to Sony Computer Entertainment Inc.. Invention is credited to Oka, Masaaki.
Application Number | 20030080417 10/262789 |
Document ID | / |
Family ID | 26623616 |
Filed Date | 2003-05-01 |
United States Patent
Application |
20030080417 |
Kind Code |
A1 |
Oka, Masaaki |
May 1, 2003 |
Semiconductor device, semiconductor package, electronic device, and
method for establishing information processing environment
Abstract
An electronic device is provided on which semiconductor packages
can be mounted efficiently. The electronic device includes a board
that can receive a plurality of first semiconductor packages each
carrying a processor device and a plurality of second semiconductor
packages each carrying a memory device. Mount regions where the
packages are to be mounted and non-mount regions are alternately
arranged in rows and columns on the board. This ensures
approximately equal wiring distances between the packages, allowing
processor devices to access associated memory devices at the same
time.
Inventors: |
Oka, Masaaki; (Kanagawa,
JP) |
Correspondence
Address: |
LERNER, DAVID, LITTENBERG,
KRUMHOLZ & MENTLIK
600 SOUTH AVENUE WEST
WESTFIELD
NJ
07090
US
|
Assignee: |
Sony Computer Entertainment
Inc.
Tokyo
JP
|
Family ID: |
26623616 |
Appl. No.: |
10/262789 |
Filed: |
October 2, 2002 |
Current U.S.
Class: |
257/734 ;
257/E23.146; 257/E25.023 |
Current CPC
Class: |
H01L 2225/1005 20130101;
H05K 2201/09418 20130101; H01L 25/18 20130101; H01L 2924/0002
20130101; Y02P 70/50 20151101; H01L 25/105 20130101; H05K
2201/10159 20130101; H01L 25/165 20130101; H01L 23/525 20130101;
H05K 2201/09409 20130101; H05K 2201/10689 20130101; H05K 1/181
20130101; H05K 2201/09709 20130101; Y02P 70/611 20151101; H01L
2924/0002 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/734 |
International
Class: |
H01L 023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 2, 2001 |
JP |
2001-306880 |
Sep 17, 2002 |
JP |
2002-270145 |
Claims
1. A semiconductor device, comprising: a plurality of function
implementation segments provided in the semiconductor device, said
function implementation segments being adapted to implement their
unique and distinctive functions; each of said function
implementation segments being electrically interconnected to other
of said function implementation segments so that each of said
function implementation segments can implement a desired function
in cooperation with said other of said function implementation
segments to which it is electrically interconnected, each of said
function implementation segments being positioned in the
semiconductor device so that each of said function implementation
segments is spaced from adjacent function implementation segments
by a wiring distance, said wiring distance between each adjacent
pair of function implementation segments being about the same.
2. A semiconductor package, comprising: a plurality of mount
regions provided in the semiconductor package, each of said mount
regions being electrically interconnected to other of said mount
regions; a semiconductor device mounted on each of at least two of
said mount regions, each of said semiconductor devices being
electrically interconnected to other of said semiconductor devices
so that each of said semiconductor devices can implement a desired
function in cooperation with said other of said semiconductor
devices to which it is electrically interconnected; each of said
mount regions being positioned in the semiconductor package so that
each of said semiconductor devices is spaced from adjacent
semiconductor devices by a wiring distance, said wiring distance
between each adjacent pair of semiconductor devices being about the
same.
3. An electronic device, comprising: a plurality of mount regions
provided in the electronic device, each of said mount regions being
electrically interconnected to other of said mount regions; a
semiconductor package mounted on each of at least two of said mount
regions, each of said semiconductor packages being electrically
interconnected to other of said semiconductor packages so that each
of said semiconductor packages can implement a desired function in
cooperation with said other of said semiconductor packages to which
it is electrically interconnected; each of said mount regions being
positioned in the electronic device so that each of said
semiconductor packages is spaced from adjacent semiconductor
packages by a wiring distance, said wiring distance between each
adjacent pair of semiconductor packages being about the same.
4. The electronic device as claimed in claim 3, further comprising:
a board; and at least one non-mount region on which no
semiconductor package is mounted; said mount regions and said
non-mount regions having rectangular shapes of equal size and being
alternately arranged in rows and columns on said board to form a
matrix pattern.
5. The electronic device as claimed in claim 3, further comprising:
a board, wherein said mount regions have a rectangular shape and a
size, said size of each of said mount regions being the same, said
mount regions being arranged in rows and columns on said board with
almost no gap between adjacent ones of said mount regions.
6. The electronic device as claimed in claim 3, further comprising:
a board, wherein said mount regions have a regular hexagonal shape
and a size, said size of each of said mount regions being the same,
said mount regions being arranged in a honeycomb pattern on said
board.
7. The electronic device as claimed in claim 3, further comprising:
a board, wherein said mount regions have a triangular shape and a
size, said size of each of said mount regions being the same, said
mount regions being arranged on said board with almost no gap
between adjacent ones of said mount regions.
8. The electronic device as claimed in claim 3, further comprising:
a board, wherein each of said plurality of mount regions is a
combination of at least two triangular regions of equal size, said
combinations being arranged on said board with almost no gap
between adjacent ones of said mount regions.
9. The electronic device as claimed in claim 3, further comprising:
a board, wherein said plurality of mount regions include a first
group of mount regions having a first shape and a second group of
mount regions having a second shape different from said first
shape, each of said mount regions being arranged on said board so
that a side of a mount region of said first group is opposed to a
side of a mount region of said second group and with almost no gap
between said side of said mount region of said first group and said
side of said mount region of said second group.
10. The electronic device as claimed in claim 3, wherein each of
said mount regions has a shape, and each of said semiconductor
packages has a mounting surface having a shape, said shape of each
of said mounting surfaces being the same as said shape of said
mount region on which said semiconductor package is mounted.
11. The electronic device as claimed in claim 10, wherein each of
said semiconductor packages includes a semiconductor device, for
each of said semiconductor packages, said semiconductor device in
said semiconductor package mounted on one of said mount regions
being different from said semiconductor device in said
semiconductor package mounted on another of said mount regions
adjacent to said one of said mount regions.
12. The electronic device as claimed in claim 11, wherein said one
of said mount regions includes an active device package having an
active device, and said another of said mount regions includes a
passive device package having a passive device.
13. The electronic device as claimed in claim 12, further
comprising: a plurality of active device packages, each of said
active device packages including an active device, each of said
active device packages being mounted on a mount region adjacent to
said another of said mount regions, said passive device being
shared among said active devices.
14. The electronic device as claimed in claim 12, further
comprising: a plurality of passive device packages, each of said
passive device packages including a passive device, each of said
passive device packages being mounted on a mount region adjacent to
said one of said mount regions, said active device communicating
with each of said passive devices.
15. The electronic device as claimed in claim 14, further
comprising: a plurality of active device packages, each of said
active device packages including an active device, each of said
active device packages being mounted on a mount region adjacent to
a mount region having one of said passive device packages, at least
one of said passive devices being shared among at least a portion
of said active devices, said active devices being configured so
that each of said active devices in said portion of said active
devices is able to read through said at least one passive device
digital information generated by other of said active devices in
said portion of said active devices.
16. The electronic device as claimed in claim 12, wherein said
active device is a processor device capable of reading digital
information, and said passive device is a memory device for storing
said digital information.
17. A method for establishing an information processing environment
in an electronic device, the electronic device including a board
and a plurality of mount regions provided on the board, each of the
mount regions being electrically interconnected to other of the
mount regions, and a semiconductor package mounted on each of at
least two of the mount regions, each of the semiconductor packages
being electrically interconnected to other of the semiconductor
packages so that each of the semiconductor packages can implement a
desired function in cooperation with the other of the semiconductor
packages to which it is electrically interconnected, said method
comprising: positioning the mount regions so that each of the
semiconductor packages is spaced from adjacent semiconductor
packages by a wiring distance, the wiring distance between each
adjacent pair of semiconductor packages being about the same;
mounting a first semiconductor package having a first processor
device on a selected mount region; mounting a second semiconductor
package having a memory device on another mount region adjacent to
the selected mount region; mounting a third semiconductor package
having a second processor device on a mount region adjacent to the
another mount region; and allowing the first processor device to
read results of information processing carried out by the second
processor device and the second processor device to read results of
information processing carried out by the first processor device
through the memory device.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims priority from Japanese
Application Nos. 2001-306880 filed Oct. 2, 2001 and 2002-270145
filed Sep. 17, 2002, the disclosures of which are hereby
incorporated by reference herein.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to an electronic device on
which a plurality of semiconductor packages can be mounted, a
semiconductor package on which a plurality of semiconductor devices
can be mounted, a semiconductor device on which a plurality of
function implementation segments are formed, and a method for
establishing an information processing environment.
[0003] Semiconductor packages are a package product which is
mounted on some or all mount regions on a board for electronic
devices and which includes active devices comprising active cells,
such as processors, or passive devices comprising passive cells,
such as memories. Semiconductor devices are, for example, an
integrated circuit which is mounted on some or all mount regions on
a board for semiconductor packages and which includes function
implementation segments with an active function, such as
processors, or function implementation segments with a passive
function, such as memories. Function implementation segments are
electronic circuits comprising semiconductor cells and electronic
parts that are provided on a semiconductor device.
[0004] Recent demands for smaller computer systems have resulted in
increasing attention to electronic devices in which a plurality of
semiconductor packages are mounted on a board. In such electronic
devices, the arrangement of a plurality of semiconductor packages
on a board is determined considering the details of processing to
be carried out by the semiconductor device(s) mounted on each
semiconductor package, as well as throughputs, processing time, and
the position of input and output terminals of the semiconductor
packages.
[0005] For example, for an electronic device that carries out
necessary processing by using two or more semiconductor packages
(hereinafter, referred to as "memory packages") on which a
semiconductor memory device (hereinafter, referred to as a "memory
device") where digital information is recorded is mounted, and two
or more other semiconductor packages (hereinafter, referred to as
"processor packages") on which a semiconductor processor device
(hereinafter, referred to as a "processor device") that performs
predetermined calculation operations is mounted, i.e., for an
electronic device in which each processor device seeks to access
each memory device to execute processing, the arrangement of the
memory packages and the processor packages on a board is determined
based on, for example, which memory device stores the digital
information to be processed by the processor device.
[0006] In general, when a processor device reads the digital
information on a plurality of memory devices for a predetermined
processing, it is necessary to ensure efficient processing by
controlling the access from the processor devices to the memory
devices at the same time. Processor devices must be arranged so
that they never cross wiring with other semiconductor packages. A
smaller electronic device can be produced with a board having as
many semiconductor packages as possible.
[0007] This also applies to where a plurality of processor devices
and a plurality of memory devices are mounted on a single
semiconductor package. In addition, the same applies where a
plurality of function implementation segments each having a
function as a processor and a plurality of function implementation
segments each having a function as a memory are formed on a single
semiconductor device.
[0008] Taking the above into consideration, an object of the
present invention is to provide an electronic device that ensures
efficient execution of desired processing and allows an increased
number of semiconductor packages to be mounted thereon.
[0009] Another object of the present invention is to provide a
semiconductor package that ensures efficient execution of desired
processing and allows more semiconductor packages to be mounted
thereon.
[0010] A still another object of the present invention is to
provide a semiconductor device that ensures efficient execution of
desired processing and allows more function implementation segments
to be formed thereon.
[0011] Another object of the present invention is to provide a
method for establishing an information processing environment.
SUMMARY OF THE INVENTION
[0012] A semiconductor device according to the present invention
includes a plurality of function implementation segments provided
in the semiconductor device, the function implementation segments
being adapted to implement their unique and distinctive functions,
each of the function implementation segments being electrically
interconnected to other of the function implementation segments so
that each of the function implementation segments can implement a
desired function in cooperation with the other function
implementation segments to which it is electrically interconnected,
each of the function implementation segments being positioned in
the semiconductor device so that each of the function
implementation segments is spaced from adjacent function
implementation segments by a wiring distance, the wiring distance
between each adjacent pair of function implementation segments
being about the same.
[0013] A semiconductor package according to the present invention
includes a plurality of mount regions provided in the semiconductor
package, each of the mount regions being electrically
interconnected to other of the mount regions; a semiconductor
device mounted on each of at least two of the mount regions, each
of the semiconductor devices being electrically interconnected to
other of the semiconductor devices so that each of the
semiconductor devices can implement a desired function in
cooperation with the other of the semiconductor devices to which it
is electrically interconnected; each of the mount regions being
positioned in the semiconductor package so that each of the
semiconductor devices is spaced from adjacent semiconductor devices
by a wiring distance, the wiring distance between each adjacent
pair of semiconductor devices being about the same.
[0014] An electronic device according to the present invention
includes a plurality of mount regions provided in the electronic
device, each of the mount regions being electrically interconnected
to other of the mount regions; a semiconductor package mounted on
each of at least two of the mount regions, each of the
semiconductor packages being electrically interconnected to other
of the semiconductor packages so that each of the semiconductor
packages can implement a desired function in cooperation with the
other of the semiconductor packages to which it is electrically
interconnected; each of the mount regions being positioned in the
electronic device so that each of the semiconductor packages is
spaced from adjacent semiconductor packages by a wiring distance,
the wiring distance between each adjacent pair of semiconductor
packages being about the same.
[0015] As is apparent from the above, the wiring distances are
equal or approximately equal between the adjacent function
implementation segments, between the adjacent semiconductor
devices, and between the adjacent semiconductor packages.
Accordingly, information can be exchanged at the same time among
the function implementation segments, among the semiconductor
devices, and among the semiconductor packages.
[0016] Specific examples of the electronic device include those
further including a board; and at least one non-mount region on
which no semiconductor package is mounted; the mount regions and
the non-mount regions having rectangular shapes of equal size and
being alternately arranged in rows and columns on the board to form
a matrix pattern. When the rectangular regions are not arranged to
have a matrix pattern on the board, specific examples of the
electronic device also include those in which the mount regions
have a rectangular shape and a size, the size of each of the mount
regions being the same, the mount regions being arranged in rows
and columns on the board with almost no gap between adjacent ones
of the mount regions; those in which the mount regions have a
regular hexagonal shape and a size, the size of each of the mount
regions being the same, the mount regions being arranged in a
honeycomb pattern on the board; those in which the mount regions
have a triangular shape and a size, the size of each of the mount
regions being the same, the mount regions being arranged on the
board with almost no gap between adjacent ones of the mount
regions; those in which each of the mount regions is a combination
of at least two triangular regions of equal size, the combinations
being arranged on the board with almost no gap between adjacent
ones of the mount regions; and those in which the plurality of
mount regions include a first group of mount regions having a first
shape and a second group of mount regions having a second shape
different from the first shape, each of the mount regions being
arranged on the board so that a side of a mount region of the first
group is opposed to a side of a mount region of the second group,
and with almost no gap between the side of the mount region of the
first group and the side of the mount region of the second
group.
[0017] In any cases, the mounting surface of the semiconductor
package is configured so that the semiconductor packages can be
mounted side by side. Preferably, each of the mount regions has a
shape, and each of the semiconductor packages includes a mounting
surface having a shape, the shape of each of the mounting surfaces
being the same as the shape of the mount region on which the
semiconductor package is mounted.
[0018] The electronic devices having any one of the above-mentioned
configurations allows efficient mounting of a larger number of
semiconductor packages on a single board.
[0019] In such electronic devices, for example, each of the
semiconductor packages includes a semiconductor device, for each of
the semiconductor packages, the semiconductor device in the
semiconductor package mounted on one of the mount regions being
different from the semiconductor device in the semiconductor
package mounted on another of the mount regions adjacent to the one
of the mount regions. For example, the one mount region may include
a semiconductor package (an active device package) having an active
device (e.g., a processor device), and the another of the mount
regions may include a semiconductor package (a passive device
package) having a passive device (e.g., a memory device on which
digital information is stored that is to be read by the processor
device). The electronic device may further include a plurality of
active device packages, each of the active device packages
including an inactive device, each of the active device packages
being mounted on a mount region adjacent to the another of the
mount regions, the passive device being shared among the active
devices. This configuration eliminates the need to provide more
passive devices than necessary, reducing the size of the resulting
electronic device. In addition, digital information obtained as a
result of certain processing can be exchanged between the active
devices in the active device packages that are not directly
interconnected to each other through a shared passive device.
Conventionally, the acquisition of a processing result that is
obtained by other active devices requires access to the passive
device storing the processing result of the corresponding active
device through the active device that has performed the relevant
processing. On the contrary, the present invention makes it
possible to obtain processing results of other active devices at a
higher speed.
[0020] The electronic device may include a plurality of passive
device packages, each of the passive device packages including a
passive device, each of the passive device packages being mounted
on a mount region adjacent to the one of the mount regions, the
active device communicating with each of the passive devices. This
allows each active device to distribute and store digital
information in the passive devices that are mounted on the adjacent
mount regions. The access time from the active device to the
passive device becomes equal for all combinations, increasing the
speed of processing to be carried out by the active devices.
[0021] A method for establishing an information processing
environment according to the present invention is a method for
establishing an information processing environment in an electronic
device including a board and a plurality of mount regions provided
on the board, each of the mount regions being electrically
interconnected to other of the mount regions, and a semiconductor
package mounted on each of at least two of the mount regions, each
of the semiconductor packages being electrically interconnected to
other of the semiconductor packages so that each of the
semiconductor packages can implement a desired function in
cooperation with the other of the semiconductor packages to which
it is electrically interconnected, the method including positioning
the mount regions so that each of the semiconductor packages is
spaced from adjacent semiconductor packages by a wiring distance,
the wiring distance between each adjacent pair of semiconductor
packages being about the same; mounting a first semiconductor
package having a first processor device on a selected mount region;
mounting a second semiconductor package having a memory device on
another mount region adjacent to the selected mount region;
mounting a third semiconductor package having a second processor
device on a mount region adjacent to the another mount region; and
allowing the first processor device to read results of information
processing carried out by the second processor device and the
second processor device to read results of information processing
carried out by the first processor device through the memory
device.
BRIEF DESCRIPTION OF THE DRAWINGS
[0022] FIG. 1 is a plan view showing an example of a board in an
electronic device according to a first embodiment of the present
invention;
[0023] FIG. 2 is a plan view showing an example of a board in an
electronic device according to a second embodiment of the present
invention;
[0024] FIG. 3 is a plan view showing an example of a board in an
electronic device according to a third embodiment of the present
invention;
[0025] FIG. 4 is a plan view showing an example of a board in an
electronic device according to a fourth embodiment of the present
invention;
[0026] FIG. 5 is a plan view showing an example of a board in an
electronic device according to a fifth embodiment of the present
invention;
[0027] FIG. 6 is a plan view showing an example of a board in an
electronic device according to a sixth embodiment of the present
invention;
[0028] FIG. 7 is a view that schematically illustrates how
processor devices are interconnected to a memory device and how the
memory device is shared among the processor devices;
[0029] FIG. 8 is a view illustrating squares stored on memory
packages M1, M2, M4, and M5 of the squares of a grid representing
data for the entire world of a 3D image;
[0030] FIG. 9 is a view illustrating a normal vector for a square
of a grid;
[0031] FIG. 10 is a view illustrating a normal vector at a grid
point; and
[0032] FIG. 11 is a view of processing carried out by a processor
package P1.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0033] Embodiments of an electronic device according to the present
invention are described below with reference to the drawings.
[0034] <First Embodiment>
[0035] Described first is an electronic device which includes a
board carrying a plurality of mount regions on which semiconductor
packages are to be mounted and a plurality of non-mount regions on
which no semiconductor package is to be mounted. In this example,
mounting surfaces (the term "mounting surface" as used herein means
the back surface of a package opposite the corresponding mount
region) of the semiconductor packages, the mount regions, and the
non-mount regions are rectangles of equal size. The semiconductor
packages to be mounted are processor packages each carrying a
processor device which is an example of an active device and memory
packages each carrying a memory device which is an example of a
passive device. However, the semiconductor packages may be those
carrying other kinds of semiconductor devices.
[0036] FIG. 1 is a plan view showing an example of a board in an
electronic device according to this embodiment. A non-mount region
4 is provided between each adjacent pair of mount regions 3 on the
board 1. The mount regions 3 and the non-mount regions 4 are
alternately arranged in rows and columns on the board 1. The board
in FIG. 1 carries memory packages M0 to M8 and processor packages
P0 to P8.
[0037] The processor package P0 is interconnected to the memory
packages M0, M1, M3, and M4 through the wiring 2. The data
associated with the processing carried out by the processor device
in the processor package P0 (e.g., data to be used for processing
or data obtained as a result of processing) are distributed over,
stored in, and read out of the memory devices in the memory
packages M0, M1, M3, and M4. The same applies to other processor
packages. More specifically, the processor package P1 is
interconnected to the memory packages M1, M2, M4, and M5. The
processor package P3 is interconnected to the memory packages M3,
M4, M6, and M7. The processor package P4 is interconnected to the
memory packages M4, M5, M7, and M8. Thus, the adjacent four memory
packages are interconnected to each other. The data associated with
processing are distributed over, stored in, and read out of the
memory devices in these memory packages.
[0038] For the processor packages P2, P5, P6, P7, and P8, only one
or two memory packages are shown just for ease of illustration.
[0039] Taking particular note of the memory packages, the memory
devices in a single memory package are shared among the processor
devices in a plurality of processor packages. In this case, the
same storage region may be shared. Alternatively, where there is
enough storage capacity, the storage region may be divided into the
same number of blocks as the number of processors among which the
storage region is to be shared, and the blocks of the storage
region may be allocated among the processor devices.
[0040] For example, the memory device in the memory package M4 is
shared among the processor devices in the processor packages P0,
P1, P3, and P4. The memory device in the memory package M5 is
shared among the processor devices in the processor packages P1,
P2, P4, and P5. Likewise, the memory device in the memory package
M7 is shared among the processor devices in the processor packages
P3, P4, P6, and P7. The memory device in the memory package M8 is
shared among the processor devices in the processor packages P4,
P5, P7, and P8.
[0041] For the other memory packages M0, M1, M2, M3, and M6, only
one or two processor packages are shown just for ease of
illustration.
[0042] The processor packages P0 to P8 may be allowed to access the
memory devices in the memory packages M0 to M8, respectively,
depicted with the same suffix to store and read the data (e.g., the
processor package P0 is allowed to access the memory package M0,
the processor package P1 is allowed to access the memory package
M1, and so on).
[0043] The above-mentioned arrangement of the processor packages
and the memory packages on the board 1 ensures equal or
approximately equal electrical wiring distances between the
semiconductor packages on the adjacent mounting regions 3. When the
semiconductor packages cooperate with each other to implement a
certain desired function, digital information can be exchanged for
an equal transmission period between any pairs of packages. In
addition, the wiring 2 may be patterned, with a possible reduction
in manufacturing costs for a board 1 for multi-processor
systems.
[0044] As apparent from the above, a plurality of memory packages
(each carrying a shared memory device) are arranged around a given
processor package. The wiring distance is approximately equal for
all pairs of processor devices and the memory devices on these
packages. Therefore, each processor device can use a plurality of
memory devices at the same time, making good use of the processor
devices. Each processor device can use the data associated with the
processing carried out by the other three processor devices that
surround the same single memory device, through that memory device.
This also improves the efficiency of processing.
[0045] While the semiconductor packages in this embodiment are of
equal size, the present invention is not limited to such a
configuration. The memory packages and the processor packages may
be of different size.
[0046] <Second Embodiment>
[0047] FIG. 2 is a plan view showing an example of a board in an
electronic device according to a second embodiment.
[0048] In this embodiment, rectangular mount regions of equal size
are provided on a board in an electronic device. However, unlike
the first embodiment, non-mount regions are not provided. Instead,
the mount regions are provided on the board almost without a gap
between them. The mounting surface of the semiconductor package to
be mounted is rectangular and equal in size to the mount region.
The board in FIG. 2 carries memory packages M1 to M9 and processor
packages P1 to P4. For convenience, the board and the wiring are
depicted by the reference numerals 1 and 2, respectively, as in the
first embodiment.
[0049] All mount regions that are arranged side-by-side in this
embodiment carry different kinds of semiconductor packages from
each other. The mount regions arranged in the diagonal directions
carry the same kind of semiconductor packages.
[0050] The processor package P1 is interconnected through the
wiring 2 to the memory packages M1, M2, M4, and M5 that are
adjacent to the processor package P1 in the vertical and horizontal
directions. The data associated with the processing carried out by
the processor device in the processor package P1 are distributed
over, stored in, and read out of the memory devices in the four
memory packages M1, M2, M4, and M5. Likewise, the processor
packages P2, P3, and P4 are interconnected to their respective
adjacent memory packages in the vertical and horizontal directions.
The data associated with processing are distributed over, stored
in, and read out of the memory devices in the relevant four memory
packages.
[0051] Taking particular note of the memory packages, for example,
the memory package M5 is interconnected to four processor packages
P1 to P4. The memory device on the memory package M5 is shared
among the four processor devices. In this case, the same storage
region may be shared. Alternatively, where there is enough storage
capacity, the storage region may be divided into the same number of
blocks as the number of processors among which the storage region
is to be shared, and the blocks of the storage region may be
allocated among the processor devices. More specifically, the
storage region in the memory device may be divided into four
blocks. The blocks of the storage region are allocated among the
processor devices in the processor packages P1 to P4, respectively.
The same applies to the other memory packages. Each memory device
is shared among the processor devices in the opposing processor
packages. The divided blocks of the storage region are allocated
among the respective processor devices.
[0052] This embodiment also ensures equal or approximately equal
electrical wiring distances between the processor packages and the
memory packages. Accordingly, digital information can be exchanged
for an equal transmission period between any pairs of packages. In
addition, the wiring may be patterned, with a possible reduction in
manufacturing costs for a board 1 for multi-processor systems.
[0053] As apparent from the above, four memory packages (each
carrying a shared memory device) are arranged around a given
processor package. The memory packages can be used at the same
time, making good use of the processor devices. Each processor
device can use the data associated with the processing carried out
by the other three processor devices that surround the same single
memory device, through that memory device. This also improves the
efficiency of processing.
[0054] The configuration without the non-mount regions according to
the second embodiment of the present invention provides a larger
available area for increasing the number of semiconductor packages,
thereby reducing the size of a resulting electronic device.
[0055] <Third Embodiment>
[0056] FIG. 3 is a plan view showing an example of a board in an
electronic device according to a third embodiment.
[0057] In this embodiment, a plurality of hexagonal, preferably
regular hexagonal mount regions of equal size are provided in a
honeycomb pattern on a board in an electronic device. The mounting
surfaces of the semiconductor packages to be mounted are all
hexagonal. The board in FIG. 3 carries memory packages M0 to M12
and processor packages P0 to P2. For convenience, the board and the
wiring are depicted by the reference numerals 1 and 2,
respectively, as in the first embodiment.
[0058] The packages are mounted so that the six sides of each
processor package are opposed to one side of each of the
surrounding six memory packages. For example, the six memory
packages MO to M5 are provided around the processor package P0 so
that the sides of the processor package P0 are opposed to one side
of each of the memory packages M0 to M5. The same applies to the
other processor packages. More specifically, the six memory
packages M1, M2, and M6 to M9 are provided around the processor
package P1. The six memory packages M2, M3, and M9 to M12 are
provided around the processor package P2.
[0059] The data associated with the processing carried out by the
processor devices in the processor packages are distributed over,
stored in, and read out of the memory devices in the surrounding
six memory packages interconnected to the relevant processor
package.
[0060] Taking particular note of the memory packages, for example,
the memory package M2 is interconnected to the three processor
packages P0 to P2. The memory device carried in the memory package
M2 is shared among the three processor devices. In this case, the
same storage region may be shared. Alternatively, where there is
enough storage capacity, the storage region may be divided into the
same number of blocks as the number of processors among which the
storage region is to be shared, and the blocks of the storage
region may be allocated among the processor devices. More
specifically, the storage region of the memory device is divided
into three blocks. The divided blocks of the storage region are
allocated among the processor devices in the processor packages P0
to P2, respectively. The same applies to the other memory packages.
Each memory package is shared among the processor devices in the
processor packages that are opposed to the sides of the respective
memory packages. The divided blocks of the storage region are
allocated among the corresponding processor devices.
[0061] This embodiment also ensures equal or approximately equal
electrical wiring distances between the processor packages and the
memory packages. Accordingly, digital information can be exchanged
for an equal transmission period between any pairs of packages. In
addition, the wiring may be patterned, with a possible reduction in
manufacturing costs for a board 1 for multi-processor systems.
[0062] As is apparent from the above, six memory packages (each
carrying a shared memory device) are arranged around a given
processor package. Each processor device is allowed to use the six
memory devices at the same time. Therefore, the performance of the
processor device can be drawn more efficiently than in the cases of
the first and second embodiments. Processing using processing
results from the three processor devices can be performed using a
single memory device.
[0063] Furthermore, since the mount regions are arranged in a
honeycomb pattern, the semiconductor packages can be mounted for
useful purposes when the board 1 has a generally circular
shape.
[0064] While the memory packages are arranged around a processor
package in this embodiment, it is possible for processor packages
to surround a memory package.
[0065] <Fourth Embodiment>
[0066] FIG. 4 is a plan view showing an example of a board in an
electronic device according to a fourth embodiment.
[0067] In this embodiment, a plurality of triangular mount regions
of equal size are provided on a board in an electronic device
without a gap between them. The mounting surfaces of the
semiconductor packages to be mounted are all triangular. The board
in FIG. 4 carries memory packages M0 to M13 and processor packages
P0 to P9. For convenience, the board and the wiring are depicted by
the reference numerals 1 and 2, respectively, as in the first
embodiment.
[0068] The packages are mounted so that the three sides of each
processor package are opposed to one side of each of the
surrounding three memory packages. For example, the three memory
packages M0, M3, and M4 are provided around the processor package
P0 so that the sides of the processor package P0 are opposed to one
side of each of the memory packages M0, M3, and M4. The same
applies to the other processor packages.
[0069] The data associated with the processing carried out by the
processor devices in the processor packages are distributed over,
stored in, and read out of the memory devices in the surrounding
three memory packages interconnected to the relevant processor
package.
[0070] Taking particular note of the memory packages, for example,
the memory package M4 is interconnected through the wiring 2 to the
three processor packages P0, P1, and P4. The memory device carried
in the memory package M4 is shared among the processor devices in
the processor packages P0, P1, and P4. In this case, the same
storage region may be shared. Alternatively, where there is enough
storage capacity, the storage region may be divided into the same
number of blocks as the number of processors among which the
storage region is to be shared, and the blocks of the storage
region may be allocated among the processor devices. More
specifically, the storage region of the memory device in the memory
package M4 is divided into three blocks. The divided blocks of the
storage region are allocated among the processor devices in the
processor package P0, P1, and P4. The data associated with the
processing carried out by the processor devices in the processor
packages P0, P1, and P4 are stored in and read out of the divided
blocks of the storage region, respectively. The same applies to the
other memory packages.
[0071] This embodiment also ensures equal or approximately equal
electrical wiring distances between the processor packages and the
memory packages. Accordingly, digital information can be exchanged
for an equal transmission period between any pairs of packages. In
addition, the wiring may be patterned, with a possible reduction in
manufacturing costs for a board 1 for multi-processor systems.
[0072] Furthermore, since the mount regions are arranged in a
triangle pattern, the semiconductor packages can be mounted for
useful purposes when the board 1 has a generally circular
shape.
[0073] <Fifth Embodiment>
[0074] FIG. 5 is a plan view showing an example of a board in an
electronic device according to a fifth embodiment.
[0075] An electronic device in this embodiment is a combination of
the third embodiment and the fourth embodiment. More specifically,
six triangular mount regions are combined into a hexagonal mount
region. The hexagonal mount regions are arranged in a honeycomb
pattern on a board. The hexagonal mount regions are interconnected
to each other through wiring 2. The mounting surfaces of the
semiconductor packages to be mounted are all triangular. By
combining them, hexagons that correspond to the mount regions are
formed. The board in FIG. 5 carries memory packages M0 to M12 (up
to six triangular memory packages per mount region) and processor
packages P0 to P2 (up to six triangular processor packages per
mount region). For convenience, the board and the wiring are
depicted by the reference numerals 1 and 2, respectively, as in the
first embodiment.
[0076] In addition to the advantages of the third and fourth
embodiments, the electronic device according to this embodiment
offers the advantage that an arbitrary number (up to six) of
triangular semiconductor packages can be mounted on each hexagonal
region.
[0077] The triangular semiconductor packages can be mounted on the
board 1 with no unnecessary gaps between the packages.
[0078] While the mount regions are hexagonal in FIG. 5, there is no
limitation on the shape of the mount regions as long as the shape
is produced as a combination of two or more triangles of equal
size.
[0079] <Sixth Embodiment>
[0080] FIG. 6 is a plan view showing an example of a board in an
electronic device according to a sixth embodiment.
[0081] In this embodiment, a plurality of mount regions of two
different sizes and shapes are provided on a board in an electronic
device. For example, some mount regions may be hexagonal regions,
preferably, regular hexagonal regions of equal size, and the other
mount regions may be triangular regions, preferably, regular
triangular regions of equal size. By combining two kinds of
regions, the mount regions may be arranged on the board almost
without a gap between them. More specifically, the mount regions
may be arranged on the board without a gap between them so that the
three sides of each triangle are opposed to one side of each of the
surrounding regular hexagons. The mounting surfaces of the
semiconductor packages to be mounted are either regular hexagonal
or regular triangular, depending on the shape of the corresponding
mount regions. The board in FIG. 6 carries memory packages MO to M3
each having a regular hexagonal mounting surface, and processor
packages P0 to P5 each having a regular triangular mounting
surface. For convenience, the board and the wiring are depicted by
the reference numerals 1 and 2, respectively, as in the first
embodiment.
[0082] The processor package P2 is interconnected through the
wiring 2 to the memory packages M0, M1, and M2. The data associated
with the processing carried out by the processor device in the
processor package P2 are distributed over, stored in, and read out
of the memory devices in the memory packages M0, M1, and M2. The
same applies to the processor package P3. More specifically, the
processor package P3 is interconnected to the memory packages M0,
M2, and M3. The data associated with the processing carried out by
the processor device in the processor package P3 are distributed
over, stored in, and read out of the memory devices in the memory
packages.
[0083] For the other processor packages P0, P1, P4, and P5, only
two memory packages are shown just for ease of illustration. The
data associated with the processing carried out by the processor
devices in the processor packages P0, P1, P4, and P5 are also
distributed over, stored in, and read out of the memory devices in
the relevant memory packages.
[0084] Taking particular note of the memory packages, for example,
the memory package M0 is interconnected to four processor packages
P0 to P3. The memory device carried in the memory package M0 is
shared among the four processor devices. In this case, the same
storage region may be shared. Alternatively, where there is enough
storage capacity, the storage region may be divided into the same
number of blocks as the number of processors among which the
storage region is to be shared, and the blocks of the storage
region may be allocated among the processor devices. More
specifically, the storage region of the memory device is divided
into four blocks. The divided blocks of the storage region are
allocated among the processor devices in the processor packages P0
to P3. The same applies to the other memory packages. The divided
blocks of the storage region are allocated among the processor
devices.
[0085] The memory package M1 is interconnected to the processor
packages P1, P2, and P5. The memory device carried in the memory
package M1 is shared among the three processor devices. The memory
package M2 is interconnected to the processor packages P2 to P5.
The memory device carried in the memory package M2 is shared among
the four processor devices. The memory package M3 is interconnected
to the processor packages P0, P3, and P4. The memory device carried
in the memory package M3 is shared among the three processor
devices.
[0086] Only three or four processor packages are interconnected to
each of the memory packages M0 to M3 just for ease of illustration.
One processor package can be interconnected to each side of the
memory package. Accordingly, in this embodiment, up to six
processor packages can be interconnected to a single memory
package. The memory device in the memory package can be shared
among all processor packages that are interconnected thereto.
[0087] This embodiment also ensures equal or approximately equal
electrical wiring distances between the processor packages and the
memory packages. Accordingly, digital information can be exchanged
for an equal transmission period between any pairs of packages. In
addition, the wiring may be patterned, with a possible reduction in
manufacturing costs for a board 1 for multi-processor systems.
[0088] As apparent from the above, a plurality of memory packages
(each carrying a shared memory device) are arranged around a single
processor package. The single processor device can use the
plurality of memory devices at the same time. Therefore, the
performance of the processor device can be drawn more efficiently.
Processing using processing results from a plurality of processor
devices can be performed through a single memory device.
[0089] This embodiment employs regular triangular mount regions for
the processor packages and regular hexagonal mount regions for the
memory packages. However, the mount regions for the processor
packages may be regular hexagonal and the mount regions for the
memory packages may be regular triangular.
[0090] In the first through sixth embodiments, other semiconductor
package(s), electronic part(s) and similar components may be
arranged on the boards in FIG. 1 to FIG. 6. However, they are not
directly associated with the implementation of the present
invention and description and illustration thereof are thus
omitted.
[0091] <Application Modes>
[0092] Next, an application mode of the electronic devices
according to the above-mentioned embodiments, in particular, a
method for establishing an information processing environment for
these electronic devices, is described.
[0093] FIG. 7 shows the relationship between the processor packages
P1 to P4 on the board 1 in FIG. 2 and the memory packages M1 to M9.
The processor packages P1 to P4 are depicted by broken lines and
the memory packages M1 to M9 are depicted by solid lines.
[0094] The data associated with the processing carried out by the
processor device in the processor package P1 are distributed over
and stored in the memory devices in the memory packages M1, M2, M4,
and M5. The data associated with the processing carried out by the
processor device in the processor package P2 are distributed over
and stored in the memory devices in the memory packages M2, M3, M5,
and M6. The data associated with the processing carried out by the
processor device in the processor package P3 are distributed over
and stored in the memory devices in the memory packages M4, M5, M7,
and M8. The data associated with the processing carried out by the
processor device in the processor package P4 are distributed over
and stored in the memory devices in the memory packages M5, M6, M8,
and M9.
[0095] The data associated with the processing carried out by the
processor device in the processor package P2 and the data
associated with the processing carried out by the processor device
in the processor package P1 are both stored in the memory device in
the memory package M2. In other words, the memory device in the
memory package M2 contains mixed data associated with the
processing carried out by the processor devices in both processor
packages P1 and P2. Accordingly, the processor device in the
processor package P1 can easily use the processing results obtained
by the processor device in the processor package P2 through the
memory device in the memory package M2. Similarly, the processor
device in the processor package P2 can easily use the processing
results obtained by the processor device in the processor package
P1 through the memory device in the memory package M2.
[0096] Likewise, the memory device in the memory package M4 allows
each processor device in the processor packages P1 and P3 to easily
use the processing results obtained by the other processor device.
The memory device in the memory package M5 allows each processor
device in the processor packages P1 to P4 to easily use the
processing results obtained by the other three processor devices.
The memory device in the memory package M6 allows each processor
device in the processor packages P2 and P4 to easily use the
processing results obtained by the other processor device. The
memory device in the memory package M8 allows each processor device
in the processor packages P3 and P4 to easily use the processing
results obtained by the other processor device. Accordingly, using
one of the above-mentioned electronic devices, the following
information processing environment can be established.
[0097] Processing of 3D images is described using the following
electronic device as an example.
[0098] The memory devices in the memory packages M1 to M9 store
distributed data that represent the entire world of a 3D image. The
processor devices in the processor packages P1 to P4 use the data
to carry out processing required to produce the entire world of a
3D image.
[0099] A curved surface in the entire world of a 3D image is
divided into grids. The data representing the curved surface are
stored in the memory devices and are processed by the processor
devices, based on a square of the grid as a unit.
[0100] FIG. 8 illustrates data representing a curved surface that
are stored in the memory devices in the memory packages M1, M2, M4,
and M5. Each memory device stores the data representing a part of
the curved surface corresponding to a grid of 8 by 8 in size.
[0101] The data representing a part of the curved surface that are
stored in the memory device in the memory package M1 are processed
by the processor device in the processor package P1. The data
representing a part of the curved surface that are stored in the
memory device in the memory package M2 are processed by the
processor devices in the processor packages P1 and P2. The data
representing a part of the curved surface that are stored in the
memory device in the memory package M4 are processed by the
processor devices in the processor packages P1 and P3. The data
representing a part of the curved surface that are stored in the
memory device in the memory package M5 are processed by the
processor devices in the processor packages P1 to P4.
[0102] As an example of the processing carried out by the processor
devices, processing to obtain a normal vector at each grid point is
described. Normal vectors at the grid points are necessary for
rendering a curved surface.
[0103] To calculate a normal vector at a grid point, normal vectors
are calculated for each square of the grid. FIG. 9 is a view
illustrating the normal vector n in the square ABCD of a grid.
[0104] First, the vector "a" is calculated from the vectors AB and
AD using the vector cross product. The vector "b" is calculated
from the vectors CB and CD using the vector cross product. The
normalized sum of the vectors "a" and "b" corresponds to the normal
vector n for the illustrated square of the grid. This can be
explained as follows. 1 a = AB .times. AD b = CB .times. CD n = ( a
+ b ) / a + b Equation 1
[0105] After the normal vectors for the squares of the grid are
calculated, normal vectors at the grid points are calculated. The
normal vector at a given grid point is the normalized sum of the
normal vectors for the four squares of the grid that share the
subject grid point (FIG. 10). Let the normal vectors for the four
squares of the grid be the vectors n1 to n4, respectively, and the
normal vector at the grid point be the vector N, then the vector N
can be given by the following equation. 2 N = ( n1 + n2 + n3 + n4 )
/ n1 + n2 + n3 + n4 Equation 2
[0106] In order to calculate the normal vectors at the grid points
in the range delimited by the heavy black line in FIG. 11 along
with those at the grid points on the line, it is necessary to
calculate the normal vectors for the squares of the grid in the
range delimited by the broken line. The normal vectors at the grid
points enclosed in the heavy black line except for those on the
line are calculated by the processor device in the processor
package P1.
[0107] For a memory package to which only one processor package is
interconnected, all data that are stored in the memory device in
the memory package are subjected to calculation by the processor
device in the single processor package.
[0108] The normal vectors for the squares between the heavy black
line and the broken line that are stored in the memory device in
the memory package M1 are calculated by the processor device in the
processor package P1. Therefore, the normal vectors at the grid
points on the heavy black line that are stored in the memory device
in the memory package M1 are calculated by the processor device in
the processor package P1.
[0109] The normal vectors for the squares between the heavy black
line and the broken line that are stored in the memory device in
the memory package M2 are calculated by the processor device in the
processor package P1 or P2. Therefore, the normal vectors at the
grid points on the heavy black line that are stored in the memory
device in the memory package M2 are calculated by the processor
device in the processor package P1 or P2.
[0110] The normal vectors for the squares between the heavy black
line and the broken line that are stored in the memory device in
the memory package M4 are calculated by the processor device in the
processor package P1 or P3. Therefore, the normal vectors at the
grid points on the heavy black line that are stored in the memory
device in the memory package M4 are calculated by the processor
device in the processor package P1 or P3.
[0111] The normal vectors for the squares between the heavy black
line and the broken line that are stored in the memory device in
the memory package M5 are calculated by the processor device in one
of the processor packages P1 to P4. Therefore, the normal vectors
at the grid points on the heavy black line that are stored in the
memory device in the memory package M5 are calculated by the
processor devices in the processor packages P1 to P4.
[0112] Conventionally, in order to use processing results obtained
by other processor devices (i.e., normal vectors for squares of a
grid that are calculated by other processor devices), a processor
device must access through the relevant other processor devices the
memory device that stores the desired processing result(s).
[0113] On the contrary, according to the present invention, the
memory devices are shared among a plurality of processor devices.
This means that necessary data are stored in the same memory
device. Processing results obtained by any processor devices are
available for all processor devices without the above-mentioned
conventional problems.
[0114] The connection paths between the processor package P1 and
each of the memory packages M1, M2, M4, and M5 are equal in length.
This ensures an identical time duration for the processor device to
access each of the memory devices.
[0115] While the above-mentioned example is for the electronic
device according to the second embodiment, similar application
modes (establishment of an information processing environment) can
be applied to the electronic devices according to other
embodiments. In other words, the electronic device of any one of
the above-mentioned embodiments can be used to implement a similar
configuration wherein the processor devices distribute data over a
plurality of memory devices and wherein the memory devices read and
store the data from the processor devices.
[0116] In the above-mentioned embodiments, the mount regions the
semiconductor packages are arranged on the board in the electronic
device. However, the following embodiment can be contemplated for a
semiconductor package and a semiconductor device according to the
present invention.
[0117] For semiconductor packages, a board for a semiconductor
package is used in place of the above-mentioned board in the
electronic device. On the board for the semiconductor package,
semiconductor devices such as memory devices or processor devices
are mounted in place of the semiconductor packages of the first to
sixth embodiments. Accordingly, mount regions for that purpose are
provided on the board for the semiconductor package.
[0118] More specifically, two semiconductor devices are alternately
arranged in rows and columns on the board for the semiconductor
package, as in the first to sixth embodiments. Alternatively, they
may be arranged in a honeycomb pattern. The shape of the
semiconductor device is not limited to a conventional rectangle.
Instead, it may be triangular or hexagonal in order to fit to the
mount regions.
[0119] As in the first to sixth embodiments, this configuration
ensures equal or approximately equal electrical wiring distances
between a specific semiconductor device and each of a plurality of
semiconductor devices adjacent to the specific semiconductor
device.
[0120] For semiconductor devices, two different function
implementation segments, such as function implementation segments
that serve as processors and function implementation segments that
serve as memories, are arranged with similar shapes and patterns to
those described in conjunction with the first to sixth
embodiments.
[0121] This configuration ensures equal or approximately equal
electrical wiring distances between a specific function
implementation segment and each of a plurality of function
implementation segments adjacent to the specific function
implementation segment, as in the first to sixth embodiments.
[0122] As apparent from the above, the electronic device according
to the present invention offers an efficient arrangement of a
plurality of semiconductor packages on a board. In addition, by
using the above-mentioned electronic device, information processing
can be performed with a high degree of efficiency by means of
cooperating semiconductor devices with each other.
[0123] The semiconductor device of the present invention allows a
plurality of function implementation segments to be formed
efficiently. In addition, information processing can be performed
with a high degree of efficiency through cooperation of the
function implementation segments.
[0124] Although the invention herein has been described with
reference to particular embodiments, it is to be understood that
these embodiments are merely illustrative of the principles and
applications of the present invention. It is therefore to be
understood that numerous modifications may be made to the
illustrative embodiments and that other arrangements may be devised
without departing from the spirit and scope of the present
invention as defined by the appended claims.
* * * * *