U.S. patent application number 10/292735 was filed with the patent office on 2003-04-03 for hardware copy assist for data communication switch.
This patent application is currently assigned to Alcatel Internetworking, Inc.. Invention is credited to Bergenfeld, Bruce Eric.
Application Number | 20030063609 10/292735 |
Document ID | / |
Family ID | 22427364 |
Filed Date | 2003-04-03 |
United States Patent
Application |
20030063609 |
Kind Code |
A1 |
Bergenfeld, Bruce Eric |
April 3, 2003 |
Hardware copy assist for data communication switch
Abstract
A hardware copy assist for a data communication switch copies
packets in a number required to meet multicasting needs. Packets
are read from a switch queue and a home mark is retained for the
packet at the head of the queue to facilitate multiple reads and to
prevent premature overwrites. Copying decisions may be made
incidental to the retrieval of outbound headers from a linked list
of table entries to minimize overhead.
Inventors: |
Bergenfeld, Bruce Eric;
(Agoura Hills, CA) |
Correspondence
Address: |
CHRISTIE, PARKER & HALE, LLP
P.O. BOX 7068
PASADENA
CA
91109-7068
US
|
Assignee: |
Alcatel Internetworking,
Inc.
|
Family ID: |
22427364 |
Appl. No.: |
10/292735 |
Filed: |
November 12, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10292735 |
Nov 12, 2002 |
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09126916 |
Jul 30, 1998 |
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6504842 |
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Current U.S.
Class: |
370/390 ;
370/270 |
Current CPC
Class: |
H04L 49/201 20130101;
H04L 12/1886 20130101; H04L 49/351 20130101; H04L 49/3018
20130101 |
Class at
Publication: |
370/390 ;
370/270 |
International
Class: |
H04L 012/56 |
Claims
1. In a data communication switch, a method for generating a
required number of copies of a packet, comprising: (a) writing a
packet into a plurality of addresses in a switch queue; (b) reading
the packet from the plurality of addresses; (c) determining if
additional copying is indicated from information in a table entry
having header data for combining with the packet; (d) if additional
copying is indicated, resetting the read address to the first
address in which the packet is written and repeating steps (b) and
(c).
2. The method for generating required copies of a packet according
to claim 1, wherein the determining step comprises: (i) consulting
the table entry; and (ii) learning if the information in the
consulted table entry has a valid index to another table entry
having header data for combining with the packet.
3. The method of claim 1, wherein if additional copying is not
indicated, advancing the read address to a first-written address of
a next packet for copying from the switch queue.
4. In a data communication switch, a method for generating a
required number of copies of a packet, comprising: (a) writing a
packet into a plurality of addresses of a switch queue; (b) setting
a home mark to the first address in which the packet is written;
(c) reading the packet from the plurality of addresses; (d)
determining if additional copying is indicated from information in
a table entry having header data for combining with the packet; (e)
if additional copying is indicated, resetting the read address to
the home mark and repeating steps (c) and (d).
5. The method of claim 4 further comprising: if additional copying
is not indicated, advancing the home mark to a first-written
address of a next packet for copying from the switch queue.
6. A method for processing an inbound packet in a data
communication switch, comprising: (a) receiving a packet in an
ingress queue, the received packet having packet identifiers and
packet data; (b) transmitting the packet identifiers to switching
logic for a forwarding decision; (c) writing the packet data into a
plurality of addresses in a switch queue; (d) consulting a table
entry at an index returned from the switching logic in response to
the packet identifiers; (e) reading the packet data from the
plurality of addresses; (f) determining if additional copying is
indicated from information in the consulted table entry, wherein
the information in the consulted table entry includes header data
for combining with the packet data and additional copying is
indicated if the information includes a valid index to another
table entry having header data for combining with the packet data;
and (g) if additional copying is indicated, resetting the read
address to the first address in which the packet data is written
and repeating steps (e) and (f).
7. The method of claim 6, wherein if additional copying is not
indicated, advancing the read address to a first-written address of
a next packet for copying from the switch queue.
8. In a data communication switch, a method for generating a
required number of copies of a packet, comprising: storing a packet
in a switch queue; obtaining a copy of the packet from the switch
queue; retrieving a first header data for the packet from a first
entry of a header table; combining the copy of the packet with the
first header data; determining if the first entry of the header
table includes a valid index to a second table entry storing a
second header data for the packet; and if the entry of the header
table includes a valid index to a second table entry: obtaining a
second copy of the packet; and combining the second copy of the
packet with the second header data.
9. The method of claim 8, wherein the obtaining of the second copy
of the packet comprises resetting a read address to a first address
in which the packet is written in the switch queue.
10. The method of claim 8 further comprising setting a mark to a
first address in which the packet is written in the switch queue,
wherein the obtaining a second copy of the packet comprises
resetting a read address to the mark.
11. The method of claim 10, wherein if the first entry of the
header table does not include a valid index to a second table
entry, advancing the mark to a first-written address of a next
packet for copying from the switch queue.
12. A data communication switch comprising: a switch queue
configured to store a packet; a header table including a first
table entry storing first header data and an index to a second
table entry storing second header data; a queue control unit
causing retrieval of a first copy of the packet, the queue control
unit further causing retrieval of a second copy of the packet if
the first table entry includes a valid index to the second table
entry storing second header data; and a packet assembly unit
receiving the first copy of the packet and the second copy of the
packet and combining the first copy of the packet with the first
header data and the second copy of the packet with the second
header data.
13. The switch of claim 12, wherein the queue control unit obtains
the second copy of the packet by resetting a read address to a
first address in which the packet is written in the switch
queue.
14. The switch of claim 12, wherein the queue control unit further
sets a mark to a first address in which the packet is written in
the switch queue and obtains the second copy of the packet by
resetting a read address to the mark.
15. The switch of claim 14, wherein if the first table entry does
not include a valid index to the second table entry, the queue
control unit advances the mark to a first-written address of a next
packet for copying from the switch queue.
16. A data communication switch comprising: means for receiving a
packet having packet identifiers and packet data; means for making
a forwarding decision based on the packet identifiers; means for
writing the packet data into a plurality of addresses; means for
consulting a table entry based on an index returned by the means
for making a forwarding decision; means for reading the packet data
from the plurality of addresses; means for determining if
additional copying is indicated from information in the consulted
table entry, wherein the information in the consulted table entry
includes header data for combining with the packet data and
additional copying is indicated if the information includes a valid
index to another table entry having header data for combining with
the packet data; and if additional copying is indicated, means for
resetting the read address to the first address in which the packet
data is written for reading the packet data again from the
plurality of addresses.
17. The switch of claim 16, further comprising: if additional
copying is not indicated, means for advancing the read address to a
first-written address of a next packet for copying the next packet.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of U.S. patent
application Ser. No. 09/126,916, filed on Jul. 30, 1998, entitled
"HARDWARE COPY ASSIST FOR DATA COMMUNICATION SWITCH."
BACKGROUND OF THE INVENTION
[0002] The present invention relates to data communication
switching and, more particularly, to methods and devices for
assisting the copying of packets for multicasting.
[0003] Data communication switches receive packets on ingress
ports, format them for the "next hop", and transmit them on egress
ports en route to their ultimate destinations. When more than one
ultimate destination is indicated, i.e., the packet requires
multicasting, th switch must generally make multiple copies of the
packet or a portion thereof and prepends each of the copies with a
different outbound header. Conventional switches have relied
heavily on software-driven central processing units (CPUs) to
accomplish the required copying. Such CPU reliance has introduced
intervening steps into the switching process which have caused
latency and imposed additional buffering requirements. Overall
switching performance has suffered as a result. Therefore, there is
a general need for methods and devices for more efficiently
processing packets requiring multicasting in data communication
switches, and a more particular need for a hardware-based solution
to the task of multicast copying.
SUMMARY OF THE INVENTION
[0004] In its most basic feature, the present invention provides a
hardware copy assist for facilitating data communication switch
multicasting.
[0005] In one aspect of the invention, packets are copies in
hardware in a quantity required to meet multicasting needs. This
inventive aspect is achieved by storing packets in a switch queue
and retaining a home mark to which a read address is reset when
additional copying is indicated. Inbound packets are stored in the
switch queue pending resolution of forwarding requirements. A home
mark is always set to the first-written address of the packet at
the head of the queue. If additional copying of the packet is
indicated, the read address is reset to the home mark after the
most recent copy of the packet is delivered. If additional copying
is not indicated, the home mark is advanced to the first-written
address for the next packet for copying from the switch queue after
the most recent copy is delivered.
[0006] In another aspect of the invention, the home mark is used in
a watermark check to guarantee that the packet at the head of the
queue is not overwritten before the required number of copies has
been made. This inventive aspect is achieved by using the
differential between the write address and the home mark (rather
than the current read address) as the benchmark of current queue
fullness in a watermark check wherein the decision is made whether
to grant queuing clearance to the next inbound data. By relying on
the write address/home mark differential (rather than the write
address/read address differential) in the watermark check, the
addresses in which the packet at the head of the queue are stored
are placed off-limits to the next inbound packet until it is
certain that additional copying of the packet at the head of the
queue will not be required.
[0007] In a preferred embodiment of the invention, the hardware
copy assist is implemented with minimal switching overhead by
making copying decisions incidental to the retrieval of outbound
headers. Outbound headers are preferably retrieved by indexing a
header table wherein all outbound headers for the same packet are
stored as a linked list of entries. A check is made of each entry
as the linked list is "walked-down" to determine if there is
another entry in the linked list, as indicated by the presence of a
valid "next entry" index. If there is a valid "next entry" index,
the read address is reset to the home mark after the most recent
copy of the packet is delivered. If there is not a valid "next
entry" index, however, the home mark is advanced to the read
address after the most recent copy of the packet is delivered.
[0008] These and other aspects of the present invention may be
better understood by reference to the following detailed
description taken in conjunction with the accompanying drawings
which are briefly described below. Of course, the actual scope of
the invention is defined by the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1 is a block diagram of a data communication switching
architecture in which the present invention may be implemented;
[0010] FIG. 2 is a more detailed block diagram of the queue control
unit of FIG. 1 including its interfaces to the ingress queue,
switch queue and header table;
[0011] FIG. 3 is a flow diagram describing a read policing
methodology performed by the queue control unit of FIG. 1;
[0012] FIG. 4 is a flow diagram describing a write policing
methodology performed by the queue control unit of FIG. 1;
[0013] FIG. 5 is a diagram illustrating the processing of an
exemplary packet within the switching architecture of FIG. 1;
and
[0014] FIGS. 6A and 6B are diagrams illustrating how a watermark
check within the switching architecture of FIG. 1 is operative to
prevent a premature overwrite of an exemplary packet.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0015] In FIG. 1, a switching architecture in which the present
invention may be implemented is shown. In the basic switching
operation, inbound packets arrive at ingress queue 100, are
formatted for the "next hop" by prepending appropriate outbound
headers, and are delivered as outbound packets to egress queue 150.
More particularly, identifiers in the headers of inbound packets
are transmitted to switching logic 120 for a switching decision. If
forwarding is indicated, switching logic 120 transmits the
appropriate forwarding index to header table 130 to retrieve
information for encoding in outbound headers for the packet. In
this regard, linked lists of entries are constructed in header
table 130 for forwarding multicast packets to an appropriate array
of destinations. In addition to storing information for encoding in
a particular outbound header, therefore, each entry may include a
valid "next entry" index which identifies the index of another
table entry having information for encoding in another outbound
header for the same packet. Packet assembly 140 receives outbound
headers from header queue 170 and combines outbound headers and
copies of packet data separately-received from switch queue 110 "on
the fly" into outbound packets which may be transferred on egress
queue 150 to the appropriate "next hops". One possible
configuration of such an "on the fly" packet assembly is described
in application Ser. No. 09/097,898 entitled PACKET ASSEMBLY
HARDWARE FOR DATA COMMUNICAITON SWITCH, owned by the assignee
hereof. Identifiers transmitted to switching logic 120 for a
switching decision may include Open System Interconnection (OSI)
Layer Two (Bridging), Layer Three (Network) and Layer Four
(Transport) addresses and identifiers, by way of example. Switching
logic 120 may make the switching decision by performing associative
comparisons of such identifiers with known identifiers stored in a
memory within switching logic 120. Such a memory may be a content
addressable memory (CAM) or may be a random access memory (RAM).
One possible RAM-based implementation of switching logic 120 is
described in application Ser. No. 08/964,597 entitled CUSTOM
CIRCUITRY FOR ADAPTIVE HARDWARE ROUTING ENGINE, owned by the
assignee hereof.
[0016] Data in inbound packets which will be included in any
counterpart outbound packet are retained in switch queue 110
pending the results of switching decisions. Data in inbound packets
which will not be included in any counterpart outbound packet may
also be stored in switch queue 110 and "skipped" upon reading the
packet from switch queue 110 to packet assembly 140. Alternatively,
such packet data may be dropped at ingress queue 100. For
simplicity, however, the data for a particular packet which are
retained in switch queue 110 will be referred to herein as a
"packet" whether the entire or only selected portions of the
inbound packet are actually retained. Queue control unit 160
manipulates the switch queue read address, in a manner hereinafter
described, to ensure delivery the number of copies of each packet
required to meet multicasting needs is delivered to packet assembly
140. Unit 160 also regulates access to switch queue 110 to prevent
packets from being overwritten before the required number of copies
is delivered. Packets are preferably transferred in and out of
switch queue 110 on a bus which, when active, transfers a
constant-bit "width" of data on each clock cycle. Each packet may
span one or more widths. In addition to having bits of packet data,
a "width" may include control bits sufficient to convey if the
width is the first or last width of a packet.
[0017] Referring now to FIG. 2, queue control unit 160 is
illustrated in greater detail. In a preferred embodiment, unit 160
includes queue flow control logic 210, write address counter 220,
read address counter 230 and home mark register 240. Logic 210
polices data flows in and out of switch queue 110 to ensure that
the appropriate number of copies of each packet are delivered to
packet assembly 140 and that packets are not prematurely
overwritten. To this end, logic 160 has a line on header queue 170
for receiving the current "next entry" index for the packet at the
head of switch queue 110 from an entry retrieved from header table
130. Write address counter 220 holds the current write address for
switch queue 110 and is incremented with each new width of data
received from ingress queue 100. Read address counter 230 holds the
current read address for switch queue 110. The value stored in read
counter is incremented with each new width of data transmitted to
packet assembly 140 and is reset under certain circumstances
hereinafter explained. Home mark register 240 retains the address
of the first width of the packet at the head of switch queue 110,
hereinafter referred to as the home mark. The value stored in home
mark register is advanced under certain circumstances hereinafter
explained.
[0018] The read policing methodology implemented with the
assistance of logic 210 is described with greater particularity in
the flow diagram of FIG. 3. When a packet is pending in switch
queue 110 (Step 310), read address counter 220 is consulted for the
current read address and the first width of the packet at the head
of the queue is read from switch queue 110 to packet assembly 140
(Step 320). Read address counter 220 is incremented (Step 330) and
the control bits associated with the width just read are consulted
to determine if the width is the last width of the packet (Step
340). If the width is not the last width, Step 320 is repeated. If
the width is the last width, however, a check is made to determine
if the packet must be retained for additional copying (Step 350).
In this regard, queue flow control logic 160 reviews the current
"next entry" index for the packet retrieved from header queue 170.
If the "next entry" index is valid, it is known that the packet
will have to be retained for additional copying to meet
multicasting needs and the multicast flag is set. Otherwise, if the
entry does not have a valid "next entry" index, it is known that
additional copies of the packet are not required and the multicast
flag is not set. If the multicast flag is set, the read address is
reset to the home mark (i.e., the first address of the current
packet) by updating read address counter 230, and Step 320 is
repeated. If the multicast flag is not set, however, the home mark
is advanced to the read address (Step 370) (i.e., the first address
of the next pending packet, if any) by updating home mark register
240, and the algorithm is exited. It will be appreciated that
through the above policing scheme, copies of packets are delivered
to packet assembly 140 in the number required to meet multicasting
needs without the need for software intervention. Moreover,
reliance on the dual purpose "next entry" index in header table 130
as the determinant of the need for additional copying allows this
advantageous result to be achieved with minimal additional
overhead.
[0019] Write policing is done to avoid overwriting the packet at
the head of switch queue 110 prematurely. In this regard, because
it is not known at the time decisions whether to write into switch
queue 10 must be made whether the packet at the head of switch
queue 110 will have to be retained for additional copying, the home
mark rather than the read address is advantageously used in the
queue fullness calculation. The preferred write policing
methodology implemented with the assistance of logic 210 is
described in FIG. 4. When a width of an inbound packet is pending
in ingress queue 100 (Step 410), a watermark check is performed
before releasing the width to switch queue 110. In the watermark
check, the difference between the write address and the home mark
(a measure of queue fullness) is compared against a configured
watermark (Step 420). If the differential is less than the
watermark, it is known there is ample room in switch queue 110 to
receive the inbound width without overwriting the packet at the
head of the switch queue 110. Therefore, the inbound width is
written to switch queue 110 (Step 430). If, on the other hand, the
differential is not less than the watermark, it is known that there
may not be ample room in switch queue 110 to receive the inbound
width without risking a premature overwrite of the packet at the
head of switch queue 110. Therefore, logic 210 asserts stall line
212 and the inbound width is not delivered to switch queue 110.
Watermark checks are performed regularly to reveal changes in the
available status of switch queue 110 resulting from advances in the
home mark. The lower limit on the configured value of the watermark
is defined by the maximum allowable packet size in the switching
architecture, such that a packet of any size may be queued in its
entirety under a condition of maximum available capacity (i.e.,
when switch queue 110 is empty). The upper limit on the configured
value of the watermark is defined by the capacity of switch queue
110.
[0020] Processing of an exemplary packet A at the head of switch
queue 110 is illustrated in FIG. 5, which may be read in
conjunction with FIG. 1. Identifiers from the exemplary packet are
sent to switching logic 120 for a switching decision. Switching
logic 120 returns forwarding index A1. Header table 130 is
consulted at index A1 and reveals header data A1' for encoding in
an outbound header. Header A1" is constructed in header queue 170
and header A1" is delivered to packet assembly 140. Separately,
packet A has advanced to the head of switch queue 110 where the
home mark is set to the first-written address for packet A. Packet
A is delivered to packet assembly 140 in a series of widths by
incrementing the read address. In packet assembly 140, header A1"
is prepended to packet A to form an outbound packet for transfer to
egress queue 150. Because "next entry" field in the entry retrieved
from index Al has a valid "next entry" index A2, it is known that
packet A must be retained for additional copying. Therefore, the
multicast flag is set and the read address is reset to the home
mark. "Next entry" index A2 is looked-up in header table 130 and
reveals header data A2' for encoding in another outbound header for
prepending to packet data A. Header A2" is constructed in header
queue 170 and header A2" is delivered to packet assembly 140.
Separately, another copy of packet data A is delivered to packet
assembly 140 using the read address to deliver successive widths of
packet A. In packet assembly 140, header A2" is prepended to packet
A to form another outbound packet for transfer to egress queue 150.
Because "next entry" field in the entry retrieved from index A2
does not have a valid "next entry" index, it is known that packet A
no longer needs to be retained for additional copying. Therefore,
the multicast flag is not set and the home mark is advanced to the
read address. Processing then begins on packet B in similar
fashion.
[0021] Finally, FIGS. 6A and 6B illustrate how the preferred
watermark check operates to prevent premature overwrite of an
exemplary packet A at the head of an exemplary switch queue 610.
First, consider FIG. 6A, wherein packet A and a width of data from
packet B are pending in switch queue 610 and a copy of packet A at
the head of the queue is in the process of being delivered to
packet assembly 140. A watermark check must be passed before
additional widths of packet B (pending in ingress queue 100) may be
delivered to switch queue 610. As illustrated in FIG. 6A, in the
watermark check, the differential between the write address and the
home mark is equal to the watermark and the watermark check is
failed. (Note that if the differential between the write address
and the read address were used as the basis for comparison, the
watermark check would be passed and packet A would be subject to a
risk of premature overwrite). The additional width is therefore not
queued. Subsequently, referring to FIG. 6B, once it is known that
no additional copies of packet A will have to be made, the home
mark is advanced to the first-written width of packet B and the
watermark check is again performed. This time, the differential
between the write address and the home mark is less than the
watermark and the watermark check is passed. The additional width
is therefore written in switch queue 610.
[0022] It will be appreciated by those of ordinary skill in the art
that the invention can be embodied in other specific forms without
departing from the spirit or essential character hereof. The
present invention is therefore considered in all respects
illustrative and not restrictive. The scope of the invention is
indicated by the appended claims, and all changes that come within
the meaning and range of equivalents thereof are intended to be
embraced therein.
* * * * *