U.S. patent application number 09/682536 was filed with the patent office on 2003-04-03 for integrated test structure and method for verification of microelectronic devices.
Invention is credited to Bulaga, Raymond J., Masi, John K., Miller, Patrick W., Styduhar, Mark S., Wheater, Donald L..
Application Number | 20030063019 09/682536 |
Document ID | / |
Family ID | 24740125 |
Filed Date | 2003-04-03 |
United States Patent
Application |
20030063019 |
Kind Code |
A1 |
Bulaga, Raymond J. ; et
al. |
April 3, 2003 |
INTEGRATED TEST STRUCTURE AND METHOD FOR VERIFICATION OF
MICROELECTRONIC DEVICES
Abstract
An integrated test structure adapted to facilitate manufacturing
verification of microelectronic devices such as Digital to Analog
Converters (DAC) is disclosed. The test circuitry and the Circuit
Under Test (CUT) are placed on an IC along with an arbitrary amount
of digital logic, which drives the input of the CUT. These inputs
are translated into an analog output. During a manufacturing test,
this output is measured in order to determine that the IC has been
manufactured correctly. The analog input of the circuit is coupled
to the analog output of the DAC. The digital output of the test
circuitry is coupled to the digital logic on the IC. This
configuration comprises a Built In Self Test (BIST) structure. The
invention allows BIST by eliminating the need to measure the analog
output of the DAC external to the IC, and enables testing the CUT
by using standard digital BIST techniques.
Inventors: |
Bulaga, Raymond J.;
(Richmond, VT) ; Masi, John K.; (Milton, VT)
; Miller, Patrick W.; (Winooski, VT) ; Styduhar,
Mark S.; (Hinesburg, VT) ; Wheater, Donald L.;
(Hinesburg, VT) |
Correspondence
Address: |
Jack P. Friedman
SCHMEISER, OLSEN & WATTS L L P
3 Lear Jet Lane
Suite 201
Latham
NY
12110
US
|
Family ID: |
24740125 |
Appl. No.: |
09/682536 |
Filed: |
September 17, 2001 |
Current U.S.
Class: |
341/120 |
Current CPC
Class: |
H03M 1/66 20130101; H03M
1/108 20130101 |
Class at
Publication: |
341/120 |
International
Class: |
H03M 001/10 |
Claims
What is claimed is:
1. A test structure adapted to test a microelectronic device, said
test structure comprising: (1) a structure for holding a voltage;
(2) at least one structure for offsetting said voltage; (3) at
least one structure for comparing said voltage to another voltage;
(4) a clocking structure coupled to said test structure; and (5) a
logic structure coupled to said test structure.
2. A test structure adapted to test a microelectronic device, said
test structure comprising: a sample and hold circuit, a sample and
hold clock, a first comparator with a first fixed internal offset
and at least a first input coupled to an output of said
microelectronic device, and a second comparator with a second fixed
internal offset and at least a second input coupled to said output
of said microelectronic device, said first fixed internal offset
different from said second fixed internal offset, said test
structure generating real time pass/fail results.
3. The test structure of claim 2 wherein said test structure is
located on an integrated circuit containing said microelectronic
device.
4. The test structure of claim 2 further comprising at least a
third comparator having a third fixed internal offset and at least
a third input, said third input coupled to said output of said
microelectronic device.
5. A test structure for testing a microelectronic device, said test
structure comprising: (1) a first test structure input; (2) a first
comparator having a first plus (+) input, a first minus (-) input,
a first internal offset and a first digital output, said first plus
(+) input coupled to an output of a sample and hold circuit, said
sample and hold circuit coupled to said first test structure input,
said first minus (-) input coupled to said first test structure
input; and (3) a second comparator having a second plus (+) input,
a second minus (-) input, a second internal offset and a second
digital output, said second minus (-) input coupled to said output
of said sample and hold circuit, said sample and hold circuit
coupled to said first test structure input, said second plus (+)
input coupled to said first test structure input.
6. The test structure of claim 5 wherein said first comparator is
configured to return a first reading at said first digital output,
and wherein said second comparator is configured to return a second
reading at said second digital output, said first and second
readings representative of the performance of said microelectronic
device
7. The test structure of claim 5 wherein said test structure is
located on an integrated circuit containing said microelectronic
device.
8. The test structure of claim 7 wherein said integrated circuit
contains digital logic, said test structure coupled between a
digital to analog converter and said digital logic on said
integrated circuit.
9. The test structure of claim 5 wherein said sample and hold
circuit is level sensitive configured to sample when a sample and
hold clock is in an active state and to hold when said sample and
hold clock is not in an active state.
10. The test structure of claim 5 further comprising at least one
analog reference coupled to at least one of said first and second
comparators.
11. The test structure of claim 10 wherein said analog reference
comprises a switch coupled to said output of said sample and hold
circuit, said switch capable of disengaging said sample and hold
circuit.
12. The test structure of claim 10 wherein said at least one analog
reference comprises a first analog reference coupled to said first
comparator and a second analog reference coupled to said second
comparator.
13. The test structure of claim 5 further comprising at least one
switch coupled to at least one of said first and second
comparators, said switch allowing said test structure to test
linearly increasing or linearly decreasing analog functions.
14. The test structure of claim 13 wherein said at least one switch
comprises a first switch and a second switch, said first and second
switches coupled to said sample and hold circuit and said first and
second comparators.
15. The test structure of claim 5 further comprising at least a
third comparator having a third fixed internal offset and at least
a third input, said third input coupled to said output of said
sample and hold circuit.
16. The test structure of claim 5, wherein said test structure is
located on an integrated circuit containing said microelectronic
device, wherein said sample and hold circuit is a level-sensitive
sample and hold circuit, and wherein said first comparator is
configured to return a first reading at said first digital output,
and wherein said second comparator is configured to return a second
reading at said second digital output, said first and second
readings representative of the performance of said microelectronic
device.
17. The test structure of claim 16 further comprising at least a
third comparator having a third fixed internal offset and at least
a third input, said third input coupled to said output of said
sample and hold circuit.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Technical Field
[0002] This invention generally relates to the testing of digital
to analog converters, and more specifically relates to a test
structure and method for testing digital to analog converters using
on-chip components.
[0003] 2. Background Art
[0004] A digital to analog converter, or DAC, is used wherever it
is necessary to covert a digitally processed signal to a continuous
output signal. As is clear from its name, a DAC accepts an input in
digital form and converts it to the analog signal seen at its
output. During the manufacturing process a DAC is tested in various
ways to ensure that its performance meets acceptable standards. The
particular tests applied to a DAC are determined according to its
target application and manufacturing cost considerations. Generally
speaking, DACs targeted for higher performance applications can
tolerate a higher manufacturing cost, and thus a more extensive
testing process, because they have a higher selling price. Market
pressures, however, are driving costs downward while elevating
performance expectations, thus increasing the need for efficient
and inexpensive testing methods.
[0005] There are two basic categories of DAC tests, namely static,
or direct current (DC) tests, and dynamic, or alternating current
(AC) tests. Dynamic testing requires specialized equipment and is
usually reserved for high performance DACs. Static testing, on the
other hand, can usually be accomplished without specialized tester
resources and can be done instead using a tester resource known as
a parametric measurement unit (PMU) that is available on virtually
any manufacturing test system. Pursuant to testing accuracy, one of
the tested parameters mentioned above, a DAC's offset, gain, and
linearity will conventionally be tested.
[0006] Offset is measured by conditioning the digital input of the
DAC with a signal, such as an input code, intended to result in a
minimum analog output voltage. The word code herein also includes a
signal of any kind that may be input to a device. A tester PMU is
then used to measure the analog output which is then compared, via
the test program software, to a predefined pass/fail limit,
sometimes referred to as the zero code. The parameter measured by
the test program software is sometimes referred to as zero code
error (ZCE). Gain is measured in a similar manner. The digital
input is conditioned with a signal, such as a code, intended to
result in a maximum analog output voltage. The PMU is used to
measure the actual analog output. The test program then processes
the result to obtain the gain.
[0007] Linearity tests are based on the assumption that each DAC
input code results in a unique analog output. The conversion
function is such that increasing values of input code result in
linearly increasing values of output code. Although not every DAC
design fits this pattern, the vast majority manufactured today do
fall into this category. The most frequently applied linearity
tests are for differential non-linearity (DNL) and integral
non-linearity (INL).
[0008] DNL can be understood as the difference between the ideal
and the actual analog step size between successive binary input
codes. For example, if a binary input code of 01 ideally results in
an analog output of 1.0 and a binary input code of 10 ideally
results in an analog output code of 2.0, then the ideal step size
is 1.0 (i.e., 2.0-1.0). The DNL test at this code consists of
measuring the actual analog outputs resulting from these two binary
input codes and subtracting them. Ideally, the difference should be
1.0. If the difference is 1.2, then the DNL error is 0.2. In
practice, this value is compared to a predefined pass/fail limit by
the test program software.
[0009] INL can be understood as the worst case deviation from a
linear response. This parameter is evaluated across all of the
possible digital input to analog output combinations. There are a
number of ways to test this in manufacturing. The data acquisition
method is conventionally the same as that used for DNL. The main
difference between the two is the calculations made by the test
program after the data are collected. In real world practice, DNL
and INL calculations are often based on a subset of all possible
conversion values, to save manufacturing costs.
[0010] A current methodology for performing the various DAC tests
described above is based on the design of a Video DAC (VDAC) core,
which allows placing the circuit into a special test mode where the
VDAC generates its own digital input pattern. This pattern is
incremented by a digital clock supplied by the test system. The
measurement technique is the same as described above. The analog
outputs of the VDAC are measured using the tester PMU.
[0011] A VDAC is constructed as a bank of current switches. In
operation, the output current is derived by summing a number of
individual current sources into a single output node. The
individual current sources are designed to have different output
values. The actual values are multiples of something known as the
Least Significant Bit (LSB). This is the finest resolution the
converter can achieve. The current sources have values of 1, 2, 4,
and 8 LSBs. The actual value of current supplied by each current
source is determined by a reference current generator built into
the VDAC core design. The reference current is defined by the value
of a resistor that is separate from the IC containing the VDAC.
This resistor doesn't exist in the standard IC test environment. To
alleviate the need for custom test interface hardware that includes
the resistor, the VDAC is designed to contain an internal resistor
that is used only during testing to supply the required current
source reference during manufacturing test. This resistor is
sensitive to manufacturing process variations.
[0012] The test procedure described above accomplishes
manufacturing test goals by verifying that all of the VDAC current
sources are operational, dynamically accounting for process
variations in the "test only" reference resistor. The test also
verifies DC gain and offset accuracy, and provides an effective
screen against non-linearities associated with manufacturing
process defects.
[0013] The current testing methodology described in the foregoing
paragraphs requires a separate tester resource such as a PMU to
make the needed measurements. This requirement leads to several
drawbacks in and complications of the testing process. The most
obvious of these may be the fact that a tester resource embodied in
a separate piece of equipment must first be located and then
physically brought to the test site and coupled to the device being
tested. Further, testing with an external resource is relatively
slow and inefficient, and limits the types of tests that may be
performed.
SUMMARY OF THE INVENTION
[0014] Therefore, there existed a need to provide a DAC
manufacturing test resource that overcomes the problems of the
current solutions by increasing the speed and accuracy with which a
manufacturing test may be performed, increasing the available types
of tests that may be run, and providing access to internal nodes
that are not accessible to an external tester resource. According
to the present invention, a DAC is part of an integrated circuit
(IC) that includes digital logic. The digital logic includes the
combinational and sequential control required to facilitate Built
In Self Test (BIST) of the type previously employed in other
solutions. The digital logic is presumed to drive the input of the
DAC, which consists of a number of digital signals. These inputs
are translated, as a function of the DAC design, into an analog
output. During manufacturing test, this analog output is measured
in order to determine that the IC has been manufactured
correctly.
[0015] The circuitry of the present invention is connected between
the DAC output and the digital logic on the IC. The analog input of
the test circuitry is coupled to the analog output of the DAC. The
two digital outputs of the test circuitry are coupled to the
digital logic on the IC. This configuration comprises a BIST
structure. The invention allows a BIST by eliminating the need to
measure the analog output of the DAC external to the IC.
[0016] The circuit of the present invention is connected between
the DAC and the digital logic on an IC, and may comprise a sample
and hold (S/H) circuit, a sample and hold (S/H) clock, a latch
clock, and two comparators with differing internal offsets, with
the offsets selected based primarily on the DNL specification for
the DAC. In one embodiment of the invention, the offsets are
different multiples of the difference between a predicted output
voltage of the DAC at a first time T1 and at a second time T2. The
predicted output signals or voltages may differ from the actual
output voltages produced when an input of the DAC is stimulated
with a code intended to produce the predicted output voltage. The
words signal, voltage, and code are used interchangeably
herein.
[0017] In one embodiment of the invention, the testing method
comprises the steps of: (1) sampling and holding a first actual
output signal or voltage of the microelectronic device being
tested, where the first actual output signal is representative of
an output of said microelectronic device at a first time T1; (2)
stimulating the device being tested causing the actual output
signal or voltage of the microelectronic device to be updated to a
second actual output signal representative of an output of said
microelectronic device at a second time T2; (3) comparing the first
and second output signals; and (4) returning a status signal
indicative of the performance of the microelectronic device.
[0018] In a particular embodiment of the invention, a manufacturing
test is performed by running a series of test cycles wherein each
test cycle includes the following steps: The number of test cycles
included in a test is arbitrary, and may vary from one
manufacturing test to another. The first step in each test cycle
conventionally involves stimulating the inputs of a DAC with a code
intended to produce a predicted output signal. The DAC actual
output signal is then sent to the comparators described herein,
which compare the first actual output signal with the second actual
output signal. The comparators contain a fixed internal offset, as
will be further described in connection with FIG. 4, and return a
signal indicative of the performance of the DAC. The digital
outputs of the comparators are sampled using standard digital
latches.
[0019] Because the circuit of the present invention is entirely
contained on the IC, there is no need for a PMU or any other tester
resource to make the measurements. This allows the test to run
significantly faster, reducing manufacturing test costs. Faster
testing also allows testing more codes, which may improve test
quality, and provides intrinsic AC test coverage: if the DAC
doesn't respond fast enough then it will fail the test. The on-chip
location of the present invention further provides access to
internal IC nodes that are not available at the IO pins. In
addition, both low and high limits are set simultaneously rather
than separately as in some previous solutions, thus saving time and
expense. Front End Hardware (FEH) noise issues are also minimized
or eliminated.
[0020] The foregoing and other features and advantages of the
invention will be apparent from the following more particular
description of specific embodiments of the invention, as
illustrated in the accompanying drawings.
BRIEF DESCRIPTION OF THE OF THE DRAWINGS
[0021] Specific embodiments of the present invention will
hereinafter be described in conjunction with the appended drawings,
where like designations denote like elements:
[0022] FIG. 1 is a block diagram of an integrated circuit
configured according to one or more embodiments of the present
invention;
[0023] FIG. 2 is a block diagram of an embodiment of the present
invention;
[0024] FIG. 3 is a symbolic representation of comparators
configured according to an embodiment of the present invention;
[0025] FIG. 4 is a graph plotting DAC output versus input code for
a correctly-functioning DAC;
[0026] FIG. 5 is a table listing comparator output values
corresponding to the FIG. 4 graph;
[0027] FIG. 6 is a graph plotting DAC output versus input code for
a malfunctioning converter;
[0028] FIG. 7 is a table listing comparator values corresponding to
the graph in FIG. 6;
[0029] FIG. 8 is a graph illustrating simulated waveforms
representative of positive gain error;
[0030] FIG. 9 is a graph illustrating simulated waveforms
representative of negative gain error;
[0031] FIG. 10 is a view of an embodiment of the present invention
adapted to detect negative gain errors;
[0032] FIG. 11 is a graph illustrating simulated waveforms
representative of a potential INL response of a DAC; and
[0033] FIG. 12 is a view of an embodiment of the invention
comprising a circuit adapted to test a linearly increasing or
decreasing analog function.
MODES FOR CARRYING OUT THE INVENTION
[0034] The present invention is an integrated test structure
adapted to facilitate and speed manufacturing verification of
microelectronic devices containing analog or mixed signal
circuitry, such as a DAC. According to an embodiment of the present
invention, test circuitry and a DAC are placed on an integrated
circuit along with digital logic, which is presumed to drive the
input of the DAC. The digital logic includes the combinational and
sequential control required to facilitate Built In Self Test (BIST)
of the type previously employed in other solutions. These inputs
are translated, as a function of the DAC design, into an analog
output. During manufacturing test, this analog output is measured
in order to determine that the IC has been manufactured correctly.
The analog input of the test circuitry is coupled to the analog
output of the DAC. The digital output of the test circuitry is
coupled to the digital logic on the IC. This configuration
comprises a BIST structure. The invention allows a BIST by
eliminating the need to measure the analog output of the DAC
external to the IC.
[0035] Referring now to the figures, and in particular to FIGS. 1
and 2, an integrated test structure 10 is located on an integrated
circuit (IC) 12. Integrated circuit 12 also comprises a Digital to
Analog Converter (DAC) 14 and digital logic 16. Integrated test
structure 10 comprises a sample and hold circuit 18, a sample and
hold clock 19, a first comparator 20, and a second comparator 22,
each with fixed internal offsets. In one embodiment of the
invention, a third comparator, not shown, with fixed internal
offset may be included to enable increased resolution of the
measurements. Additional comparators beyond three may also be
included to further increase the resolution of the measurements.
Test structure 10 further includes an analog input 24, a first
digital output 26, and a second digital output 28. A latch clock 30
of test structure 10 may connect with at least one sequential
storage element 32. Digital input 34 of DAC 14 is in one embodiment
of the invention driven by digital logic 16 on IC 12.
[0036] Digital logic 16 includes the combinational and sequential
control required to facilitate Built In Self Test (BIST) of a type
well known in the art. A conventional DAC has a number of digital
inputs 34, which DAC 14 converts into an analog output. This output
is analog input 24: the analog value output by DAC 14 may be input
into test structure 10, where it is analyzed as described
herein.
[0037] First and second digital outputs 26 and 28 are coupled to
digital logic 16 on IC 12. This configuration comprises a BIST
structure. Test structure 10 allows BIST by eliminating the need to
measure analog input 24 external to IC 12. This improves the
manufacturing testing of DAC 14 in a variety of ways, including
increased accuracy and speed, as will be described below.
[0038] The manner in which sample and hold clock 19, latch clock
30, and digital inputs 34 to DAC 14 are generated is well known,
and one of ordinary skill in the art will be aware of a number of
techniques for doing so, any one of which may be used in
conjunction with the present invention. In one embodiment of the
present invention, these events may occur sequentially in the
following order: DAC 14 update; latch clock 30; and sample and hold
clock 19.
[0039] In one embodiment of the invention, the testing method
comprises the following steps. A first output signal of DAC 14, or
other microelectronic device being tested, is sampled and held.
This may be accomplished by sample and hold circuit 18, or by any
other device or method suitable for storing an analog signal on a
microelectronic device. The first actual output signal is sampled
at analog input 24, and is representative of an output of DAC 14 at
a first time T1. A second actual output signal of DAC 14 is then
generated, also at analog input 24, representative of an output of
DAC 14 at a second time T2. The first and second output signals are
compared to see if they fall within a pre-determined range, as
dictated by the internal offset of the comparators. Finally, test
structure 10 returns at digital outputs 26 and 28 a status signal
indicative of the performance of DAC 14.
[0040] More specifically, digital outputs 26 and 28 may return a
zero or pass reading if the first and second output signals fall
within a pre-determined range of each other. Said another way,
digital outputs 26 and 28 may return a zero or pass reading if the
actual output signals are within a pre-determined amount of the
predicted output signals. Furthermore, digital outputs 26 and 28
represent the relationship of analog input 24 sampled and held at
time T1 to the updated analog input 24 at time T2.
[0041] In a particular embodiment of test structure 10, a
manufacturing test is performed by running a series of test cycles
wherein each test cycle includes the steps described below. The
number of test cycles included in a test is arbitrary, and may vary
from one manufacturing test to another. The first step in each test
cycle conventionally involves stimulating inputs 34 of DAC 14 with
a code intended to produce a predicted output voltage. The actual
output voltage of DAC 14 is then sent to comparators 20 and 22,
which compare the first actual output voltage of DAC 14 with the
second actual output voltage of DAC 14. Comparators 20 and 22 have
built in offsets at the plus (+) and minus (-) inputs,
respectively, as will be further described below, and output a
voltage at digital outputs 26 and 28 indicative of the performance
of DAC 14. Digital outputs 26 and 28 of comparators 20 and 22 are
sampled using standard digital latches 32.
[0042] Sample and hold circuit 18 may be level sensitive. In other
words, sample and hold circuit 18 "samples" when sample and hold
clock 19 is active; at other times, it "holds." During sampling,
the analog value on the input 24 of sample and hold circuit 18 is
passed to an output 36 of sample and hold circuit 18. During
holding, output 36 of sample and hold circuit 18 remains equal to
the last previously sampled analog input 24.
[0043] Comparators 20 and 22, in at least one embodiment, are not
latched, and may be constructed with offsets, as follows. First
comparator 20 may be constructed so that a first plus (+) input 38
has an internal offset 0.5 times the value of the step size being
detected. This multiplier is based on the desired test performance,
primarily the DNL specification for DAC 14. First comparator 20
also has a first minus (-) input 40. The offsets of comparators 20
and 22 are added to the values detected at the appropriate inputs
of the comparators. Thus, for example, if the step size is one, and
the value at input 38 of first comparator 20, the 0.5 offset
results in a value at input 38 of 1.5.
[0044] Referring now to FIG. 3, the operation of comparators,
including comparators with an internal offset, will be further
explained. Specifically, the operation of the comparators,
including the concept of an internally applied offset voltage, will
be described in mathematical terms. For each of the three
comparators shown, V1 is the signal connected to the plus (+)
input, and V2 is the signal connected to the minus (-) input. Av is
the voltage gain of the comparator circuit. Vout is the output
signal of the comparator. Comparator 21 represents a comparator
with no internal offset. The voltage transfer function is
Vout=Av(V1-V2). If (V1-V2) is positive, Vout will be a logic 1, or
high. If (V1-V2) is negative, Vout will be a logic 0, or low.
[0045] Comparator 23 is a comparator with an internal offset
voltage at the plus (+) input. First comparator 20 of the present
invention is of this type. Vos is an offset voltage internal to
comparator 23. The voltage transfer function is
Vout=Av[(V1+Vos)-V2]. If [(V1+Vos)-V2] is positive, Vout will be a
logic 1, or high. If [(V1+Vos)-V2] is negative, Vout will be a
logic 0, or low.
[0046] Referring still to FIG. 3, comparator 25 is a comparator
with an internal offset voltage at the minus (-) input, and
corresponds to second comparator 22 of the present invention. Vos
is an offset voltage internal to comparator 25. Here, the voltage
transfer function is Vout=Av[V1-(V2+Vos)]. If [V1-(V2+Vos)] is
positive, Vout will be a logic 1, or high. If [V1-(V2+Vos)] is
negative, Vout will be a logic 0, or low.
[0047] Second comparator 22 may be constructed so that a second
minus (-) input 44 has an internal offset 1.5 times the value of
the step size being detected. The step size in many of the examples
herein will be equal to one, although other step sizes are
certainly possible. As with first comparator 20, this multiplier is
based on the desired test performance, and in particular the DNL
specification for DAC 14. Thus, as will be readily apparent to
those of ordinary skill in the art, fixed offsets of other values
may also be used for both comparators 20 and 22. Second comparator
22 also has a second plus (+) input 42. Digital outputs 26 and 28
of comparators 20 and 22 are sampled via standard digital latches
32. The output of latches 32 are fed back to the BIST logic 16 on
IC 12.
[0048] The actual operation of integrated test structure 10 may be
understood by considering the waveforms at inputs 38, 40, 42, and
44 of comparators 20 and 22, with the comparator internal offsets
included. These waveforms are shown graphically in FIG. 4 and
tabulated in FIG. 5, where column C20-OUT represents the output of
comparator 20 and where column C22-OUT represents the output of
comparator 22. These outputs are interpreted by BIST logic 16 to
determine the pass/fail status of each test.
[0049] In FIG. 4, a line 50 represents the output value of DAC 14.
This value is equal to the value that gets input at analog input
24. A line 52 represents the value detected by first plus (+) input
38 of comparator 20, taking into account the offset applied by
comparator 20, and a line 54 represents the value detected by
second minus (-) input 44 of second comparator 22, taking into
account the offset applied by comparator 22.
[0050] Referring again to FIG. 5, the INPUT column contains
consecutive numerals zero through 15, with a step size between
successive rows equal to one. The data in this column are
equivalent to those depicted by line 50 of FIG. 4, and represent
voltage or other stimulus applied to analog input 24. The column
labeled C20 OFF contains the value detected by first plus (+) input
38 of first comparator 20, including its offset, and is equivalent
to line 52 of FIG. 4. The column labeled C22 OFF is equivalent to
line 54 of FIG. 4, and contains the value detected by the second
minus (-) input 44 of second comparator 22, including the offset.
The C20-OUT and the C22-OUT columns represent, respectively, the
output of comparators 20 and 22. In this example, a zero entry
represents a pass reading for the part being tested, while a
non-zero entry represents a failing reading. A slight variation of
the circuit configuration may result in a non-zero corresponding to
a pass condition. In FIG. 5, the only non-zero entry occurs on the
first row of column C20-OUT. This "failing" reading may be
disregarded since it occurs only because of the zero voltage
applied to analog input 24 during the first test cycle: first minus
(-) input 40 of first comparator 20 is thus artificially depressed
below the value of first plus (+) input 38 for the first test cycle
only. During subsequent test cycles, and assuming a properly
functioning DAC, the magnitudes are reversed as expected.
[0051] The various values detected by test structure 10 will now be
explained using the second row of FIG. 5 as an example. Recall that
these values are representative of a properly functioning DAC. The
INPUT column of the second row contains a one, corresponding to a
stimulus of one volt on analog input 24. Sample and hold circuit 18
contains a value of zero volts because at this stage of the test
cycle it is in the "hold" phase. This zero value from the previous
cycle is read by first plus (+) input 38 of first comparator 20.
When the offset of first comparator 20 is included, the value at
input 38 becomes 0.5 volts, the number in column C20-OFF. The input
voltage of one is meanwhile transferred, according to the circuitry
of structure 10 as shown in FIG. 2, to first minus (-) input 40 of
first comparator 20. The difference across inputs 38 and 40 is thus
-0.5 volts and the C20-OUT column gives a zero reading.
[0052] Similarly, taking the same second row of FIG. 5, the one
volt input gets passed to second plus (+) input 42 of second
comparator 22. The value detected by inverting input 44 has passed
through sample and hold circuit 18 and thus is equal to zero. After
inclusion of the offset, the value becomes 1.5. This value is the
number contained in the C22-OFF column. Here again, the difference
across inputs 42 and 44 of second comparator 22 is (-0.5)" within
the acceptable range assumed by this illustration. The C22-OUT
column thus provides an output of zero, indicating a passing
result.
[0053] During testing, if one of the analog outputs from DAC 14
(corresponding to analog input 24) has more error than allowed by
the offset of comparators 20 and 22, then comparators 20 and 22
will not maintain the expected data output pattern. This is
illustrated by the waveforms and data in FIGS. 6 and 7. Lines 60,
62, and 64 in FIG. 6 represent, respectively, the input value from
analog input 24, the value, offset included, at first plus (+)
input 38, and the value, offset included, at second minus (-) input
44. Note that the input value of 5.4 should really be 6.0. Since
the allowable error programmed into the comparator offsets is
+/-0.5 and this indicates a -0.6 error it is flagged by comparators
20 and 22, as indicated by bars 66 and 68, as a pattern fail. For
manufacturing, this is all that is necessary to screen a bad
part.
[0054] More specifically, two test cycles give rise to the error
indication. The first cycle is represented by the row having the
value 5.4 in the INPUT column. Before running the test, of course,
it is not known that that value is being read at analog input 24.
Test structure 10 detects it as follows, with the general details
being the same as in the discussion accompanying FIG. 5 above. In
particular, as shown in the first of the two test cycles under
discussion, first comparator 20 experiences a spread of +0.1 across
inputs 38 and 40 (5.5 volts on input 38 and 5.4 volts on input 40).
Because this is outside the acceptable error of +/-0.5, first
digital output 26, represented by the C20-OUT column, returns a
non-zero value. In the following row, having a seven in the INPUT
column, second comparator 22 detects a spread of +0.1 across inputs
42 and 44 (7.0 volts on input 42 and 6.9 volts on input 44). As
before, a non-zero reading for second digital output 28,
represented in column C22-OUT, is the result.
[0055] The present invention is well adapted to detect positive
gain errors, as illustrated in FIG. 8, where a line 70 indicates
the input seen at analog input 24, a line 72 represents the value,
offset included, seen at first plus (+) input 38, and a line 74
represents the value, with offset included, seen at second minus
(-) input 44. However, negative gain errors may be missed, as
illustrated in FIG. 9, where lines 80, 82, and 84 correspond to
lines 70, 72, and 74 of FIG. 8.
[0056] This limitation may be overcome by making a single full
scale reading using the tester PMU to verify circuit gain.
Alternately, test structure 10 may be modified to include an analog
reference 90 (see FIG. 10) used to verify full scale. This
reference may be supplied by the tester, or it may be supplied by
an on-chip circuit such as a Band Gap Reference. FIG. 10
illustrates an embodiment of the present invention showing the
modification under discussion. A switch 92 may be controlled by
BIST logic 16. In use, analog reference 90 may provide one or more
test limits based on something other than the previous analog
input. This could be used to solve the gain test problem described
above, by designing the reference voltage to provide a full scale
reference to comparators 20 and 22. The embodiment of FIG. 10 may
also be used to improve the INL response of structure 10. The
waveforms in FIG. 11, where lines 100, 102, and 104 correspond to
lines 70, 72, and 74 of FIG. 8, and a line 106 represents the ideal
response of DAC 14, illustrate the worst case INL that could be
missed using the FIG. 10 embodiment.
[0057] Note that the worst case INL error happens at code 8, in the
FIG. 11 simulated example. To see this, compare the INPUT and Ideal
lines. For this simulation, the magnitude of the error is 2.4 LSB.
Also note that this error is "masked" by the dynamic nature of the
pass/fail limit generation. Testing the INPUT against the analog
reference at input code 8 would provide INL coverage by
guaranteeing the actual signal is within an acceptable margin of
the expected/ideal line. This method could be used at multiple
strategic points in the transfer function to improve INL test
coverage.
[0058] In another embodiment of the present invention, structure 10
may have separate analog references 90 (and switches 92) for
comparator 20 and comparator 22. This would allow using a different
pass/fail margin for full scale and INL checks. Integrated test
structure 10 may in another embodiment be modified to allow testing
a linearly increasing or decreasing analog function by providing
switches 110 as illustrated in FIG. 12.
[0059] The foregoing disclosure has described an integrated test
structure to facilitate and speed manufacturing verification of
microelectronic devices containing analog or mixed signal
circuitry, such as a Digital to Analog Converter (DAC). The test
circuitry and the DAC are placed on an integrated circuit along
with digital logic, which is presumed to drive the input of the
DAC. These inputs are translated, as a function of the DAC design,
into an analog output. During manufacturing test, this analog
output is measured in order to determine that the IC has been
manufactured correctly. The analog input of the circuit is coupled
to the analog output of the DAC. The digital output of the circuit
is coupled to the digital logic on the IC. This configuration
comprises a BIST structure. The invention allows BIST by
eliminating the need to measure the analog output of the DAC
external to the IC.
[0060] While the invention has been particularly shown and
described with reference to specific embodiments thereof, it will
be understood by those skilled in the art that various changes in
form and details may be made therein without departing from the
spirit and scope of the invention. For example, it will be
understood that the circuit and measurement technique described
herein is not limited to DAC testing. It can be used to test
various analog nodes within an IC, with the limitation that during
test, the analog node being tested must change by an equal
magnitude with each successive test cycle.
* * * * *