U.S. patent application number 10/288491 was filed with the patent office on 2003-03-20 for system and method for decoding signal and method of generating lookup table for using in signal decoding.
Invention is credited to Ishii, Daiji.
Application Number | 20030053700 10/288491 |
Document ID | / |
Family ID | 26334447 |
Filed Date | 2003-03-20 |
United States Patent
Application |
20030053700 |
Kind Code |
A1 |
Ishii, Daiji |
March 20, 2003 |
System and method for decoding signal and method of generating
lookup table for using in signal decoding
Abstract
A signal decoding system performs variable length decoding and
inverse quantization at high speed. From a bit stream temporarily
held in a bit string buffer, the bit string is parsed as a table
address for a lookup table in a table looking-up unit and a table
selecting unit. By looking up the table address in the lookup
table, variable length decoding is performed simultaneously for a
maximum of two codewords. Furthermore, the decoded data is
inversely quantized in parallel by using inverse quantizers. The
results of inverse quantization are stored at appropriate positions
in the block by the block storage unit.
Inventors: |
Ishii, Daiji; (Tokyo,
JP) |
Correspondence
Address: |
DICKSTEIN SHAPIRO MORIN & OSHINSKY LLP
1177 AVENUE OF THE AMERICAS (6TH AVENUE)
41 ST FL.
NEW YORK
NY
10036-2714
US
|
Family ID: |
26334447 |
Appl. No.: |
10/288491 |
Filed: |
November 6, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10288491 |
Nov 6, 2002 |
|
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09078251 |
May 13, 1998 |
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Current U.S.
Class: |
382/233 ;
375/E7.14; 375/E7.144; 375/E7.211; 375/E7.213; 375/E7.214;
382/246 |
Current CPC
Class: |
H04N 19/61 20141101;
H04N 19/91 20141101; H04N 19/126 20141101; H04N 19/436
20141101 |
Class at
Publication: |
382/233 ;
382/246 |
International
Class: |
G06K 009/36; G06K
009/46 |
Foreign Application Data
Date |
Code |
Application Number |
May 14, 1997 |
JP |
122738/1997 |
Jan 7, 1998 |
JP |
1256/1998 |
Claims
What is claimed is:
1. A signal decoding system comprising: a decoder which performs a
variable length decoding process simultaneously for multiple
codewords of a variable length code; and inverse quantization means
for inversely quantizing in parallel the multiple decoded codewords
received from said decoder.
2. A signal decoding system as set forth in claim 1, wherein said
decoder comprises a plurality of lookup tables showing
correspondence between codeword data and decoded data, and table
lookup means for selectively looking-up data in said lookup
tables.
3. A signal decoding system as set forth in claim 2, wherein said
data looked-up in said lookup tables includes run and level data
for each codeword, and said inverse quantization means inversely
quantizes only said level data in parallel.
4. A signal decoding system as set forth in claim 1, wherein said
inverse quantization means includes multiple inverse quantizers for
performing in parallel inverse quantization for decoded data.
5. A signal decoding system as set forth in claim 1, wherein said
variable length code represents a moving picture.
6. A signal decoding system as set forth in claim 1, wherein the
maximum number of codewords in said multiple codewords is two.
7. A signal decoding system as set forth in claim 1, wherein said
decoder performs said variable length decoding process to yield a
set of run and level data for each codeword, and said inverse
quantization means inversely quantizes said level data in
parallel.
8. A signal decoding method comprising the steps of: simultaneously
decoding multiple codewords of a variable length code; and
inversely quantizing in parallel the decoded multiple
codewords.
9. A signal decoding method as set forth in claim 8, wherein said
variable length code represents a moving picture.
10. A signal decoding method as set forth in claim 8, wherein the
maximum number of codewords in said multiple codewords is two.
11. A signal decoding method as set forth in claim 8, wherein the
decoding step is performed using a plurality of lookup tables
showing correspondence between codeword data and decoded data.
12. A signal decoding method as set forth in claim 8, wherein said
step of simultaneously decoding multiple codewords yields a set of
run and level data for each codeword, and said step of inversely
quantizing in parallel is performed only on said level data.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This is a divisional of U.S. patent application Ser. No.
09/078,251, filed on May 13, 1998, entitled SYSTEM AND METHOD FOR
DECODING SIGNAL AND METHOD OF GENERATING LOOKUP TABLE FOR USING IN
SIGNAL DECODING PROCESS.
FIELD OF THE INVENTION
[0002] The present invention relates to a signal decoding system, a
signal decoding method and a generation method of a lookup table
for using in a signal decoding process. More specifically, the
invention; relates to a signal decoding system and a signal
decoding method for performing a block decoding process of DCT
coefficients.
BACKGROUND OF THE INVENTION
[0003] In general, upon encoding a video signal, video compression
standards such as MPEG (Moving Picture Experts Group) (1995,
ISO/IEO13818.2) and so forth have been widely used. In MPEG, a
transform coding and motion compensation are central principles for
compression, in which the transform coding is performed in the
following manner. At first, a region of eight pixels by eight
pixels is referred to as a pixel block. For the pixel block, a
two-dimensional discrete cosine transformation (DCT) is performed
to obtain a DCT coefficient block as a 8 by 8 matrix of DCT
coefficients. Next, each coefficient in the DCT coefficient block
is quantized on the basis of a predetermined quantization step.
Each coefficient in the DCT coefficient block after quantization,
is scanned in a predetermined scanning order for Huffman coding a
set of the number of successive zero coefficients (run) and a
quantized value of the subsequent non-zero coefficient (level).
[0004] On the other hand, on a decoding side, a bit stream thus
coded is decoded in the following manner. At first, from the bit
stream as a sequence of codewords, the code word is parsed. By
performing a variable length decoding for the codeword, the
corresponding set of the run and the level is obtained. Then, at a
position in the block designated by a scanning order and the run, a
inversely quantized value of the level is stored. In the foregoing
block, in the positions where the inversely quantized value is not
stored, a value "zero (0)" is stored.
[0005] Here, inverse quantization is a process for obtaining a DCT
coefficient by performing multiplication of a predetermined
quantization step and an element of a quantization matrix after a
correction of the doubled value of the level, and dividing the
multiplication result by "16" (decimal number). It should be noted
that the inverse quantization is defined by an MPEG standard.
[0006] In the following disclosure, the foregoing series of process
steps will be referred to as a DCT coefficient block decoding. For
the DCT coefficient block decoded as set forth above, an inverse
discrete cosine-transformation is performed to obtain a desired
pixel block.
[0007] Conventionally, each process step in the DCT coefficient
block decoding process is performed for each block. FIG. 34 is a
block diagram showing a construction of the conventional DCT
coefficient block decoding system.
[0008] In FIG. 34, the conventional system includes a
variable-length decoding unit 202 sequentially performing a
variable-length decoding with serially reading a bit stream 201 to
obtain a set of the run and the level in one block, a storage unit
204 storing the level of the value "0" at an appropriate position
in the block on the basis of an obtained set 203 of the run and the
level in one block and outputting a block 205, a inverse quantizing
unit 206 performing inverse quantization for each coefficient in
the block 205 for obtaining a DCT coefficient block 207. The
variable-length decoding unit 202 includes a lookup table taking a
set of the run and the level corresponding to one codeword and the
codeword length as a table element.
[0009] Next, operation will be discussed with reference to FIG. 34.
The bit stream 201 is inputted into the variable-length decoding
unit 202. In the variable length decoding unit 202, a bit string
which has a maximum length of one codeword is parsed from the bit
stream 201, and then, a table element is specified for outputting
the run and the level by using the parsed string as the table
address.
[0010] Furthermore, using the code word length obtained by looking
up the table, the lead of the next codeword is specified among the
bit stream 201. The foregoing operation is repeated until a
codeword "End Of Block (EOB)" which indicates the end of the
non-zero coefficient appears. Thereafter, set 203 of the run and
the level in one block is outputted.
[0011] In the storage unit 204, a DCT coefficient block where all
coefficients have value "0" is preliminarily prepared. In the
position determined by a scanning order and the run in the DCT
coefficient block, the level is stored sequentially. The block 205
storing the levels in one block is inputted into the inverse
quantizing unit 206. In the inverse quantizing unit 206, inverse
quantization is performed with respect to all coefficients in the 8
by 8 matrix to output the DCT coefficient block 207.
[0012] On the other hand, a technique for speeding up
variable-length decoding in the DCT coefficient block decoding has
been disclosed in "Superscalar Huffman Decoder hardware Design"
(SPIE Vol. 2186, Image and Video Compression, pp. 38-47, 1994).
[0013] In the above-identified publication, speeding up of
variable-length decoding is achieved by simultaneously decoding
multiple codewords.
[0014] FIG. 35 is a block diagram showing a construction of another
conventional variable-length decoding system. In FIG. 35, the
conventional system includes a bit string buffer 702 storing a bit
stream 702, a table looking-up unit 704 for variable-length
decoding and a lookup table 707.
[0015] In the bit string buffer 702, the bit stream 701 and an
output 705 of the table looking-up unit 704 are inputted and a
17-bit string 703 whose length is maximum of one codeword is
outputted.
[0016] The lookup table 707 has the table address 706 as the input
and outputs the table element 708 identified by the address. The
lookup table 707 is a table whose elements include the set of the
run and the level and a total codeword length corresponding to
multiple codewords, and is constructed to obtain the sets of the
run and the level and the total codeword length corresponding to
all codewords contained in the 17-bit string 706 by only one lookup
operation.
[0017] The table looking-up unit 704 has a seventeen bit output 703
of the bit string buffer 702 as the input and outputs a bit string
703 as the table address 706. On the other hand, the table
looking-up unit 704 has the table element 708 as the input and
outputs multiple runs 709 and multiple levels 710 contained in the
table element 708. Furthermore, the table looking-up unit 704
outputs a bit string 705 in which decoded codewords are excluded
form the bit string 703.
[0018] Next, the operation of the conventional system set forth
above will be discussed with reference to FIG. 35. At first, the
bit stream 701 is stored in the bit string buffer 702. The bit
string buffer 702 outputs the 17-bit string 703 from the lead of
the bit stream 701 stored therein. The 17-bit string 703 is
outputted as the table address 706 in the table looking-up unit
709. Then, by using the table address 706, the table element 708 in
the lookup table 707 is identified. The obtained table element 708
is outputted as multiple runs 709 and multiple levels 710 from the
table looking-up unit 704. In the table looking-up unit 704,
further by using the total codeword length, the bit string 705 in
which the decoded codewords are excluded from the 17-bit string 703
is returned to the bit string buffer 702. In the bit string buffer
702, the bit string 705 is concatenated with the lead of the stored
bit stream 701.
[0019] As shown in FIG. 34, the conventional DCT coefficient block
decoding unit cannot start decoding the next codeword until the
length of the codeword which is decoded currently is specified.
Therefore, the variable-length decoding inherently becomes
sequential processing per each codeword, so that the processing
speed decreases.
[0020] On the other hand, as shown in FIG. 35, in the DCT
coefficient block decoding, when all codewords contained in the
17-bit string read from the bit stream are decoded simultaneously,
a huge amount of memory is necessary for the lookup table.
Particularly, when the variable-length decoding is implemented as a
software of a microprocessor, decoding performance may be degraded
by cache-miss.
SUMMARY OF INVENTION
[0021] The present invention has been worked out for solving the
drawbacks in the prior art. Therefore, it is an object of the
present invention to provide a signal decoding system, a signal
decoding method and a generation method of a lookup table for a
signal decoding process which can achieve DCT coefficient block
decoding at high speed.
[0022] According to the first aspect of the present invention, a
signal decoding system comprises
[0023] decoding means for simultaneously performing variable length
decoding process for multiple codewords; and
[0024] inverse quantization means for inversely quantizing multiple
results obtained by the decoding means in parallel.
[0025] According to the second aspect of the present invention, a
signal decoding method comprises:
[0026] decoding step of simultaneously performing variable length
decoding process for multiple codewords; and
[0027] inverse quantization step of inversely quantizing multiple
results obtained by the decoding means in parallel.
[0028] According to the third aspect of the present invention, a
method of generating a lookup table to be used in variable length
decoding, comprises the steps of:
[0029] storing, in a corresponding table address, the runs and
levels corresponding to two concatenated code words and the total
length of the concatenated two codewords when the concatenated two
codewords equal a prefix in K bit (K is an integer greater than or
equal to two and less than seventeen) representation of a table
address value;
[0030] storing, in a corresponding table address, the runs and
levels corresponding to the first one of two concatenated codewords
and the length of the same codeword when the concatenated two
codewords do not equal a prefix in K bit representation of a table
address value and when the first one of the two codewords equals a
prefix of the K bit representation; and
[0031] storing, in a corresponding table address, the run and level
corresponding to the first one of the concatenated codewords and
the length of the same codeword when the concatenated two codewords
do not equal a prefix in K bit representation of a table address
value and when the first one of the two codewords equals the prefix
of the K bit representation; and
[0032] storing a dummy data in a table address; when the
concatenated two codewords do not equal a prefix in K bit
representation of a table address value and when the first one of
the two codewords does not equal the prefix of the K bit
representation;
[0033] wherein the steps above are performed for all table
addresses in the lookup table.
[0034] In short, in the present invention, variable length decoding
and inverse quantization for multiple codewords are performed in
parallel. More particularly, variable length decoding of multiple
codewords is performed simultaneously, and inverse quantization of
multiple levels obtained by the decoding means can be performed in
parallel. Thus, by performing variable length decoding and inverse
quantization for multiple codewords simultaneously, variable length
decoding on a one by one basis can be avoided to improve the
processing speed of the DCT coefficient block decoding.
Furthermore, by performing inverse quantization only for the
levels, the speed of the DCT coefficient block decoding process can
be increased in comparison with the conventional system.
[0035] On the other hand, by restricting the number of codewords
decoded simultaneously to be less than or equal to two and using a
lookup table having a small memory capacity, memory cost can be
reduced. In particular, when the variable length decoding is
implemented by software with a microprocessor, decoding performance
can be degraded due to cache miss. In addition, by combining
parallel variable length decoding means and parallel inverse
quantization means, faster DCT coefficient block decoding can be
achieved in comparison with the conventional system. It should be
noted that the inverse quantization means is suitable for software
implementation on microprocessors which have parallel operation
capabilities.
BRIEF DESCRIPTION OF THE DRAWINGS
[0036] The present invention will be understood more fully from the
detailed description given below and from the accompanying drawings
of the preferred embodiment of the present invention, which should
not be taken to be limiting to the invention, but are for
explanation and understanding only.
[0037] In the drawings:
[0038] FIG. 1 is a block diagram showing a construction of one
embodiment of a signal decoding system according to the present
invention;
[0039] FIG. 2 is a block diagram showing an example of a
construction of a bit string buffer in FIG. 1;
[0040] FIG. 3 is a block diagram showing an example of a
construction of a table looking-up unit of FIG. 1;
[0041] FIG. 4 is a block diagram showing an example of a
construction of a table selecting unit in FIG. 1;
[0042] FIG. 5 is a block diagram showing an example of a
construction of a DCT coefficient block storage unit in FIG. 1;
[0043] FIG. 6 is an illustration showing a decoded data and
codeword length corresponding to a codeword whose length is greater
than or equal to two and less than or equal to nine in a Huffman
code table for DCT coefficient in MPEG standard;
[0044] FIG. 7 is an illustration showing a decoded data and
codeword length corresponding to a codeword whose length is eleven
or thirteen in a Huffman code table for DCT coefficient in MPEG
standard;
[0045] FIG. 8 Is an illustration showing a decoded data and
codeword length corresponding to a codeword whose length is
fourteen in a Huffman code table for DCT coefficient in MPEG
standard;
[0046] FIG. 9 is an illustration showing a decoded data and
codeword length corresponding to a codeword whose length is fifteen
in a Huffman code table for DCT coefficient in MPEG standard;
[0047] FIG. 10 is an illustration showing a decoded data and
codeword length corresponding to a codeword whose length is sixteen
in a Huffman code table for CT coefficient in MPEG standard;
[0048] FIG. 11 is an illustration showing a decoded data and
codeword length corresponding to a codeword whose length is
seventeen in a Huffman code table for DCT coefficient in MPEG
standard;
[0049] FIG. 12 is an illustration showing a decoded data, a
codeword length, a bit position matching codeword and a table
address corresponding to two codewords whose total codeword length
is greater than or equal to five and less than or equal to seven,
or the codeword whose length is greater than or equal to two or
less than or equal to five in a lookup table for parallel decoding
in FIG. 1;
[0050] FIG. 13 is an illustration showing a decoded data, a
codeword length, a bit position matching codeword and a table
address corresponding to the codeword whose length is greater than
or equal to six and less than or equal to eight in a lookup table
for parallel decoding in FIG. 1;
[0051] FIG. 14 is an illustration showing a decoded data, a
codeword length, a bit position matching codeword and a table
address corresponding to the codeword whose length is nine or
eleven in a lookup table for parallel decoding in FIG. 1;
[0052] FIG. 15 is an illustration showing a decoded data, a
codeword length, a bit position matching codeword and a table
address corresponding to the codeword whose length is thirteen in a
lookup table for parallel decoding in FIG. 1;
[0053] FIG. 16 is an illustration showing a decoded data, a
codeword length, a bit position matching codeword and a table
address corresponding to the codeword whose length is fourteen in a
lookup table for parallel decoding in FIG. 1;
[0054] FIG. 17 is an illustration showing a decoded data, a
codeword length, a bit position matching codeword and a table
address corresponding to the codeword whose length is fifteen in a
lookup table for parallel decoding in FIG. 1;
[0055] FIG. 18 is an illustration showing a decoded data, a
codeword length, a bit position matching codeword and a table
address corresponding to the codeword whose length is sixteen in a
lookup table for parallel decoding in FIG. 1;
[0056] FIG. 19 is an illustration showing a decoded data, a
codeword length, a bit position matching codeword and a table
address corresponding to the codeword whose length is seventeen in
a lookup table for parallel decoding in FIG. 1;
[0057] FIG. 20 is a block diagram showing a construction in the
case of implementing the signal decoding system of the present
invention by a software;
[0058] FIG. 21 is an illustration showing an arithmetic and logic
unit which a microprocessor premised by the present invention will
have;
[0059] FIG. 22 is a flowchart showing a content of a program in the
case where the signal decoding system based on the present
invention is implemented by software;
[0060] FIG. 23 is a block diagram showing a construction of another
embodiment of the signal decoding system according to the present
invention.
[0061] FIG. 24 is an illustration showing a decoded data, a
codeword length, a bit position matching codeword and a table
address corresponding to two codewords whose total code word length
is greater than or equal to five and less than or equal to eight in
the lookup for parallel decoding in the present invention;
[0062] FIG. 25 is an illustration showing a decoded data, a
codeword length, a bit position matching codeword and a table
address corresponding to two codewords whose total codeword length
is nine in the lookup table for parallel decoding in the present
invention;
[0063] FIG. 26 is an illustration showing a decoded data, a
codeword length, a bit position matching codeword and a table
address corresponding to a codeword whose length is greater than or
equal to two and less than or equal to nine in the lookup table for
parallel decoding in the present invention;
[0064] FIG. 27 is an illustration showing a decoded data, a
codeword length, a bit position matching codeword and a table
address corresponding to a codeword whose length is eleven in the
lookup table for parallel decoding in the present invention;
[0065] FIG. 28 is an illustration showing a decoded data, a
codeword length, a bit position matching codeword and a table
address corresponding to a codeword whose length is thirteen in the
lookup table for parallel decoding in the present invention;
[0066] FIG. 29 is an illustration showing a decoded data, a
codeword length, a bit position matching codeword and a table
address corresponding to a codeword whose length is fourteen in the
lookup table for parallel decoding in the present invention;
[0067] FIG. 30 is an illustration showing a decoded data, a
codeword length, a bit position matching codeword and a table
address corresponding to a codeword whose length is fifteen in the
lookup table for parallel decoding in the present invention;
[0068] FIG. 31 is an illustration showing a decoded data, a
codeword length, a bit position matching codeword and a table
address corresponding to a codeword whose length is sixteen in the
lookup table for parallel decoding in the present invention;
[0069] FIG. 32 is an illustration showing a decoded data, a
codeword length, a bit position matching codeword and a table
address corresponding to a codeword whose length is seventeen in
the lookup table for parallel decoding in the present
invention;
[0070] FIG. 33 is a flowchart showing a generation method of the
lookup table for parallel decoding in FIG. 23;
[0071] FIG. 34 is a block diagram showing a construction and
operation of the conventional signal decoding system; and
[0072] FIG. 35 is a block diagram showing a construction and
operation of another conventional signal decoding system.
DESCRIPTION OF THE PREFERRED EMBODIMENT
[0073] The present invention will be discussed hereinafter in
detail in terms of the preferred embodiment of the present
invention with reference to the accompanying drawings. In the
following description, numerous specific details are set forth in
order to provide a thorough understanding of the present invention.
It will be obvious, however, for those skilled in the art that the
present invention may be practiced without these specific details.
In other instances, well-known structures are not shown in detail
in order to avoid unnecessarily obscuring the present
invention.
[0074] FIG. 1 is a block diagram showing one embodiment of a signal
decoding system according to the present invention, in which a
construction example of an image signal decoding system is
illustrated. In FIG. 1, the shown embodiment of the signal decoding
system includes a bit string buffer 102 for temporarily holding an
input bit stream 101, a table looking-up unit 104 for
variable-length decoding, lookup tables 114 and 115, a table
selecting unit 107 for selecting among these tables, inverse
quantizers 124 and 125 for inversely quantizing the levels obtained
from the reference to one of lookup tables 114, 115, and a DCT
coefficient block storage unit 128 for storing the result of
inverse quantization in a DCT coefficient block.
[0075] In the bit string buffer 102, the bit stream 101 and an
output 105 of the table looking-up unit 104 are inputted and a
17-bit string 103 whose length is a maximum of one codeword length
is outputted.
[0076] The looking-up table 114 is a table whose elements have two
sets of runs and levels corresponding to two codewords and their
total codeword length or a set of run and level corresponding one
codeword and the codeword length. The lookup table 114 has a table
address 112 as the input and outputs a table element 116 identified
by the table address 112.
[0077] Similarly, the lookup table 115 is a table whose elements
have a set of the run and the level corresponding to one code word
and the code word length. The lookup table 115 has a table address
113 as the input and outputs a table element 117 identified by the
table address 113.
[0078] The table looking-up unit 104 outputs a leading bit 103 of
the bit string buffer 102 as a bit string 106. On the other hand, a
table element 119 which is a result of the look-up operation is
inputted into the table looking-up unit 104.
[0079] In addition, the table looking-up unit 104 outputs two runs
120, 123 and two levels 121, 122 contained in the table element
119. Then, the table looking-up unit 104 obtains a bit string 105
in which the codewords used for looking-up the table are excluded
from the bit string 103 by using the codeword length, and returns
the string 105 to the bit string buffer 102.
[0080] The table selecting unit 107 derives an address 108 from the
output 106 of the table looking-up unit 104, and outputs control
signals 109 and 110 for switching switches 111 and 118 to select
one of the lookup tables 114 and 115. The control signals 109 and
110 are set to "0" when the table 114 is to be selected and set to
"1" when the table 115 is to be selected.
[0081] The inverse quantizer 124 has the level 121 as the input and
outputs a result 126 of inverse quantization. Similarly, the
inverse quantizer 125 has the level 122 as the input and outputs a
result 127 of inverse quantization.
[0082] The DCT coefficient block storage unit 128 has two inverse
quantization results 126 and 127 and runs 120 and 123 as the input
and stores the inverse quantization results 126 and 127 in the
block positions designated by the scanning order and two runs 120
and 123.
[0083] Here, referring to FIG. 2, the bit string buffer 102 is
constructed with a buffer 102a temporarily holding a 64-bit string,
a buffer 102b temporarily holding a 17-bit string and a control
portion 102c putting an input 102d from the buffer 102a and an
input 105 from the table looking-up unit 104 into the buffer 102b.
A bit string parsed from the input bit stream is inputted into the
buffer 102a. The bit string 102d whose length is based on the
control signal 102f from the control portion 102c is outputted.
[0084] The 17-bit string 103 is outputted from the bit string
buffer 102b. Thereafter, the bit string 102d and the bit string 105
are inputted into the buffer 102b. The control portion 102c
controls switch groups 102e and 102h through a control signals 102f
and 102g so that the bit string 105 and the bit string 102d are
stored at the appropriate positions.
[0085] Referring to FIG. 3, the table looking-up unit 104 includes
a buffer 104a for temporarily holding a 17-bit string, a return bit
selecting portion 104b for controlling the bit string 105 to be
returned to the bit string buffer 102, and a demultiplexer 104c
outputting two runs 120 and 123, two levels 121 and 122 and the
codeword length 104e in the table element 119. The 17-bit output
103 of the bit string buffer 102 is inputted into the buffer 104a.
The buffer 104a outputs the bit string 105 of an appropriate length
based on the control signal 104f of the return bit selecting
portion 104b. Input and output is switched by the switch 104d.
[0086] The codeword length 104e obtained from the table lookup
operation is inputted into the return bit selecting portion 104b.
Then, the return bit selecting portion 104b outputs the control
signal 104f for outputting the bit string 105 in which the codeword
used for table looking-up is excluded from the contents of the
buffer 104a. The demultiplexer 104c outputs the input table element
119 as the runs 120 and 123, the levels 121 and 122 and the
codeword length 104e.
[0087] Furthermore, referring to FIG. 4, the table selecting unit
107 is constructed with a buffer 107a temporarily holding a 17-bit
string, a pattern matching portion 107b matching between upper bits
107d of the bit string held in the buffer 107a and a certain bit
string pattern, and an output control portion 107c controlling
output of the buffer 107a. The 17-bit string 106 is inputted into
the buffer 107a. The buffer 107a outputs a bit string 108 based on
a control signal 107f of the output control portion 107c.
[0088] The pattern matching portion 107b reads upper bits 107d of
the bit string held in the buffer 107a, and performs matching
between the upper bits 107d and a certain bit string pattern. Then,
the pattern matching portion 107b output signal 109 and 110 for
selecting lookup table 114 or 115 and matching information 107e.
The output control portion 107c outputs a signal 107f controlling
output 108 of the buffer 107a based on the matching information
107e.
[0089] Referring to FIG. 5, the DCT coefficient block storage unit
128 is constructed with a storage portion 128a determining
positions where the inverse quantization results 126 and 127 are
stored based on the scanning order and the runs 120 and 123, and a
DCT coefficient storage portion 128b where the inverse quantization
results are stored. The runs 120 and 123 and the inverse
quantization results 126 and 127 are inputted into the storage
portion 128a. The storage portion 128a then outputs the inverse
quantization results through appropriate two wires of output wiring
group 128c. The DCT coefficient storage portion 128b has a storage
region capable of storing sixty-four coefficients.
[0090] Here, construction of the lookup tables 114 and 115 will be
discussed in detail.
[0091] At first, the lookup table 114 has an address expressed by
seven bit binary value. In each address of the lookup table 114,
when the address has a form where two codewords whose total length
is less than or equal to seven are concatenated with a bit string
whose length is greater than or equal to zero, two sets of {run
level} corresponding to two codewords and the total codeword length
are stored in the table element corresponding to the address. On
the other hand, in each address of the lookup table 114, except for
the foregoing case, the address has a form where the codeword whose
length is less than or equal to five are concatenated with a bit
string whose length is greater than or equal to zero, {run, level}
and the codeword length corresponding to the codeword are stored in
the table element corresponding to the address. In each address of
the lookup table 114, except for the foregoing two cases, arbitrary
values are stored in the table element corresponding to the
address.
[0092] On the other had, the lookup table 115 has an address
expressed by seventeen bit binary value. In each address of the
lookup table 115, when the address has a form where the codeword
whose length is greater than or equal to six is concatenated with a
bit string whose length is greater than or equal to zero, {run,
level} corresponding to the codeword and the codeword length are
stored in the table element corresponding to the address.
Otherwise, in each address of the lookup table 115, arbitrary
values are stored in the table element corresponding to the
address.
[0093] Next, discussion will be given for construction examples of
the lookup tables 114 and 115 with reference to the drawings.
[0094] FIGS. 6 to 11 are illustrations showing Huffman code for DCT
coefficient in MPEG standard. FIG. 6 is an illustration showing a
decoded data and codeword length corresponding to a codeword whose
length is greater than or equal to two and less than or equal to
nine in the Huffman code table for DCT coefficients in MPEG
standard, FIG. 7 is an illustration showing a decoded data and
codeword length corresponding to a codeword whose length is eleven
or thirteen in the Huffman code table for DCT coefficient in MPEG
standard, FIG. 8 is an illustration showing a codeword data and
codeword length corresponding to a codeword whose length is
fourteen in the Huffman code table for DCT coefficient in MPEG
standard, FIG. 9 is an illustration showing a decoded data and
codeword length corresponding to a codeword whose length is fifteen
in the Huffman code table for DCT coefficient in MPEG standard,
FIG. 10 is an illustration showing a decoded data and codeword
length corresponding to a codeword whose length is sixteen in the
Huffman code table for DCT coefficient in MPEG standard, and FIG.
11 is an illustration showing a decoded data and codeword length
corresponding to a codeword whose length is seventeen in the
Huffman code table for DCT coefficient in MPEG standard.
[0095] In each table of the foregoing drawings, i.e. FIGS. 6 to 11,
"codeword", "decoded data" corresponding to the "codeword", and
"codeword length" are shown.
[0096] In the column of "codeword", respective codewords are shown.
In the column of "decoded data", {run, level} corresponding to
codewords shown in the column of "codeword" are shown. In the
column of "codeword length", the lengths of codewords shown in the
column of "codeword" are shown.
[0097] It should be noted that codewords "10" and "000001" are
special. Namely, the codeword "10" represents EOB and the codeword
"000001" represents a symbol "Escape" for expressing sets of run
and level not defined in the Huffman table.
[0098] FIG. 12 is an illustration for explaining a construction of
the lookup table 114, and FIGS. 13 to 19 are illustrations for
explaining a construction of the lookup table 115.
[0099] FIG. 12 is an illustration showing a decoded data, a
codeword length, a bit position matching codeword and a table
address corresponding to two codewords whose total length is
greater than or equal to five and less than or equal to, seven, or
one codeword whose length is greater than or equal to two and less
than or equal to five in the lookup table 114 for parallel decoding
in FIG. 1, FIG. 13 is an illustration showing a decoded data, a
codeword length, a bit position matching codeword and a table
address corresponding to one codeword whose length is greater than
or equal to six and less than or equal to eight in the lookup table
115 for parallel decoding in FIG. 1, FIG. 14 is an illustration
showing a decoded data, a codeword length, a bit position matching
codeword and a table address corresponding to one codeword whose
length is equal to nine or eleven in the lookup table 115 for
parallel decoding in FIG. 1, FIG. 15 is an illustration showing a
decoded data, a codeword length, a bit position matching codeword
and a table address corresponding to one codeword whose length is
thirteen in the lookup table 115 for parallel decoding in FIG. 1,
FIG. 16 is an illustration showing a decoded data, a codeword
length, a bit position matching codeword and a table address
corresponding to one codeword whose length is fourteen in the
lookup table 115 for parallel decoding in FIG. 1, FIG. 17 is an
illustration showing a decoded data, a codeword length, a bit
position matching codeword and a table address corresponding to one
codeword whose length is fifteen in the lookup table 115 for
parallel decoding in FIG. 1, FIG. 18 is an illustration showing a
decoded data, a codeword length, a bit position matching codeword
and a table address corresponding to one codeword whose length is
sixteen in the lookup table 115 for parallel decoding in FIG. 1,
and FIG. 19 is an illustration showing a decoded data, a codeword
length, a bit position matching codeword and a table address
corresponding the one codeword whose length is seventeen in the
lookup table 115 for parallel decoding in FIG. 1.
[0100] At first, in FIG. 12, the "codeword", the "decoded data"
corresponding to the "codeword", the "codeword length", a "bit
position matching codeword" and "table address" are shown with
these items, the lookup table 114 is generated.
[0101] In the column of "codeword", concatenated two codewords,
whose total codeword length is less than or equal to seven, or the
codeword whose length is less than or equal to five are shown.
[0102] In the column of "bit position matching codeword", the 7-bit
string where a bit string shown in the column of "code word" is
concatenated with arbitrary bit string is shown. "?" represents
that the corresponding bit is "1" or "0".
[0103] In the column of "decoded data", if the bit string shown in
the column of "code word" is a concatenation of two codewords, two
sets of {run, level} corresponding to these codewords are shown.
Otherwise, {run, Level} corresponding to one codeword is shown.
[0104] In the column of "codeword length", if the bit string shown
in the column "codeword" is a concatenation of two codewords, the
total codeword length is shown. Otherwise, the length of one
codeword is shown.
[0105] The column of "table address" is consisted of columns of
"minimum value" and "maximum value". The column of "minimum value"
has decimal values obtained by substituting "0" for all "?" in
respective bit strings shown in "bit position matching
codeword".
[0106] The column of "maximum value" has decimal values obtained by
substituting "I" for all "?" in respective bit strings shown in
"bit position matching code word".
[0107] Here, the lookup table 114 is constructed in the following
manner.
[0108] At first, discussion will be given for the case where 7-bit
addresses of the lookup table falls within a zone defined between
"minimum value" and "maximum value" of FIG. 12. If the bit string
shown in the column of "codeword" corresponding to the address is a
concatenation of two codewords, two sets of {run, level} in the
column of "decoded data" and the total codeword length in the
column of "codeword length" corresponding to the above zone are
stored in the table element specified by the corresponding address.
If the bit string shown in the column of "codeword" corresponding
to the address is one codeword, {run, level} in the column of
"decoded data" and the codeword length in "codeword length"
corresponding to the above zone are stored in the table element
specified by the corresponding address.
[0109] In each 7-bit address of the lookup table 114, if the
address does not fall in any zone, a dummy data is stored in the
table element specified by the corresponding address.
[0110] On the other hand, each table of FIGS. 13 to 19 consists of
"codeword", "decoded data" corresponding to the "codeword",
"codeword length", "bit position matching codeword" and "table
address".
[0111] In the column of "codeword", the codewords whose lengths are
greater than or equal to six are written. In the column of "bit
position matching codeword", the 17-bit strings where bit strings
shown in the column of "codeword" are concatenated with arbitrary
bit string respectively are shown.
[0112] In the column of "decoded data", {run, length} corresponding
to the codewords written in the column of "code word" are shown. In
the column of "codeword length", lengths of codewords shown in the
column of "codeword" are shown.
[0113] The column of "minimum value" of "table address" has decimal
values obtained by substituting "0" for all "?" in respective bit
strings shown in "bit position matching codeword". The column of
"maximum value" of the "table address" has decimal values obtained
by substituting "1" for all "?" in respective bit strings shown in
"bit position matching codewords".
[0114] Here, the lookup table 115 is constructed in the following
manner.
[0115] If 17-bit addresses of the lookup table 115 falls within a
zone defined between "minimum value" and "maximum value" of FIGS.
13 to FIG. 19, {run, level} shown in the column of "decoded data"
and the codeword length corresponding to the above zone are stored
in the table element specified by the corresponding address.
Otherwise, dummy data is stored in the table element specified by
the corresponding address.
[0116] Next, operation of the shown embodiment of the signal
decoding system will be discussed with reference to FIG. 1.
[0117] At first, the bit stream 101 of FIG. 1 is inputted into the
left side of the buffer 102a and temporarily held therein. The bit
string buffer 102 outputs the 17-bit string 103 which is held in
the buffer 102b.
[0118] Subsequently, the bit string 105 in which decoded codewords
are excluded from the bit string 103 is inputted in the bit string
buffer 102. By controlling the switch group 102h, the bit string
105 is stored in the front portion of the buffer 102b. In addition,
by controlling the switch group 102e, the front half portion 102d
of the buffer 102a is stored in the end portion of the buffer 102b.
It should be noted that the control portion 102c controls the
length of the bit string 102d so that the total length of the two
strings 102d and 105 becomes seventeen bits.
[0119] The bit string 103 is outputted as the bit string 106 in the
table look-up unit 104. The table selecting 107 selects one of two
tables 114 and 115 based on the bit string 106.
[0120] More particularly, when the leading two bits of the 17-bit
string 106 are "00", the lookup cable 115 is selected. Then, in the
pattern matching portion 107b, the control signals 109 and 110 are
both set to "1". Otherwise, the lookup table 114 is selected.
[0121] Then, in the pattern portion 107b, the control signals 109
and 110 are both set to "0".
[0122] This is based on the fact that the 2-bit prefixes of the bit
portion matching codewords shown in FIGS. 13 to 19 are all "00",
and that the 2-bit prefixes of the bit position matching codewords
shown in FIG. 12, are all "01", "10" or "11".
[0123] Furthermore, in the table selecting unit 107, when the
lookup table 114 is selected, the 7-bit prefix of the 17-bit string
106 is outputted as the table address 108. This is performed by
shifting the buffer 107a 7 bits toward the left, via the output
control portion 107c, and the remaining 10-bits are flushed
(erased). When the lookup table 115 is selected, the 17-bit string
106 is outputted as the table address 108. This is performed by
shifting the buffer 107a 17 bits toward the left via the output
control portion 107c.
[0124] For example, the 17-bit output 106 of the table looking-up
unit 104 is selected to be "11111000000001110". Then, since the
2-bit prefix of "11111000000001110" is "11", the 7-bit prefix
"1111100" in the bit string 106 is outputted as the table address
108 in table selecting unit 107, and both control signals 109 and
110 are set to "0".
[0125] In the selected lookup table 114, the table element is
identified by table address 112 which is the output 108 of the
table selecting unit 107. Then, the table element 119 is outputted.
The table element 119 is outputted as two runs 120 and 123 both
being "0" and levels 121 and 122 being "-1" and "1" respectively,
via the demultiplexer 104c in the table looking-up unit 104. In the
table looking-up unit 104, by using the total codeword length 104e
"6", the bit string in which decoded codewords are excluded from
the 17-bit string 103, namely 11-bit (=17-6(bit)) string
"00000001110" following concatenated two codewords "111110" is
outputted as the input 105 for the bit string buffer 102. This is
done by shifting the buffer 104a toward left via the return bit
selecting portion 104b based on the total codeword length 104e.
[0126] The level 121 "-1" is inversely quantized by the inverse
quantizer 124 and the level 122 "1" is inversely quantized by the
inverse quantizer 125, in parallel.
[0127] In the DCT coefficient block storage unit 128, the storage
position is designated in the following manner. Namely, the storage
portion 128a stores the inverse quantization result 126 at a
position in the DCT coefficient storage portion 128b specified by
the scanning order and then run 120 "0". On the other hand, the
storage portion 128a stores the inverse quantization result 127 at
a position identified by the scanning order and the run 123
"0".
[0128] As set forth above, in the shown embodiment of the signal
decoding system, a variable-length decoding of a maximum of two
code words is performed by only one table lookup operation. For the
levels obtained by decoding, inverse quantization is performed in
parallel. Furthermore, by eliminating the inverse quantization step
for zero coefficients, the process speed of the DCT coefficient
block decoding can be increased.
[0129] The foregoing statement has been discussed with respect to a
structure of two kinds of lookup tables. However, it should be
clear that a construction including three or more kinds of lookup
tables may be applied. Additionally, two kinds of lookup tables
which are different from the foregoing may be employed.
[0130] Furthermore, while lookup tables simultaneously decoding two
code words has been discussed, it is clearly possible to employ
lookup tables simultaneously decoding three or more codewords. In
such case, however, the memory requirement for achieving such
lookup tables becomes huge, and the memory IC to be used for such
lookup tables must be selected accordingly. As set forth above, by
employing lookup tables which simultaneously decode a maximum of
two code words at a time, the signal decoding system can be
constructed with a memory having a relatively small storage
capacity. Such construction will be discussed later with reference
to FIG. 23.
[0131] The DCT coefficient block decoding system shown in FIG. 1
can be achieved by programs using a microprocessor. FIG. 20 shows
such construction.
[0132] The DCT coefficient block decoding system in FIG. 1 is
constructed with a storage medium 303 storing programs for
performing a DCT coefficient block decoding, a main memory 302 for
temporarily storing programs read out from the storage medium 303,
and a microprocessor 301 executing the DCT coefficient block
decoding under control by the programs. Then, as shown in FIG. 1,
the bit string buffer 102, the table looking-up unit 104, the table
selecting unit 107 and the lookup tables 114 and 115 can be easily
implemented as programs of the microprocessor 301.
[0133] Here, it has been premised that the microprocessor 301 has
an arithmetic and logic unit (ALU) as shown in FIG. 21.
[0134] In FIG. 21, two 32-bit registers 401 and 402 are shown, each
of which are divided into an upper sixteen bits and a lower sixteen
bits, respectfully. For the sixteen bits of the registers 401 and
402, sixteen bit ALU 403 is provided. In addition, for the lower
sixteen bits of the registers 401 and 402, sixteen bit ALU 404 is
provided.
[0135] The ALUs 403 and 404 may execute 16-bit addition, 16-bit
subtraction and 16 bit multiplication. By operating two ALUs 403
and 404 in parallel, 16-bit arithmetic operations can be performed
in parallel. The result of the ALU 403 is stored in the upper
sixteen bits of the register 405, and the result of the ALU 404 is
stored in the lower sixteen bits of the register 405.
[0136] Thus, by using ALU 403 for achieving the inverse quantizer
124 and by using ALU 404 for achieving the inverse quantizer 125,
the inverse quantization of the levels 121 and 122 can be executed
in parallel.
[0137] On the other hand, the DCT coefficient block storage unit
128 may also be easily implemented as the program of the
microprocessor 301.
[0138] Next, the content of the program stored in the storage
medium 303 will be discussed with reference to FIG. 22. FIG. 22 is
a flowchart showing a procedure of DCT coefficient block decoding
for one block. At first, for all coefficient in the block 128b, "0"
is stored (step 501). Then, the 17-bit string 103 is read from the
bit string buffer 102 is loaded in the register of the
microprocessor 301 (step 502).
[0139] By using the read bit string 103 or a part thereof as an
address, lookup tables 114 and 115 are looked up (step 503). By
using the codeword length 104e obtained at step 503, the bit string
105 in which the decoded codewords are excluded from the string 103
is returned to the bit string buffer 102 (step 504). If the
codeword decoded at step 503 indicates EOB, the DCT coefficient
block decoding is terminated (steps 505 to 508). Otherwise, the
next step 506 is executed (step 505).
[0140] Two or one levels 121 and 122 obtained at step 503 are
inversely quantized (step 506). By using the scanning order and the
runs 120 and 123 obtained at step 503, two or one inversely
quantized values 126 and 127 obtained at step 506 are stored in the
DCT coefficient block 128b (step 507).
[0141] Subsequently, the process of the steps 502 to 507 is
repeated. Thus, one DCT coefficient block is decoded.
[0142] It should be noted that, in addition to a semiconductor
memory or a magnetic disk device, various other storage mediums can
be employed as the storage medium 303 set forth above.
[0143] On the other hand, FIG. 23 is a block diagram showing
another embodiment of the signal decoding system according to the
present invention. In the following discussion, the same elements
as those in the foregoing embodiment will be identified by the same
reference numerals and detailed discussion thereof will be
neglected for avoiding redundant discussion to keep the disclosure
simple enough to facilitate clear understanding of the present
Invention.
[0144] In FIG. 23, the shown embodiment of the signal decoding
system according to the present invention is different from the
image signal decoding system of FIG. 1 in that seven lookup tables
114-1 to 114-7 are provided. The lookup table 114-1 is a table
whose elements have two or one sets of run and level corresponding
two or one codewords and the total codeword length, similar to that
of the former embodiment of FIG. 1. The lookup tables 114-2 to
114-7 are tables whose elements have a set of run and level
corresponding to one codeword and the codeword length, similar to
those of the former embodiment of FIG. 1. These lookup tables have
the table address 108 as the input and output a table element 119
identified by the address. It should be noted that other portions
shown in FIG. 23 operate as those of FIG. 1.
[0145] Here, detailed discussion will be given with respect to the
construction of the lookup table 114-1 to 114-7.
[0146] At first, the lookup table 114-1 is looked up by using an
address expressed by a nine binary value. In each address of lookup
table 114-1, if the address is a 9-bit string where two codewords
are concatenated with a bit string whose length is greater than or
equal to zero, two sets of {runs, levels} corresponding to two
codewords and the total codeword length are stored in the table
element identified by the address. On the other hand, in each
address of the lookup table 114-1 except for the foregoing, if the
address is a 9-bit string where a codeword is concatenated with a
bit string whose length is greater than or equal to zero, {run,
level} corresponding to the codeword and the codeword length are
stored in the table element identified by the address. In each
address of the decoding reference table 114-1 except for foregoing
two cases, an arbitrary value is stored in the cable element
identified by the address. The lookup table 114-1 corresponds to
FIG. 6 set forth above.
[0147] The lookup table 114-2 is looked up by using an address
expressed by an 11-bit binary value. If the address equals an
11-bit codeword, {run, level} corresponding to the codeword and the
codeword length are stored in the table element identified by the
address. Otherwise, in each address of the lookup table 114-2, an
arbitrary value is stored in the table element identified by the
address. The lookup table 114-2 corresponds to a part of FIG. 7 set
forth above.
[0148] The lookup table 114-3 is looked by up using an address
expressed by a 13-bit binary value. If the address equals a 13-bit
codeword, {run, level}, corresponding to the codeword and the
codeword length are stored in the table element identified by the
address. Otherwise, in each address of the lookup table 114-3, an
arbitrary value is stored in the table element identified by the
address. The lookup table 114-3 corresponds to a part of FIG. 7 set
forth above.
[0149] The lookup table 114-4 is looked up by using an address
expressed by a 14-binary value. If the address equals a 14-bit
codeword, {run, level}, corresponding to the codeword and the
codeword length are stored in the table element identified by the
address. Otherwise, in each address of the lookup table 114-4, an
arbitrary value is stored in the table element identified by the
address. The lookup table 114-4 corresponds to FIG. 8 set forth
above.
[0150] The lookup table 141-5 is looked up by using an address
expressed by a 15-bit binary value. If the address equals a 15-bit
codeword, {run, level} corresponding to the codeword and the
codeword length are stored in the table element identified by the
address. Otherwise, in each address of the lookup table 114-5, an
arbitrary value is stored in the table element identified by the
address. The lookup table 114-5 corresponds to FIG. 9 set forth
above.
[0151] The lookup table 114-6 is looked up by using an address
expressed by a 16-bit binary value. If the address equals a 16-bit
codeword, {run, level} corresponding to the codeword and the
codeword length are stored in the table element identified by the
address. Otherwise, in each address of the lookup table 114-6, an
arbitrary value is stored in the table element identified by the
address. The lookup table 114-6 corresponds to FIG. 10 set forth
above.
[0152] The lookup table 114-7 is looked up by using an address
expressed by a 17-bit binary value. If the address equals a 17-bit
codeword, {frun, level} corresponding to the codeword and the
codeword length are stored in the table element identified by the
address. Otherwise, in each address of the lookup table 114-7, an
arbitrary value is stored in the table element identified by the
address. The lookup table 114-7 corresponds to FIG. 11 set forth
above.
[0153] FIGS. 24 to 26 consist of tables having columns labeled as
"codeword", "decoded data" corresponding to "codeword length", "bit
position matching codeword" and "table address". In the "codeword"
column of FIG. 24, among the two codeword definition which can be
decoded simultaneously by the lookup table 114-1, the concatenated
two codewords whose total length is less than or equal to eight are
shown. In the "codeword" column of FIG. 25, among the two
definition codewords which can be decoded simultaneously by the
lookup table 114-1, the concatenated two codewords whose total
length is nine are shown. In the "codeword" column of FIG. 26, the
single codewords which can be decoded by the lookup table 114-1
whose length is greater than or equal to two and less than or equal
to nine are shown.
[0154] In the column of "bit position matching codeword" in FIGS.
24 to 26, the 9-bit string where each bit string shown in the
column of "codeword" is concatenated with an arbitrary bit string
wherein each "?" represents "1" or "0". In the column of "decoded
data" of FIGS. 24 to 26, when the bit string shown in the column of
"codeword" consists of two concatenated codewords, two sets of
{run, level} corresponding to the two codewords are written.
Otherwise, {run, level} corresponding to the one code word shown in
the column of "codeword" is written. In the column of "codeword
length" of FIGS. 24 to 26, when the bit string shown in the column
of "codeword" consists of two concatenated codeword, the total
codeword length is written. Otherwise, the length of the one
codeword in the column of "codeword" is written.
[0155] In FIGS. 24 to 26, the column of "table address" consists of
columns labeled "minimum value" and "maximum value". In the column
of "minimum value", the decimal value in which all "?"s of each bit
string shown in the column of "bit position matching code word" are
set to "0" is written. In the column of "maximum value", the
decimal value in which all "?"s of each bit string shown in the
column of "bit position matching codeword" are set to "1" is
written. Here, the lookup table 114-1 is constructed in the
following manner.
[0156] At first, discussion will be given for the case where each
9-bit address in the lookup table 114-1 falls within a zone between
the "minimum value" and the "maximum value". If the bit string
shown in the column of "codeword" corresponding to the address zone
consists of two concatenated codewords, two sets of {run, level}
corresponding to the two codewords in the column of "decoded data"
and the total codeword length are stored in the table element of
the corresponding address. Otherwise, {run, length} corresponding
to the one codeword in the column of "decoded data" and the
codeword length corresponding to the address zone are stored in the
table element of the corresponding address.
[0157] On the other hand, in each 9-bit address of the lookup table
114-1, when the address does not fall within any zone between the
"minimum value" and the "maximum value" of FIGS. 24 to 26, a dummy
data is stored in the table element of the corresponding address.
The lookup table 114-1, has 9.sup.th power of 2, i.e. 512 table
elements, since the address length is 9-bits.
[0158] FIG. 27 is an illustrative exchange for the structure of the
lookup table 114-2. In FIG. 27 for each one codeword which can be
decoded by the lookup table 114-2, columns labeled "codeword",
"decoded data", "codeword length" and "table address" are shown. In
the column of "codeword", 11-bit codewords are written. In the
column of "decoded data", {run, level} corresponding to the
codewords shown in the column of "codeword" are written. In the
column of "codeword length", codeword length 11 is written. In the
column of "table address", values derived by converting the bit
strings shown in the column of "codeword" into their decimal values
are written.
[0159] The lookup table 114-2 is constructed as follows. In each
11-bit address of the lookup table 114-2, when the address equals a
value shown in the column of "table address", {run, level} in the
column of "decoded data" corresponding to the value and the
codeword length are stored in the table element of the
corresponding address.
[0160] Otherwise, in each remaining 11-bit address of the lookup
table 114-2, a dummy data is stored in the table element of the
corresponding address. Since the address length of the lookup table
114-2 is element bits, the number of table elements is (11)th power
of 2 (=2048). However, in practice, since the six bit prefix of the
codeword consists of all "0", the maximum value of the address is
31, and a memory region capable of storing only 32 table elements
is needed.
[0161] FIG. 28 is an illustrative example for the structure of the
lookup table 114-3. In FIG. 28, for one codeword which can be
decoded by the lookup table 114-3, "codeword", "decoded data"
"codeword length" and "table address" are shown. In the column of
"codeword", the 13-bit codewords are written. In the column of
"decoded data", {run, level} corresponding to the codewords shown
in the column of "codeword" are written. In the column of "codeword
length", codeword length 13 is written. In the column of "codeword
address", values derived by converting the codewords into their
decimal values are written.
[0162] The lookup table 114-3 is constructed as follows: In each
13-bit address of the lookup table 114-3, when the address equals a
value shown in the column of "table address" in FIG. 28, {run,
level} in the column of "decoded data" corresponding to the value
and the codeword length are stored in the table element of the
corresponding address.
[0163] Otherwise, in each remaining 13-bit address of the lookup
table 114-3, a dummy is stored in the table element of the
corresponding address. Since the address of the lookup table 114-3
is thirteen bits, the number of table elements is (13) the power of
2 (=8192). However, in practice, since the 7-bit prefix of the
codeword consists of all "0", the maximum value of the address is
63, and a memory region capable of storing only 64 table elements
is needed.
[0164] FIG. 29 is an illustrative example for the structure of the
lookup table 114-4. In FIG. 29, for each one codeword which can be
decoded by the lookup table 114-4, columns labeled "codeword",
"decoded data", "codeword length" and "table address" are shown. In
the column of "codeword", the 14-bit codewords are written. In the
column of "decoded data", {run, level} corresponding to the
codewords shown in the column of "codeword" are written. In the
column of "codeword length", codeword length 14 is written. In the
column of "table address", values derived by converting the
codewords into their decimal values are written.
[0165] The lookup table 114-4 is constructed as follows. In each
14-bit address of the lookup table 114-4, when the address equals a
value shown in the column of "table address" in FIG. 29, {run,
level} in the column of "decoded data" corresponding to the value
and the codeword length are stored in the table element of the
corresponding address.
[0166] Otherwise, in each remaining 14-bit address of the lookup
table 114-4, a dummy data is stored in the table element of the
corresponding address. Since the address of the lookup table 114-4
is fourteen bits, the number of table elements is (14)th power of 2
(=16384). However, in practice, since the 8-bit prefix of the
codeword consists of all "0", the maximum value of the address is
63, and a memory region capable of storing only 64 table elements
is needed.
[0167] FIG. 30 is an illustrative example for the structure of the
lookup table 114-5. In FIG. 30, for each codeword which can be
decoded by the lookup table 114-5, "codeword", "decoded data",
"codeword length" and "table address" are shown. In the column of
"codeword", the 15-bit codewords are written. In the column of
"decoded data", {run, level} corresponding to the codewords shown
in the column of "codeword" are written. In the column of "codeword
length", codeword length 15 is written. In the column of "table
address", values derived by converting the codewords into their
decimal values are written.
[0168] The lookup table 114-5 is constructed as follows. In each
15-bit address of the lookup table 114-5, when the address equals a
value shown in the column of "table address" in FIG. 30, {run,
level} in the column of "decoded data" corresponding to the value
and the codeword length are stored in the table element of the
corresponding address.
[0169] Otherwise, in each remaining 15-bit address of the lookup
table 114-5, a dummy data is stored in the table element of the
corresponding address. Since the address of the lookup table 114-5
is fifteen bits, the number of table elements is (15)th power of 2
(=32768). However, in practice, since the 9-bit prefix of the
codeword consists of all "0", the maximum value of the address is
63, and a memory region capable of storing only 64 table elements
is needed.
[0170] FIG. 31 is an illustrative for example the structure of the
lookup table 14-6. In FIG. 31, for each one codeword which can be
decoded by the lookup table 114-6, columns labeled "codeword",
"decoded data", "codeword length" and "table address" as shown. In
the column of "codeword", the 16-bit codeword is written. In the
column of "decoded data", {run, level} corresponding to the
codewords shown in the column of "codeword" are written. In the
column of "codeword length", codeword length 16 is written. In the
column of "table address", values derived by converting the
codewords into their decimal values are written.
[0171] The lookup table 114-6 is constructed as follows. In each
16-bit address of the lookup table 114-6, when the address equals a
value shown in the column of "table address" in FIG. 31, {run,
length} in the column of "decoded data" corresponding to the value
and the codeword length are stored in the table element of the
corresponding address.
[0172] Otherwise, in each remaining 16-bit address of the lookup
table 114-6, a dummy data is stored in the table element of the
corresponding address. Since the address of the lookup table 114-6
is sixteen bits, the number of table elements is (16)th power of 2
(=65536). However, in practice, since the 10-bit prefix of the
codeword consists of all "0", the maximum value of the address is
63, and a memory region capable of storing only 64 table elements
is needed.
[0173] FIG. 32 is an illustrative example for the structure of the
lookup table 114-7. In FIG. 32, for each one codeword which can be
decoded by the lookup table 114-7, columns labeled "codeword",
"decoded data", "codeword length" and "table address" are shown. In
the column of "codeword", the 17-bit codewords are written. In the
column of "decoded data", {run, length} corresponding to the
codewords shown in the column of "codeword" are written. In the
column of "codeword length", codeword length 17 is written. In the
column of "table address", values derived by converting the
codewords into their decimal values are written.
[0174] The lookup table 114-7 is constructed as follows. In each
17-bit address of the lookup table 114-7, when the address equals a
value shown in the column of "table address" in FIG. 32, {run,
level} in the column of "decoded data" corresponding to the value
and the codeword length are stored in the table element of the
corresponding address.
[0175] Otherwise, in each 17-bit address of the lookup table 114-7,
a dummy data is stored in the table element of the corresponding
address. Since the address of the lookup table 114-7 is seventeen
bits, the number of table elements is (17)th power of 2 (=131072).
However, in practice, since the 11-bit prefix of the codeword
consists of all "0", the maximum value of the address is 63, and a
memory region capable of storing only 64 table elements is
needed.
[0176] By constructing the lookup tables as set forth above, the
total number of the table elements becomes 864. Therefore, compared
with the number of table elements ((17)th power of 2 (=131072)) in
the conventional method, the number of table elements can be
reduced significantly.
[0177] A method constructing the lookup tables 114-1 to 114-7, in
FIG. 23 will be discussed with reference to FIG. 33. FIG. 33 is a
flowchart showing a procedure in constructing the lookup table
114-1 with K-bit address. In the lookup table, the number of table
elements is assumed to be 2.sup.K, where K is less than 17.
[0178] A memory region for each table element in the lookup table
114-1 is allocated (step 601). Then, the addresses i (i is an
integer greater than or equal to 0 and less than 2.sup.K) are
assigned to each table element (step 602).
[0179] Next, i is set to zero (step 603). At step 604, when a
prefix in the K bit representation of the address i equals the
concatenation C1.vertline.C2 of codewords C1 and C2, {run, level}
corresponding to the codeword C1 and {run, level} corresponding to
the codeword C2 and the bit length of C1.vertline.C2 are stored in
the table element of address i (step 605), and step 609 is
executed. Otherwise, step 606 is executed.
[0180] At step 606, when a prefix in the K bit representation of
the address i equals the codeword C1, {run, level} corresponding to
the codeword C1 and the length of C1 are stored in the table
element of the address i (step 607), and step 609 is executed.
Otherwise, step 608 is executed.
[0181] At step 608, a dummy data is stored in the table element of
the address i. At step 609, the address i is incremented by one.
Subsequently, if i is greater than or equal to 2.sup.K,
construction of the decoding reference table 114-1 is terminated
(steps 610 to 611). Otherwise, step 605 is executed.
[0182] It should be noted that the lookup table 114-1 shown in
FIGS. 24 to 26 as set forth above is for the case where K=9, i.e.,
the address length is nine bits. According to the flowchart shown
in FIG. 33, the program is generated. It is clear that by using
this program, the computer is controlled to generate the lookup
table 114-1. A semiconductor memory, magnetic disk device and so
forth, can be used as the storage medium for storing such
programs.
[0183] A method for constructing the lookup tables set forth above,
has been disclosed by the inventors, Daiji Ishii et al, in
"PARALLEL VARIABLE LENGTH DECODING WITH INVERSE QUANTIZATION FOR
SOFTWARE MPEG-2 DECODERS", 1997,
[0184] IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEM SiPS 97 Design and
implementation, pp. 500 to 509.
[0185] The operation of the shown embodiment on the signal decoding
system will be discussed with reference to FIG. 23. At first, the
bit stream 101 is inputted into the buffer 102a of the bit string
buffer 102. The bit string buffer 102 outputs the 17-bit string 103
stored in the buffer 102b.
[0186] Thereafter, the bit string 105 in which the decoded codeword
is excluded from the bit string 103 is inputted into the buffer
102. Through control of the switch group 102h by the control
portion 102c, the bit string 105 is stored in the front part of the
buffer 102b. In addition, through control of the switch group 102e
by the control portion 102c, the front part 102d of the buffer 102a
is stored in the end part of the buffer 102b. It should be
appreciated that the control portion 102c controls the length of
the string 102d outputted from the buffer 102a so that the total
length with the bit string 105 becomes seventeen bits.
[0187] The inputted string 103 is outputted as the bit string 106
from the table looking-up unit 104. The table selecting unit 107
stores the inputted string 106 in the buffer 107a, and selects one
of the seven lookup tables 114-1 to 114-7 based on the bit string
held in the buffer 107a.
[0188] Hereinafter, the operation of the table selecting unit 107
will be discussed more particularly.
[0189] When a prefix in the bit string held in the buffer 107a
matches with one of "1", "01", "001", "0001", "00001" and "000001",
the lookup table 114-1 is selected. This is based on the fact that
the prefixes of the codewords illustrated in FIGS. 24 to 26 of "1",
"01", "001", "0001", "00001" and "000001". Table selection is
performed by connecting the switches 111 and 118 to the lookup
table 114-1 through the control signals 109 and 110.
[0190] The table selecting unit 107 outputs the nine bit prefix in
the bit string held in the buffer 107a, and flushes (erases) the
remaining bit string. When a prefix in the bit string held in the
buffer 107a matches with the pattern "0000001", the lookup table
114-2 is selected. This is based on the fact that the prefixes of
all codewords in FIG. 27 are "0000001". Table selection is
performed by connecting the switches 111 and 118 to the lookup
table 114-2 through the control signals 109 and 110.
[0191] The cable selecting unit 107 outputs the eleven bit prefix
in the bit string held in the buffer 107a, and flushes the
remaining bit string. When a prefix in the bit string held in the
buffer 107a matches with the pattern "00000001", the lookup table
114-3 is selected. This is based on the fact that the prefixes all
codewords shown in FIG. 28 are "00000001". Table selection is
performed by connecting the switches 111 and 118 to the lookup
table 114-3 through the control signals 109 and 110.
[0192] The table selecting unit 107 outputs the thirteen bit prefix
in the bit string held in the buffer 107a, and flushes the
remaining bit string. When a prefix in the bit string held in the
buffer 107a matches with the pattern "000000001", the lookup table
114-4 is selected. This is based on the fact that the prefixes of
all codewords shown in FIG. 29 are "000000001". Table selection is
performed by connecting the switches 111 and 118 to the lookup
table 114-4 through the control signals 109 and 110.
[0193] The table selecting unit 107 outputs fourteen bit prefix in
the bit string held in the buffer 107a, and flushes the remaining
bit string. When a prefix in the bit string held in the buffer 107a
matches with the pattern "0000000001", the lookup table 114-5 is
selected. This is based on the fact that the prefixes of all
codewords shown in FIG. 30 are "0000000001". Table selection is
performed by connecting the switches 111 and 118 to the lookup
table 114-5 through the control signals 109 and 110.
[0194] The table selecting unit 107 outputs the fifteen bit prefix
in the bit string held in the buffer 107a and flushes the remaining
bit string. When a prefix in the bit string held in the buffer 107a
matches with the pattern "00000000001", the lookup table 114-6 is
selected. This is based on the fact that the prefixes of all
codewords shown in FIG. 31 are "00000000001". Table selection is
performed by connecting the switches 111 and 118 to the lookup
table 114-6 through the control signals 109 and 110.
[0195] The table selecting unit 107 outputs the sixteen bit prefix
in the bit string held in the buffer 107a and flushes the remaining
bit string. When a prefix in the bit string held in the buffer 107a
matches with the pattern "000000000001", the lookup table 114-7 is
selected. This is based on the fact that the prefixes of all
codewords shown in FIG. 32 are "000000000001". Table selection is
performed by connecting the switches 111 and 118 to the lookup
table 114-7 through the control signals 109 and 110.
[0196] The table selecting means 107 outputs the seventeen bit
string held in the buffer 107a.
[0197] Suppose, for example, that the 17-bit strings 103 and 106
are "11111000000001110". Since the 1-bit prefix of the bit string
"11111000000001110" is "1", the 9-bit prefix "111110000" in the
17-bit string 106 is outputted as the table address 108. Then, by
the control signals 109 and 110, the switches 111 and 118 are
connected to the lookup table 114-1. In the selected lookup table
114-1, the table address 108 which is the output of the table
selecting unit 107 identifies a table element 119. Thus, the table
element 119 is outputted. The obtained table element 120 is
outputted as runs 120 "0" and 123 "0" and levels 121 "-1" and 122
"1" through the demultiplexer 104c of the table looking-up unit
104. In the table looking-up unit 104, by using the total codeword
length 104e "6", the bit string in which the decoded codewords are
excluded from the 17-bit string, namely the 11(=17-6)-bit string
"00000001110" following "111110" from the two concatenated
codewords is outputted to the bit string buffer 102. This is
performed by shifting the buffer 104a toward left based on the
total codeword length 104e of the return bit selecting portion
104b. Among the levels 121 "-1" and 122 "1", level 121 is inversely
quantized by the inverse quantizer 124 and level 122 is inversely
quantized by the inverse quantizer 125, in parallel. Then, the
results of inverse equalization are stored in the DCT coefficient
block storage unit 128 in the following manner. The storage portion
128a determines a position to store the inverse quantization result
126 in the DCT storing portion 128b by the scanning order and the
run 120 "0".
[0198] On the other hand, the storage portion 128a determines the
portion to store the inverse quantization result 127 in the DCT
coefficient storing portion 128b by the scanning order and the run
123 "0". As set forth above, in the shown unit, variable length
decoding is performed for at most two code words by only one table
lookup operation. Furthermore, for the levels obtained by decoding,
inverse quantization is performed in parallel to achieve high speed
DCT coefficient block decoding. In addition, by restricting the
number of the codewords to be decoded simultaneously to be less
than or equal to two, the system can be constructed with a memory
IC which has a small capacity.
[0199] While the foregoing discussion has been given for an
embodiment where seven lookup tables are employed, it is clear that
the signal decoding system according to the present invention can
be constructed with more than or less than seven lookup tables.
[0200] Additionally, the seven lookup tables may be constructed in
other ways. All components in the DCT coefficient block decoding
system in FIG. 23 may be implemented as programs of microprocessor,
in which case, the DCT coefficient block decoding processing system
may be constructed as shown in the embodiment of FIGS. 20 to
22.
[0201] While the foregoing discussion has been given for decoding
and inverse quantization of the image signal, the present invention
is, of course, applicable for other type of signals.
[0202] As set forth above, according to the present invention, DCT
coefficient block decoding process speed can be increased by
simultaneously performing variable length decoding for multiple
codewords, performing inverse quantization in parallel and
neglecting inverse quantization for zero coefficients. In addition,
by using lookup tables having fewer number of table elements, the
necessary memory amount can be reduced.
[0203] Although the present invention has been illustrated and
described with respect to an exemplary embodiment thereof, it
should be understood by those skilled in the art that the foregoing
and various other changes, omissions and additions may be made
therein and thereto, without departing from the spirit and scope of
the present invention. Therefore, the present invention should not
be understood as limited to the specific embodiment set forth above
but to include all possible embodiments which can be embodied
within a scope encompassed and equivalents thereof with respect to
the features set forth in the appended claims.
* * * * *