U.S. patent application number 10/180388 was filed with the patent office on 2003-02-13 for method for making a semiconductor device having copper conductive layers.
Invention is credited to Jain, Ajay.
Application Number | 20030032271 10/180388 |
Document ID | / |
Family ID | 24981862 |
Filed Date | 2003-02-13 |
United States Patent
Application |
20030032271 |
Kind Code |
A1 |
Jain, Ajay |
February 13, 2003 |
Method for making a semiconductor device having copper conductive
layers
Abstract
A method for making a semiconductor device is described. That
method comprises forming a copper containing layer on a substrate,
then forming a tantalum containing layer on the copper containing
layer. After the tantalum containing layer is oxidized, an etch
stop layer may be formed on the oxidized tantalum layer.
Inventors: |
Jain, Ajay; (Hillsboro,
OR) |
Correspondence
Address: |
Michael A. Bernadicou
BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN LLP
Seventh Floor
12400 Wilshire Boulevard
Los Angeles
CA
90025-1026
US
|
Family ID: |
24981862 |
Appl. No.: |
10/180388 |
Filed: |
June 25, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10180388 |
Jun 25, 2002 |
|
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09741716 |
Dec 19, 2000 |
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Current U.S.
Class: |
438/586 ;
257/E21.576; 257/E21.592 |
Current CPC
Class: |
H01L 21/76834 20130101;
H01L 21/76888 20130101 |
Class at
Publication: |
438/586 |
International
Class: |
H01L 021/3205 |
Claims
What is claimed is:
1. A method of forming a semiconductor device comprising: forming
on a substrate a copper containing layer; forming a tantalum
containing layer on the copper containing layer; oxidizing the
tantalum containing layer; and forming an etch stop layer on the
oxidized tantalum layer.
2. The method of claim 1 wherein the tantalum containing layer is
less than about 5 nanometers thick.
3. The method of claim 2 wherein the etch stop layer comprises
silicon nitride.
4. The method of claim 2 wherein the etch stop layer comprises
silicon carbide.
5. The method of claim 1 further comprising applying a chemical
mechanical polishing step to the copper containing layer prior to
forming the tantalum containing layer on the copper containing
layer.
6. The method of claim 1 wherein the tantalum containing layer is
completely oxidized by exposing it to air to form a native
dielectric oxide that is between about 2 and about 5 nanometers
thick.
7. The method of claim 1 wherein the step of forming a tantalum
containing layer on the copper containing layer forms a layer that
consists essentially of tantalum.
8. The method of claim 1 wherein the step of forming on a substrate
a copper containing layer forms a layer that consists essentially
of copper.
9. A method of forming a semiconductor device comprising: forming
on a substrate a copper containing layer; applying a chemical
mechanical polishing step to the copper containing layer; forming a
layer that consists essentially of tantalum on the copper
containing layer; and exposing the tantalum containing layer to air
to completely oxidize it to form a native dielectric oxide that is
between about 2 and about 5 nanometers thick.
10. The method of claim 9 further comprising forming an etch stop
layer on the native dielectric oxide.
11. The method of claim 10 wherein the etch stop layer comprises a
material selected from the group consisting of silicon nitride and
silicon carbide.
12. A semiconductor device comprising: a copper containing layer
formed on a substrate; and a native dielectric oxide that is formed
on the copper containing layer, the native dielectric oxide being
between about 2 and about 5 nanometers thick and being formed by
exposing a tantalum containing layer to air.
13. The semiconductor device of claim 12 further comprising an etch
stop layer that is formed on the native dielectric oxide.
14. The semiconductor device of claim 13 wherein the etch stop
layer comprises a material selected from the group consisting of
silicon nitride and silicon carbide.
15. The semiconductor device of claim 14 wherein the copper
containing layer consists essentially of copper.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to semiconductor devices that
include copper conductive layers.
BACKGROUND OF THE INVENTION
[0002] Semiconductor devices include metal layers that are
insulated from each other by dielectric layers. When copper is used
to make those metal layers, it may be desirable to form an etch
stop layer or layers, e.g., a layer comprising silicon nitride or
silicon carbide, on such copper containing layers. Unfortunately,
current processes for applying such an etch stop layer to copper
containing layers may yield a device with marginal adhesion between
those layers, which may degrade electromigration performance.
[0003] Accordingly, there is a need for an improved method for
making a semiconductor device that includes copper conductive
layers. There is a need for such a process that improves adhesion
between copper conductive layers and an etch stop layer that is
formed on them. The present invention provides such a process.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIGS. 1a-1c illustrate cross-sections of structures that may
result when the method of the present invention is used to make a
semiconductor device.
DETAILED DESCRIPTION OF THE PRESENT INVENTION
[0005] A method of forming a semiconductor device is described.
That method comprises forming on a substrate a copper containing
layer, then forming a tantalum containing layer on the copper
containing layer. After oxidizing the tantalum containing layer, an
etch stop layer is formed on the oxidized tantalum layer. Set forth
below is a description of a number of embodiments for this method
of forming a semiconductor device--made with reference to FIGS.
1a-1c. In the following description, numerous specific details are
set forth such as material types, dimensions, etc., to provide a
thorough understanding of the present invention. However, it will
be apparent to those skilled in the art that the invention may be
practiced in many ways other than those expressly described here.
The invention is thus not limited by the specific details disclosed
below.
[0006] With reference to FIG. 1a, an embodiment of the method for
making a semiconductor device of the present invention starts with
a structure that comprises copper containing layers 101 and 102
that sandwich dielectric layer 103. Those layers are formed on
substrate 100. Substrate 100 may be any surface, generated when
making a semiconductor device, upon which a conductive layer may be
formed. Substrate 100 may include, for example, active and passive
devices that are formed on a silicon wafer such as transistors,
capacitors, resistors, diffused junctions, gate electrodes, local
interconnects, etc. . . . Substrate 100 also may include insulating
materials (e.g., silicon dioxide, either undoped or doped with
phosphorus (PSG) or boron and phosphorus (BPSG); silicon nitride;
silicon oxy-nitride; silicon carbide; a carbon doped oxide; or a
polymer) that separate such active and passive devices from the
conductive layer or layers that are formed on top of them, and may
include previously formed conductive layers.
[0007] Dielectric layer 103 preferably comprises silicon dioxide,
which is deposited on the surface of substrate 100 using a
conventional plasma enhanced chemical vapor deposition ("PECVD")
process that employs tetraethylorthosilicate (TEOS) as the silicon
source. Although preferably made of silicon dioxide, dielectric
layer 103 may be made from other materials that may insulate one
conductive layer from another, as will be apparent to those skilled
in the art. For example, dielectric layer 103 may comprise an
organic polymer selected from the group that includes polyimides,
parylenes, polyarylethers, polynaphthalenes, and polyquinolines, or
copolymers thereof. Alternatively, dielectric layer 103 may
comprise fluorinated silicon dioxide or a porous silicon dioxide,
e.g., silicon dioxide doped with carbon. Dielectric layer 103
preferably has a thickness of between about 2,000 and about 20,000
angstroms.
[0008] Dielectric layer 103 may be formed using conventional
deposition techniques, e.g., a conventional spin-on deposition or
PECVD process. Copper containing layers 101 and 102 may be formed
within dielectric layer 103 in the conventional way, e.g., by
etching vias and/or trenches into dielectric layer 103, then
filling those etched regions with copper. Layers 101 and 102 may
comprise contacts, single damascene interconnects, dual damascene
interconnects, or other types of interconnects. Copper containing
layers 101 and 102 may be formed using a conventional copper
electroplating process, e.g., a process where a copper layer is
formed on barrier and seed layers used to line regions that had
been etched into dielectric layer 103. The barrier layer may
comprise a refractory material, such as titanium nitride, but may
also include an insulating material, such as silicon nitride.
Suitable seed materials for the deposition of copper include copper
and nickel.
[0009] When an excess amount of copper is formed on the surface of
layer 103, a chemical mechanical polishing ("CMP") step may be
applied to remove the excess material and to planarize the surface
of layers 101 and 102. When an electroplating process is used to
form those copper containing layers, that CMP step removes both the
excess copper and the underlying barrier layer. When layer 103
comprises silicon dioxide, that layer provides a CMP stop layer for
such a CMP step.
[0010] FIG. 1a shows the structure that results after filling
regions that were etched into dielectric layer 103 with a copper
containing material, then applying a CMP step to remove excess
material from the surface of layer 103 to produce copper containing
layers 101 and 102. After forming the structure shown in FIG. 1a,
tantalum containing layer 104 is formed on copper containing layers
101 and 102, and on dielectric layer 103, to generate the structure
shown in FIG. 1b. In a preferred embodiment, tantalum containing
layer 104 should be thin enough to completely oxidize, when exposed
to air. In a particularly preferred embodiment, tantalum containing
layer 104 should be less than about 5 nanometers thick. That layer
may be formed using a conventional chemical vapor deposition
process, and preferably consists of substantially pure
tantalum.
[0011] After forming tantalum containing layer 104, the resulting
structure is exposed to air to completely oxidize layer 104 to form
native dielectric oxide 105. That oxide preferably is between about
2 and about 5 nanometers thick. Native dielectric oxide 105 should
adhere to copper layers 101 and 102 in a desirable manner.
Following that step, etch stop layer 106, e.g., a layer comprising
silicon nitride or silicon carbide, may be formed on oxide 105, to
generate the structure shown in FIG 1c. Etch stop layer 106, like
layers 101 and 102, should adhere well to oxide 105.
[0012] The method of the present invention thus improves adhesion
between etch stop layer 106 and copper containing layers 101 and
102 by forming an intermediate layer, which is sandwiched between
those layers, that adheres well to both the etch stop layer and the
copper containing layers. Although the foregoing description has
specified certain steps, materials, and equipment that may be used
in such a method, those skilled in the art will appreciate that
many modifications and substitutions may be made. The process of
the present invention may improve adhesion between an etch stop
layer and a copper containing layer, irrespective of the function
that the copper containing layer performs--whether it be a contact,
a single damascene interconnect, a dual damascene interconnect, or
another type of interconnect. Accordingly, it is intended that all
such modifications, alterations, substitutions and additions be
considered to fall within the spirit and scope of the invention as
defined by the appended claims.
* * * * *