U.S. patent application number 09/920866 was filed with the patent office on 2003-02-06 for programming methods for multi-level flash eeproms.
Invention is credited to Chen, Chun, Prall, Kirk D..
Application Number | 20030026132 09/920866 |
Document ID | / |
Family ID | 25444536 |
Filed Date | 2003-02-06 |
United States Patent
Application |
20030026132 |
Kind Code |
A1 |
Chen, Chun ; et al. |
February 6, 2003 |
PROGRAMMING METHODS FOR MULTI-LEVEL FLASH EEPROMS
Abstract
A method is provided for programming a memory cell of an
electrically erasable programmable read only memory. The memory
cell is fabricated on a substrate and comprises a source region, a
drain region, a floating gate, and a control gate. The memory cell
has a threshold voltage selectively configurable into one of at
least three programming states. The method includes generating a
drain current between the drain region and the source region by
applying a drain-to-source bias voltage between the drain region
and the source region. The method further includes injecting hot
electrons from the drain current to the floating gate by applying a
gate voltage to the control gate. A selected threshold voltage for
the memory cell corresponding to a selected one of the programming
states is generated by applying a selected constant drain-to-source
bias voltage and a selected gate voltage.
Inventors: |
Chen, Chun; (Boise, ID)
; Prall, Kirk D.; (Boise, ID) |
Correspondence
Address: |
KNOBBE MARTENS OLSON & BEAR LLP
2040 MAIN STREET
FOURTEENTH FLOOR
IRVINE
CA
92614
US
|
Family ID: |
25444536 |
Appl. No.: |
09/920866 |
Filed: |
August 2, 2001 |
Current U.S.
Class: |
365/185.18 |
Current CPC
Class: |
G11C 16/0483 20130101;
G11C 11/5628 20130101 |
Class at
Publication: |
365/185.18 |
International
Class: |
G11C 016/04 |
Claims
We claim:
1. A method for programming a memory cell of an electrically
erasable programmable read only memory, the memory cell fabricated
on a substrate and comprising a source region, a drain region, a
floating gate, and a control gate, the memory cell having a
threshold voltage selectively configurable into one of at least
three programming states, the method comprising: generating a drain
current between the drain region and the source region by applying
a drain-to-source bias voltage between the drain region and the
source region; and injecting hot electrons from the drain current
to the floating gate by applying a gate voltage to the control
gate, whereby a selected threshold voltage for the memory cell
corresponding to a selected one of the programming states is
generated by applying a selected constant drain-to-source bias
voltage.
2. The method of claim 1, wherein a transistor comprising a
transistor control gate is connected in series between the drain
region of the memory cell and a drain voltage generator, whereby a
control voltage applied to the transistor control gate adjusts a
voltage applied to the drain region of the memory cell.
3. The method of claim 1, wherein a plurality of circuit segments
are connected in parallel between the drain region of the memory
cell and a drain voltage generator, each circuit segment comprising
a resistor connected in series with a transistor having a
transistor control gate, whereby selectively applying a control
voltage to at least one transistor adjusts a voltage applied to the
drain region of the memory cell.
4. The method of claim 1, wherein a reverse back bias is applied
between the substrate and the source region.
5. A method for setting a threshold voltage of a memory cell of an
electrically erasable programmable read only memory to correspond
to one of at least three programming states, the memory cell
fabricated on a substrate and comprising a source region, a drain
region, a floating gate, and a control gate, the method comprising:
generating a drain current between the drain region and the source
region by applying a drain-to-source bias voltage between the drain
region and the source region, the drain-to-source bias voltage
comprising at least one voltage pulse; and injecting hot electrons
from the drain current to the floating gate by applying a gate
voltage to the control gate, whereby a selected threshold voltage
for the memory cell corresponding to a selected one of the
programming states is generated by applying a selected
drain-to-source bias voltage.
6. The method of claim 5, wherein the voltage pulse has a period of
between approximately 1 ns and approximately 10 .mu.s.
7. The method of claim 5, wherein different selected threshold
voltages are generated by different periods of the voltage
pulse.
8. The method of claim 5, wherein a transistor comprising a
transistor control gate is connected in series between the drain
region of the memory cell and a drain voltage generator, whereby a
control voltage applied to the transistor control gate adjusts a
voltage applied to the drain region of the memory cell.
9. The method of claim 5, wherein a plurality of circuit segments
are connected in parallel between the drain region of the memory
cell and a drain voltage generator, each circuit segment comprising
a resistor connected in series with a transistor having a
transistor control gate, whereby selectively applying a control
voltage to at least one transistor adjusts a voltage applied to the
drain region of the memory cell.
10. The method of claim 5, wherein the drain-to-source bias voltage
is selected to maintain a drain current having a substantially
constant magnitude.
11. The method of claim 5, wherein a reverse back bias is applied
between the substrate and the source region.
12. A method for selecting a threshold voltage corresponding to one
of at least three programming states of a memory cell of an
electrically erasable programmable read only memory, the memory
cell fabricated on a substrate and comprising a source region, a
drain region, a floating gate, and a control gate, the method
comprising: generating a drain current between the drain region and
the source region by applying a drain-to-source bias voltage
between the drain region and the source region, the drain-to-source
bias voltage comprising at least one voltage pulse; and injecting
hot electrons from the drain current to the floating gate by
applying a gate voltage to the control gate, whereby a selected
threshold voltage for the memory cell corresponding to a selected
one of the programming states is generated by applying a selected
gate voltage.
13. The method of claim 12, wherein the drain-to-source bias
voltage is selected to maintain a drain current having a
substantially constant magnitude.
14. The method of claim 12, wherein a transistor comprising a
transistor control gate is connected in series between the drain
region of the memory cell and a drain voltage generator, whereby a
control voltage applied to the transistor control gate adjusts a
voltage applied to the drain region of the memory cell.
15. The method of claim 12, wherein a plurality of circuit segments
are connected in parallel between the drain region of the memory
cell and a drain voltage generator, each circuit segment comprising
a resistor connected in series with a transistor having a
transistor control gate, whereby selectively applying a control
voltage to at least one transistor adjusts a voltage applied to the
drain region of the memory cell.
16. The method of claim 12, wherein a reverse back bias is applied
between the substrate and the control gate.
17. A method for programming a memory cell of an electrically
erasable programmable read only memory, the memory cell fabricated
on a substrate and comprising a source region, a drain region, a
floating gate, and a control gate, the memory cell having a
threshold voltage selectively configurable into one of at least
three programming states, the method comprising: generating a drain
current between the drain region and the source region by applying
a drain-to-source bias voltage between the drain region and the
source region; and injecting hot electrons from the drain current
to the floating gate by applying a gate voltage to the control
gate, the gate voltage comprising at least one voltage pulse,
whereby a selected threshold voltage for the memory cell
corresponding to a selected one of the programming states is
generated by applying a selected gate voltage.
18. The method of claim 17, wherein the voltage pulse has a period
of between approximately 1 ns and approximately 10 .mu.s.
19. The method of claim 17, wherein different selected threshold
voltages are generated by different periods of the voltage
pulse.
20. The method of claim 17, wherein a transistor comprising a
transistor control gate is connected in series between the drain
region of the memory cell and a drain voltage generator, whereby a
control voltage applied to the transistor control gate adjusts a
voltage applied to the drain region of the memory cell.
21. The method of claim 17, wherein a plurality of circuit segments
are connected in parallel between the drain region of the memory
cell and a drain voltage generator, each circuit segment comprising
a resistor connected in series with a transistor having a
transistor control gate, whereby selectively applying a control
voltage to at least one transistor adjusts a voltage applied to the
drain region of the memory cell.
22. The method of claim 17, wherein the drain current has a
substantially constant magnitude.
23. The method of claim 17, wherein a reverse back bias is applied
between the substrate and the control gate.
24. A method for programming a memory cell of an electrically
erasable programmable read only memory, the memory cell fabricated
on a substrate and comprising a source region, a drain region, a
floating gate, and a control gate, the memory cell having a
threshold voltage selectively configurable into one of at least
three programming states, the method comprising: generating a drain
current between the drain region and the source region by applying
a drain-to-source bias voltage between the drain region and the
source region; and injecting hot electrons from the drain current
to the floating gate by applying a gate voltage to the control
gate, the gate voltage being ramped from an initial magnitude to a
final magnitude greater than the initial magnitude, the gate
voltage ramped with a ramping rate, whereby a selected threshold
voltage for the memory cell corresponding to a selected one of the
programming states is generated by a gate voltage with a selected
final magnitude.
25. The method of claim 24, wherein the ramping rate is between
approximately 5.5 V/ms and approximately 10.5 V/ms.
26. The method of claim 24, wherein different selected threshold
voltages are generated by different ramping rates of the gate
voltage.
27. The method of claim 24, wherein the final magnitude is between
approximately 5.5 V and approximately 10.5 V.
28. The method of claim 24, wherein the drain-to-source bias
voltage is substantially constant and different selected threshold
voltages are generated by different drain-to-source bias
voltages.
29. The method of claim 24, wherein the drain-to-source bias
voltage comprises at least one voltage pulse having a period.
30. The method of claim 29, wherein different selected threshold
voltages are generated by different periods of the voltage
pulse.
31. The method of claim 24, wherein a transistor comprising a
transistor control gate is connected in series between the drain
region of the memory cell and a drain voltage generator, whereby a
control voltage applied to the transistor control gate adjusts a
voltage applied to the drain region of the memory cell.
32. The method of claim 24, wherein a plurality of circuit segments
are connected in parallel between the drain region of the memory
cell and a drain voltage generator, each circuit segment comprising
a resistor connected in series with a transistor having a
transistor control gate, whereby selectively applying a control
voltage to at least one transistor adjusts a voltage applied to the
drain region of the memory cell.
33. The method of claim 24, wherein the drain-to-source bias
voltage is selected to maintain a drain current having a
substantially constant magnitude.
34. The method of claim 24, wherein a reverse back bias is applied
between the substrate and the control gate.
35. A method for programming a memory cell of an electrically
erasable programmable read only memory, the method comprising
selectively configuring the memory cell into one of at least three
programming states without a verification step.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention generally relates to electrically
reprogrammable nonvolatile memory devices and methods of utilizing
the same. More particularly, the invention relates to processes and
structures for programming erasable programmable read-only memories
(EEPROMs).
[0003] 2. Description of the Related Art
[0004] Memory devices such as erasable programmable read-only
memories (EPROMs), electrically erasable programmable read-only
memories (EEPROMs), or flash erasable programmable read-only
memories (FEPROMs) are erasable and reusable memory cells which are
often used in digital cellular phones, digital cameras, LAN
switches, cards for notebook computers, etc. A memory cell operates
by storing electric charge (representing either a binary "1" or "0"
state of one data bit) on an electrically isolated floating gate,
which is incorporated into a transistor. This stored charge affects
the threshold voltage (V.sub.T) of the transistor, thereby
providing a way to read the memory element. It is therefore crucial
that the memory cell be able to maintain the stored charge over
time, so that charge leakage does not cause data errors by
converting the data bit from one binary state to another.
[0005] A memory cell typically consists of a transistor, a floating
gate, and a control gate above the floating gate in a stacked gate
structure. The floating gate, typically composed of polycrystalline
silicon (i.e., "polysilicon"), is electrically isolated from the
underlying semiconductor substrate by a thin dielectric layer,
which is typically formed of an insulating oxide, and more
particularly, silicon oxide. This dielectric layer is often
referred to as a "tunnel oxide" layer, and is typically
approximately 100.ANG. thick. Properties of the tunnel oxide layer
must be strictly controlled to ensure the ability to read and write
by transferring electrons across the tunnel oxide layer, while
avoiding data loss through charge trapping or leakage. The control
gate is positioned above the floating gate, and is electrically
isolated from the floating gate by a storage dielectric layer, such
as oxide-nitride-oxide (ONO). Electrical access to the floating
gate is therefore only through capacitors.
[0006] A programmed memory cell has its V.sub.T increased by
increasing the amount of negative charge stored on the floating
gate, i.e., for given source and drain voltages, the control gate
voltage which allows a current to flow between the source and the
drain of a programmed memory cell is higher than that of a
non-programmed memory cell. Therefore, the state of a memory cell
is read by applying a control gate voltage below the predetermined
level corresponding to the programmed state, but sufficiently high
to allow a current between the source and the drain in a
non-programmed memory cell. If a current is detected, then the
memory cell is read to be not programmed.
[0007] One method to erase a memory cell (i.e., return the cell to
its non-programmed state) is by exposing the floating gate to
ultraviolet light, which excites the stored electrons out of the
floating gate. The erasure of an EEPROM or FEPROM cell can also be
accomplished via Fowler-Nordheim tunneling of charge from the
floating gate, across the tunnel oxide, to the substrate, thereby
reducing the stored charge in the floating gate. Under this
mechanism for discharging the floating gate, for example, a large
negative voltage (e.g., -10 V) is applied to the control gate, and
a positive voltage (e.g., 5-6 V) is applied to the source while the
drain is left floating. Electrons then tunnel from the floating
gate through the tunnel oxide, and are accelerated into the
source.
[0008] In an attempt to increase the storage density of an array of
memory cells, efforts have been made to utilize multilevel memory
cells, which are capable of representing more than two states by
specifying more than one predetermined V.sub.T level. In such
multilevel memory cells, each range of levels defined by the
predetermined V.sub.T levels corresponds to a separate state.
Therefore, to reliably distinguish between the various states, the
multilevel memory cells must be programmed with narrow V.sub.T
distributions within the ranges defined by the predetermined
V.sub.T levels. Traditionally, these narrow V.sub.T distributions
have been achieved using short programming pulses interleaved with
verification read pulses in order to closely monitor the programmed
level of a given cell. Examples of such multilevel memory cell
programming are disclosed by Kucera, et al., U.S. Pat. No.
6,091,631; Fazio, et al., U.S. Pat. No. 5,892,710; and Harari, U.S.
Pat. No. 5,293,560.
[0009] Such use of verification steps has two potential drawbacks.
First, the circuitry needed to confirm that a particular cell has
been properly programmed takes up valuable space on the
semiconductor die. Second, the frequent verification steps take a
substantial amount of time, thereby prolonging the programming
process.
SUMMARY OF THE INVENTION
[0010] By eliminating the verification steps, the present invention
achieves faster multilevel programming of flash memory devices. In
accordance with one aspect of the present invention, a method is
provided for programming a memory cell of an electrically erasable
programmable read only memory. The memory cell is fabricated on a
substrate and comprises a source region, a drain region, a floating
gate, and a control gate. The memory cell has a threshold voltage
selectively configurable into one of at least three programming
states. The method comprises generating a drain current between the
drain region and the source region by applying a drain-to-source
bias voltage between the drain region and the source region. The
method further comprises injecting hot electrons from the drain
current to the floating gate by applying a gate voltage to the
control gate. A selected threshold voltage for the memory cell
corresponding to a selected one of the programming states is
generated by applying a selected constant drain-to-source bias
voltage.
[0011] In accordance with another aspect of the present invention,
a method is provided for programming a memory cell of an
electrically erasable programmable read only memory. The memory
cell is fabricated on a substrate and comprises a source region, a
drain region, a floating gate, and a control gate. The memory cell
has a threshold voltage selectively configurable into one of at
least three programming states. The method comprises generating a
drain current between the drain region and the source region by
applying a drain-to-source bias voltage between the drain region
and the source region. The drain-to-source bias voltage comprises
at least one voltage pulse. The method further comprises injecting
hot electrons from the drain current to the floating gate by
applying a gate voltage to the control gate. A selected threshold
voltage for the memory cell corresponding to a selected one of the
programming states is generated by applying a selected
drain-to-source bias voltage.
[0012] In accordance with yet another aspect of the present
invention, a method is provided for programming a memory cell of an
electrically erasable programmable read only memory. The memory
cell is fabricated on a substrate and comprises a source region, a
drain region, a floating gate, and a control gate. The memory cell
has a threshold voltage selectively configurable into one of at
least three programming states. The method comprises generating a
drain current between the drain region and the source region by
applying a drain-to-source bias voltage between the drain region
and the source region. The drain-to-source bias voltage comprises
at least one voltage pulse. The method further comprises injecting
hot electrons from the drain current to the floating gate by
applying a gate voltage to the control gate. A selected threshold
voltage for the memory cell corresponding to a selected one of the
programming states is generated by applying a selected gate
voltage.
[0013] In accordance with yet another aspect of the present
invention, a method is provided for programming a memory cell of an
electrically erasable programmable read only memory. The memory
cell is fabricated on a substrate and comprises a source region, a
drain region, a floating gate, and a control gate. The memory cell
has a threshold voltage selectively configurable into one of at
least three programming states. The method comprises generating a
drain current between the drain region and the source region by
applying a drain-to-source bias voltage between the drain region
and the source region. The method further comprises injecting hot
electrons from the drain current to the floating gate by applying a
gate voltage to the control gate. The gate voltage comprises at
least one voltage pulse. A selected threshold voltage for the
memory cell corresponding to a selected one of the programming
states is generated by applying a selected gate voltage.
[0014] In accordance with yet another aspect of the present
invention, a method is provided for programming a memory cell of an
electrically erasable programmable read only memory. The memory
cell is fabricated on a substrate and comprises a source region, a
drain region, a floating gate, and a control gate. The memory cell
has a threshold voltage selectively configurable into one of at
least three programming states. The method comprises generating a
drain current between the drain region and the source region by
applying a drain-to-source bias voltage between the drain region
and the source region. The method further comprises injecting hot
electrons from the drain current to the floating gate by applying a
gate voltage to the control gate. The gate voltage is ramped from
an initial magnitude to a final magnitude greater than the initial
magnitude, and the gate voltage is ramped with a ramping rate. A
selected threshold voltage for the memory cell corresponding to a
selected one of the programming states is generated by applying a
gate voltage with a selected final magnitude.
[0015] In accordance with yet another aspect of the present
invention, a method is provided for programming a memory cell of an
electrically erasable programmable read only memory. The method
comprises selectively configuring the memory cell into one of at
least three programming states without a verification step.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] FIG. 1 schematically illustrates a semiconductor substrate
with a memory cell compatible with the present invention.
[0017] FIG. 2 schematically illustrates channel hot-electron (CHE)
injection as a method of charge transfer to the floating gate.
[0018] FIG. 3 schematically illustrates an array of NOR-type flash
memories.
[0019] FIG. 4 schematically illustrates Fowler-Nordheim (FN)
tunneling as a method of charge transfer to the floating gate.
[0020] FIG. 5 schematically illustrates an array of NAND-type flash
memories.
[0021] FIG. 6 schematically illustrates the variation of floating
gate charge as a function of time upon applying voltages
corresponding to CHE injection to the memory cell.
[0022] FIG. 7A schematically illustrates the multilevel states
achieved by using different drain voltages during the CHE injection
operation.
[0023] FIG. 7B schematically illustrates the threshold voltage
achieved as a function of time by applying different drain voltages
during the CHE injection operation.
[0024] FIG. 8 schematically illustrates the multilevel states
achieved by using different gate voltages during the CHE injection
operation.
[0025] FIG. 9 schematically illustrates the multilevel states
achieved by using different pulse widths on the voltages during the
CHE injection operation.
[0026] FIG. 10 schematically illustrates the variation of the drain
current as a function of time upon applying a ramped gate voltage
as compared to a constant gate voltage.
[0027] FIG. 11 schematically illustrates the multilevel states
achieved by using different ramping rates on the gate voltage.
[0028] FIG. 12 schematically illustrates the drain region of a
memory cell connected to a transistor.
[0029] FIG. 13 schematically illustrates the drain region of a
memory cell connected to a plurality of pairs of transistors and
resistors, the pairs connected in parallel.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0030] FIG. 1 schematically illustrates a semiconductor substrate
10 with a memory cell 20 compatible with the present invention. The
memory cell 20 includes a transistor 30, a floating gate 40, and a
control gate 50 above the floating gate 40 in a stacked gate
structure. The transistor 30 comprises a source region 32, a drain
region 34, and a channel 36 between the source region 32 and the
drain region 34. The floating gate 40, typically composed of
polycrystalline silicon (i.e., "polysilicon"), is electrically
isolated from the underlying semiconductor substrate 10 by a tunnel
dielectric layer 60, which is a thin dielectric layer, typically
formed of an insulating oxide, and more particularly, silicon
oxide, and is typically approximately 100.ANG. thick. The control
gate 50 is positioned above the floating gate 40, and is
electrically isolated from the floating gate 40 by a storage
dielectric layer 70, such as oxide-nitride-oxide (ONO). Electrical
access to the floating gate 40 is therefore only through
capacitors. It should be noted that the materials mentioned herein
are merely exemplary.
[0031] An array of memory cells can be programmed by transferring
charge from the semiconductor substrate to the floating gates of
selected memory cells. One method of achieving this charge transfer
is via channel hot-electron (CHE) injection, which is a
three-terminal process, schematically illustrated by FIG. 2. CHE
injection utilizes a high positive voltage (e.g., approximately 10
V) applied to the control gate 50, grounding the source region 32
of the transistor 30, and applying a high positive voltage (e.g.,
approximately 5 V) to the drain region 34 of the transistor 30,
thereby creating a high drain-to-source bias voltage (e.g.,
approximately 5 V). An inversion region is created in the channel
36 between the source 32 and drain 34 regions by the gate voltage,
and electrons 80 are accelerated from the source region 32 to the
drain region 34 by the drain-to-source bias voltage, thereby
creating a drain current between the source region 32 and drain
region 34. Some fraction 82 of the electrons 80 will have
sufficient energy to surmount the barrier height of the tunnel
dielectric 60 and reach the floating gate 40, thereby charging the
floating gate 40. By collecting and storing a sufficient amount of
charge on the floating gate 40, the V.sub.T of the transistor 30 is
increased to be above a predetermined level corresponding to a
programmed binary state (e.g., "0"). A memory cell 20 with no
charge on its floating gate 40, and with a correspondingly lower
V.sub.T, is in a non-programmed state (e.g., "1").
[0032] CHE programming is typically used to program NOR-type flash
memories, as schematically illustrated in FIG. 3. In NOR-type flash
memories, the memory cells 20 are connected in parallel with the
drain region 34 of each memory cell 20 connected to a respective
bit-line 90 and with the source region 32 of each memory cell
connected to a common source line (not shown). A select line 92
connects the control gates 50 of a column of memory cells 20, one
on each bit-line 90, allowing several memory cells 20, such as a
byte or a word, to be accessed in parallel. While NOR-type flash
memories provide fast random access, its parallel structure reduces
its memory density.
[0033] Another method of storing charge on the floating gate 40 is
via Fowler-Nordheim (FN) tunneling, schematically illustrated in
FIG. 4, which is a two-terminal process and does not utilize a
drain current 80 between the source 32 and drain 34 regions of the
transistor 20. By applying a high positive voltage (e.g.,
approximately 10 V) to the control gate 50, a high negative voltage
(e.g., approximately -10 V) to the p-well substrate 10 containing
the flash memory cell 20, and floating the source 32 and drain 34
regions, an electric field is created which is sufficient for
electrons 84 to tunnel through the tunnel dielectric 60 from the
p-well substrate 10 and to enter the floating gate 40, thereby
programming the memory cell 20. FN tunneling can occur in any two
terminal device (such as a capacitor) and does not require a
drain-to-source bias voltage. Compared to CHE programming, FN
programming requires higher voltages and has slower programming
speeds (typically requiring greater than 1 ms to program as
compared to a few .mu.s for CHE programming). However, the lower
current densities of FN programming make it easier to use as a
method of programming many flash memory cells at the same time
(i.e., in parallel).
[0034] FN tunneling is typically used to program NAND-type flash
memories, as schematically illustrated in FIG. 5. In NAND-type
flash memories, the memory cells 20 are connected serially to form
strings 96 of memory cells 20, with each string 96 having a string
select gate 98 at one end which connects the string 96 to a
bit-line 100 and a ground select gate at the opposite end of the
string which connects the string to ground (not shown). A select
line 102 connects the control gates 50 of a column of memory cells
20, one on each string 96. Because no outside contact is needed
within a string 96 of memory cells 20, NAND-type flash memories
provide increased memory density. However, because selected memory
cells 20 must be accessed through the other unselected memory cells
20 of the string 96, the reading speed is limited.
[0035] As described above, the traditional programming method for
multilevel memory cells has been to program the memory cell using
short programming pulses of the control gate voltage and drain
voltage. To achieve the narrow V.sub.T distributions, the short
programming pulses are typically interleaved with verification read
pulses in order to closely monitor the programmed level of a given
cell. The short programming pulses and frequent verification steps
make the program operation very time consuming.
[0036] In addition, use of CHE injection to program flash EPROM
devices has the disadvantage of requiring rather high drain
currents in order to generate the charge which is stored on the
floating gate 40. Because the total current available to program
the memory cells is limited at any one time, the high drain
currents constrain the number of memory cells 20 which can be
programmed in parallel to typically a few hundred cells maximum.
One way to reduce the peak programming current, as disclosed by
Keeney, et al. in U.S. Pat. Nos. 5,553,020 and 5,487,033, is to
step the gate voltage of the memory cell 20 as it is being
programmed, in increments from an initial minimum value to a
maximum value based upon the number of levels to program in the
memory cell 20. Each step of the gate voltage is accompanied by a
corresponding pulse of the drain voltage and a verifying pulse
until the desired threshold voltage is reached on the floating
gate. In this way, the drain current can be reduced; however, there
is a corresponding increase in the time required to charge the
floating gate 40 to a given level.
[0037] Similarly, while use of FN tunneling to program flash EPROM
devices does not utilize drain current, stepping up the gate
voltage of the memory cell 20 as it is being programmed reduces the
tunneling current and significantly increases the time required to
program the memory cell 20. The programming current can be further
reduced by applying a reverse back bias between the substrate 10
and the control gate 50 to increase the gate current efficiency, as
is described by Hu, et al., in "Substrate-Current-Induced Hot
Electron (SCIHE) Injection: A New Convergence Scheme For Flash
Memory," IEDM Tech. Dig., pp. 283-286, 1995, which is incorporated
by reference herein.
[0038] The charge Q applied to the floating gate 40 varies with
time during the charging from an initial value of Q.sub.0 (equal to
zero prior to applying the voltages corresponding to CHE injection
at t.sub.0) to a saturation value Q.sub.1, at a later time
t.sub..infin.. FIG. 6 schematically illustrates the variation of
floating gate charge Q as a function of time upon applying voltages
corresponding to CHE injection to the memory cell 20. As more
charge is built up in the floating gate 40, the electric field
which attracts the hot electrons in the channel 36 toward the
floating gate 40 is lessened. Once the floating gate 40 has the
saturation charge Q.sub.1, the hot electrons in the channel 36 are
shielded from the gate voltage V.sub.G and no more hot electrons
reach the floating gate 40. The amount of saturation charge
Q.sub.1, is dependent on the gate voltage V.sub.G, as is apparent
from FIG. 6, which shows three different saturation charge levels
for three different gate voltages. The time to reach the saturation
charge Q.sub.1 does not exhibit a large dependency on the gate
voltage V.sub.G, but it is typically between approximately 100 ns
and 10 .mu.s. The threshold voltage V.sub.T is dependent on the
amount of charge applied to the floating gate 40.
[0039] In certain embodiments of the present invention, the memory
cell 20 is programmed using CHE injection by applying a constant
drain-to-source bias voltage between the drain region 34 and source
region 32 and a gate voltage to the control gate 50 without
verification read pulses. Selected threshold voltages for the
memory cell 20 corresponding to a selected one of the multilevel
programming states are generated by applying different selected
drain-to-source bias voltages during the CHE injection operation.
In one such embodiment, schematically illustrated in FIG. 7A, each
cell has two bits, and hence four states: (00), (01), (10), and
(11). In certain embodiments, one of the four states (e.g., (00))
corresponds to the cell after erase. The magnitude of the drain
voltage V.sub.D is selected to provide a selected threshold voltage
corresponding to one of the three other possible states: (01),
(10), and (11), with the gate voltage V.sub.G and the source
voltage V.sub.S set at constant values (e.g., V.sub.G is set to
approximately +10 V, V.sub.S is set to approximately 0 V). The
amount of charge injected onto the floating gate 40 corresponds to
the potential difference between the source region 32 and the drain
region 34, i.e., the drain-to-source bias voltage. For example,
referring to FIG. 7A, to apply a charge to the floating gate 40 of
a memory cell 20 so that the threshold voltage corresponds to a
(01) state, the drain voltage V.sub.D is set to a voltage
substantially equal to V.sub.D1. Similarly, the (10) state is
achieved by applying a drain voltage that is substantially equal to
V.sub.D2, and the (11) state is achieved by applying a drain
voltage that is substantially equal to V.sub.D3.
[0040] Referring to FIG. 7B, various values of the drain voltage
V.sub.D (e.g., V.sub.D1=4 V; V.sub.D2=5 V; V.sub.D3=6 V) produce
different threshold voltages Vt after a fixed program time. By
halting the programming of a cell after a fixed time, embodiments
of the present invention achieve selected multilevel programming
states while avoiding the verification steps of the prior art.
[0041] In other embodiments of the present invention, selected
threshold voltages corresponding to selected multilevel programming
states are generated by applying different gate voltages during the
CHE injection operation. As schematically illustrated in FIG. 8,
the memory cell 20 is programmed using CHE injection by setting the
drain voltage and the source voltage to constant values (e.g.,
V.sub.D of approximately +5 V and V.sub.S of approximately 0 V).
The magnitude of the gate voltage V.sub.G is selected to provide a
selected threshold voltage corresponding to one of the four
possible multilevel states. The amount of charge injected onto the
floating gate 40 corresponds to the gate voltage. For example,
referring to FIG. 8, to apply a charge to the floating gate 40 of a
memory cell 20 so that the threshold voltage corresponds to a (01)
state, the gate voltage V.sub.G is set to a voltage substantially
equal to V.sub.G1 (e.g., V.sub.G1=6 V). Similarly, the (10) state
is achieved by applying a gate voltage substantially equal to
V.sub.G2 (e.g., V.sub.G2=8 V), and the (11) state is achieved by
applying a gate voltage substantially equal to V.sub.G3 (e.g.,
V.sub.G3=10 V).
[0042] In still other embodiments of the present invention, the
time profile of the applied voltages, as schematically illustrated
in FIG. 9, is utilized to set the threshold voltage to one of the
four possible states. A selected threshold voltage corresponding to
a selected multilevel programming state is generated by applying
voltages comprising at least one voltage pulse, with a selected
pulse period during the CHE injection operation. For example,
referring to FIG. 9, to apply a charge to the floating gate 40 of a
memory cell 20 so that the threshold voltage corresponds to a (01)
state, a single gate voltage pulse V.sub.G with a magnitude of
approximately 10 V and a period of approximately (t.sub.1-t.sub.0)
is applied to the control gate 50 while the source voltage and
drain voltage are set at constant values (e.g., V.sub.S of
approximately 0 V, V.sub.D of approximately 5 V). Similarly, the
(10) state is achieved by applying a voltage pulse with a period
approximately equal to (t.sub.2-t.sub.0), and the (11) state is
achieved by applying a voltage pulse with a period approximately
equal to (t.sub.3-t.sub.0). In certain embodiments, the total time
in which the appropriate voltages for CHE injection are applied to
the memory cell 20 are distributed among a plurality of pulses
(i.e., the sum of the pulse periods of the plurality of pulses has
the required time duration to achieve the desired state of the
memory cell 20). The voltage pulse of the gate voltage V.sub.G
preferably has a period of between approximately 1 ns and
approximately 10 .mu.s. For example, V.sub.G can be applied for 2
ns to program the (01) state, 0.1 .mu.s to program the (10) state,
and 2 .mu.s to program the (11) state.
[0043] Alternatively, in other embodiments, the drain voltage
V.sub.D can be pulsed and the gate voltage V.sub.G selected to
generate a selected threshold voltage corresponding to a selected
multilevel programming state. For example, V.sub.D can be applied
for 2 ns to program the (01) state, 0.1 .mu.s to program the (10)
state, and 2 .mu.s to program the (11) state. The voltage pulse of
the drain voltage V.sub.D preferably has a period of between
approximately 1 ns and approximately 10 .mu.s. Alternatively, in
still other embodiments, the drain voltage V.sub.D can be pulsed,
the source voltage V.sub.S can be pulsed, or any combination of the
gate voltage V.sub.G, drain voltage V.sub.D, and source voltage
V.sub.S can be pulsed to set the threshold voltage to one of the
four possible states.
[0044] In still other embodiments of the present invention,
selected threshold voltages corresponding to selected multilevel
programming states are generated by ramping the voltages applied to
the memory cell 20 during the CHE injection operation without
applying verification pulses. As described above, as charge
accumulates in the floating gate 40, the hot electrons in the
channel 36 are increasingly shielded from the gate voltage V.sub.G,
thereby reducing the rate of charge injection and eventually
reaching a saturation level corresponding to a saturation threshold
voltage. When applying a constant gate voltage V.sub.G, as
schematically illustrated in FIG. 10, there will be a high drain
current at the beginning of the programming, due to the large
potential difference between the floating gate 40 and the channel
36. By ramping the gate voltage V.sub.G during the CHE injection
from an initial magnitude to a final magnitude greater than the
initial magnitude, the drain current will be constant over an
extended period of time, at a lower level, as schematically
illustrated in FIG. 10. The saturation threshold will be determined
by both the drain voltage, and the final gate voltage at the end of
the ramp.
[0045] In certain embodiments, a ramped gate voltage V.sub.G is
used with different values of the drain voltage V.sub.D, the values
of the applied drain voltage V.sub.D selected to generate selected
threshold voltages for the memory cell 20 corresponding to selected
multilevel programming states. Such embodiments are similar to
those discussed in relation to FIG. 7, but with lessened drain
currents due to the ramping of the gate voltage V.sub.G, so that a
large number of cells can be programmed in parallel. In certain
other embodiments, a ramped gate voltage V.sub.G is used with
different pulse periods of the drain voltage V.sub.D, the pulse
periods selected to generate selected threshold voltages
corresponding to selected multilevel programming states of the
memory cell 20. Such embodiments are similar to those discussed in
relation to FIG. 9, but with lessened drain currents due to the
ramping of the gate voltage V.sub.G, so that a large number of
cells can be programmed in parallel. In still other embodiments,
the value of the final gate voltage V.sub.G during the ramping is
selected to generate selected threshold voltages corresponding to
selected multilevel programming states of the memory cell 20. Such
embodiments are similar to those discussed in relation to FIG. 8,
but with lessened drain currents due to the ramping of the gate
voltage V.sub.G, and again a large number of cells can be
programmed at the same time. For example, 7 V, 9 V, and 11 V can be
used as the final gate voltage for programmed states (01), (10),
and (11), respectively.
[0046] As schematically illustrated in FIG. 11, by selecting the
rate of ramping of the gate voltage V.sub.G, selected threshold
voltages corresponding to selected multilevel programming states of
the memory cell 20 can be generated. The amount of charge on the
floating gate 40 after CHE injection for a time (t.sub.1-t.sub.0)
is dependent on the ramping rate of the gate voltage V.sub.G.
Slower ramping rates correspond to slower charge injection on the
floating gate 40, and less charge on the floating gate 40 after a
known time (t.sub.1t.sub.0). Therefore, the ramping rate of V.sub.G
can be selected to yield a particular amount of charge on the
floating gate 40 after a known charging time, thereby setting the
threshold voltage to one of the four possible states. For example,
within 1 ms, the gate voltage can be ramped from 0 V to 6 V, 8 V,
and 10 V for programmed states (01), (10), and (11), respectively.
In certain embodiments, the injection of charge is performed for
the known time (t.sub.1-t.sub.0) by pulsing the voltages applied to
the memory cell 20 (e.g., pulsing the drain voltage V.sub.D, the
source voltage V.sub.S, the gate voltage V.sub.G, or any
combination of the gate voltage V.sub.G, drain voltage V.sub.D, and
source voltage V.sub.S).
[0047] In certain other embodiments, where the drain voltage does
not have a constant magnitude, the drain region 34 can be connected
to a constant current source. In this way, the drain current is
maintained to have a substantially constant magnitude throughout
the charging operation. The amount of charge injected onto the
floating gate 40 varies with the amount of drain current, so
multilevel states are generated by using different drain currents
during the CHE injection operation. Such a constant drain current
can be utilized with any of the above-described embodiments.
[0048] In still other embodiments, a reverse back bias can be
applied between the substrate 10 and control gate 50 to increase
the fraction of hot electrons which are injected from the channel
36 to the floating gate 40. When combined with the above-described
embodiments, the reverse back bias improves the programming
efficiency and yields faster convergence to the desired saturation
threshold voltage. Values of the back bias compatible with
embodiments of the present invention range from approximately 0 V
to approximately -4 V.
[0049] Different voltages on the drain region 34 can be achieved by
connecting a transistor 110 in series between the drain region 34
of the memory cell 20 and a drain voltage generator (not shown).
For example, as schematically illustrated in FIG. 12, a transistor
110 is connected on a bit line in series to the drain region 34,
the transistor 110 having a transistor control gate 112. Multilevel
states are achieved by using different control voltages on the
transistor control gate 112 during the programming operation to
adjust a voltage applied to the drain region 34 of the memory cell
20. Such a transistor 110 can be utilized with any of the
above-described embodiments.
[0050] In alternative embodiments, as schematically illustrated in
FIG. 13, a plurality of pairs of transistors 120 and resistors 124,
in which each transistor 120 has a transistor control gate 122 and
is in series with a corresponding resistor 124, are connected in
parallel between the drain region 34 of the memory cell 20 and a
drain voltage generator (not shown). The resistors 124 each have a
different resistance, and multilevel states are achieved by
selectively applying a control voltage to at least one transistor
120, thereby applying different voltages to the drain region 34
during the programming operation. Such a plurality of pairs of
transistors 120 and resistors 122 can be utilized with any of the
above-described embodiments.
[0051] In the embodiments described above, the memory cells are
initially discharged or erased, and the appropriate amount of
charge is applied to the floating gate 40 to correspond to one of
the multilevel programming states. In still other embodiments
compatible with the present invention, the memory cells are
initially charged to a selected value, and then discharged by a
selected amount, resulting in the appropriate amount of charge on
the floating gate 40 to correspond to one of the multilevel
programming states.
[0052] Although described above in connection with particular
embodiments of the present invention, it should be understood the
descriptions of the embodiments are illustrative of the invention
and are not intended to be limiting. Various modifications and
applications may occur to those skilled in the art without
departing from the true spirit and scope of the invention as
defined in the appended claims.
* * * * *