U.S. patent application number 10/251889 was filed with the patent office on 2003-01-30 for high speed digital-to -analog converter.
Invention is credited to Ganesan, Bharathi, Yeap, Tet Hin.
Application Number | 20030020644 10/251889 |
Document ID | / |
Family ID | 4163106 |
Filed Date | 2003-01-30 |
United States Patent
Application |
20030020644 |
Kind Code |
A1 |
Yeap, Tet Hin ; et
al. |
January 30, 2003 |
HIGH SPEED DIGITAL-TO -ANALOG CONVERTER
Abstract
An high speed analog-to-digital converter, for converting an
analog input signal (u(t)) with a maximum frequency (F.sub.max) to
a digital output signal (x(n)) with an output sampling rate
(F.sub.s) at least double the maximum frequency (F.sub.max),
comprises a plurality of analog narrowband filters
(F.sub.o-F.sub.M-1) for filtering the analog input signal (u(t)) to
produce a corresponding plurality of narrowband signals
(X.sub.0-X.sub.M-1). Each narrowband filter has a passband. The sum
of the gains of the narrowband filters at any frequency within an
operating frequency band of the plurality of narrowband filters is
substantially unity. Each of a corresponding plurality of
analog-to-digital converter units (AD.sub.0-AD.sub.M-1) comprises a
sample-and-hold device (SH) and a quantizer (Q). The
sample-and-hold devices are clocked by a corresponding plurality of
clock signals (.PHI..sub.0-.PHI..sub.M-1) respectively, each of the
plurality of clock signals having a frequency at least double the
bandwidth of the corresponding narrowband filter and an integer
division of said predetermined sampling rate. The converter also
comprises sampling and summing circuitry for sampling the outputs
of the analog-to-digital converter units sequentially at the
predetermined sampling rate (Fs) and summing the resulting sampled
signals to produce the digital output signal (x(n)). The
frequencies of the plurality of clock signals, and their
phase-displacements relative to the output sampling clock signal,
are such that each sample of the analog-to-digital converter output
signal corresponds to a sampling edge of a different one of the
sample-and-hold clock signal.
Inventors: |
Yeap, Tet Hin; (Ottawa,
CA) ; Ganesan, Bharathi; (Nepean, CA) |
Correspondence
Address: |
Adams Patent & Trademark Agency
P.O. Box 11100, Station H
Ottawa
ON
K2H 7T8
CA
|
Family ID: |
4163106 |
Appl. No.: |
10/251889 |
Filed: |
September 23, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10251889 |
Sep 23, 2002 |
|
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09466839 |
Dec 20, 1999 |
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6476749 |
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Current U.S.
Class: |
341/144 |
Current CPC
Class: |
H03M 1/121 20130101;
H03M 1/662 20130101 |
Class at
Publication: |
341/144 |
International
Class: |
H03M 001/66 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 21, 1998 |
CA |
2,256,779 |
Claims
What is claimed is:
1. An analog-to-digital converter for converting an analog input
signal (u(t)) having a frequency up to a predetermined maximum
frequency (F.sub.max) to a digital output signal (x(n)) having a
predetermined output sampling rate (F.sub.s) equal to at least
double the maximum frequency (F.sub.max), the analog-to-digital
converter comprising: (i) a plurality of analog narrowband filters
(F.sub.0-F.sub.M-1;F.sub.L,F.sub.H- ,F.sub.P) for filtering the
analog input signal (u(t)) to produce a corresponding plurality of
narrowband signals (X.sub.0-X.sub.M-1; X.sub.L,X.sub.H,X.sub.P),
each narrowband filter having a passband, the sum of the gains of
the narrowband filters at any frequency within an operating
frequency band of the plurality of narrowband filters being
substantially unity; (ii) a corresponding plurality of
sample-and-hold devices (SH.sub.0-SH.sub.M-1;
SH.sub.L,SH.sub.H,SH.sub.P) clocked by a plurality of clock signals
(.PHI..sub.0-.PHI..sub.M-1), respectively, each of the plurality of
clock signals having a frequency at least double the bandwidth of
the corresponding narrowband filter; and (iii) a plurality of
quantizers (Q.sub.0-Q.sub.M-1; Q.sub.L,Q.sub.H,Q.sub.P) each
connected to a respective one of the sample-and-hold devices
(SH.sub.0-SH.sub.M-1; SH.sub.L,SH.sub.H,SH.sub.P) and operable to
provide a digitized value of each sample held by the corresponding
sample-and-hold device; (iv) sampling and summing means
(12,R.sub.0-R.sub.M-1; 12.sub.1,12.sub.2,14; 12,14.sub.1,14.sub.2;
R.sub.L,R.sub.H,R.sub.P) for sampling and summing the outputs of
the quantizers to produce said digital output signal (x(n)), the
sampling being carried out sequentially at the predetermined
sampling rate (Fs) in response to an output clock signal (CLK), the
frequencies and phase-relationships of the plurality of clock
signals (.PHI..sub.0-.PHI..sub.M-1) being such that each sample
point of the output clock signal coincides with a sample point of
one of the plurality of clock signals.
2. An analog-to-digital converter according to claim 1, wherein the
sampling-and-summing means (12, 12.sub.1, 12.sub.2 14, 14.sub.1,
14.sub.2, R.sub.0-R.sub.M-1,) comprises means (R.sub.L-R.sub.H) for
sampling the outputs of the quantizers at the predetermined rate
(F.sub.s) and means (12') for summing the samples from the sampling
means (R.sub.0-R.sub.M-1).
3. An analog-to-digital converter according to claim 1, wherein the
sampling-and-summing means (12, 12.sub.1, 12.sub.2 14, 14.sub.1,
14.sub.2, R.sub.0-R.sub.M-1,) comprises summing means
(12.sub.1-12.sub.2) for summing digitized values from the plurality
of quantizers and sampling means (14) for sampling the summed
digitized values.
4. An analog-to-digital converter according to claim 1, wherein the
plurality of narrowband filters all have the same bandwidth equal
to one half of said predetermined output sampling rate (Fs) divided
by the number (M) of said narrowband signals (X.sub.0-X.sub.M-1),
and said plurality of clock signals (.PHI..sub.0-.PHI..sub.M-1) all
have the same frequency and are uniformly phase-displaced relative
to each other by a phase angle equal to one cycle of said same
frequency divided by the number (M) of said plurality of clock
signals.
5. An analog-to-digital converter according to claim 1, wherein the
plurality of analog narrowband filters have non-uniform bandwidths
for filtering the analog input signal (u(t)) to produce a
corresponding plurality of narrowband signals (X.sub.0-X.sub.M-1)
having different bandwidths.
6. A digital-to-analog converter, for converting a digital input
signal (x(n)) into an analog output signal (u(t)), comprising an
analog synthesis filter bank (DA.sub.0-DA.sub.M-1) having a
plurality of inputs and a plurality of outputs, the plurality of
outputs being connected in common to a summing device (2) for
summing respective output signals from the synthesis filter bank to
provide an analog output signal (u(t)), and a plurality of
digital-to-analog converter units (DA.sub.0-DA.sub.M-1) having
their inputs connected in common to receive the digital input
signal (x(n)) and each having its output connected to a respective
one of said plurality of inputs of the synthesis filter bank
(DA.sub.0-DA.sub.M-1), the digital-to-analog converter units
(DA.sub.0-DA.sub.M-1) being clocked by a plurality of clock signals
(.PHI..sub.0-.PHI..sub.M-1), respectively, the frequencies and
relative phase differences of the plurality of clock signals
((.PHI..sub.0-.PHI..sub.M-1) being arranged so that a sampling
point of the input digital signal (x(n)) coincides with a sampling
point of one of the plurality of clock signals
(.PHI..sub.0-.PHI..sub.M-1).
Description
BACKGROUND OF THE INVENTION
[0001] 1. TECHNICAL FIELD
[0002] The invention relates to analog-to-digital and
digital-to-analog converters, and is especially applicable to high
speed analog-to-digital converters for wireless communications.
[0003] 2. BACKGROUND ART
[0004] High speed analog-to-digital converters and
digital-to-analog converters are used in wireless
telecommunications systems, where digital receivers are preferred,
for high speed instruments, for example oscilloscopes, and for
various other applications. Typically, an analog-to-digital
converter comprises a clock-driven sample-and-hold circuit, which
samples the analog signal at intervals and holds the sample values,
and a quantizer which converts each quantized sample into a digital
numerical representation. Typically, the quantizer will compare the
sample value with a number of different voltage thresholds in order
to determine the value of the sample to within a fairly small band
and represent it digitally. It is desirable to provide high
resolution as well as high speed, but these tend to be
incompatible. Higher resolutions entail more comparisons, i.e. with
a larger number of discrete voltage thresholds, which will increase
the processing time required to perform the calculations.
[0005] One of the fastest A/D converters, known as the "Flash ADC",
applies the sample value to a bank of comparators, each of which
compares it with a different reference or threshold value. The
outputs of the bank of comparators are applied to a Gray code
decoder. Unfortunately, such Flash A/D converters require a ladder
network of accurate resistors, preferably laser-trimmed, and so are
expensive to produce. Consequently, most high speed devices
presently available commercially have limited resolution are able
to digitize a 500 MHz analog signal. Current applications, however,
may require conversion of signals at 1 GHz and higher.
[0006] In order to convert higher frequency signals, it has been
proposed to time-interleave two or more such high speed A/D
converters. In a paper entitled "Time Interleaved Converter
Arrays", IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 6,
December 1980, William C. Black, Jr., et al, disclosed a time
interleaved A/D converter which used four sample-and-hold circuits
and four quantizers and a multiplexer to obtain analog-to-digital
conversion of an analog signal having a frequency four times that
of the signal handled by each converter. In a paper entitled "A
1-GHz 6-bit ADC System", IEEE Journal of Solid-State Circuits, Vol.
SC-22, No. 6, December 1987, Ken Poulton et al disclosed a
time-interleaved analog-to-digital converter capable of a sampling
rate of one Gigasample per second using four sample-and-hold
circuits and four quantizers. However, instead of a multiplexer,
Poulton et al's converter used four memory banks read sequentially.
In both cases, the time-interleaved converter arrays used offset
clock signals for the four different sample-and-hold circuits.
Black et al's multiplexer and Poulton et al's memory readout,
however, operated at the speed of the system clock which was four
times the speed of the individual sample-and-hold clock signals.
Consequently, the sample-and-hold circuits operated at only one
quarter of the overall sampling rate. A disadvantage of such
time-interleaved converters is that phase jitter is produced
because the offset clock signals are not precisely 90 degrees out
of phase with each other, and errors arise because of variations in
the high-speed clock which operates the multiplexer or memory
readout. Also, the sample-and-hold circuits each see the full
wideband signal, which places limitations on their
capabilities.
[0007] The problem of obtaining both high speed and high resolution
has been addressed by a number of people. In a paper entitled "High
Speed A/D Conversion Using QMF Banks", Proceedings of IEEE
International Symposium on Circuits and Systems (1990), Petraglia
et al disclosed a technique for performing A/D conversion using
quadrature mirror filter banks. Petraglia et al used an analysis
filter bank which comprised a bank of switched capacitance filters
and a bank of downsamplers. The downsampled subband signals were
converted by a bank of A/D converter units and then applied to a
synthesis filter bank which comprised a bank of upsamplers and a
bank of digital filters. Although Petraglia et al's approach avoids
the need for offset clock signals, and hence avoids the phase
jitter problem, it is not entirely satisfactory because it uses
switched capacitance filters. Discrete time-switched capacitance
filters limit the speed and introduce switching noise, reducing
signal-to-noise ratio. Reducing signal-to-noise ratio reduces
resolution.
[0008] U.S. Pat. No. 5,568,142 issued Oct. 22, 1996 (Velazquez et
al), disclosed an A/D converter using an analog analysis filter
bank and a digital synthesis filter bank. The use of an analog
(continuous time) analysis filter bank avoids the problems
associated with discrete time switched capacitor filters. However,
with present technology, it would be extremely difficult to achieve
1 Gigasample per second conversion rates with the analog-to-digital
converter disclosed by Velazquez et al. In particular, Velazquez et
al use several 64 tap digital filters in the synthesis filter bank.
Hence, with a rate of 1 Gigasample per second, each digital filter
would have to perform 65.times.10.sup.9 multiplication operations
per second and 64.times.10.sup.9 addition operations per second.
With current technology, this number of operations is not
feasible.
SUMMARY OF THE INVENTION
[0009] The present invention seeks to eliminate, or at least
mitigate, the disadvantages of these known analog-to-digital
converters.
[0010] According to one aspect of the present invention, there is
provided an analog-to-digital converter for converting an analog
input signal (u(t)) having a frequency up to a predetermined
maximum frequency (F.sub.max) to a digital output signal (x(n))
having a predetermined output sampling rate (F.sub.s) equal to at
least double the maximum frequency (F.sub.max), the
analog-to-digital converter comprising a plurality of analog
narrowband filters (F.sub.0-F.sub.M-1; F.sub.L,F.sub.H,F.sub.P) for
filtering the analog input signal (u(t)) to produce a corresponding
plurality of narrowband signals (X.sub.0-X.sub.M-1;
X.sub.L,X.sub.H,X.sub.P), each narrowband filter having a passband,
the sum of the gains of the narrowband filters at any frequency
within the passbands of the plurality of narrowband filters being
substantially unity, a corresponding plurality of sample-and-hold
devices (SH.sub.0-SH.sub.M-1; SH.sub.L,SH.sub.H,SH.sub.P) clocked
by a plurality of clock signals (.PHI..sub.0-.PHI..sub.M-1;
.PHI..sub.1,.PHI..sub.2), respectively, each of the plurality of
clock signals having a frequency at least double the bandwidth of
the corresponding narrowband filter, and a plurality of quantizers
(Q.sub.0-Q.sub.M-1) each connected to a respective one of the
sample-and-hold devices (SH.sub.0-SH.sub.M-1) and operable to
provide a digitized value of each sample held by the corresponding
sample-and-hold device, the converter further comprising sampling
and summing means (12,R.sub.0-R.sub.M-1; 12.sub.1,12.sub.2,14;
12,14.sub.1,14.sub.2; R.sub.L,R.sub.H,R.sub.P) for sampling and
summing the outputs of the quantizers to produce said digital
output signal (x(n)), the sampling being carried out sequentially
at the predetermined sampling rate (Fs) in response to an output
clock signal (CLK; .PHI..sub.2), the frequencies and
phase-relationships of the plurality of clock signals
(.PHI..sub.0-.PHI..sub.M-1; .PHI..sub.1,.PHI..sub.2,.PHI..sub.3)
being such that each sample point of the output clock signal (CLK;
.PHI..sub.2) coincides with a sample point of one of the plurality
of clock signals (.PHI..sub.0-.PHI..sub.M-1;
.PHI..sub.1,.PHI..sub.2; .PHI..sub.1,.PHI..sub.2,.PHI..sub.3)
[0011] In one preferred embodiment of the invention, the plurality
of narrowband filters all have the same bandwidth equal to one half
of the predetermined output sampling rate (Fs) divided by the
number (M) of said narrowband signals, and the plurality of clock
signals (.PHI..sub.0-.PHI..sub.M-1) all have the same frequency
equal to the predetermined sampling rate (Fs) divided by the number
(M) of narrowband signals and are phase-displaced relative to each
other by one cycle of such same frequency divided by the number (M)
of clock signals.
[0012] In an alternative embodiment, the plurality of analog
narrowband filters have non-uniform bandwidths for filtering the
analog input signal (u(t)) to produce a corresponding plurality of
narrowband signals (X.sub.0-X.sub.M-1) having different
bandwidths.
[0013] The sample-and-hold devices perform the downsampling
function of the usual analysis filter bank. Consequently, providing
the narrowband filters meet certain requirements, the plurality of
narrowband filters and the plurality of sample-and-hold devices
form an analysis filter bank. An important one of the requirements
is that, at each frequency in the operating band, the sum of the
squares of the magnitudes of the frequency response is equal to
unity.
[0014] The foregoing and other objects, features, aspects and
advantages of the present invention will become more apparent from
the following detailed description, taken in conjunction with the
accompanying drawings, of preferred embodiments of the invention,
which are described by way of example only.
BRIEF DESCRIPTION OF DRAWINGS:
[0015] FIG. 1 is a block schematic representation of a generic
M-band analog-to-digital converter according to one aspect of the
invention;
[0016] FIG. 2 is a block schematic diagram of a two-band uniform
resolution analog-to-digital converter embodying the invention;
[0017] FIG. 3 is a timing diagram for the analog-to-digital
converter of FIG. 2;
[0018] FIG. 4 is a detail diagram illustrating a modification to
the output portion of the analog-to-digital converter of FIG.
2;
[0019] FIG. 5 is a block schematic representation of a second
two-band uniform resolution analog-to-digital converter embodying
the invention;
[0020] FIG. 6 is a timing diagram for the analog-to-digital
converter of FIG. 5;
[0021] FIG. 7 is a block schematic representation of a
multi-resolution analog-to-digital converter embodying the
invention;
[0022] FIG. 8 is a timing diagram for the multi-resolution
analog-to-digital converter of FIG. 7;
[0023] FIG. 9 illustrates an octave band filter bank suitable for
use in the analog-to-digital converter of FIG. 8; and
[0024] FIG. 10 is a schematic diagram of an M-band
digital-to-analog converter according to a second aspect of the
invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
[0025] Referring to FIG. 1, a high speed analog-to-digital
converter for providing a digital output signal x(n) from an analog
input signal u(t) comprises a bank of M narrowband analog filters
F.sub.0 to F.sub.M-1, the input terminals of which are connected in
common to an input terminal 11 to receive the analog input signal
u(t). The maximum frequency of input signal u(t) is F.sub.max.
There is a certain degree of overlap between the frequency spectra
of the analog filters F.sub.0 to F.sub.M-1, for reasons which will
be explained in more detail later. The output terminals of the
analog filters F.sub.0 to F.sub.M-1 are each connected to a
corresponding one of the inputs of a plurality of sample-and-hold
circuits SH.sub.0 to SH.sub.M-1, respectively, which have their
output terminals connected to a corresponding plurality of
quantizers Q.sub.0 to Q.sub.M-1, respectively, which convert each
sample to a corresponding digitized value. Each combination of a
sample-and-hold circuit and a quantizer itself constitutes an
analog-to-digital converter. Consequently, the sample-and-hold
circuits and associated quantizers comprise a bank of
analog-to-digital converter units AD.sub.0 to AD.sub.M-1 which may
be of known construction, for example as used in high speed
oscilloscopes. The sample-and-hold circuits SH.sub.0 to SH.sub.M-1
are clocked by clock signals .PHI..sub.0 to .PHI..sub.M-1,
respectively. The digitized values output from the quantizers
Q.sub.0 to Q.sub.M-1 are buffered by a plurality of registers
R.sub.0 to R.sub.M-1, respectively, each clocked by a master clock
signal CLK having a frequency equal to a predetermined sample rate
Fs for the digital output signal x(n). A summing device 12 sums the
buffered digitized values. The output from the summer 12 is passed
through an output register R.sub.out which buffers the digital
output signal x(n). The output register R.sub.out is clocked by a
clock .sub.{overscore (CLK)} which is the inverse of the master
clock CLK. The clock signals .PHI..sub.0 to .PHI..sub.M-1 are
derived from the master clock signal CLK so that each sampling edge
of the master clock signal CLK coincides with a sampling edge of
one of the plurality clock signals.
[0026] In order to meet Nyquist criteria, the output sample rate Fs
is at least double the maximum input frequency F.sub.max.
[0027] Providing the narrowband filters F.sub.0 to F.sub.M-1 meet
requirements of unity gain mentioned above the bank of narrowband
filters and the bank of sample-and-hold devices SH.sub.0 to
SH.sub.M-1 form an analysis filter bank. Hence, when the narrowband
signals X.sub.0 to X.sub.M-1, from analog filters F.sub.0 to
F.sub.M-1 respectively, have been sampled by sample-and-hold
circuits SH.sub.0 to SH.sub.M-1, they comprise subband signals.
[0028] The subband signals are low pass, band pass and high pass
signals, each having its own spectral information, and each having
a sample rate determined by the predetermined sample rate (Fs) of
the output digital signal x(n) and the bandwidth of the
corresponding filter relative to maximum input signal frequency
F.sub.max. For example, if maximum frequency F.sub.max is equal to
1 GHz., Fs is equal to 2 Gigasamples/second, and the filter bank
comprises two equal filter which have the same bandwidth of 500
MHz., each of the sample-and-hold circuits will operate at 1
Gigasamples/second. Each sample-and-hold circuit would hold the
sample value for two periods of the master clock signal CLK.
[0029] The mathematical input-output relationship of the M band
embodiment of the invention shown in FIG. 1, and additional
requirements which, preferably, are met by the narrowband filters,
will now be described, for the case where the narrowband filter
bank is uniform. In the time domain, signals are represented in
lower case, e.g. u(t), x(n). In the frequency domain, upper case is
used, e.g. U(j.OMEGA.), X(e.sup.j.omega.).
[0030] In the frequency domain, the result of filtering an input
signal U(j.OMEGA.), band-limited to .OMEGA..sub.k rad/sec (k=0 . .
. M-1), through each of the analog narrowband filters F.sub.0 to
F.sub.M-1 whose transfer function is F.sub.k(j.OMEGA.) is
X.sub.k(j.OMEGA.) and is given by,
X.sub.k(j.OMEGA.)=U(j.OMEGA.) F.sub.k(j.OMEGA.) (1)
[0031] Errors for each of the A/D converter units AD.sub.0 to
AD.sub.M-1 are modelled as gain error a.sub.k and DC offset error
b.sub.k. Hence, in the time domain, the relationship between the
output signal d.sub.k(n) of an ideal A/D converter unit AD and the
corresponding narrowband signal x.sub.k(n) is given by:
d.sub.k(n)=(1+a.sub.k)x.sub.k(n)+b.sub.k (2)
[0032] In the frequency domain, aliasing error will be seen along
with the gain error and D.C. offset error. Hence, in the frequency
domain, the output signal D.sub.k(e.sup.jw) from each of the A/D
converter units AD.sub.0 to AD.sub.M-1, is given by the
expression:-- 1 D k ( e j ) = 1 + a k T l = 0 M - 1 X k ( j T - j2
l T ) + b k l = 0 M - 1 2 ( - 2 l ) ( 3 )
[0033] where .delta. is a delta function, T is the sampling period
given by 2 T = M k ,
[0034] and the term 3 X k ( j2 l T )
[0035] is the aliasing error.
[0036] Substituting for X.sub.k(j.OMEGA.) from equation (1) gives:
4 D k ( e j ) = 1 + a k T l = 0 M - 1 U ( j T - j2 l T ) F k ( j T
- j2 l T ) + b k l = 0 M - 1 2 ( - 2 l ) ( 4 )
[0037] The wideband digital output signal X(e.sup.j.OMEGA.)
obtained by summing the signals D.sub.k(e.sup.J.OMEGA.) from the
A/D converter units AD.sub.0 to AD.sub.M-1 is given by: 5 X ( j ) =
k = 0 M - 1 D k ( j ) ( 5 )
[0038] Combining equations (4) and (5) gives: 6 X ( j ) = k = 0 M -
1 1 + a k T l = 0 M - 1 U ( j T - j2 l T ) F k ( j T - j2 l T ) + k
= 0 M - 1 b k l = 0 M - 1 2 ( - 2 l ) ( 6 )
[0039] The summation terms in equation (6) can be rearranged and
written as, 7 X ( j ) = k = 0 M - 1 U ( j T - j2 l T ) ( k = 0 M -
1 l + a k T F k ( j T - j2 l T ) ) + k = 0 M - 1 b k l = 0 M - 1 2
( - 2 l ) ( 7 )
[0040] Equation (7) can be simplified by substituting functions
A.sub.p(e.sup.j.OMEGA.) and .beta., to give: 8 X ( j ) = p = 0 M -
1 U ( j T - j2 p T ) A p ( j ) + ( 8 )
[0041] where A.sub.p(e.sup.jw) is the aliasing function for the
whole high speed A/D converter and is given by the expression: 9 A
p ( j ) = k = 0 M - 1 1 + a k T F k ( j T - j2 p T ) , p = 0 M - 1
( 9 )
[0042] and the total DC offset error .beta. for the whole
high-speed A/D converter is given by the expression: 10 = 2 k = 0 M
- 1 b k p = 0 M - 1 ( M - 2 p ) . ( 10 )
[0043] The condition for avoiding aliasing is:
A.sub.o(e.sup.j.OMEGA.)=e.sup.j.OMEGA.d p=0 (11)
A.sub.p(e.sup.j.OMEGA.)=0 p=1 . . . (M-1) (12)
[0044] where d is the overall system delay, i.e. for the whole
high-speed A/D converter. The condition for zero D.C. offset error
is :
[0045] .beta.=0
[0046] In order for the digital output signal x(n) to be a
so-called perfect or pseudo-perfect representation of the input
signal u(n), the analysis filter bank formed by the analog filters
F.sub.0 to F.sub.M-1 and sample-and-hold circuits SH.sub.0 to
SH.sub.M-1 should be designed so that, at any frequency within the
operating range, zero to F.sub.max, the gains of the filters sum to
unity, i.e. .vertline.F.sub.0(j.OMEGA.).vertl-
ine..sup.2+.vertline.F.sub.1(j.OMEGA.).vertline..sup.2+ . . . ,
+.vertline.F.sub.M-1(j.OMEGA.).vertline..sup.2.congruent.1
[0047] This is analogous to the output of an analysis filter bank
being capable of perfect or pseudo-perfect reconstruction using a
corresponding synthesis filter bank.
[0048] The frequencies and relative phase-displacements of the
clock signals .PHI..sub.0 to .PHI..sub.M-1 are selected so that
every sample point of the output signal corresponds to a sample
point of one of the clock signals .PHI..sub.0 to .PHI..sub.M-1.
Where the analog filters F.sub.0-F.sub.M-1 have the same bandwidth,
the clock signals have the same frequency and are phase-shifted
uniformly relative to each other by 2.pi./M radians so as to
subdivide each clock period of the input signal u(t) into M equal
segments. Hence, for a two-band A-to-D converter, there would be
two sample-and-hold circuits clocked by two clock signals
180.degree. out of phase with each other, the data being stored on
the rising edges of each of the clock signals. For a four-band
converter, the clock signals would be phased at 90.degree.
increments relative to each other.
[0049] The implementation and operation of a two-band high speed
analog-to-digital converter will now be described with reference to
FIGS. 2 and 3.
[0050] Referring to FIG. 2, the high speed analog-to-digital
converter comprises a high-pass filter F.sub.H and a low-pass
filter F.sub.L with their inputs connected in common to an input
terminal 11 to receive the input signal u(t) to be digitized. The
narrowband signal X.sub.H from the high-pass filter F.sub.H is
applied to the respective inputs of a pair of sample-and-hold
circuits SH.sub.0 and SH.sub.1 which are clocked by clock signals
.PHI..sub.1 and .PHI..sub.2, respectively, which are in antiphase
relative to each other so that the sample-and-hold circuits
SH.sub.0 and SH.sub.1 operate in time-interleaved manner. The
samples from the sample-and-hold circuits SH.sub.0 and SH.sub.1 are
applied to quantizers Q.sub.0 and Q.sub.1, respectively. In a
similar manner, the narrowband signal X.sub.L from lowpass filter
F.sub.L is applied to the inputs of a second pair of
sample-and-hold circuits SH.sub.2 and SH.sub.3 which also are
clocked by clock signals .PHI..sub.1 and .PHI..sub.2, respectively.
The samples from sample-and-hold circuits SH.sub.2 and SH.sub.3 are
applied to quantizers Q.sub.2 and Q.sub.3, respectively.
[0051] The quantized values L.sub.1 and H.sub.1 from quantizers
Q.sub.0 and Q.sub.1, respectively, are summed by a first summing
device 12.sub.1 and the quantized values L.sub.2 and H.sub.2 from
quantizers Q.sub.1 and Q.sub.2, respectively, are summed by summing
device 12.sub.2. A switching device 14, conveniently a time
multiplexer, clocked by clock signal .PHI..sub.2, which here serves
also as the output clock signal, selects the outputs of summers
12.sub.1, and 12.sub.2, alternately, for output as digitized output
signal x(n). The switching device 14 is clocked so that, when clock
signal .PHI..sub.2 is high, the output of summer 12.sub.2 is
selected. Conversely, when the clock signal .PHI..sub.2 is low,
clock signal .PHI..sub.1 is high and the output is taken from
summer 12.sub.1. Hence, the digitized values in summers 12.sub.1
and 12.sub.2 are sampled on both the rising and falling edges of
clock signal .PHI..sub.2, which is equivalent to sampling on the
rising edges of main clock signal CLK.
[0052] Operation of the two-band analog-to-digital converter of
FIG. 2 will now be described with reference to the timing diagram
in FIG. 3. For reference purposes, successive periods of the main
clock signal CLK are numbered as T.sub.1 to T.sub.8. Clock signals
.PHI..sub.1 and .PHI..sub.2 are derived from a master clock signal
CLK, specifically by dividing it by two.
[0053] At the beginning of period T.sub.1 of clock signal CLK a
leading edge of clock signal .PHI..sub.1 causes the sample-and-hold
circuits SH.sub.0 and SH.sub.1 to sample signals X.sub.L and
X.sub.H. The resulting samples, respectively, immediately are
quantized to produce values L.sub.11 and H.sub.11 which are summed
by summing device 12, to produce value A.sub.11. As can be seen
from FIG. 3, there will be some delay due to the time taken for
quantization and also for summing.
[0054] At the beginning of interval T2 of main clock CLK, clock
signal .PHI..sub.2 causes sample-and-hold circuits SH.sub.1 and
SH.sub.3 to sample signals X.sub.L and X.sub.H. The resulting
samples are quantized to produce quantized values L.sub.21 and
H.sub.21 which are summed by summer 12.sub.2 to produce value
A.sub.21.
[0055] The process is repeated to produce two series of values of
A.sub.1 and A.sub.2 at the poles of switching device 14, vis.
A.sub.10, A.sub.11, A.sub.12, A.sub.13 and so on at one pole and
A.sub.20, A.sub.21, A.sub.22, A.sub.23, and so on at the other
pole.
[0056] The switching device 14 selects the values alternately at
the frequency of main clock signal CLK. Thus, when clock signal
.PHI..sub.2 is low, and clock signal .PHI..sub.1 is high, values of
A.sub.1 are selected. When clock signal .PHI..sub.2 is low and
clock signal .PHI..sub.1 is low, values of A.sub.2 are
selected.
[0057] Typically, for example, for an input u(t) having a maximum
frequency of 1 gigahertz, the filters F.sub.L and F.sub.H would be
0-500 MHz and 500-1000 MHz, respectively. Each of the
sample-and-hold circuits SH.sub.0 -SH.sub.3 will sample at a rate
of 1 gigasample per second. The output signal rate will be at least
2 gigasamples per second.
[0058] Each A/D converter unit samples at one half of the output
rate F.sub.s, but each narrowband subband signal is sampled by two
sample-and-hold converter units, offset by 180.degree., so that the
effective sampling is at the full output rate.
[0059] The analog-to-digital converter of FIG. 2 is capable of high
accuracy and high speeds without the usual problems associated with
time-interleaving. In particular, because the sampled signals
X.sub.L and X.sub.H are narrowband signals, the dynamic response
requirements for the sample-and-hold circuits SH.sub.0 -SH.sub.3 is
reduced.
[0060] As illustrated in FIG. 4, it would be possible to modify the
output portion of the analog-to-digital converter of FIG. 2 so as
to avoid the use of two summers 12.sub.1 and 12.sub.2. Thus, in
FIG. 4 the outputs L.sub.1 and L.sub.2 from quantizers Q.sub.0 and
Q.sub.1 are supplied to a switching device 14.sub.1, for example a
multiplexer, while the output H.sub.1 and H.sub.2 from the
quantizers Q.sub.2 and Q.sub.3 are supplied to a second switching
device 14.sub.2, for example another multiplexer. The switching
devices 14.sub.1 and 14.sub.2 are clocked by clock signal
.PHI..sub.2, as before. The outputs of the switching devices
14.sub.1 and 14.sub.2 are summed by summing device 12 to provide
the digitized output signal x(n). With this arrangement, only one
summer 12 is needed, but it must be capable of operation at double
the rate of summers 12.sub.1 and 12.sub.2 of FIG. 2.
[0061] Although the analog-to-digital converters of FIGS. 2 and 4
produce very accurate results, acceptable accuracy for many
applications can be obtained with fewer sample-and-hold circuits,
as illustrated in FIG. 5. Thus, in the analog-to-digital converter
shown in FIG. 5, high pass filter F.sub.H and low pass filter
F.sub.L have their inputs connected in common to the input terminal
to receive the analog signal u(t). The narrowband signals X.sub.H
and X.sub.L from high pass filter F,, and low-pass filter F.sub.L,
respectively, are applied to sample-and-hold circuits SH.sub.H and
SH.sub.L, respectively. The sample-and-hold circuits SH.sub.H and
SH.sub.L are clocked by clock signals .PHI..sub.1 and .PHI..sub.2,
respectively. As in the embodiments of FIGS. 2 and 4, the clock
signals .PHI..sub.1 and .PHI..sub.2 are at one half the sampling
rate Fs of the output signal and in anti-phase relative to each
other. Hence, the sample-and-hold circuits SH.sub.L to SH.sub.H
perform downsampling, so the high-pass filter F.sub.H, the low-pass
filter F.sub.L, and the two sample-and-hold circuits SH.sub.H and
SH.sub.L effectively form an analysis filter bank having the
"perfect reconstruction/representation" or "pseudo-perfect
reproduction/representa- tion" capabilities previously discussed.
The samples from sample-and-hold circuits SH.sub.H and SH.sub.L are
digitized by quantizers Q.sub.H and Q.sub.L, respectively, to
provide digitized values D.sub.H and D.sub.L, respectively. The
series of values D.sub.H and D.sub.L from the quantizers Q.sub.L
and Q.sub.H are buffered by registers R.sub.L and R.sub.H clocked
by main clock signal CLK. The buffered digital signals A.sub.11,
and A.sub.L are summed by summing device 12, the output of which is
buffered by an output register R.sub.out, clocked by clock signal
.sub.{overscore (CLK)} i.e. the inverse of master clock signal CLK,
before being output as the digital representation x(n) of the
analog input signal u(t).
[0062] Operation of the two-band high speed analog-to-digital
converter of FIG. 5 will now be described with reference to FIG. 6
which depicts the timing diagrams for the device.
[0063] For reference purposes, successive cycles of the main clock
CLK which are shown in FIG. 6 are numbered T.sub.1 through T.sub.8,
inclusive. At the beginning of first period T.sub.1, the rising
edge of clock signal .PHI..sub.1 causes the sample-and-hold circuit
SH.sub.L to sample the low-pass narrowband signal X.sub.L to
produce, and hold, a first sample L.sub.1. Quantizer Q.sub.L in
analog-to-digital converter unit AD.sub.L quantizes the sample
L.sub.1 to produce a corresponding digital representation D.sub.L1.
The sampling and quantizing take a certain amount of time, which is
much less than one period of clock signal .PHI..sub.1. On the
following rising edge of main clock CLK, i.e. at the beginning of
period T.sub.2, the digital value D.sub.L1 is clocked into the
register R.sub.L which stores it as value AL.sub.1 during periods
T.sub.2 and T.sub.3 of main clock signal CLK, since the value
D.sub.L1 persists at the output of analog-to-digital converter unit
AD.sub.L when the register R.sub.L is clocked again at the
beginning of period T.sub.3.
[0064] The high pass narrowband signal X.sub.H, is digitized in a
similar manner. During the first period T.sub.1 of main clock
signal CLK, clock signal .PHI..sub.2 is low. On the rising edge of
clock signal .PHI..sub.2 at the end of first clock period T.sub.1,
clock signal .PHI..sub.2 causes the sample-and-hold circuit
SH.sub.H in analog-to-digital converter unit AD.sub.H to sample the
narrowband signal X.sub.H to acquire and hold sample H.sub.1.
Quantizer Q.sub.H quantizes the sample value H.sub.1 to produce a
corresponding digital value D.sub.H1 and, on the next rising edge
of clock signal CLK (start of period T.sub.3), transfers the value
D.sub.H1 into register R.sub.H which stores it as value A.sub.H1
for two periods of clock signal CLK.
[0065] The summing device 12 sums the instant values of A.sub.H and
A.sub.L continuously and supplies the sum to register R.sub.out
which outputs the value on each falling edge of clock CLK (i.e.
rising edge of inverse clock .sub.{overscore (CLK)}).
[0066] Hence, on the falling edge of main clock CLK occurring in
period T.sub.3, register R.sub.out outputs the value
A.sub.L1+A.sub.H1 as the digital representation of the current
sample of input signal u(t). While this processing of samples
H.sub.1 and L.sub.1 is taking place, the process of sampling and
quantizing is already being repeated for the next pair of samples.
Thus, on the rising edge of clock signal .PHI..sub.1 at the start
of period T.sub.3, analog-to-digital converter unit AD.sub.L
acquires a second sample L.sub.2 and quantizes it to produce a
corresponding digital representation D.sub.L2, which is stored in
register R.sub.L. Likewise, the rising edge of clock signal
.PHI..sub.2 at the start of period T.sub.4 causes the
sample-and-hold circuit SH.sub.H in analog-to-digital converter
unit AD.sub.H to obtain and hold sample H.sub.2 which is quantized
and stored in register R.sub.H. On the next falling edge of main
clock signal CLK, the register R.sub.out outputs the sum
A.sub.L12+A.sub.H2. The sequence is repeated for subsequent
samples.
[0067] It can be seen from FIG. 6 that the values in the registers
R.sub.H and R.sub.L are each stored for two cycles of the main
clock signal CLK. However, the contents of the registers R.sub.H ,
and R.sub.L do not change at the same time, but rather at times
which are separated by one clock period of main clock signal CLK.
Consequently, the stored values overlap. Because register R.sub.out
is clocked at the rate of main clock signal CLK, it samples the sum
of the two overlapped signals A.sub.H and A.sub.L once each clock
period.
[0068] Providing the analysis filter bank 10 meets the conditions
set out hereinbefore, the digital signal x(n) outputted from
register R.sub.out will be a "perfect or pseudo-perfect
representation" of the analog input signal u(t).
[0069] If the input signal is a wideband signal having a bandwidth,
say, of 500 MHz, the main clock signal CLK must have a minimum
frequency of 1 GHz to meet Nyquist criteria.
[0070] It will be seen from FIGS. 5 and 6, that the
analog-to-digital converter units AD.sub.H and AD.sub.L sample the
narrowband signals at a rate which is one half of the output sample
rate Fs. For example, for an input signal having a bandwidth of 500
MHz, and an output signal x(n) having a sampling rate Fs of 1
Gigasample/sec, each of the analog-to-digital converter units
AD.sub.H and AD.sub.L samples at a rate of only 500
Megasamples/sec.
[0071] Each output sample value is alternately a value which was
obtained within the previous half cycle of the main clock CLK and a
value which was obtained approximately one cycle previously. At any
given time, therefore, the output from a particular one of the A-D
converter units ADH and ADL will be current or delayed. Because the
signals supplied to the quantizers Q.sub.H and Q.sub.L are, in
effect, subband signals, and the analysis filter bank
characteristics are carefully selected to ensure correlation
between these subband signals, in particular in accordance with the
principles of "perfect or pseudo-perfect reconstruction", the
output signal x(n) is an accurate representation of the analog
input signal u(t).
[0072] It should be noted that the high speed analog-to-digital
converter uses what, in effect, is an analysis filter bank to
divide the input signal into subband signals, but does not use the
usual synthesis filter bank to recombine them. It should also be
noted that an analysis filter bank comprises a set of narrowband
filters followed by a set of downsamplers. In this case, the
sample-and-hold units SH.sub.L and SH.sub.H provide the
downsampling because each samples at one half of the rate of the
output signal, and at least double the bandwidth of the
corresponding one of narrowband filters F.sub.L and F.sub.H.
[0073] The analog-to-digital converter units AD.sub.H and AD.sub.L
do not operate directly upon the input signal but rather upon the
narrowband signals. Consequently, the need for wideband
analog-to-digital converter units is avoided. Because the
analog-to-digital converter units operate with a narrow bandwidth,
they are less susceptible to phase errors. For an input signal u(t)
having a maximum frequency of, say, 500 MHz, and two narrowband
filters F.sub.L and F.sub.H of equal bandwidth, each
analog-to-digital converter unit would handle only 250 MHz
bandwidth. Consequently, since each analog-to-digital converter
unit is still clocked at 500 samples per second, it oversamples the
narrowband signal and so is less affected by phase error. It should
also be noted that, because the outputs from the two A-D converter
units AD.sub.L and AD.sub.H are added, differences between the two
A-to-D converter units would offset each other, making the device
less susceptible to gain error.
[0074] An advantage of the embodiment of FIG. 5 is that it requires
only two A-D converter units AD.sub.L and AD.sub.H to produce a
satisfactory output suitable for use in most wireless
telecommunications applications, and the like. If even greater
accuracy is desired, however, such as for instrumentation
applications, and the expense of additional analog-to-digital
converter units can be tolerated, the analog-to-digital converters
of FIGS. 2 and 4 might be preferred. The embodiments of FIGS. 2 and
4 potentially are more accurate than that of FIG. 5 because they do
not rely upon correlation between the instant and previous values
of the two narrowband signals X.sub.H and X.sub.L. Rather, each
narrowband signal is sampled at the full output rate.
[0075] There are applications where a multi-resolution A/D
converter would be desirable. Such a multi-resolution A/D converter
is illustrated in FIG. 7. The analog input signal u(t) having a
frequency up to a maximum F.sub.max is supplied in common to the
inputs of a bank of narrowband filters comprising a low pass filter
F.sub.L, a bandpass filter F.sub.P and a high pass filter F.sub.H,
all having different bandwidths. For example, the bandwidths might
be 0-250 MHz, 250-500 MHz and 500 MHz to 1 GHz, respectively. The
narrowband signals X.sub.L, X.sub.P and X.sub.H from the filters
F.sub.L, F.sub.P and F.sub.H are supplied to three sample-and-hold
circuits SH.sub.L, SH.sub.P and SH.sub.H, respectively. The samples
from the sample-and-hold circuits SH.sub.L, SH.sub.P and SH.sub.H
are quantized by quantizers Q.sub.L, Q.sub.P and Q.sub.H,
respectively, to provide digitized samples D.sub.L, D.sub.P and
D.sub.H which are clocked into registers R.sub.L, R.sub.P and
R.sub.H, respectively. The outputs of the registers are connected
to respective inputs of a summing device 12 which sums the outputs
G.sub.L, G.sub.P and G.sub.H from the registers R.sub.L, R.sub.P
and R.sub.H and supplies the sum to output register R.sub.out,
which acts as a buffer. Registers R.sub.L, R.sub.P and R.sub.H are
clocked by main clock signal CLK at the predetermined sampling rate
F.sub.s while output register R.sub.out is clocked by the inverse
clock signal .sub.{overscore (CLK)}, i.e. on the falling edges of
main clock signal CLK.
[0076] The frequencies of clock signals .PHI..sub.1, .PHI..sub.2
and .PHI..sub.3, and their relative phases, are selected so that
each sampling point/edge of the main clock signal CLK substantially
coincides with one of the sampling points/edges of the clock
signals .PHI..sub.1, .PHI..sub.2, and .PHI..sub.3. For example, if
F.sub.max is 1 GHz, the bandwidths of filters F.sub.L, F.sub.P and
F.sub.H are 0-250 MHz, 250-500 MHz and 500 MHz-1 GHz, respectively,
and the output sample rate F.sub.s is equal to at least 2
Gigasamples/second, suitable frequencies for clock signals
.PHI..sub.1, .PHI..sub.2, and .PHI..sub.3 are 500 MHz, 500 MHz and
1 GHz, respectively.
[0077] Again, the filters F.sub.L, F.sub.P and F.sub.H, together
with the sample-and-hold circuits SH.sub.L, SH.sub.P and SH.sub.H,
constitute an analysis filter bank. Also, each combination of a
sample-and-hold circuit and a quantizer constitutes an
analog-to-digital converter unit.
[0078] The filters X.sub.L, X.sub.P and X.sub.H could comprise an
octave filter bank as shown in FIG. 9. The octave filter bank
comprises a first stage formed by a lowpass filter F.sub.LP and a
high pass filter F.sub.H having their inputs connected in common to
receive the input signal u(t). The narrowband signal from filter
F.sub.H is the high pass signal X.sub.H. The filtered signal from
filter F.sub.LP is filtered by additional two filters F.sub.L and
F.sub.P to provide the low pass signal X.sub.L and the bandpass
signal X.sub.P. Filters F.sub.Lp and F.sub.H would have the same
bandwidth, e.g. 500 MHz, and filters F.sub.L and F.sub.P would have
the same, lower bandwidth, e.g. 250 MHz.
[0079] The frequency of clock signal .PHI..sub.3 is one half of the
rate of master clock signal CLK, and the clock signals .PHI..sub.2
and .PHI..sub.1 have the same frequency equal to one half the rate
of clock signal .PHI..sub.3.
[0080] The operation of the multi-resolution A/D converter, which
is analogous to that of the uniform analog-to-digital converter of
FIG. 2, will now be described with reference also to FIG. 8. At the
beginning of clock period T1 of main clock signal CLK, the rising
edge of clock signal .PHI..sub.1 causes sample-and-hold circuit
SH.sub.L to sample narrowband signal X.sub.L. The sample is
quantized by quantizer Q.sub.L to produce quantized sample D.sub.L1
which is clocked into register R.sub.L, as value G.sub.L1, by the
rising edge at the beginning of main clock period T2. The
sample-and-hold circuit SH.sub.L holds the sample for one complete
cycle of clock signal .PHI..sub.1, and the digitized value G.sub.L1
remains in the register R.sub.L for a similar length of time,
specifically until the end of period T5 of main clock signal
CLK.
[0081] At the beginning of period T2 of clock signal CLK, the
rising edge of clock signal .PHI..sub.3 causes sample-and-hold
circuit SH.sub.H to sample high pass signal X.sub.H and the sample
is quantized by quantizer Q.sub.H to produce digitized value
DH.sub.1. The corresponding digitized value G.sub.H1 is clocked
into register R.sub.H at the beginning of main clock period T3 of
main clock signal CLK. In this case, digitized value G.sub.H1 is
stored in register R.sub.H for only two periods of main clock
signal CLK.
[0082] At the beginning of period T3 of main clock signal CLK, the
rising edge of clock signal .PHI..sub.2 causes sample-and-hold
circuit SH.sub.P to sample bandpass signal X.sub.P. The resulting
sample is quantized by quantizer Q.sub.P and clocked into register
R.sub.P by the rising edge at the beginning of period T4 of main
clock signal CLK. The corresponding digitized value G.sub.P1 is
stored in register R.sub.P for four periods of main clock signal
CLK.
[0083] The summing device 12 (FIG. 9) sums the outputs of registers
R.sub.L, R.sub.P and R.sub.H at the beginning of each period of
main clock signal CLK. Allowing for processing time, the result,
G.sub.L1 and G.sub.P0 and G.sub.H0 is available by the next falling
edge of clock signal CLK, and is clocked into output register
R.sub.out. Values G.sub.P0 and G.sub.H0 are, of course, values
previously obtained by a similar process.
[0084] The sequence is repeated for subsequent samples of the
narrowband signals X.sub.L, X.sub.P and X.sub.H to produce a series
of values, G.sub.L1+G.sub.P0+G.sub.H0, G.sub.L1+G.sub.P0+G.sub.H1,
G.sub.L1+G.sub.P1+G.sub.H1, and so on as the digital output signal
x(n) at the sampling F.sub.s.
[0085] As before, in view of the continuous nature of the analog
signal u(t) and the analysis filter bank characteristics of the A-D
converter, x(n) is an accurate representation of input signal u(t),
even though each of the individual sample-and-hold circuits
SH.sub.L, SH.sub.P and SH.sub.H does not necessarily sample at
double the maximum frequency of the corresponding one of the
narrowband signals X.sub.L, X.sub.P and X.sub.H.
[0086] Various modifications may be made to the above-described
embodiments without departing from the scope of the present
invention. Thus, in FIGS. 3, 6 and 8, sampling is carried out on
the rising edges of the clock signals, but it would also be
possible to carry out sampling on the falling or trailing edges, in
which case suitable alternative components would be selected.
[0087] It should be noted that embodiments of the invention differ
from time-interleaved D-A converters in that the inputs to the A/D
converter units are subband signals of the wide-band continuous
time input signal u(t). Another important difference in embodiments
of this invention is that, unlike the time interleaved converters,
the outputs are not time-multiplexed, but rather are summed.
[0088] Referring now to FIG. 10, a digital-to-analog converter
suitable for converting a high speed digital signal x(n) to an
analog signal u(t) comprises a bank of lower speed D-A converter
units DA.sub.0, DA.sub.1 . . . DA.sub.M-1 having their inputs
connected in common to receive the input digital signal x(n). The
outputs of the D-A converters DA.sub.0-DA.sub.M-1 are applied to
the inputs of a bank of narrowband filters P.sub.0,
P.sub.1-P.sub.M-1, respectively, the outputs of which are summed by
analog summing device 20 to form the analog output signal u(t). The
bank of narrowband filters P.sub.0-P.sub.M-1 and summing device 20
constitute an analog synthesis filter bank.
[0089] The bank of D-A converters DA.sub.0-DA.sub.M-1 are clocked
by a corresponding plurality of clock signals
.PHI..sub.0-.PHI..sub.M-1 which all have the same frequency but are
offset in phase relative to each other, conveniently uniformly. As
in the case of the A-D converter described hereinbefore, the phase
offsets are such that each sampling point of the input signal x(n)
coincides with a sampling point of one of the clock signals
.PHI..sub.1-.PHI..sub.M-1.
[0090] Although embodiments of the invention have been described
and illustrated in detail, it is to be clearly understood that the
same are by way of illustration and example only and not to be
taken by way of the limitation, the spirit and scope of the present
invention being limited only by the appended claims.
* * * * *