U.S. patent application number 10/252710 was filed with the patent office on 2003-01-23 for semiconductor device having a chip, reinforcing plate, and sealing material sharing a common rear surface.
This patent application is currently assigned to Mitsubishi Denki Kabushiki Kaisha. Invention is credited to Baba, Shinji, Tomita, Yoshihiro.
Application Number | 20030016511 10/252710 |
Document ID | / |
Family ID | 17944279 |
Filed Date | 2003-01-23 |
United States Patent
Application |
20030016511 |
Kind Code |
A1 |
Tomita, Yoshihiro ; et
al. |
January 23, 2003 |
Semiconductor device having a chip, reinforcing plate, and sealing
material sharing a common rear surface
Abstract
A plurality of chips are mounted on a substrate, coupling
portions between the chips and the substrate are sealed, the chips
have rear surfaces thereof collectively polished, and the substrate
with the chips thereon are separated into independent semiconductor
devices.
Inventors: |
Tomita, Yoshihiro; (Tokyo,
JP) ; Baba, Shinji; (Tokyo, JP) |
Correspondence
Address: |
Mcdermott, Will & Emery
600 13th Street, N.W.
Washington
DC
20005-3096
US
|
Assignee: |
Mitsubishi Denki Kabushiki
Kaisha
Tokyo
JP
|
Family ID: |
17944279 |
Appl. No.: |
10/252710 |
Filed: |
September 24, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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10252710 |
Sep 24, 2002 |
|
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09521568 |
Mar 9, 2000 |
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Current U.S.
Class: |
361/783 ;
174/260; 257/780; 257/E23.062; 361/760 |
Current CPC
Class: |
H01L 2224/73204
20130101; H01L 2224/83102 20130101; H01L 2224/92125 20130101; H01L
2924/01033 20130101; H01L 2924/3512 20130101; H01L 2224/32225
20130101; H01L 2924/15153 20130101; H01L 2924/00014 20130101; H01L
2224/92125 20130101; H01L 2224/27013 20130101; H01L 2924/00014
20130101; H01L 2224/97 20130101; H01L 2924/01082 20130101; H01L
2224/97 20130101; H01L 2224/83051 20130101; H01L 24/32 20130101;
H01L 2224/16225 20130101; H01L 2924/18161 20130101; H01L 2224/97
20130101; H01L 24/97 20130101; H01L 2924/1517 20130101; H01L
2224/73204 20130101; H01L 2924/01004 20130101; H01L 2224/97
20130101; H01L 23/49822 20130101; H01L 2224/83 20130101; H01L
2224/32225 20130101; H01L 2924/00 20130101; H01L 2224/73204
20130101; H01L 2224/81 20130101; H01L 2224/16225 20130101; H01L
2224/0401 20130101; H01L 2224/32225 20130101; H01L 2924/00012
20130101; H01L 2224/16225 20130101; H01L 2924/00 20130101; H01L
2224/73204 20130101 |
Class at
Publication: |
361/783 ;
257/780; 174/260; 361/760 |
International
Class: |
H01L 023/48; H05K
007/02; H05K 007/06 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 27, 1999 |
JP |
11-305368 |
Claims
What is claimed is:
1. A semiconductor device having a thin semiconductor element
mounted thereon, the semiconductor element being obtained by
mounting a plurality of semiconductor elements on a substrate,
polishing rear surfaces of the semiconductor elements after sealing
coupling portions, and separating the substrate with the
semiconductor elements thereon into independent semiconductor
devices.
2. The semiconductor device according to claim 1, wherein a
reinforcing plate is fixed on the substrate, and the substrate with
the semiconductor elements thereon are separated into the
independent semiconductor devices after assembly.
3. The semiconductor device according to claim 1, wherein a
reinforcing plate is fixed on the substrate, the reinforcing plate
comprising a metallic plate and a wiring plate in layered fashion,
and conduction is made between the wiring plate and wiring on the
substrate.
4. A semiconductor device having thin semiconductors element
mounted thereon, the semiconductor elements being obtained by
mounting a plurality of semiconductor elements, sealing the
semiconductor elements, providing a laminate on rear surfaces of
the semiconductor elements to form a wiring layer with the
semiconductor elements included therein after polishing the rear
surfaces of the semiconductor elements, and wiring, followed by
repeating the same step.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to a semiconductor device
which has a thin semiconductor element mounted thereon.
DISCUSSION OF BACKGROUND
[0002] When, in particular, a thin semiconductor element (having a
thickness not greater than 0.1 mm for instance) is mounted on a
conventional semiconductor device, a wafer is preliminarily ground
to a thin one, the wafer is separated into independent chips by
dicing, and the independent chips are mounted on substrates or lead
frames in a usual method.
[0003] The usual method has created a problem in that a chip is
likely to be fractured in handling, or that when a chip is mounted
on a substrate, a stress is generated by bonding electrode portions
to damage a coupling portion or the semiconductor element.
SUMMARY OF THE INVENTION
[0004] It is an object of the present invention to solve the
problem, and provides a semiconductor device having a thin
semiconductor element mounted thereon, the semiconductor element
being obtained by mounting a plurality of chips on a substrate
before thinning the thickness of the chips, and polishing rear
surfaces of the chips with coupling portions protected by sealing
after, e.g. testing or repairing or with a stress to the chips
lessened.
[0005] According to a first aspect of the present invention, there
is provided semiconductor device having a thin semiconductor
element mounted thereon, the semiconductor element being obtained
by mounting a plurality of semiconductor elements on a substrate,
polishing rear surfaces of the semiconductor elements after sealing
coupling portions, and separating the substrate with the
semiconductor elements thereon into independent semiconductor
devices.
[0006] According to a second aspect of the present invention, a
reinforcing plate is fixed on the substrate, and the substrate with
the semiconductor elements thereon are separated into the
independent semiconductor devices after assembly.
[0007] According to a third aspect of the present invention, a
reinforcing plate is fixed on the substrate, the reinforcing plate
comprising a metallic plate and a wiring plate in layered fashion,
and conduction is made between the wiring plate and wiring on the
substrate.
[0008] According to a fourth aspect of the present invention, there
is provided a semiconductor device having thin semiconductors
element mounted thereon, the semiconductor elements being obtained
by mounting a plurality of semiconductor elements, sealing the
semiconductor elements, providing a laminate on rear surfaces of
the semiconductor elements to form a wiring layer with the
semiconductor elements included therein after polishing the rear
surfaces of the semiconductor elements, and wiring, followed by
repeating the same step.
[0009] The present invention is constructed as stated earlier,
offering the following advantages.
[0010] In accordance with the first aspect, the plural
semiconductor elements are mounted on a substrate, and the rear
surfaces of the semiconductor elements are polished after sealing.
As a result, the semiconductor elements can be made thin without
damaging the semiconductor elements.
[0011] In accordance with the second aspect, the reinforcing plate
is fixed on the substrate. Even if the substrate has low rigidity,
the substrate can ensure required flatness, allowing polishing of
the rear surfaces to be carried out with good precision.
[0012] In accordance with the third aspect, the reinforcing plate
is fixed on the substrate, and conduction is made between the
wiring plate and the wiring on the substrate. Thus, the
semiconductor device can improve a wiring allowance for the
substrate, can have a thin semiconductor element mounted thereon,
and the semiconductor element can be made smaller.
[0013] In accordance with the fourth aspect, semiconductor elements
are mounted, the semiconductor elements are sealed, a wiring layer
is provided by laminating after polishing rear surfaces of the
semiconductor elements, and followed by the repeating the same
step. This arrangement can provide a semiconductor device with a
plurality of chips mounted thereon in high density.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] A more complete appreciation of the invention and many of
the attendant advantages thereof will be readily obtained as the
same becomes better understood by reference to the following
detailed description when considered in connection with the
accompanying drawings, wherein:
[0015] FIG. 1 is a cross-sectional side view showing the
semiconductor device according to a first embodiment of the present
invention;
[0016] FIG. 2 is a fabrication flowchart for preparing the
semiconductor device according to the first embodiment;
[0017] FIG. 3 is a cross-sectional side view showing the
semiconductor device according to a second embodiment of the
present invention;
[0018] FIG. 4 is a fabrication flowchart for preparing the
semiconductor device according to the second embodiment;
[0019] FIG. 5 is a cross-sectional side view showing the
semiconductor device according to a third embodiment of the present
invention;
[0020] FIG. 6 is a cross-sectional view showing the semiconductor
device according to a fourth embodiment of the present invention,
and
[0021] FIG. 7 is a fabrication flowchart for preparing the
semiconductor device according to the fourth embodiment.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0022] Now, preferred embodiments of the present invention will be
described in detail, referring to FIGS. 1 through 7.
EMBODIMENT 1
[0023] In FIG. 1 is shown a cross-sectional side view of the
semiconductor device according to a first embodiment of the present
invention. In FIG. 1, reference numeral 1 designates a thin chip as
a semiconductor element, which has been polished thin, reference
numeral 2 designates a substrate, reference numeral 3 designates a
bump, which couples the thin chip 1 and the substrate 2, reference
numeral 4 designates a sealing resin, and reference numeral 5
designates an external terminal provided on the substrate 2.
[0024] In FIG. 2 is shown an example of the fabrication flowchart
for preparing the semiconductor device shown in FIG. 1. As shown in
FIG. 2, a plurality of chips 1 are mounted on the substrate 2 (Step
S1), coupling portions between the substrate 2 and the chips 1 are
sealed (Step S2), and then the chips 1 have rear surfaces thereof
collectively ground (Step S3), and the substrate with the chips
thereon is separated into independent semiconductor devices (Step
S4).
[0025] As explained, in accordance with the semiconductor device
and the fabrication method of the first embodiment, the rear
surfaces of the chips 1 can be ground thin without damaging the
chips 1 or the bumps 3 as the coupling portions. The collective
grinding of the rear surfaces can increase productivity.
EMBODIMENT 2
[0026] In FIG. 3 is shown a cross-sectional side view of the
semiconductor device according to a second embodiment of the
present invention. In FIG. 3, reference numeral 6 designates a
reinforcing plate, which is fixed on the substrate 2. The other
elements are the same as those of the first embodiment.
[0027] In FIG. 4 is shown an example of the fabrication flowchart
for preparing the semiconductor device according to the second
embodiment. As shown in FIG. 4, a plurality of chips 1 are mounted
on the substrate 2, (Step S11), reinforcing plates are fixed on the
substrate (Step S12), the coupling portions between the chips 1 and
the substrate 2 are sealed (Step S13), the chips 1 have rear
surfaces thereof polished (Step S14), and then the substrate 2 with
the chips thereon are separated into independent semiconductor
devices (Step S15).
[0028] As explained, the semiconductor device and the fabrication
method according to the second embodiment can ensure the flatness
of the substrate and polish the rear surfaces of the chips with
good precision even if the substrate has low rigidity.
EMBODIMENT 3
[0029] In FIG. 5 is shown a cross-sectional side view of the
semiconductor device according to a third embodiment of the present
invention. In FIG. 5, reference numeral 6 designates a reinforcing
plate, which comprises a metallic plate 8 and wiring plates 7 in
three-layered fashion. Reference numeral 10 designates a wire for
electrical conduction between the reinforcing plate 6 and the
substrate 2. Although the reinforcing plate 6 has such a
three-layered structure of the wiring plate 7/the metallic plate
8/the wiring plate 7 in the third embodiment, the layered structure
or the order of the plates in the layered structure is not limited
to the shown fashion.
[0030] As explained, the semiconductor device according to the
third embodiment can improve the wiring allowance for the substrate
and can have thin semiconductor elements mounted thereon in a
smaller size.
EMBODIMENT 4
[0031] In FIG. 6 is shown a cross-sectional side view of the
semiconductor device according to a fourth embodiment of the
present invention. In FIG. 6, reference numeral 20 designates a
wiring layer, which is layered on the substrate 2, and which
include chips 1 in plural sublayers. Reference numerals 15, 16 and
17 designate the respective wiring sublayers.
[0032] In FIG. 7 is shown an example of the fabrication flowchart
for preparing the semiconductor device according to the fourth
embodiment. The wiring layer 20 shown in FIG. 6 is prepared by
coupling chips 1 (Steps S21 and S26), sealing (Step S22), polishing
the rear surfaces of the chips (Step S23), providing a laminate on
the rear surfaces (Step S24), and wiring (Step S25), repeating
these steps, and finally separating the substrate with the wiring
layer thereon into independent semiconductor devices as shown in
the flowchart of FIG. 7.
[0033] As explained, the semiconductor device and the fabrication
method according to the fourth embodiment can provide a
semiconductor device with plural thin chips mounted thereon in high
density.
* * * * *