U.S. patent application number 10/150974 was filed with the patent office on 2003-01-16 for semiconductor device and method for producing same.
Invention is credited to Komatsu, Hiroshi.
Application Number | 20030011035 10/150974 |
Document ID | / |
Family ID | 26523049 |
Filed Date | 2003-01-16 |
United States Patent
Application |
20030011035 |
Kind Code |
A1 |
Komatsu, Hiroshi |
January 16, 2003 |
Semiconductor device and method for producing same
Abstract
A semiconductor device having a substrate, an insulating film
formed in the substrate, a conductive layer formed on the
insulating film and having at least a part in contact with the
insulating film made of a conductive material having a work
function near a substantial center of an energy band gap of the
substrate material and containing a predetermined amount of
impurity, and a takeout electrode formed in the substrate and a
method for producing the same.
Inventors: |
Komatsu, Hiroshi; (Kanagawa,
JP) |
Correspondence
Address: |
Ronald P. Kananen
RADER, FISHMAN & GRAUER, PLLC
Suite 501
1233 20th Street, N.W.
Washington
DC
20036
US
|
Family ID: |
26523049 |
Appl. No.: |
10/150974 |
Filed: |
May 21, 2002 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10150974 |
May 21, 2002 |
|
|
|
09413193 |
Oct 5, 1999 |
|
|
|
6417565 |
|
|
|
|
Current U.S.
Class: |
257/407 ;
257/E21.203; 257/E29.161; 438/407 |
Current CPC
Class: |
H01L 29/4975 20130101;
H01L 21/28097 20130101 |
Class at
Publication: |
257/407 ;
438/407 |
International
Class: |
H01L 031/119 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 8, 1998 |
JP |
P10-287077 |
Aug 2, 1999 |
JP |
P11-219318 |
Claims
What is claimed is:
1. A semiconductor device comprising: a substrate, an insulating
film formed in the substrate, a conductive layer formed on the
insulating film and having at least a part in contact with the
insulating film made of a conductive material having a work
function near a substantial center of an energy band gap of the
substrate material and containing a predetermined amount of
impurity, and a takeout electrode formed in the substrate.
2. A semiconductor device as set forth in claim 1, wherein the
impurity is an impurity suppressing the grain growth of the
conductive material.
3. A semiconductor device as set forth in claim 1, wherein the
impurity is oxygen, nitrogen, or boron.
4. A semiconductor device as set forth in claim 1, wherein the
conductive layer has the layer comprised of a conductive material
containing impurity having different concentrations in a depth
direction and having the work function near the substantial center
of the energy band gap of the substrate material.
5. A semiconductor device as set forth in claim 1, wherein the
conductive layer has a refractory metal silicide layer or a
refractory metal layer containing an impurity with different
concentrations in a depth direction.
6. A semiconductor device as set forth in claim 1, wherein the
conductive layer has a layer comprised of a conductive material
with a center region with respect to a depth direction thereof
containing an impurity having a higher concentration than those of
upper and lower regions thereof having the work function near the
substantial center of the energy band gap of a substrate
material.
7. A semiconductor device as set forth in claim 1, wherein the
conductive layer has a refractory metal silicide layer or a
refractory metal layer with a center region with respect to a depth
direction thereof containing an impurity having a higher
concentration than those of upper and lower regions thereof.
8. A semiconductor device as set forth in claim 1, wherein the
conductive layer contains two or more types of impurities.
9. A semiconductor device as set forth in claim 8, wherein at least
one of the two or more types of impurities is oxygen, nitrogen, or
boron.
10. A semiconductor device as set forth in claim 8, wherein the
conductive layer contains each of the two or more types of
impurities in concentrations of 1.times.10.sup.19/cm.sup.3 to
1.times.10.sup.21/cm.sup.- 3.
11. A semiconductor device as set forth in claim 1, wherein the
substrate material is silicon and the conductive material is a
refractory metal silicide or a refractory metal.
12. A semiconductor device as set forth in claim 11, wherein the
refractory metal silicide is one, two or more types selected from a
group consisting of tungsten silicide (WSi.sub.x), molybdenum
silicide (MoSi.sub.x), tantalum silicide (TaSi.sub.x), and titanium
silicide (TiSi.sub.x).
13. A semiconductor device as set forth in claim 11, wherein the
refractory metal is one, two or more types selected from a group
consisting of tungsten (W), tantalum (Ta), and titanium (Ti).
14. A semiconductor device comprising: a silicon substrate, a gate
insulating film formed in the silicon substrate, a gate electrode
formed on the gate insulating film and having at least a part in
contact with the gate insulating film made of a refractory metal
silicide layer containing an impurity or a refractory metal layer
containing an impurity, and a takeout electrode formed in the
silicon substrate.
15. A semiconductor device as set forth in claim 14, wherein the
impurity is an impurity suppressing the grain growth of the
refractory metal silicide or the refractory metal.
16. A semiconductor device as set forth in claim 14, wherein the
refractory metal silicide or the refractory metal contains an
impurity with different concentrations in a depth direction.
17. A semiconductor device as set forth in claim 14, wherein the
refractory metal silicide layer or the refractory metal layer
contains an impurity having a higher concentration in a center
region with respect to a depth direction thereof than those of
upper and lower regions thereof.
18. A semiconductor device as set forth in claim 14, wherein the
impurity is oxygen, nitrogen, or boron.
19. A semiconductor device as set forth in claim 14, wherein the
refractory metal silicide layer or the refractory metal layer
contains two or more types of impurities.
20. A semiconductor device as set forth in claim 19, wherein at
least one of the two or more types of impurities is oxygen,
nitrogen, or boron.
21. A semiconductor device as set forth in claim 19, wherein the
refractory metal silicide layer or the refractory metal layer
contains each of the two or more types of impurities in
concentrations of 1.times.10.sup.19/cm.sup.3 to
1.times.10.sup.21/cm.sup.3.
22. A semiconductor device as set forth in claim 14, wherein the
refractory metal silicide is one, two or more types selected from a
group consisting of tungsten silicide (WSi.sub.x), molybdenum
silicide (MoSi.sub.x), tantalum silicide (TaSi.sub.x), and titanium
silicide (TiSi.sub.x).
23. A semiconductor device as set forth in claim 14, wherein the
refractory metal is one, two or more types selected from a group
consisting of tungsten (W), tantalum (Ta), and titanium (Ti).
24. A method for producing a semiconductor device comprising steps
of: forming an insulating film in a substrate, forming a conductive
layer made of a conductive material having a work function near a
substantive center of an energy band gap of the substrate material
on the insulating film, doping an impurity into the conductive
layer, and forming a takeout electrode in the substrate.
25. A method for producing a semiconductor device as set forth in
claim 24, wherein the step of doping the impurity into the
conductive layer has a step of doping the impurity into the
conductive layer by an ion implantation process.
26. A method for producing a semiconductor device as set forth in
claim 24, wherein the step of doping the impurity into the
conductive layer has a step of forming a conductive film containing
the impurity on the insulating film by a chemical vapor deposition
process.
27. A method for producing a semiconductor device as set forth in
claim 24, wherein the step of doping the impurity into the
conductive layer has a step of doping into the conductive layer a
impurity suppressing a grain growth of the conductive layer.
28. A method for producing a semiconductor device as set forth in
claim 24, wherein the step of doping the impurity into the
conductive layer has a step of doping into the conductive layer the
impurity so that an impurity concentration varies in a depth
direction.
29. A method for producing a semiconductor device as set forth in
claim 24, wherein the step of doping the impurity into the
conductive layer has a step of doping the impurity so that a
concentration of the impurity contained in a center region of the
conductive layer with respect to a depth direction thereof becomes
higher than impurity concentrations of upper and lower regions
thereof.
30. A method for producing a semiconductor device as set forth in
claim 24, wherein the step of doping the impurity into the
conductive layer has a step of doping oxygen, nitrogen, or boron
into the conductive layer.
31. A method for producing a semiconductor device as set forth in
claim 24, wherein the step of doping the impurity into the
conductive layer has a step of doping two or more types of
impurities into the conductive layer.
32. A method for producing a semiconductor device as set forth in
claim 31, wherein the step of doping the impurity into the
conductive layer has a step of doping at least oxygen, nitrogen, or
boron into the conductive layer.
33. A method for producing a semiconductor device as set forth in
claim 31, wherein the step of doping the impurity into the
conductive layer has a step of doping each of the two or more types
of impurities into the conductive layer with the concentration of
1.times.10.sup.19/cm.sup.3 to 1.times.10.sup.21/cm.sup.3.
34. A method for producing a semiconductor device as set forth in
claim 24, wherein a silicon substrate is used as the substrate.
35. A method for producing a semiconductor device as set forth in
claim 31, wherein the step of forming the conductive layer made of
the conductive material having the work function near the
substantive center of the energy band gap of the substrate material
has a step of forming a refractory metal silicide layer or a
refractory metal layer on the substrate.
36. A method for producing a semiconductor device as set forth in
claim 35, wherein the step of forming the refractory metal silicide
layer has a step of forming a layer made of one, two or more types
selected from a group consisting of tungsten silicide (WSi.sub.x),
molybdenum silicide (MoSi.sub.x), tantalum silicide (TaSi.sub.x),
and titanium silicide (TiSi.sub.x).
37. A method for producing a semiconductor device as set forth in
claim 35, wherein the step of forming the refractory metal layer
has a step of forming a layer made of one, two or more types
selected from a group consisting of tungsten (W), tantalum (Ta),
and titanium (Ti).
38. A method for producing a semiconductor device comprising steps
of: forming a gate insulating film in a silicon substrate, forming
a conductive layer made of a conductive material having a work
function of a substantial center of an energy band gap of the
silicon on the gate insulating film, doping an impurity into the
conductive layer, forming a gate electrode by processing the
conductive layer, and forming a takeout electrode in the silicon
substrate.
39. A method for producing a semiconductor device as set forth in
claim 38, wherein the step of doping the impurity into the
conductive layer has a step of doping the impurity into the
conductive layer by an ion implantation process.
40. A method for producing a semiconductor device as set forth in
claim 38, wherein the step of doping the impurity into the
conductive layer has a step of forming a conductive film containing
the impurity on the insulating film by a chemical vapor deposition
process.
41. A method for producing a semiconductor device as set forth in
claim 38, wherein the step of doping the impurity into the
conductive layer has a step of doping into the conductive layer a
impurity suppressing a grain growth of the conductive layer.
42. A method for producing a semiconductor device as set forth in
claim 38, wherein the step of doping the impurity into the
conductive layer has a step of doping into the conductive layer the
impurity so that an impurity concentration varies in a depth
direction.
43. A method for producing a semiconductor device as set forth in
claim 38, wherein the step of doping the impurity into the
conductive layer has a step of doping the impurity so that a
concentration of the impurity contained in a center region of the
conductive layer with respect to a depth direction thereof becomes
higher than impurity concentrations of upper and lower regions
thereof.
44. A method for producing a semiconductor device as set forth in
claim 38, wherein the step of doping the impurity into the
conductive layer has a step of doping oxygen, nitrogen, or boron
into the conductive layer.
45. A method for producing a semiconductor device as set forth in
claim 38, wherein the step of doping the impurity into the
conductive layer has a step of doping two or more types of
impurities into the conductive layer.
46. A method for producing a semiconductor device as set forth in
claim 45, wherein the step of doping the impurity into the
conductive layer has a step of doping at least oxygen, nitrogen, or
boron into the conductive layer.
47. A method for producing a semiconductor device as set forth in
claim 45, wherein the step of doping the impurity into the
conductive layer has a step of doping each of the two or more types
of impurities into the conductive layer with the concentration of
1.times.10.sup.19/cm.sup.3 to 1.times.10.sup.21/m.sup.3.
48. A method for producing a semiconductor device as set forth in
claim 38, wherein the step of forming the conductive layer made of
the conductive material having the work function near the
substantive center of the energy band gap of the substrate material
has a step of forming a refractory metal silicide layer or a
refractory metal layer on the substrate.
49. A method for producing a semiconductor device as set forth in
claim 48, wherein the step of forming the refractory metal silicide
layer has a step of forming a layer made of one, two or more types
selected from a group consisting of tungsten silicide (WSi.sub.x),
molybdenum silicide (MoSi.sub.x), tantalum silicide (TaSi.sub.x),
and titanium silicide (TiSi.sub.x).
50. A method for producing a semiconductor device as set forth in
claim 48, wherein the step of forming the refractory metal layer
has a step of forming a layer made of one, two or more types
selected from a group consisting of tungsten (W), tantalum (Ta),
and titanium (Ti).
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor device and
a method for producing the same, more particularly relates to a
semiconductor device having a conductive layer in which a work
function of a conductive material located at a boundary with an
insulating film formed on a substrate is controlled to near the
substantial center of an energy band gap of a substrate material,
that is, the "mid-gap", and to a method for producing the same.
[0003] 2. Description of the Related Art
[0004] In semiconductor devices in recent years, complete
separation among elements has become easy by using a
silicon-on-insulator or semiconductor-on-insulator (SOI) substrate
as the substrate. Further, it is known that, if such an SOI
substrate is used, the control of the latchup and the software
error peculiar to a complementary metal oxide semiconductor (MOS)
transistor (CMOSTr) becomes possible, so studies have been
conducted on the increase of speed and increase of reliability of
large-scale integrated circuits (LSIs) comprised of CMOSTrs using
SOI substrates having silicon (Si) active layers of a thickness of
about 500 nm from a relatively early stage.
[0005] Further, recently, it has been learned that if the Si active
layer of the SOI substrate surface is made further thinner to about
100 nm and the impurity concentration of a channel region is
controlled to be relatively low to make substantially the entire Si
active layer depleted (make it a full depletion type), excellent
characteristics such as suppression of a short channel effect and
improvement of a current driving capability of the MOSTr are
obtained.
[0006] On the other hand, as a gate electrode material,
polycrystalline silicon doped with an n-type impurity
(n.sup.+poly-Si) has been frequently used in the past. However, in
order to set a threshold voltage (Vth) of an n-channel MOS
transistor (NMOSTr) to near 0.5 to 1.0V of a usual enhancement type
MOS transistor by using n.sup.+poly-Si for the gate electrode
material, it is necessary to control the impurity concentration of
the channel region to about 10.sup.17/cm.sup.3 or more.
[0007] Further, in order to prepare a full depletion type
enhancement type MOSTr, the method has been studied of using a
polycrystalline silicon doped with boron as a p-type impurity
(p.sup.+poly-Si) as the gate electrode material in place of the
n.sup.+poly-Si for the gate electrodes of the NMOSTr.
[0008] In this method of using p.sup.+poly-Si for the gate
electrodes of an NMOSTr, if the impurity is not included in the
channel region (non-doped), Vth becomes substantially 1.0V.
Further, where it is intended to make Vth a further lower value, it
has been necessary to perform counter-doping to dope an n-type
impurity, for example, phosphorus (P.sup.+), in the channel region
of the NMOSTr. However, when performing the counter-doping, the
short channel effect is increased, so this not preferred for a
miniaturized LSI.
[0009] In this way, in any case of using n.sup.+poly-Si and
p.sup.+poly-Si as the gate electrode material, in the preparation
of a semiconductor device using an SOI substrate having a fine
structure with a thin silicon active layer, it was extremely
difficult to control the Vth of a full depletion type MOSTr to a
suitable value of about 0.5V.
[0010] Further, even in the case of preparing a MOSTr with a
channel region of a partial depletion type, careless increase of
the impurity concentration of the channel region is not preferred
in that it increases the drain leak current.
[0011] Further, semiconductor devices using bulk silicon substrates
have been being miniatured as well. When using a bulk silicon
substrate, it is not possible to form a surface channel type MOSTr
resistant to a short channel effect simultaneously in both of the
N-channel and the P-channel using only n.sup.+poly-Si for the gate
electrodes. Therefore, as shown in FIGS. 1A to 1C, a so-called dual
gate process of using n.sup.+poly-Si for the NMOSTrs (shown in FIG.
1A) and using p.sup.+poly-Si for the p-channel MOS transistors
(PMOSTr) (shown in FIG. 1B) has been studied for the purpose of
adjustment of the Vth by using the work function of the gate
electrodes.
[0012] However, in this dual gate process as well, when using
poly-Si gate electrodes 14a and 14b of different types of dopants
between the NMOSTr (shown in FIG. 1A) and the PMOSTr (shown in FIG.
1B), as shown in FIG. 1C, there is a problem that impurities in the
gate electrodes diffuse into from each other (indicated by arrows
in the figure) in parts at which the n.sup.+poly-Si gates of the
NMOSTr and the p.sup.+poly-Si gates of the PMOSTr are connected and
that the work functions of the gate electrodes largely
fluctuate.
[0013] This problem becomes particularly conspicuous when a
silicide is further formed at an upper layer of the poly-Si to be
made to tungsten polycide (W-polycide) in order to lower the
resistance of the gate electrodes formed by the dual gate process,
as shown in FIGS. 1A to 1C, since the diffusion coefficient of the
dopant in the tungsten silicide (WSi.sub.x) is extremely large.
[0014] Note that, in FIGS. 1A to 1C, 11 denotes a silicon
substrate, 12 a field oxide film, 13 a gate insulating film, 14a a
gate electrode of a NMOS transistor, 14b a gate electrode of a PMOS
transistor, 14c a junction portion of the gate electrodes of the
NMOS transistor side and the PMOS transistor side, and 15 an
inter-layer insulating film.
[0015] In this way, even in a case where a SOI substrate is used
and even in a case where a bulk silicon substrate is used, in order
to deal with the miniaturization of semiconductor devices in the
future, there is a problem with usage of different types of poly-Si
for the gate electrode material. In place of this, it has been
considered necessary to use a gate electrode material having a work
function near the mid-gap.
[0016] The energy band of the semiconductor has a structure where
an electronically filled band (a filled band or a valence band) and
an empty band (conduction band) are separated by a prohibit band,
and in the present invention, a gate electrode material having a
work function near the mid-gap means a conductive material which
has a work function (energy difference between a vacuum level and a
Fermi level) almost the same as that near the center (near mid-gap)
of the width of this prohibit band (band gap).
[0017] Summarizing the problem to be solved by the invention, among
the gate electrode materials having a work function near this
mid-gap, refractory metal silicide or refractory metal does not
directly react with the SiO.sub.2 and does not cause conspicuous
deterioration of the gate withstand voltage, so attracts attention
as particularly preferred material and has been studied as gate
electrode material.
[0018] However, as shown in FIG. 2, when a gate insulating film 23
is formed on a silicon substrate 21 and a gate electrode is further
formed on this by a single layer film 24 made of WSi.sub.x or
another refractory metal suicide, there is the problem that a
reduction of the gate insulation withstand voltage or a reduction
of a gate capacity occurs in comparison with the case of the
related art where a gate electrode such as poly-Si (or W-polycide)
is used. Note that, in FIG. 2, 21 denotes a silicon substrate, 22 a
field oxide film, 23 a gate insulating film, 24 a gate electrode
made of a single WSi.sub.x layer, and 25 an inter-layer insulating
film.
[0019] The reduction of the gate insulation withstand voltage is
not preferred for a next generation device which is further
miniaturized and where the gate oxide film is made further thinner.
Further, the reduction of the gate capacity invites a reduction of
the drive capability of the transistors etc. and as a result ends
up lowering the operating speed of the device.
SUMMARY OF THE INVENTION
[0020] An object of the present invention is to provide a
semiconductor device having a conductive layer, preferably a gate
electrode, using a conductive material having a work function near
the mid-gap of the energy band gap of the substrate material,
preferably silicon, at least in the vicinity of the boundary with
an insulating film, preferably gate oxide film, formed on the
substrate, not causing deterioration of the insulation withstand
voltage of the insulating film formed on the substrate, not causing
a reduction of the capacity (gate capacity) of the conductive layer
after formation, and maintaining the operating speed of the device
and a method for producing the semiconductor device.
[0021] The present inventor discovered the fact that the reduction
of the gate insulation withstand voltage and the reduction of the
gate capacity in the case of forming the gate electrodes by a
single layer film made of WSi.sub.X or another refractory metal
silicide were due to the heat treatment step performed after the
gate electrodes were formed and to the As and other impurities
being taken into the WSi.sub.x or other refractory metal silicide
and resulting growth of the grain of the WSi.sub.x or other
refractory metal silicide.
[0022] Accordingly, if the growth of the grain of the WSi.sub.x or
other refractory metal silicide can be suppressed by a certain
method, it can be expected that a gate electrode can be obtained in
which the short channel effect is suppressed and the operating
speed of the device is maintained without adding any change to
conditions of the heat treatment step or step for doping the
impurity and without inviting a reduction of the gate insulation
withstand voltage or a reduction of the gate capacity.
[0023] The present inventor engaged in intensive studies and as a
result discovered that by using refractory metal silicide,
refractory metal or other conductive materials having a work
function near the mid-gap of the energy band gap of the substrate
material (silicon) and causing doping of a certain type of impurity
into the conductive material, it is possible to suppress the grain
growth of the conductive material and thereby completed the present
invention.
[0024] Namely, the present invention provides a semiconductor
device comprising a substrate, an insulating film formed in the
substrate, a conductive layer formed on the insulating film and
having at least a part in contact with the insulating film made of
a conductive material having a work function near a substantial
center of an energy band gap of the substrate material, and a
takeout electrode formed in the substrate, characterized in that
the conductive material contains a predetermined amount of
impurity.
[0025] In the semiconductor device of the first aspect of the
invention, the impurity is preferably an impurity suppressing the
grain growth of the conductive material. As the impurity, more
concretely, oxygen, nitrogen, boron, etc. is more preferably
used.
[0026] Alternatively, the conductive layer preferably has a
conductive material containing impurity having different
concentrations in a depth direction (perpendicular direction with
respect to the substrate) and having a work function near the
substantial center of the energy band gap of the substrate
material, for example, a refractory metal silicide layer or a
refractory metal layer, more preferably has a conductive material
with a center region with respect to a depth direction thereof
containing an impurity having a higher concentration than those of
upper and lower regions thereof having the work function near the
substantial center of the energy band gap of a substrate material,
for example, a refractory metal silicide layer or a refractory
metal layer.
[0027] Alternatively, more preferably, the conductive layer
contains two or more types of impurities. Preferably, at least one
of the two or more types of impurities is oxygen, nitrogen, or
boron. Each of the two or more types of impurities further
preferably are contained in a concentration of
1.times.10.sup.19/cm.sup.3 to 1.times.10.sup.21/cm.sup.3- .
[0028] Further, the substrate material is preferably silicon, and
the conductive material is preferably a refractory metal silicide
or a refractory metal.
[0029] As the refractory metal silicide, one, two or more types
selected from a group consisting of tungsten silicide (WSi.sub.x),
molybdenum silicide (MoSi.sub.x), tantalum silicide (TaSi.sub.x),
and titanium silicide (TiSi.sub.x) can be exemplified.
[0030] As the refractory metal, one, two or more types selected
from a-group consisting of tungsten (W), tantalum (Ta), and
titanium (Ti) can be exemplified.
[0031] Further, as the takeout electrode, for example, a source and
a drain formed on the substrate can be mentioned.
[0032] The present invention provides, second, a semiconductor
device comprising a silicon substrate, a gate insulating film
formed in the silicon substrate, a gate electrode formed on the
gate insulating film and having at least a part in contact with the
gate insulating film made of a refractory metal silicide layer
containing an impurity or a refractory metal layer containing an
impurity, and a takeout electrode formed in the silicon substrate.
The second aspect of the invention more concretely specifies the
semiconductor device of the first aspect of the invention.
[0033] In the second aspect of the invention, as the silicon
substrate, an n-type silicon semiconductor substrate, a p-type
silicon semiconductor substrate, an by SOI substrate, etc. can be
used.
[0034] The present invention provides, third, a method for
producing a semiconductor device comprising steps of forming an
insulating film in a substrate, forming a conductive layer made of
a conductive material having a work function near a substantive
center of an energy band gap of the substrate material on the
insulating film, doping an impurity into the conductive layer, and
forming a takeout electrode in the substrate.
[0035] In the third aspect of the invention, the step of doping the
impurity into the conductive layer preferably has a step of doping
the impurity into the conductive layer by an ion implantation
process, a step of doping a impurity suppressing a grain growth of
the conductive layer into the conductive layer by the ion
implantation process and/or a step of forming the conductive film
containing the impurity on the insulating film by a chemical vapor
deposition process (CVD process).
[0036] Further, the step of doping the impurity into the conductive
layer preferably has a step of doping the impurity so that an
impurity concentration varies in a depth direction and more
preferably has a step of doping the impurity into the conductive
layer so that a concentration of the impurity contained in a center
region thereof with respect to a depth direction thereof becomes
higher than impurity concentrations of upper and lower regions
thereof.
[0037] More concretely, the step of doping the impurity into the
conductive layer preferably has a step of doping oxygen, nitrogen,
or boron into the conductive layer.
[0038] Further, the step for doping the impurity into the
conductive layer preferably has a step of doping two or more types
of impurities into the conductive layer and, in this case, more
preferably, has a step of doping at least oxygen, nitrogen, or
boron into the conductive layer and further preferably has a step
of doping each of the two or more types of impurities into the
conductive layer with the concentration of
1.times.10.sup.19/cm.sup.3 to 1.times.10.sup.21/cm.sup.3.
[0039] In the third aspect of the invention, as the substrate,
preferably a silicon substrate such as a p-type silicon
semiconductor substrate, n-type silicon semiconductor substrate, or
SOI substrate is used.
[0040] The step of forming the conductive layer made of the
conductive material having the work function near the substantive
center of the energy band gap of the substrate material preferably
has a step of forming a refractory metal silicide layer or a
refractory metal layer on the substrate.
[0041] The step of forming the refractory metal silicide layer
preferably has a step of forming a layer made of one, two or more
types selected from a group consisting of tungsten silicide
(WSi.sub.x), molybdenum silicide (MoSi.sub.x), tantalum silicide
(TaSi.sub.x), and titanium silicide (TiSi.sub.x).
[0042] Further, the step of forming the refractory metal layer
preferably has a step of forming a layer made of one, two or more
types selected from a group consisting of tungsten (W), tantalum
(Ta), and titanium (Ti).
[0043] Further, the present invention provides, fourth, a method
for producing a semiconductor device comprising steps of forming a
gate insulating film in a silicon substrate, forming a conductive
layer made of a conductive material having a work function of a
substantial center of an energy band gap of the silicon on the gate
insulating film, doping an impurity into the conductive layer,
forming a gate electrode by processing the conductive layer, and
forming a takeout electrode in the silicon substrate. The fourth
aspect of the invention more concretely specifies the invention of
the method of production of the third aspect of the invention and
is the method for producing a semiconductor device according to the
second aspect of the invention.
[0044] In the fourth aspect of the invention, as the silicon
substrate, a p-type silicon semiconductor substrate, n-type silicon
semiconductor substrate, SOI substrate, etc. can be preferably
used.
[0045] The semiconductor devices of the first and second aspects of
the invention are characterized in that at least a part of a
conductive layer, preferably gate electrode, in contact with the
insulating film, preferably gate insulating film, is made of a
conductive material having a work function near the substantive
center of the energy band gap of the substrate material, preferably
refractory metal silicide or refractory metal, and the conductive
material contains an impurity.
[0046] Accordingly, the semiconductor devices of the first and
second aspects of the invention are semiconductor devices having
conductive layers (gate electrodes) in which a so-called short
channel effect is suppressed and the operating speed of the device
is maintained. In addition, they are semiconductor devices in which
the dielectric breakdown of the insulating film of the lower layer
accompanied with grain growth of the refractory metal silicide or
the refractory metal or other conductive material or in a MOSTr the
insulating film (gate insulating film) dielectric breakdown and the
reduction of the gate capacity, which had become a problem of the
related art, are suppressed.
[0047] Further, when the conductive material of the conductive
layer of the semiconductor device of the present invention contains
two or more types of impurities, in comparison with a case where
one type of impurity is doped, it is possible to more effectively
suppress the grain growth of the conductive layer. Accordingly,
even in a case where a thinner insulating film, for example a gate
insulating film having a thickness of about 4 nm, is formed, the
semiconductor devices having a conductive layer, that is, gate
electrodes, excellent in a reliability without causing
deterioration of the insulation withstand voltage are provided.
[0048] Further, according to the method of production of the
semiconductor devices of the third and fourth aspects of the
invention, a semiconductor device can be produced having a
conductive layer, that is, gate electrodes, in which the short
channel effect is suppressed and the operating speed of the device
is maintained without adding any change to the conditions of the
heat treatment step and the step of doping the impurity after this
and without causing a reduction of the insulation withstand voltage
and the reduction of the gate capacity.
[0049] Further, by doping the impurity nonuniformly in the depth
direction of the conductive layer, preferably so that the center
portion with respect to the depth direction of the conductive layer
has a relatively high concentration and the upper and lower regions
thereof have a relatively low concentration, a MOSTr having
insulating film boundary surface characteristics similar to those
of the case where the impurity is not doped can be formed.
Accordingly, according to the methods of production of a
semiconductor device of the present invention, the degree of
freedom of process design of the semiconductor device is not
lowered.
[0050] Further, when there is the step of doping the impurity into
the conductive layer by the ion implantation process, the impurity
can be ion implanted with a correctly controlled acceleration
energy and dosage.
[0051] Accordingly, according to the present invention, the degree
of integration of the LSI can be improved, the drive capability of
the MOSTr can be improved according to the design rule, and high
speed operation of the device becomes possible.
BRIEF DESCRIPTION OF THE DRAWINGS
[0052] These and other objects and features of the present
invention will become clearer from the following description of the
preferred embodiments given with reference to the accompanying
drawings, in which:
[0053] FIGS. 1A to 1C are conceptual views for explaining the
problem of the dual gate process in the related art;
[0054] FIG. 2 is a conceptual view for explaining the problem where
a gate electrode made of a single layer of a refractory metal
silicide of the related art is formed;
[0055] FIGS. 3A to 3B are sectional views of the structure of a
region in which a MOS transistor of a semiconductor device of the
present invention is formed;
[0056] FIGS. 4A to 4B are sectional views of the structure of a
region in which a MOS transistor of a semiconductor device of the
present invention is formed;
[0057] FIGS. 5A to 5D are sectional views of principal steps of a
method for producing a semiconductor device of the present
invention;
[0058] FIGS. 6A to 6D are sectional views of principal steps of a
method for producing a semiconductor device of the present
invention;
[0059] FIGS. 7A to 7D are sectional views of principal steps of a
method for producing a semiconductor device of the present
invention;
[0060] FIGS. 8A to 8D are sectional views of principal steps of a
method for producing a semiconductor device of the present
invention;
[0061] FIGS. 9A to 9C are sectional views of principal steps of a
method for producing a semiconductor device of the present
invention;
[0062] FIGS. 10A to 10C are sectional views of principal steps of a
method for producing a semiconductor device of the present
invention;
[0063] FIGS. 11A to 11C are sectional views of principal steps of a
method for producing a semiconductor device of the present
invention;
[0064] FIG. 12 is a view of results of an evaluation test results
of the gate withstand voltage characteristics (TZDB: Time Zero
Dielectric Breakdown) in a case where a gate insulating film is
formed on a silicon substrate and a gate electrode made of a
WSi.sub.x film containing various concentrations of nitrogen is
further formed thereon, in which an ordinate represents a
cumulative failure rate, and an abscissa represents a gate
withstand voltage; and
[0065] FIG. 13 is a view of results of an evaluation test of the
gate withstand voltage characteristics (TZDB) in a case where a
gate insulating film is formed on a silicon substrate and a gate
electrode made of a WSi.sub.x film containing a predetermined
concentration of nitrogen and various concentrations of boron is
further formed thereon, in which an ordinate represents the
cumulative failure rate, and an abscissa represents the gate
withstand voltage.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0066] Below, embodiments of the present invention will be
explained by referring to the drawings.
[0067] First Embodiment
[0068] The first embodiment is a semiconductor device having a
p-channel MOS transistor as shown in FIG. 3A.
[0069] The semiconductor device shown in FIG. 3A has a gate oxide
film 103 made of silicon oxide on a region of an n-type silicon
semiconductor substrate 101 sectioned by a field oxide film 102 and
further has a gate electrode having a single layer structure made
of a WSi.sub.x (tungsten silicide) film 104 having a thickness of
about 100 nm on this gate oxide film 103.
[0070] Further, an impurity diffusion region (source and drain
region) doped with the p-type impurity is formed in a peripheral
area below a gate electrode of the n-type silicon semiconductor
substrate 101 and electrically connected to an interconnection
layer 108 via connection plugs 107. The upper portion of the gate
electrode has a structure covered by an inter-layer insulating film
106.
[0071] The WSi.sub.x film 104 of the gate electrode of this
semiconductor device contains oxygen in a dosage of
5.times.10.sup.14/cm.sup.2 (about 5.times.10.sup.19/cm.sup.3 in
concentration). As a result, the grain size of the WSi.sub.x film
104 is suppressed to a size of about 20 nm at the maximum even
after heat treatment at for example 850.degree. C. for 30
minutes.
[0072] Accordingly, the semiconductor device of the present
embodiment is a semiconductor device having a MOS transistor with a
high reliability in which the short channel effect is suppressed
without causing a reduction of the insulation withstand voltage and
the reduction of the gate capacity and by which the operating speed
of the device is maintained.
[0073] Second Embodiment
[0074] The second embodiment is a semiconductor device having an
n-channel MOS transistor as shown in FIG. 3B. The semiconductor
device shown in FIG. 3B has substantially the same structure as
that of the semiconductor device shown in the first embodiment. The
gate electrode is formed by a single WSi.sub.x film layer 204
containing oxygen as an impurity.
[0075] In this semiconductor device, the oxygen concentration in
the WSi.sub.x film 204 is changed with respect to the depth
direction. Namely, the WSi.sub.x film 204 has a structure where the
oxygen concentration is sufficiently low (about 10.sup.17/cm.sup.3
or less) in the boundary surface region with a gate oxide film 203
(WSi.sub.x film 204a: region with a thickness of about 10 nm from
the gate oxide film 203 side), then the oxygen concentration
becomes for example about 5.times.10.sup.19/cm.sup.3 in the center
region (WSi.sub.x film 204b: region with a thickness of about 30 nm
from 204a side), and further the oxygen concentration becomes about
1.times.10.sup.17cm.sup.3 or less in the region above the former
(WSi.sub.x film 204c: region with a thickness of about 60 nm from
204b side).
[0076] By forming the gate electrode of the semiconductor device of
the present embodiment by such a structure, it becomes possible to
suppress the grain growth of the WSi.sub.x film 204a in the
vicinity in contact with at least the gate oxide film 203 of the
WSi.sub.x film 204 while holding the boundary surface
characteristic between the WSi.sub.x film 204 and the underlying
gate oxide film 203.
[0077] Namely, in the center region (WSi.sub.x film 204b) in which
the oxygen concentration is relatively high, i.e., about
5.times.10.sup.19/cm.sup.3, the grain growth of the WSi.sub.x is
obstructed due to the influence of this oxygen. Also, in the
WSi.sub.x film 204a of the part (lower region) in contact with the
gate oxide film having a relatively low oxygen concentration, the
grain growth is suppressed due to the restriction of the grain
growth in the depth direction thereof.
[0078] Further, the region with the thickness of 60 nm of the
WSi.sub.x film 204c located in the uppermost layer (upper region)
of the gate electrode, the impurity concentration of the oxygen is
also relatively low (it is not necessary to raise the oxygen
concentration) and the thickness is relatively large, so the grains
are relatively large and grow to the size of about 50 nm, but the
growth of the WSi.sub.x film 204c does not assist the deterioration
of the gate-insulation withstand voltage and the reduction of the
gate capacity and contribute to only the reduction of the
resistance of the gate electrode.
[0079] Accordingly, the semiconductor device of the present
embodiment is a semiconductor device having a MOS transistor with
an extremely high reliability in which the short channel effect is
suppressed, the operating speed of the device is maintained, and
gate insulating film dielectric breakdown and the reduction of the
gate capacity are further suppressed.
[0080] Third Embodiment
[0081] The third embodiment is a semiconductor device having a
similar structure to that of the semiconductor device of the first
embodiment (illustration is omitted for convenience). The gate
electrode of this semiconductor device is made of a single layer of
a WSi.sub.x film doped with nitrogen in a dosage of
5.times.10.sup.15/cm.sup.2 (5.times.10.sup.20/cm.sup.3 in terms of
concentration) in place of oxygen.
[0082] In this case as well, the grain size of the WSi.sub.x film
is a size within about 20 nm even after heat treatment at for
example 850.degree. C. for 30 minutes.
[0083] Accordingly, the semiconductor device of the present
embodiment is a semiconductor device having a MOS transistor with
an extremely high reliability in which the short channel effect is
suppressed, the operating speed of the device is maintained, and
gate insulating film dielectric breakdown and the reduction of the
gate capacity are further suppressed.
[0084] Fourth Embodiment
[0085] The fourth embodiment is a semiconductor device having an
n-channel MOS transistor as shown in FIG. 4A.
[0086] The semiconductor device shown in FIG. 4A has a gate oxide
film 303 made of silicon oxide on a region of a p-type silicon
semiconductor substrate 301 sectioned by a field oxide film 302 and
further has a gate electrode having a single layer structure of a
WSi.sub.x (tungsten silicide) film 304 having a thickness of about
100 nm on this gate oxide film 303.
[0087] This semiconductor device has a lightly doped drain (LDD)
structure in which a side wall protection film 306 is formed on a
side wall portion of the gate electrode, an n.sup.+ impurity
diffusion region (source and drain region) 307 doped with an n-type
impurity is formed in a peripheral area below the side wall
protection film 306 of the p-type silicon semiconductor substrate
301, and further an .sup.- impurity diffusion region 305 is formed
in the channel region adjoining the n.sup.+ impurity diffusion
region. For this reason, the influence upon the source end is
suppressed by having the drain field absorbed into the .sup.-
impurity diffusion region 305 and the field intensity is
reduced.
[0088] Further, the n.sup.+ impurity diffusion region 307 is
electrically connected to an interconnection layer 310 via
connection plugs 309. The upper portion of the gate electrode has a
structure covered by an inter-layer insulating film 308.
[0089] In the WSi.sub.x film 304 of the gate electrode of this
semiconductor device, nitrogen in a dosage of
5.times.10.sup.15/cm.sup.2 (about 5.times.10.sup.20/cm.sup.3 in
concentration) and boron in a dosage of 5.times.10.sup.15/cm.sup.2
(about 5.times.10.sup.20/cm.sup.3 in concentration) are
simultaneously doped.
[0090] As a result, the grain size of the WSi.sub.x film 304
becomes a size within about 15 nm even after heat treatment at for
example 850.degree. C. for 30 minutes. The grain growth of the
WSi.sub.x film is further suppressed from that of the case where
only nitrogen is doped.
[0091] Accordingly, the semiconductor device of the present
embodiment is a semiconductor device having a MOS transistor with
an extremely high reliability in which gate insulating film
dielectric breakdown and the reduction of the gate capacity are
further suppressed.
[0092] Fifth Embodiment
[0093] The fifth embodiment is a semiconductor device having an
n-channel MOS transistor having a similar structure to that of the
semiconductor device of the second embodiment (the illustration is
omitted for convenience).
[0094] The gate electrode of this semiconductor device has a gate
electrode made of a single layer structure of a WSi.sub.x film
having a thickness of about 100 nm containing nitrogen and boron as
impurities. The WSi.sub.x film uniformly contains the boron in a
concentration of about 1.times.10.sup.19/cm.sup.3 and contains the
nitrogen in varied concentrations thereof with respect to the depth
direction.
[0095] Namely, this WSi.sub.x film has a structure in which the
nitrogen concentration is sufficiently low (about
10.sup.19/cm.sup.3 or less) in the surface boundary region with the
gate oxide film (first region with a thickness of about 10 nm from
the gate oxide film side), then the nitrogen is contained with a
concentration of for example about 1.times.10.sup.21/cm.sup.3 in
the center region (second region with a thickness of about 30 nm
from the first region side), and further the oxygen is contained so
that the concentration becomes about 1.times.10.sup.19/cm.sup.3 or
less in the region above this (third region with a thickness of
about 60 nm from the second region side).
[0096] By forming the gate electrode of the semiconductor device of
the present embodiment with such a structure, it becomes possible
to suppress the grain growth of the WSi.sub.x film of the first
region in the vicinity in contact with the gate oxide film while
holding an excellent surface boundary characteristic between the
WSi.sub.x film and the gate oxide film of the underlying layer.
[0097] Namely, in the center region (second region) in which the
nitrogen concentration is relatively high, i.e.,
1.times.10.sup.21/cm.sup.3, the grain growth of the WSi.sub.x is
obstructed due to the influence of the nitrogen and boron. Also, in
the WSi.sub.x film of the part (first region) in contact with the
gate oxide film in which the nitrogen concentration is relatively
low, the grain growth is suppressed due to the restriction of the
grain growth in its thickness direction.
[0098] Further, in the region with a thickness of 60 nm of the
WSi.sub.x film located in the uppermost layer (third region) of the
gate electrode, the impurity concentration of the nitrogen is also
relatively low (it is not necessary to raise the nitrogen
concentration) and the film substrate is relatively thick,
therefore the go grains grow relatively large (about 30 nm), but
the growth of the WSi.sub.x film in this third region does not
assist the deterioration of the gate insulation withstand voltage
and the reduction of the gate capacity and only contributes to the
reduction of the resistance of the gate electrode.
[0099] Accordingly, the semiconductor device of the present
embodiment is one having a MOS transistor with an extremely high
reliability in which the gate insulating film dielectric breakdown
and the reduction of the gate capacity are further suppressed.
[0100] In the first to fifth embodiments explained above, the
present invention was explained by taking as an example a
semiconductor device having a gate electrode made of a single
WSi.sub.x film. The semiconductor device of the present invention
is not limited to this, however. The gate electrode thereof may be
formed by another refractory metal silicide, for example,
molybdenum silicide (MoSi.sub.x), tantalum silicide (TaSi.sub.x),
or titanium silicide (TiSi.sub.x), a refractory metal, for example,
tungsten (W), tantalum (Ta), or titanium (Ti), or another
conductive material.
[0101] Sixth Embodiment
[0102] Further, it is possible even if the gate electrode is formed
by a laminate of a refractory metal silicide or refractory metal
and conductive polycrystalline silicon layer doped with a p-type
impurity or n-type impurity. The sixth embodiment is a
semiconductor device having such a gate electrode.
[0103] The semiconductor device shown in FIG. 4B has a gate oxide
film 403 made of silicon oxide on a region of an n-type silicon
semiconductor substrate 401 sectioned by a field oxide film 402 and
further has a gate electrode having a dual layer structure
comprising a WSi.sub.x film 404a having a thickness of about 60 nm
on this gate oxide film 403 and a conductive polycrystalline
silicon layer 404b on the WSi.sub.x film 404a.
[0104] Further, in the peripheral region below the gate electrodes
of the n-type silicon semiconductor substrate 401, an impurity
diffusion region (source and drain region) 405 doped with the
p-type impurity is formed and electrically connected to an
interconnection layer 408 via connection plugs 407. The upper
portion of the gate electrode has a structure covered by an
inter-layer insulating film 406.
[0105] The WSi.sub.x film 404a of the gate electrode of this
semiconductor device is formed in contact with the top of the gate
insulating film 403 and contains oxygen in a dosage of
5.times.10.sup.14/cm.sup.2 (about 5.times.10.sup.19/cm.sup.3 in
concentration). As a result, the grain size of the WSi.sub.x film
404a is suppressed to a size of about 20 nm at the maximum even
after heat treatment at for example 850.degree. C. for 30
minutes.
[0106] Accordingly, in the semiconductor device of the present
embodiment as well, a semiconductor device having a MOS transistor
with a high reliability in which the short channel effect is
suppressed and the operating speed of the device is maintained
without inviting a reduction of the insulation withstand voltage
and a reduction of the gate capacity is obtained.
[0107] In the sixth embodiment, an explanation was made by taking
as an example a semiconductor device having a gate electrode of a
laminate structure of a WSi.sub.x film and conductive
polycrystalline silicon, but it may also be formed by a laminate of
a refractory metal silicide or refractory metal other than
WSi.sub.x and the conductive polycrystalline silicon. Note that the
boundary part with at least the gate insulating film must be formed
by a conductive material having a work function of the substantive
center of the mid-gap of the substrate material.
[0108] Further, in the first to sixth embodiments, the explanation
was made by taking as an example a semiconductor device in which
the conductive layer was the gate electrode formed on the gate
insulating film, but it may also be a semiconductor device in which
the conductive layer is a MOS capacitor of a similar structure
other than this or a semiconductor device in which a conductive
layer doped with an impurity is used for the electrodes of the
MOSTr MOS capacitor formed on a p-well or an n-well provided on the
silicon semiconductor substrate.
[0109] Further, in the first to sixth embodiments, a bulk silicon
substrate (n-type silicon semiconductor substrate) was used as the
substrate, but it may also be a bulk silicon substrate (p-type
silicon semiconductor substrate) or substrate of an SOI
structure.
[0110] Next, the method for producing the semiconductor device will
be explained in detail.
[0111] Note that the thickness of the conductive layer (WSi.sub.x
film), the dosage of impurity suppressing the grain growth,
implantation conditions, conditions of heat treatment, etc. in the
following embodiments are only examples thereof and that the design
can be appropriately changed according to the semiconductor device
to be formed.
[0112] Seventh Embodiment
[0113] The seventh embodiment is a method for producing a
semiconductor device of the first embodiment. FIG. 5A to FIG. 5D
and FIG. 6A to FIG. 6D show the steps of production of the MOSTr
produced according to the present embodiment.
[0114] First, an explanation will be made of the steps up to FIG.
5A. On the p-type silicon semiconductor substrate 101, the field
oxide film 102 is formed to a thickness of about 400 nm by the
local-oxidation-of-silico- n (LOCOS) process for wet oxidation at
for example 950.degree. C.
[0115] Next, the ions for the threshold voltage (Vth) are implanted
in a surface layer portion of the active region serving as the
source and drain region and the channel region, and the ions for
forming a buried layer for preventing punch through are implanted
in a deep portion of the silicon semiconductor substrate 101
(illustration omitted).
[0116] Then, pyrogenic oxidation is carried out at a temperature
condition of 850.degree. C. by using a gas mixture of H.sub.2 and
O.sub.2. The gate oxide film 103 is formed on the region of the
silicon substrate 101 sectioned by the field oxide film 102 with a
thickness of for example 5 nm. A structure shown in FIG. 5A is
obtained as described above.
[0117] Thereafter, as shown in FIG. 5B, the WSi.sub.x film 104 of
the gate electrode is stacked to about 100 nm. The WSi.sub.x (film)
104 is formed by a low pressure chemical vapor deposition (LP-CVD)
process under the following silicon-rich (WSi.sub.x: x=3.0)
conditions in an SiH.sub.2Cl.sub.2+WF.sub.6 reaction system so as
not to conspicuously cause deterioration of the bonding and gate
withstand voltage even if directly stacked on the gate oxide film
103.
[0118] Conditions for Forming WSi.sub.x film 104
[0119] Film forming device: Cold-Wall type LP-CVD device
[0120] Film forming temperature: 600.degree. C.
[0121] Film forming pressure: 40 Pa
[0122] Film forming gas (flow rate):
SiH.sub.2Cl.sub.2/WF.sub.6/Ar=160/1.6- /100 sccm
[0123] Note that, as the tungsten silicide represented by WSi.sub.x
(x represents any number of 1 to 3), for example, W.sub.2Si.sub.3,
WSi.sub.2, WSi.sub.3, etc. have been known.
[0124] Then, as shown in FIG. 5C, oxygen ions (O.sub.2.sup.+ ions)
are implanted into the entire surface under the conditions of an
acceleration energy of 15 keV and a dosage of
5.times.10.sup.14/cm.sup.2 in order to suppress the grain growth of
the WSi.sub.x film 104. The ions are implanted at this time so that
the range of flight of the O.sub.2.sup.+ ions is in the WSi.sub.x
film 104.
[0125] Further, as shown in FIG. 5D, a photoresist 109 is coated on
the entire surface, patterning is carried out, and a resist pattern
of the gate electrodes copying the gate electrode pattern is
formed.
[0126] Next, as shown in FIG. 6A, the WSi.sub.x film 104 is etched
with this pattern formed resist 109 as a mask to form the gate
electrodes.
[0127] The etching conditions at this time are for example as
follows:
[0128] Etching device: ECR (electron cyclotron resonance) plasma
etching device
[0129] Etching temperature: 20.degree. C.
[0130] Pressure: 0.4 Pa
[0131] RF power: Step 1=80W, Step 2=30W
[0132] Gas flow rate: Cl.sub.2/O.sub.2=75/5 sccm
[0133] Then, as shown in FIG. 6B, for example the p-type impurity
BF.sub.2.sup.+ is implanted with an acceleration energy of about 20
keV and a dosage of about 3.times.10.sup.15/cm.sup.2 into the
region of the n-type silicon semiconductor substrate 101 sectioned
by the field oxide film 102 at the peripheral area below the gate
electrodes using the resist mask 110 and the gate electrode 104 as
a mask. Thereafter, heat treatment is carried out for 30 minutes at
850.degree. C. in an N.sub.2 atmosphere, then the impurity is
activated so as to form a p-type impurity diffusion region (source
and drain region) 105.
[0134] Thereafter, as shown in FIG. 6C, the resist mask 110 ,is
removed and, as shown in FIG. 6D, the low pressure CVD process
using for example O.sub.2-TEOS (tetraethylorthosilicate) is used to
stack the inter-layer insulating film 106 over the entire
surface.
[0135] Further, contact holes reaching the p-type impurity
diffusion region 105 are opened in the inter-layer insulating film
106 and a metal such as tungsten or aluminum is buried in the
contact holes to form the contact plugs 110. The interconnection
layer 111 made of aluminum or the like is then sequentially formed
to produce a semiconductor device having the p-channel MOS
transistor as shown in FIG. 3A.
[0136] According to the present embodiment, the WSi.sub.x film 104
of the gate electrode doped with oxygen in a dosage of
5.times.10.sup.14/cm.sup.- 2 (about 5.times.10.sup.19/cm.sup.3 in
concentration) can be formed conveniently and with a good yield.
Further, the grain size of this WSi.sub.x film 104 can be
suppressed to a size of about 20 nm at the maximum even after heat
treatment (annealing after ion implantation) at for example
850.degree. C. for 30 minutes. Accordingly, a semiconductor device
having a MOS transistor with a high reliability in which the gate
insulation layer dielectric breakdown and the reduction of the gate
capacity are suppressed can be produced.
[0137] Eighth Embodiment
[0138] The present embodiment is an example of producing the
semiconductor device of the second embodiment. In the seventh
embodiment, the oxygen ions are uniformly. implanted into the
WSi.sub.x film on the gate oxide film, but in the present
embodiment, the concentration of the oxygen ions contained in the
WSi.sub.x film constituting the gate electrode is varied in the
depth direction.
[0139] First, as shown in FIG. 7A, similar to the first embodiment,
a field oxide film 202 is formed to a thickness of about 400 nm on
the p-type silicon semiconductor substrate 201 by the LOCOS process
for wet oxidation at for example 950.degree. C.
[0140] Then, ions for the threshold voltage (Vth) adjustment are
implanted in the surface layer portion of the active region forming
the source and drain region and the channel region, and ions for
forming the buried layer for preventing punchthrough are implanted
at the deep portion of the silicon semiconductor substrate 201
(illustration omitted).
[0141] Then, the pyrogenic oxidation is carried out at the
temperature condition of 850.degree. C. by using the gas mixture of
H2 and O2, and the gate oxide film 203 is formed on the region
sectioned by the field oxide film 202 of the silicon substrate 201
with a thickness of for example 5 nm. A structure shown in FIG. 7A
is obtained as described above.
[0142] Then, as shown in FIG. 7B, the CVD process using
SiH.sub.2Cl.sub.2--WF.sub.6 is used to form a WSi.sub.x film 204'
stacked on the gate oxide film 203 to a thickness of 100 nm.
Thereafter, the oxygen ions are implanted in the WSi.sub.x film
204' so that the concentration of oxygen ions varies in the
thickness direction (depth direction).
[0143] The ion implantation process can accurately control the
energy and dosage of the ion implantation when the impurity is
implanted and can determine the position of ions to be implanted by
adjusting the energy (that is, it is determined to how deep a
position from the surface on the ion implantation side the impurity
ions are implanted). Further, by adjusting the dosage of the ion
implantation, the concentration of the impurity to be doped can be
adjusted.
[0144] In the present embodiment, the oxygen ions are implanted
under for example the following conditions:
[0145] First, the oxygen ions are implanted within the range of
about 10 nm in an upward direction from the gate oxide film
boundary surface of the part in contact with the gate oxide film of
the WSi.sub.x film 204' so that the oxygen concentration becomes
1.times.10.sup.17/cm.sup.3 or less (formation of the WSi.sub.x film
204a).
[0146] Then, the oxygen ions are implanted in the WSi.sub.x film
having a thickness of about 30 nm in the center region located
within the range of 10 to 40 nm in the upward direction from the
gate-oxide film boundary surface of the WSi.sub.x film 204' so that
the oxygen concentration becomes about 5.times.10.sup.19/cm.sup.3
(formation of the WSi.sub.x film 204b).
[0147] Finally, the ions are implanted in the WSi.sub.x film 204'
within the range of about 60 nm on this so that the oxygen
concentration becomes about 1.times.10.sup.17/cm.sup.3 or less
formation of the WSi.sub.x film 204c).
[0148] As described above, as shown in FIG. 7C, an WSi.sub.x film
204 is obtained containing oxygen so that the oxygen concentration
varies in the thickness direction (depth direction).
[0149] Next, similar to the seventh embodiment, a not illustrated
photoresist is coated on the entire surface and then patterned to
form a resist pattern of gate electrodes copying the gate electrode
pattern. Further, the WSi.sub.x film 204 is etched with this
pattern-formed resist 109 as a mask to form the gate electrodes. A
structure shown in FIG. 7D is obtained in the above way.
[0150] Thereafter, a similar process as that of the seventh
embodiment is followed to produce the semiconductor device as shown
in FIG. 3B.
[0151] According to the present embodiment, the grain growth of the
WSi.sub.x film 204a in the vicinity in contact with at least the
gate oxide film 203 of the WSi.sub.x film 204 can be suppressed
while holding the boundary surface characteristic between the
WSi.sub.x film 204 and the gate oxide film 203 of the underlying
layer.
[0152] Namely, in the center region (WSi.sub.x film 204b) in which
the oxygen concentration is relatively high, i.e.,
5.times.10.sup.19/cm.sup.3- , the grain growth of the WSi.sub.x is
obstructed due to the influence of the oxygen. Further, in the
WSi.sub.x film 204a of the part (lower region) in contact with the
gate oxide film in which the oxygen concentration is relatively
low, the grain growth in the thickness direction is restricted, so
the grain growth can be suppressed.
[0153] Further, in the region with the thickness of 60 nm of the
WSi.sub.x film 204c located in the uppermost layer (upper region)
of the gate electrode, the impurity concentration of oxygen is
relatively low (it is not necessary to raise the oxygen
concentration) and the thickness is relatively large, so the grains
are also relatively large and grow to a size of about 50 nm, but
the growth of the WSi.sub.x film 204c in this part does not assist
the deterioration of the gate insulation withstand voltage and the
reduction of the gate capacity and only contributes to the
reduction of the resistance of the gate electrodes.
[0154] Accordingly, according to the present embodiment, a
semiconductor device having a MOS transistor with an extremely high
reliability in which the gate insulation dielectric breakdown and
the reduction of the gate capacity are further suppressed can be
produced.
[0155] Ninth Embodiment
[0156] The ninth embodiment is an example of production of the
semiconductor device shown in the fourth embodiment. Below, the
method of production of the semiconductor device of the present
embodiment will be explained by referring to the drawings.
[0157] First, as shown in FIG. 8A, a field oxide film 302 is formed
on an n-type silicon semiconductor substrate 301 to a thickness of
about 400 nm by the LOCOS process for wet oxidation at for example
950.degree. C.
[0158] Next, ions for the threshold voltage (Vth) adjustment are
implanted at the surface layer portion of the active region forming
the source and drain region and the channel region, and ions for
forming the buried layer for preventing the punchthrough are
implanted at the deep portion of the silicon semiconductor
substrate 301 (illustration omitted).
[0159] Next, pyrogenic oxidation is carried out under temperature
conditions of 850.degree. C. by using a gas mixture of H.sub.2 and
O.sub.2 to form a gate oxide film 303 on the region of the silicon
substrate 301 sectioned by the field oxide film 3O.sub.2 to a
thickness of for example 4 nm.
[0160] Then, as shown in FIG. 8B, a WSi.sub.x film 304' is formed
on the gate oxide film 303 to a thickness of about 100 nm. This
WSi.sub.x film 304' must be formed under silicon-rich (WSi.sub.x:
x=3.0) conditions in the reaction system of
SiH.sub.2Cl.sub.2+WF.sub.6 so as not to conspicuously cause the
deterioration of the bonding and gate withstand voltage even if the
WSi.sub.x film 304' is directly stacked on the gate oxide film
303.
[0161] Next, the impurity is doped into the WSi.sub.x film. The
doping of the impurity is effectively carried out before the
application of the heat treatment at first after stacking the
WSi.sub.x. Most preferably, it is doped in-situ when the WSi.sub.x
is stacked. In the present embodiment, the boron is uniformly doped
in the thickness direction of the WSi.sub.x, and the nitrogen is
doped after the formation of the WSi.sub.x film. For example, under
the following conditions, an Si.sub.x film doped with the boron
in-situ is formed:
[0162] Film forming device: Cold-Wall type LP-CVD device
[0163] Film forming temperature: 680.degree. C.
[0164] Film forming pressure: 40 Pa
[0165] Film forming gas (flow rate):
SiH.sub.2Cl.sub.2/WF.sub.6/B.sub.2H.s- ub.6/Ar=160/1.6/0.5/100
sccm.
[0166] Then, as shown in FIG. 8C, nitrogen ions are implanted into
the entire surface under conditions of for example an energy of 20
keV and a dosage of 5.times.10.sup.15/cm.sup.2. At this time, the
range of flight of the nitrogen ions must be in the WSi.sub.x
film.
[0167] Thereafter, as shown in FIG. 8D, a resist pattern 311 of the
gate electrodes is formed, then, as shown in FIG. 9A, the resist
pattern 311 is used as a mask to process the WSi.sub.x film 304'
under the following etching conditions to form the gate electrodes
304.
[0168] Etching Conditions of WSi.sub.x
[0169] Etching device: ECR Plasma Etcher
[0170] Etching temperature: 20.degree. C.
[0171] Etching pressure: 0.4 Pa
[0172] Rf Power: Step 1=80W, Step 2=30W
[0173] Etching gas: Cl.sub.2/O.sub.2=75/5 sccm
[0174] Next, as shown in FIG. 9B, by doping the impurity into the
peripheral area below the gate electrode of the region of the
silicon substrate 301 sectioned by the field oxide film 302, the
p-type impurity diffusion region 305 is formed. In the present
embodiment, a PMOS transistor is formed, therefore, BF.sub.2.sup.+
ions are implanted with an acceleration energy of about 20 keV and
a dosage of 3.times.10.sup.15/cm.sup.2.
[0175] In this case, when an NMOS transistor is formed, As ions can
be implanted in place of BF.sub.2.sup.+ ions. Further, for example,
where an n-channel MOS transistor and p-channel MOS transistor are
formed on the same silicon substrate like a CMOS transistor, it is
necessary to use a resist mask to separately implant impurity ions
of different conductivity types in the regions for forming the
n-channel MOS transistor and the p-channel MOS transistor.
[0176] Next, as shown in FIG. 9C, silicon oxide film is stacked by
the LP-CVD process using for example O.sub.2-TEOS, then the side
wall protection film 303 is formed by anisotropic etching.
[0177] Thereafter, the impurity is implanted in the peripheral area
below the gate electrodes at the region of the silicon substrate
301 sectioned by the field oxide film 302 using the side wall
protection film 303 as a mask. In the present embodiment, a PMOS
transistor is formed, so as the condition of the ion implantation,
for example, BF.sub.2.sup.+ ions are implanted with an acceleration
energy of 10 to 30 keV and a dosage of
3.times.10.sup.15/cm.sup.2.
[0178] In this case, when an NMOS transistor is formed, As ions are
implanted in place of BF.sub.2.sup.+ ions. Further, for example,
where an n-channel MOS transistor and p-channel MOS transistor are
formed on the same silicon substrate like in a CMOS, it is
necessary to use a resist mask to separately implant impurity ions
of different conductivity types in the regions for forming the
n-channel MOS transistor and the p-channel MOS transistor.
[0179] Further, the impurity is diffused, then the impurity is
activated under the following conditions in an N.sub.2 atmosphere
to form the source and drain region 307.
[0180] Heat Treatment Conditions of Activation
[0181] Device: Electric furnace annealing device
[0182] Temperature: 850.degree. C.
[0183] Time: 30 minutes
[0184] Then, by the usual process, an inter-layer insulating film
308 comprising three layers of a silicon oxide film, silicon
nitride film, and boro-phosphosilicate glass (BPSG) (or non-doped
silicate glass (NSG)) film is formed. For example, a silicon oxide
film of a thickness of about 100 nm is stacked at a temperature of
about 450.degree. C. by a LP-CVD process using a gas mixture of
SiH.sub.4 and O.sub.2, a silicon nitride film is formed on the
silicon oxide film to a thickness of about 30 to 80 nm at a
temperature of 760.degree. C. by the LP-CVD process using a gas
mixture of for example SiH.sub.2Cl.sub.2 and NH.sub.3, and further
a BPSG film or NSG film is formed on this silicon nitride film to a
thickness of about 250 nm at a temperature of about 700.degree. C.
by the low pressure CVD process using a gas mixture of for example
O.sub.2 and TEOS, whereby an inter-layer insulating film 308
comprising three layers can be obtained.
[0185] Thereafter, a not illustrated resist pattern for forming the
contact holes is formed on the inter-layer insulating film 308,
then the BPSG (or NSG) film, silicon nitride film, and silicon
oxide film are sequentially etched by anisotropic etching using the
resist pattern as a mask, whereby not illustrated contact holes
reaching the source and drain region 307 are opened. Then, these
contact holes are buried with tungsten by for example the CVD
process to form the connection plugs 309, then an interconnection
layer 310 made of aluminum or the like is formed on this and other
steps gone through to produce the semiconductor device as shown in
FIG. 4A.
[0186] In the above way, a semiconductor device having a gate
electrode made of WSi.sub.x containing boron and nitrogen as
impurities can be produced conveniently and with a good yield. The
semiconductor device of the present embodiment is a semiconductor
device having a MOS transistor with a high reliability in which
gate insulating film dielectric breakdown and the reduction of the
gate capacity are further suppressed since it has the gate
electrodes formed of WSi.sub.x containing boron and nitrogen as
impurities.
[0187] Particularly, in the present embodiment, when stacking
WSi.sub.x, the boron is doped in-situ, therefore it becomes
possible to dope this so that the concentration becomes uniform in
the depth direction in comparison with the case where this is doped
by ion implantation.
[0188] 10th Embodiment
[0189] The 10th embodiment is an example of the method of
production of the semiconductor device shown in the fifth
embodiment. First, after going through similar processes to those
of the ninth embodiment, as shown in FIG. 10A, a gate oxide film
503 is formed on a region of an n-type silicon semiconductor
substrate 501 separated by a field oxide film 502.
[0190] Then, by combining the following conditions, a WSi.sub.x
film containing nitrogen and varying in concentration in the
thickness direction (depth direction) is stacked on the gate
insulating film.
[0191] As the first step, as shown in FIG. 10B, a WSi.sub.x film
504a is formed under the following conditions:
[0192] Film forming device: Cold-Wall type LP-CVD device
[0193] Film forming temperature: 680.degree. C.
[0194] Film forming pressure: 40 Pa
[0195] Film forming gas (flow rate):
SiH.sub.2Cl.sub.2/WF.sub.6/B.sub.2H.s- ub.6/Ar=160/1.6/0.5/100
sccm
[0196] As the second step, as shown in FIG. 10C, a WSi.sub.x film
504b is formed under the following conditions:
[0197] Film forming device: Cold-Wall type LP-CVD device
[0198] Film forming temperature: 680.degree. C.
[0199] Film forming pressure: 40 Pa
[0200] Film forming gas (flow rate):
SiH.sub.2Cl.sub.2/WF.sub.6/B.sub.2H.s-
ub.6/Ar/NH.sub.3=160/1.6/0.5/100/1.0 sccm
[0201] As the third STEP, as shown in FIG. 11A, a WSi.sub.x film
504c is formed under the following conditions:
[0202] Film forming device: Cold-Wall type LP-CVD device
[0203] Film forming temperature: 680.degree. C.
[0204] Film forming pressure: 40 Pa
[0205] Film forming gas (flow rate):
SiH.sub.2Cl.sub.2/WF.sub.6/B.sub.2H.s- ub.6/Ar=160/1.6/0.5/100
sccm
[0206] Further, a not illustrated resist pattern for forming the
gate electrodes is formed and the WSi.sub.x films 504a and 504b and
504c are etched similar to the ninth embodiment to form the gate
electrodes as shown in FIG. 11B.
[0207] Thereafter, while the illustration of the steps is omitted,
in the same way as in the ninth embodiment, a p-type impurity is
diffused in the peripheral area below the gate electrodes of the
silicon semiconductor substrate 501 by the ion implantation
process, then activated by applying heat treatment (annealing),
whereby the source and drain region 505 is formed. An inter-layer
insulating film 506 is formed on the entire surface, then contact
holes reaching the source and drain region 505 are formed in the
inter-layer insulating film 506 and are buried by a conductive
material such as tungsten to form the contact plugs 507. An
interconnection layer 508 made of aluminum or the like is formed on
this, whereby the semiconductor device as shown in FIG. 11C can be
produced.
[0208] In the present embodiment, as the method of nonuniformly
doping the impurity obstructing the grain growth of WSi.sub.x in
the depth direction of the WSi.sub.x film 504, the CVD steps are
changed (first step->second step->third step) and the
impurity profile is controlled to mix in the impurity. By forming
the WSi.sub.x film while varying the nitrogen concentration in the
depth direction in this way, the grain growth of WSi.sub.x is
obstructed in the center region (504b) of the WSi.sub.x film 504.
By the restriction of the grain growth in the depth direction
thereof, the grain growth in the WSi.sub.x film 504a can be
suppressed near the boundary surface (504a) with the thermal oxide
film 503 of the lower region thereof while maintaining the bonding
and work function in a state not influenced by the mixing of this
impurity (while holding an excellent boundary surface
characteristic). Further, in the upper layer part (upper region
504c) of the WSi.sub.x film 504, the grains of the WSi.sub.x film
grow large without being influenced by the impurity, but this
influence is not exerted near the boundary surface (504a) with the
thermal oxide film 503, so a WSi.sub.x film 504c with a low
resistance is obtained.
[0209] Accordingly, the semiconductor device of the present
embodiment has a MOS transistor with a high reliability in which
gate insulation dielectric breakdown and the reduction of the gate
capacity are suppressed.
[0210] Note that, in the present embodiment, the concentration of
the nitrogen contained in the WSi.sub.x film is varied in the depth
direction according to whether or not NH.sub.3 is added to the gas
composition in the CVD step, but it is also possible to form the
WSi.sub.x film so that the concentration of the nitrogen contained
in the WSi.sub.x film continuously varies in the thickness
direction by continuously changing the flow rate of the
NH.sub.3.
[0211] 11th Embodiment
[0212] In the present embodiment, it is checked how the withstand
voltage characteristic of the gate oxide film varies when changing
the content of the nitrogen as the impurity in the WSi.sub.x film
when forming a gate oxide film on a silicon semiconductor substrate
and further forming an WSi.sub.x film on the gate oxide film.
[0213] Namely, a gate oxide film of a thickness of 4.0 nm was
formed on a silicon semiconductor substrate, a WSi.sub.x film with
a thickness of 70 nm was formed on this, N.sub.2.sup.+ ions were
implanted with a predetermined dosage into the WSi.sub.x film, then
heat treatment was carried out at 850.degree. C. for 30 minutes,
then the gate electrodes were formed by the etching process and the
withstand voltage characteristics of the gate oxide film were
checked.
[0214] The results are shown in FIG. 12. In FIG. 12, the ordinate
represents a cumulative failure (x 100%), and the abscissa
represents the gate withstand voltage, that is, the "time zero
dielectric breakdown voltage (TZDB (V))". Further, the curve a
indicates a case where the nitrogen ions were not implanted, b
indicates a case where nitrogen ions were implanted with a dosage
of 5.times.10.sup.15/cm.sup.2, c indicates a case where nitrogen
ions were implanted with a dosage of 7.5.times.10.sup.15/cm.sup.2,
and d indicates a case where nitrogen ions were implanted with a
dosage of 1.times.10.sup.16/cm.sup.2.
[0215] It is seen from FIG. 12 that excellent gate withstand
voltage characteristics are obtained in all cases where nitrogen
ions are implanted in comparison with the case where nitrogen ions
are not implanted.
[0216] 12th Embodiment
[0217] In the 12th embodiment, it is checked how the withstand
voltage characteristics of the gate oxide film vary when doping the
nitrogen uniformly as the impurity in the WSi.sub.x film and
changing the content of the boron when forming a gate oxide film on
a silicon semiconductor substrate and further forming an WSi.sub.x
film on the gate oxide film.
[0218] Namely, a gate oxide film of a thickness of 4.0 nm was
formed on a silicon semiconductor substrate, an WSi.sub.x film of a
thickness of 70 nm was formed on this, N.sub.2.sup.+ ions of a
dosage of 5.times.10.sup.15/cm.sup.2 were implanted into the entire
surface of the WSi.sub.x film, B.sup.+ ions were implanted in
various dosages, heat treatment was carried out at 850.degree. C.
for 30 minutes, then gate electrodes was formed by etching process
and the withstand voltage characteristics of the gate oxide film
were checked.
[0219] The results are shown in FIG. 13. In FIG. 13, the ordinate
represents the cumulative failure (x 100%), and the abscissa
represents the time zero dielectric breakdown (TZDB (V)). Further,
the curve a indicates a case where the B.sup.+ ions were not
implanted, b indicates a case where B.sup.+ ions were implanted
with a dosage of 1.times.10.sup.15/cm.sup.2, c indicates a case
where B.sup.+ ions were implanted with a dosage of
3.times.10.sup.15/cm.sup.2, and d and e indicate cases where
B.sup.+ ions were implanted with dosages of
5.times.10.sup.15/cm.sup.2. d and e are results of experiments
carried out by using two wafers under the same conditions.
[0220] As shown in FIG. 13, it was seen that almost the same
results were obtained and there was reproducibility.
[0221] Further, it was seen from FIG. 13 that excellent time zero
dielectric breakdown characteristics were obtained in all cases
where the nitrogen ions and the B.sup.+ ions were implanted in
comparison with the case where only the nitrogen ions were
implanted.
[0222] Summarizing the effects of the invention, as explained
above, the semiconductor devices of the first and second aspects of
the invention are characterized in that a part of the conductive
layer (preferably gate electrode) in contact with at least the
insulating film (preferably gate insulating film) is made of a
conductive material (preferably refractory metal silicide or
refractory metal) having a work function near the substantive
center of the energy band gap of the substrate material and in that
the conductive material contains an impurity.
[0223] Accordingly, the semiconductor devices of the first and
second aspects of the invention are semiconductor devices having
conductive layers (gate electrodes) in which a so-called short
channel effect is suppressed and the operating speed of the device
is maintained. In addition, they are semiconductor devices in which
the dielectric breakdown of the insulating film of the lower layer
accompanied the grain growth of the refractory metal silicide, the
refractory metal or other conductive material or in a MOSTr the
dielectric breakdown of the insulating film (gate insulating film)
and the reduction of the gate capacity, which have been problems of
the related art, are suppressed.
[0224] Further, when the conductive material of the conductive
layer of the semiconductor device of the present invention contains
two or more types of impurities, it is possible to more effectively
suppress the grain growth of the conductive material in comparison
with the case where one type of impurity is doped. Accordingly,
even in a case where a thinner insulating film (for example, gate
insulating film having a thickness of about 4 nm) is formed, the
result is a semiconductor device having a conductive layer (gate
electrodes) with excellent reliability without causing the
deterioration of the insulation withstand voltage.
[0225] Further, according to the methods of production of
semiconductor devices of the third and fourth aspects of the
invention, a semiconductor device can be produced having a
conductive layer (gate electrodes) in which the short channel
effect is suppressed and the operating speed of the device is
maintained without adding any change to the conditions of the heat
treatment step and the impurity doping step after this and without
causing a reduction of the insulation withstand voltage and the
reduction of the gate capacity.
[0226] Further, by doping the impurity nonuniformly in the depth
direction of the conductive layer, preferably so that the
concentration of the center portion with respect to the depth
direction of the conductive layer becomes relatively high and the
concentration of the upper and lower regions thereof becomes
relatively low, a MOSTr having a similar insulating film boundary
surface characteristic to that of the case where the impurity is
not doped can be formed. Accordingly, according to the methods of
production of the semiconductor devices of the present invention,
the degree of freedom of the process design of the semiconductor
device will not be lowered.
[0227] Further, where there is a step for doping the impurity into
the conductive layer by the ion implantation process, the impurity
can be implanted with the correctly controlled acceleration energy
and dosage.
[0228] Accordingly, according to the present invention, the degree
of integration of the LSI can be improved, the drive capability of
the MOSTr can be improved according to the design rule, and high
speed operation of the device becomes possible.
* * * * *