U.S. patent application number 09/504058 was filed with the patent office on 2002-12-26 for method of polishing a substrate.
Invention is credited to Mueller, Brian L., Schroeder, David J..
Application Number | 20020197935 09/504058 |
Document ID | / |
Family ID | 24004682 |
Filed Date | 2002-12-26 |
United States Patent
Application |
20020197935 |
Kind Code |
A1 |
Mueller, Brian L. ; et
al. |
December 26, 2002 |
Method of polishing a substrate
Abstract
A method of polishing a substrate by providing a polishing
slurry comprising water and silica particles, wherein the average
size (by number) of the silica particles is less than 30 nm,
providing a polymeric polishing pad substantially free of bound
abrasive particles and having a polishing surface comprising a
multiplicity of cavities, and polishing the surface of the
substrate by contacting the polishing slurry and the polishing pad
with the substrate and moving the polishing pad relative to the
substrate.
Inventors: |
Mueller, Brian L.; (Aurora,
IL) ; Schroeder, David J.; (Aurora, IL) |
Correspondence
Address: |
PHYLLIS T. TURNER-BRIM, ESQ., LAW DEPARTMENT
CABOT MICROELECTRONICS CORPORATION
870 NORTH COMMONS DRIVE
AURORA
IL
60504
US
|
Family ID: |
24004682 |
Appl. No.: |
09/504058 |
Filed: |
February 14, 2000 |
Current U.S.
Class: |
451/36 ;
451/41 |
Current CPC
Class: |
B24B 37/044 20130101;
C09G 1/02 20130101 |
Class at
Publication: |
451/36 ;
451/41 |
International
Class: |
B24B 001/00 |
Claims
What is claimed is:
1. A method of polishing a substrate, which method comprises (a)
providing a polishing slurry comprising a liquid carrier and silica
particles, wherein the average size of the silica particles is less
than 30 nm, (b) providing a polymeric polishing pad substantially
free of bound abrasive particles and having a polishing surface
comprising a multiplicity of cavities, and (c) polishing the
surface of the substrate by contacting the polishing slurry and the
polishing pad with the substrate and moving the polishing pad
relative to the substrate.
2. The method of claim 1, wherein the polishing surface is
polyurethane.
3. The method of claim 1, wherein about 90% or more of the abrasive
particles (by number) have a particle size less than about 30
nm.
4. The method of claim 1, wherein the silica particles have an
average particle size of about 20 nm or less.
5. The method of claim 1, wherein about 90% or more of the abrasive
particles (by number) have a particle size of about 20 mn or
less.
6. The method of claim 1, wherein the silica particles are
condensation-polymerized silica particles.
7. The method of claim 1, wherein the polishing slurry consists
essentially of silica particles and water.
8. The method of claim 1, wherein the polishing slurry is
basic.
9. The method of claim 8, wherein the polishing slurry has a pH of
about 8.5-12.
10. The method of claim 1, wherein the substrate is a semiconductor
device.
11. The method of claim 1, wherein the substrate is a dielectric
layer of a semiconductor device.
12. The method of claim 10, wherein the polishing pad is not
conditioned during the polishing of the semiconductor device.
13. The method of claim 12, wherein the polishing pad is
conditioned before and/or after polishing the semiconductor
device.
14. The method of claim 10, wherein the semiconductor device
comprises device geometries below about 0.25 .mu.m.
15. The method of claim 1, wherein the silica particles communicate
with the polishing surface to form an in situ fixed abrasive.
16. The method of claim 1, wherein the silica particles and the pad
communicate in a manner consistent with a self-regenerating fixed
abrasive article.
Description
TECHNICAL FIELD OF THE INVENTION
[0001] This invention pertains to a method of polishing a
substrate, in particular a method of polishing a semiconductor
device.
BACKGROUND OF THE INVENTION
[0002] In the production of semiconductor devices, it is often
necessary to achieve a high degree of planarity in the surface of
the device materials, for example, to allow the formation of
inter-level dielectrics, while minimizing the amount of field
dielectric loss and number of surface defects caused by the
planarization process. As devices become smaller, the planarity,
field loss, and defectivity of the device surfaces become
increasingly important. One accepted method of planarizing
semiconductor devices is through polishing the surface of the
semiconductor with a polishing composition and/or a polishing pad.
Various pads, polishing compositions, and methods of polishing
semiconductor devices are known. For example, U.S. Pat. No.
5,575,837 discloses a polishing composition containing silica
particles 30 nm and larger in size and a persulfate or hydrazine
compound. U.S. Pat. No. 5,489,233 discloses the use of polishing
pads having a surface texture or pattern. U.S. Pat. No. 5,958,794
discloses a fixed abrasive polishing pad. However, there continues
to be a need for more efficient and more effective planarization
and polishing methods. The present invention provides such a
method. These and other advantages of the present invention, as
well as additional inventive features, will be apparent from the
description of the invention provided herein.
BRIEF SUMMARY OF THE INVENTION
[0003] This invention provides a method of polishing a substrate,
which method comprises providing a polishing slurry comprising
water and silica particles, wherein the average size (by number) of
the silica particles is less than 30 nm, providing a polymeric
polishing pad substantially free of bound abrasive particles and
having a polishing surface comprising a multiplicity of cavities,
and polishing the surface of the substrate by contacting the
polishing slurry and the polishing pad with the substrate and
moving the polishing pad relative to the substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIG. 1A-1D are schematic views of a semiconductor device
before the formation of a trench or opening (FIG. 1A), after the
formation of a trench or opening (FIG. 1B), after the deposition of
a dielectric layer (FIG. 1C), and after planarization of the
dielectric layer (FIG. 1D) in the stages of a typical shallow
trench isolation procedure.
[0005] FIGS. 2A and 2B depict a typical semiconductor device
comprising an interlayer dielectric before planarization (FIG. 2A)
and after planarization (FIG. 2B).
[0006] FIG. 3 is a graph of step height remaining (.ANG.) versus
polish time (sec.) with respect to the use of the method of the
present invention (involving 20 nm colloidal silica polishing
slurry) in conjunction with a grooved pad and a perforated pad to
planarize the dielectric layer of a semiconductor device (with 52%
pattern density).
DETAILED DESCRIPTION OF THE INVENTION
[0007] The present invention provides a method of polishing a
substrate, which method comprises abrading the surface of a
substrate with a polishing slurry and polishing pad. For the
purposes of the present invention, the terms "polish" and
"planarize" are used interchangeably to refer to abrasion of the
surface of a substrate.
[0008] The Substrate
[0009] The present method of polishing a substrate can be used to
polish or planarize any substrate, for example, a substrate
comprising a metal, metal oxide, metal composite, semiconductor
base material, or mixture thereof. The substrate can comprise,
consist essentially of, or consist of any suitable metal. Suitable
metals include, for example, copper, aluminum, tantalum, titanium,
tungsten, gold, platinum, iridium, ruthenium, and combinations
(e.g., alloys or mixtures) thereof. Preferably, the metal of the
substrate is tungsten. The substrate also can comprise, consist
essentially of, or consist of any suitable metal oxide. Suitable
metal oxides include, for example, alumina, silica, titania, ceria,
zirconia, germania, magnesia, and combinations thereof. Preferably,
the metal oxide of the substrate is silica. In addition, the
substrate can comprise, consist essentially of, or consist of any
suitable metal composite. Suitable metal composites include, for
example, metal nitrides (e.g., tantalum nitride, titanium nitride,
and tungsten nitride), metal carbides (e.g., silicon carbide and
tungsten carbide), nickel-phosphorus, alumino-borosilicate,
borosilicate glass, phosphosilicate glass (PSG),
borophosphosilicate glass (BPSG), silicon/germanium alloys, and
silicon/germanium/carbon alloys. The substrate also can comprise,
consist essentially of, or consist of any suitable semiconductor
base material. Suitable semiconductor base materials include
single-crystal silicon, poly-crystalline silicon, amorphous
silicon, silicon-on-insulator, and gallium arsenide.
[0010] The present method is especially useful in polishing or
planarizing a semiconductor device, for example, semiconductor
devices having device feature geometries of about 0.25 .mu.m or
smaller (e.g., 0.18 .mu.m or smaller). The term "device feature" as
used herein refers to a single-function component, such as a
transistor, resistor, capacitor, integrated circuit, or the like.
As device features of the semiconductor substrate become
increasingly small, the degree of planarization becomes more
critical. A surface of a semiconductor device is considered to be
sufficiently planar when the dimensions of the smallest device
features (e.g., device features of 0.25 .mu.m or smaller, such as
device features of 0.18 .mu.m or smaller) can be resolved upon the
surface via photolithography. The planarity of the substrate
surface also can be expressed as a measure of the distance between
the topographically highest and lowest points on the surface. In
the context of semiconductor substrates, the distance between the
high and low points on the surface desirably is less than about
2000 .ANG., preferably less than about 1500 .ANG., more preferably
less than about 500 .ANG., and most preferably less than about 100
.ANG..
[0011] The present method can be used in the manufacture of a
semiconductor device, for example, in the formation of isolation
structures by shallow trench isolation methods (STI) during the
fabrication of a semiconductor device. As illustrated in FIG.
1A-1D, STI involves forming a trench or opening (i.e., via) (12) in
the surface of the semiconductor base (10), which base is formed
from any appropriate semiconductor material, such as single crystal
silicon, gallium arsenide, silicon-on-insulator, or other suitable
semiconductor materials known in the art. The base material (10) is
preferably coated with a hard mask (11) of suitable material such
as silicon nitride, tantalum nitride, or titanium nitride, prior to
forming the trench or opening (12). The trench or opening (12) can
be formed using any suitable means, for example, by a
photolithographic etching means. The surface of the semiconductor
base material (10), including the trenches or openings (12), is
then coated with a suitable dielectric material (13) such as
silicon oxide, poly-crystalline silicon, PSG, or BPSG. The
dielectric layer (13) will conform to the non-planar surface of the
semiconductor base (10), and the trenches and/or openings (12)
formed thereupon, to create a non-planar dielectric surface (13)
comprising relatively low topographical regions (12') within the
trenches and openings (12), and relatively high topographical
regions (14) in the areas in-between the trenches and openings
(12). The relatively high topographical regions (14) are known as
the "over-active" regions. The relatively low topographical regions
(12') are known as the "over-trench" regions. The surface of the
non-planer planar dielectric layer (13) is then planarized, wherein
the over-active regions (14) are sufficiently reduced so as to
expose the mask layer (11) without exposing the underlying
semiconductor base layer (10), thereby leaving the over-trench
dielectric layer within the trench or opening (13'). This is
accomplished, for example, by polishing the non-planar dielectric
layer (13) according to the polishing method of the present
invention.
[0012] The present method also can be used to polish a
semiconductor device comprising an inter-layer dielectric (ILD).
FIGS. 2A and 2B illustrate a typical semiconductor device
comprising an interlayer dielectric. For the sake of clarity,
well-known features such as doped regions, active devices,
epitaxial layers, carrier oxides, as well as other such features
have been omitted. As illustrated in FIGS. 2A and 2B, a typical
semiconductor device comprising an ILD has a semiconductor base
(20) made from any appropriate material, for example, single
crystal silicon, gallium arsenide, or other suitable semiconductor
materials known in the art. As those of skill in the art will
appreciate, the semiconductor base layer (20) can also represent
previous layers of interconnects or gate level dielectric layers.
Over the semiconductor base (20), a dielectric layer (21) is
deposited, which layer typically contains silicon dioxide, PSG,
BPSG, silicon nitride, tantalum nitride, titanium nitride, or other
suitable dielectric materials known in the art. Metal interconnects
(22) are placed over, or embedded within, the dielectric layer
(21), for example, by using a photolithography process, thereby
creating a metallized layer. Metal interconnects (22) can be made
from any suitable metal, for example, aluminum, copper, tungsten,
polysilicon, gold, platinum, iridium, ruthenium, alloys, and the
like. Generally, a second layer of dielectric material (23) is
applied over the metal interconnects and the regions in-between
between the metal interconnects (22), resulting in a non-planar
dielectric surface (23) that must be polished or planarized before
an additional layer of circuitry (e.g., metal interconnects and/or
additional dielectric layers) can be applied. The dielectric layer
(23) overlying the metal interconnects (22) forms topographically
high regions in the surface of the dielectric known as the "stack"
dielectric regions (24). The dielectric layer overlying regions
in-between the metal interconnects form topographically low regions
referred to as the field dielectric regions (25, 26). The
difference in height between the relatively low regions (field)
(25, 26) and the relatively high regions (stack) (24) of the
dielectric is known as the step height. As the dielectric surface
is polished (i.e., according to the present inventive method), the
step height is reduced. The step height can be measured directly by
methods known in the art, such as by using a profilometer. The step
height also can be determined by measuring the stack and field
thicknesses and calculating the step height using the following
formula:
step height=initial step height-(.DELTA.stack
thickness+.DELTA.field thickness).
[0013] The present method can be used to polish or planarize any
part of a semiconductor device, e.g., the metallized (e.g., metal
interconnects) (22), dielectric (21, 23), or base layer (20) of a
semiconductor device, as described above. The present method can be
used, for example, to polish the surface dielectric layer (23) of a
semiconductor device with or without breaking through the stack
dielectric material to polish the underlying metal interconnects
(22), underlying dielectric material (21), or base materials (20).
The present method is preferably used to polish the dielectric
layer of a semiconductor substrate without breaking through to
polishing the underlying metal interconnects. However, if used to
polish a metal substrate (e.g., the metal interconnects underlying
the dielectric layer), it is preferable that the substrate
comprises metals that do not react with the silica abrasive, e.g.,
a substrate that does not comprise aluminum.
[0014] It is desirable to polish the stack dielectric regions (24),
or over-active dielectric regions (14), of a semiconductor
substrate with as little loss as possible of the field dielectric
(25, 26), or over-trench regions (12'), thereby yielding a high
planarization efficiency. Planarization efficiency is the relative
difference between the amount of stack dielectric or over-active
dielectric removed and the amount of field dielectric or
over-trench dielectric removed during the polishing or planarizing
process. Planarization efficiency will depend, in part, on the
pattern density of the substrate. In the context of ILD
applications, the pattern density is the fractional surface area of
the substrate surface comprising circuitry (e.g., metal
interconnects (22) or stack dielectric regions (24) overlying the
metal interconnects (22)). In the context of STI applications, the
pattern density is the fractional surface area of the substrate
surface comprising trenches or openings (12). Furthermore, the
pattern density can vary within a given substrate ("die"). Thus,
different areas of the substrate can be polished at different rates
(e.g., areas of the ILD having lower pattern densities will be
polished at a higher rate than areas having higher pattern
densities) giving rise to "within die non-uniformity"(WIDNU) as
illustrated by FIG. 2B. Methods of polishing or planarizing a
substrate with high planarization efficiency (high selectivity to
stack dielectric regions (in the context of ILD) or over-active
dielectric regions (in the context of STI)) will tend to reduce
WIDNU.
[0015] The present method can be used to polish a semiconductor
substrate with a high planarization efficiency. For example, the
present method can be used to polish a semiconductor substrate
comprising at least 50% pattern density with an efficiency of at
least 75%, preferably at least 80%, more preferably at least 90%.
This efficiency is, in part, attributed to a high selectivity of
the present method to polishing the relatively high topographical
regions of the dielectric (e.g., the stack dielectric regions
overlaying the metal interconnects in the context of ILD
applications, or the over-active dielectric regions in-between the
trenches or openings in the context of STI applications) at a
faster rate than the relatively low topographical regions of the
dielectric (e.g., the regions of dielectric between the metal
interconnects in the context of ILD applications, or the regions of
dielectric within the trenches in the context of STI applications).
The selectivity can be expressed as a ratio of the planarization
rate of the stack or over-active dielectric regions to the
planarization rate of the field or over-trench dielectric regions.
The present inventive method can be used to polish or planarize a
substrate with a selectivity ratio of at least about 2:1,
preferably at least about 5:1. In preferred modes of practicing the
present invention, the selectivity ratio will decrease as
planarization continues, thereby exhibiting a "self-stopping"
behavior.
[0016] The Polishing Pad
[0017] The polishing pad can comprise materials of varying
compositions and hardnesses, provided the polishing pad comprises a
polymeric polishing surface capable of communicating with the
silica abrasive particles of the polishing slurry. The term
"communicating" as it is used in conjunction with the present
invention refers to the interaction of the silica abrasive
particles with the polymeric polishing surface. While not wishing
to be bound by any particular theory, it is thought that, when
using a polishing pad and silica abrasives as described herein, the
silica abrasive particles associate with, or temporarily adhere to,
the surface of the polishing pad. This may be caused, for example,
by chemical, physical/mechanical, or hydrogen bonding forces, or a
combination of such mechanisms, or even other mechanisms. The
silica particles and/or polymeric polishing pad surface may, for
instance, become slightly, partially, or wholly softened or
dissolved during polishing according to the method described
herein. As a result, the silica particles are believed to adhere to
the polishing surface of the polishing pad forming an in situ fixed
abrasive article, more specifically a self-regenerating in situ
fixed abrasive article, which allows planarization of a substrate
with the efficiency of a fixed abrasive article while causing
significantly fewer defects to form in the substrate surface.
[0018] The polishing pad and/or polishing surface can be woven or
non-woven and can comprise any suitable polymer of varying density,
hardness, thickness, compressibility, ability to rebound upon
compression, and compression modulus. The polishing pad used in
conjunction with the present inventive method preferably has a
density of about 0.6-0.95 g/cm.sup.3, a Shore A hardness rating of
less than about 100 (e.g., about 40-90), a thickness of at least
about 0.75 mm (e.g., about 0.75-3 mm), compressibility of about
0-10% (by volume), the ability to rebound to at least about 25% (by
volume) (e.g., 25-100%) after compression at about 35 kpa, and a
compression modulus of at least about 1000 kPa. Examples of
suitable polymers include polyurethanes, polymelamines,
polyethylenes, polyesters, polysulfones, polyvinyl acetates,
polyacrylic acids, polyacrylamides, polyviylchlorides,
polyvinylfluorides, polycarbonates, polyamides, polyethers,
polystyrenes, polypropylenes, nylons, fluorinated hydrocarbons, and
the like, and mixtures, copolymers, and grafts thereof Preferably,
the polishing pad comprises a polyurethane polishing surface. The
polishing pad and/or surface can be formed from such materials
using suitable techniques recognized in the art, for example, using
thermal sintering techniques. Furthermore, the polishing pad formed
from such materials may be substantially porous (i.e, having open
or closed pores) or substantially non-porous. Porous pads
preferably have a pore diameter of about 1-1000 .mu.m and a pore
volume of about 15-70%. The polishing pad and/or surface also can
be perforated or unperforated to any degree. Preferably, the
polishing pad comprises a perforated polishing surface.
[0019] The polishing surface of the polishing pad preferably
comprises a multiplicity of cavities which can include and/or be in
addition to any pores or perforations as previously described.
Without wishing to be bound by any particular theory, the
multiplicity of cavities are thought to provide channels through
which the polishing slurry can flow. Cavities, for the purpose of
the present invention, includes recesses or indentations in the
surface of the pad, protrusions arranged in such fashion as to form
recesses between the protruding portions of the surface of the pad,
or any combination of recesses and protrusions. The recesses or
protrusions can be any suitable size or shape. The multiplicity of
cavities form a macro-texture on the polishing surface of the
polishing pad, which can further include a micro-texture imposed
upon the recessed and/or protruding portions of the macro-texture.
The multiplicity of cavities forming the macro-texture and/or
micro-texture can have any dimension and arrangement. The cavities
can, for example, be arranged randomly or as a pattern. Preferably,
the cavities are arranged in a non-circular or non-spiral
arrangement. For example, it is preferred that the cavities are
arranged so as not to form trenches or grooves over a substantial
portion of the polishing surface of the pad. Thus, preferably at
least about 50% (e.g., about 50%-75%) o even at least about 80%
(e.g., about 90%-100%) of the pad surface should be essentially
free of concentric or spiral grooves or trenches. The pad can, for
example, be grooved to the extent required to facilitate removal of
the semiconductor substrate from the polishing pad and/or platen,
as will be appreciated by those of ordinary skill in the art.
[0020] The polishing pad optionally comprises a backing. The
backing portion can comprise any suitable backing material known in
the art. The backing can, for example, be flexible or rigid in
varying degrees, as will be appreciated by those of ordinary skill
in the art. Typical backing materials, for example, include
polymeric films, metal foils, cloth, paper, vulcanized fiber, and
combinations thereof.
[0021] The polishing pad used in conjunction with the present
method should be substantially free of bound abrasive particles.
The term "bound abrasive particles," as used in the context of this
invention, refers to abrasive particles that are affixed to the
polishing surface of the polishing pad by way of an adhesive,
binder, ceramer, resin, or the like. The term "bound abrasive
particles" also refers to abrasives that have been impregnated
within a polishing pad so as to form an integral part of the
polishing pad, such as, for example, a fibrous batt impregnated
with an abrasive-containing polyurethane dispersion. Silica
particles that become associated with the polishing surface of a
polishing pad during polishing according to the methods described
herein, i.e., by communicating with the polishing surface of the
polishing pad as described previously, are not considered to be
"bound abrasive particles" in the context of the present
invention.
[0022] The Polishing Slurry
[0023] The polishing slurry for use in conjunction with the present
method comprises a liquid carrier and silica particles as an
abrasive. Suitable silica particles are commercially available and
can be prepared by known methods, for example, by wet chemical
methods such as condensation-polymerization or colloidal
precipitation. In preferred preparations, the silica particles have
an average particle size of less than 30 nm, preferably having an
average particle size of about 25 nm or less, more preferably about
20 nm or less. Preferred preparations contain silica particles
about 90% or more of which (by number) have a particle size less
than 30 nm (e.g., a particle size of about 20 nm or less).
Preferably, the abrasive particles are such that at least about
95%, 98%, or even substantially all (or actually all) of the
abrasive particles (by number) have a particle size less than 30 nm
(e.g., a particle size of about 20 nm or less). These particle size
preferences for the abrasive particles (i.e., whereby at least
about 90%, 95%, 98%, substantially all, and all of the abrasive
particles (by number) are less than or equal to a specific size of
abrasive particle) also can pertain to other particle sizes, such
as 25 nm, 20 nm, 15 nm, and 10 nm.
[0024] Similarly, the abrasive particles of the composition of the
present invention can be such that at least about 90%, 95%, 98%, or
even substantially all (or actually all) of the abrasive particles
(by number) have a particle size no less than l nm. These particle
size preferences for the abrasive particles (i.e., whereby at least
about 90%, 95%, 98%, substantially all, and all of the abrasive
particles (by number) are no less than a specific size of abrasive
particle) also can pertain to other particle sizes, such as 7 nm,
10 nm, 15 nm, and 25 nm.
[0025] The percentage values used herein to describe the nature of
the abrasive particles in terms of particle size are percentages
"by number," rather than being weight percentages, unless otherwise
noted. The particle size of the abrasive particles refers to the
particle diameter. The particle size can be measured by any
suitable technique. The particle size values set forth herein are
based on a visual inspection, specifically by way of transmission
electron micrography (TEM), of a statistically significant sample
of the abrasive particles, preferably at least 200 particles.
[0026] The particle size distribution of abrasive particles can be
characterized by geometric standard deviation by number, referred
to as sigma-g (.sigma.g). The .sigma.g values can be obtained by
dividing (a) the diameter at which 84% of the abrasive particles
(by number) are less than by (b) the diameter at which 16% of the
abrasive particles (by number) are less than (i.e.,
.sigma..sub.g-d.sub.84/d.sub.16). Monodispersed abrasive particles
have a .sigma..sub.g value of about 1. As the abrasive particles
become polydispersed (i.e., include particles of increasingly
different size), the .sigma..sub.g value of the abrasives particles
increases above 1. The abrasive particles typically have a
.sigma..sub.g value of about 2.5 or less (e.g., about 2.3 or less).
The abrasive particles desirably have a .sigma..sub.g value of at
least about 1.1 (e.g., about 1.1-2.3 or even about 1.1-1.3),
preferably a .sigma..sub.g value of at least about 1.3 (e.g., about
1.5-2.3 or even about 1.8-2.3).
[0027] The polishing slurry typically will contain from about
0.5-50 wt. % of the silica abrasive particles. Preferred
formulations comprise about 10-40 wt. % silica, more preferably
about 20-35 wt. % silica (e.g., about 30-35 wt. % silica).
[0028] The liquid carrier of the polishing slurry can comprise any
suitable liquid; however, preferred preparations of the polishing
slurry comprise an aqueous liquid carrier. The liquid carrier also
can contain various additives known in the art. As those of
ordinary skill in the art will appreciate, the additives used in
the polishing slurry will vary depending on the application in
which the polishing slurry will be used. Such additives include
surfactants (e.g., cationic surfactants, anionic surfactants,
nonionic surfactants, amphoteric surfactants, fluorinated
surfactants, and mixtures thereof), polymeric stabilizers or other
surface active dispersing agents (e.g., phosphoric acid, organic
acids, tin oxides, and phosphonate compounds), pH buffers (e.g.,
potassium phosphate), and polishing accelerators such as catalysts,
oxidizers, and chelating or complexing agents (e.g., metal,
particularly ferric, nitrates, sulfates, halides (including
fluorides, chlorides, bromides, and iodides), compounds with
carboxylate, hydroxyl, sulfonic, and/or phosphonic groups, di-,
tri-, multi-, and poly-carboxylic acids and salts (such as tartaric
acids and tartrates, malic acid and malates, malonic acid and
malonates, gluconic acid and gluconates, citric acid and citrates,
phthalic acid and phthalates, pyrocatecol, pyrogallol, gallic acid
and gallates, tannic acid and tannates), amine-containing compounds
(such as primary, secondary, tertiary, and quaternary amines and
amino acids), peroxides, periodic acid and salts, perbromic acid
and salts, perchloric acid and salts, perboric acid and salts,
iodic acid and salts, permaganates, potassium ferricyanide,
chlorates, percarbonates, persulfates, bromates, chromates, cerium
compounds, and mixtures thereof). However, preferred preparations
of the polishing slurry consist essentially of silica particles and
water.
[0029] The pH of the polishing slurry can be any suitable pH. The
pH may affect performance and, therefore, generally is selected
based upon the nature of the substrate being polished, including
the chemical composition and topography of the substrate. In some
cases, e.g., where the substrate contains metal oxide or (e.g.,
silicon dioxide) or metal nitride (e.g., titanium nitride), the
polishing slurry preferably has a pH greater than 7. In some
instances, the pH of the polishing slurry is about 7-13, preferably
about 8.5-12, especially about 9 to 11. The pH of the polishing
slurry can be adjusted using any suitable pH adjusting agent.
Examples of suitable agents include hydroxide compounds such as
potassium hydroxide, sodium hydroxide, ammonium hydroxide, lithium
hydroxide, magnesium hydroxide, calcium hydroxide, barium
hydroxide, and basic compounds such as amines and the like. The pH
adjusting agent can be a mixture of compounds, such as a mixture of
potassium hydroxide and lithium hydroxide. The pH adjusting agents
can be in the form of a solution, e.g., an aqueous solution. An
example of a metal hydroxide-containing solution is a solution of
potassium hydroxide in deionized or distilled water in which the
potassium hydroxide concentration is about 0.1-0.5 wt. % (e.g.,
about 0.2-0.3 wt. %).
[0030] Process Conditions
[0031] The present method can further comprise a conditioning step
wherein the polishing surface of the polishing pad is cleaned. Such
conditioning can be used to control the rate of silica buildup on
the pad and, thereby, control the rate of planarization and
planarization efficiency achieved using the present inventive
method. The polishing surface can be conditioned according to
techniques commonly known to those of skill in the art. For
example, the polishing surface can be contacted with a conditioning
brush, tool, or pad. Preferably, a conditioning tool or pad, for
example, a diamond grit conditioning tool or pad, having a
coarseness (grit) number of 100 or finer, is used to condition the
polishing surface.
[0032] The polishing surface can be conditioned during the
polishing or planarization of the substrate (in situ conditioning),
or the polishing surface can be conditioned before and/or after
polishing the substrate (ex situ conditioning), for example, by
conditioning between the polishing of two semiconductor devices.
Preferably, the polishing surface is conditioned before and/or
after the polishing of the semiconductor device, and is not
conditioned during the polishing step.
[0033] In general, there can be numerous planarization steps for a
single substrate. For example, a substrate can be wholly or
partially planarized (e.g., to remove insulating layers of a
semiconductor device without polishing underlying metal
interconnects) using the polishing methods disclosed herein, and
finished or buffed by other methods. Any suitable polishing pad and
polishing slurry can be used to buff the polished substrate. Such
polishing pads and polishing slurries are commonly known in the
art. When using the present inventive method in conjunction with a
finishing or buffing step, a relatively high removal rate of the
insulating layers is preferred. If the insulating layer is a metal
oxide such as silicon dioxide, the removal rate should be at least
100 Angstroms per minute, preferably at least 500 Angstroms per
minute, more preferably at least 1000 Angstroms per minute, and
most preferably at least 1500 Angstroms per minute. In some
instances, it may be desirable for the removal rate to be as high
as at least 2000 Angstroms per minute, and even at least 3000 or
4000 Angstroms per minute. If the material being removed during
planarization is harder and/or more chemically durable than silica,
then the removal rates may be lower. Conversely, if the material
being removed during planarization is softer than silica, then the
removal rates may be higher. However, although it is generally
desirable to have a high removal rate, the removal rate must be
selected such that it does not compromise the desired topography of
the wafer surface.
[0034] The interface pressure between the polishing pad and
semiconductor wafer (i.e., the contact pressure) is any suitable
pressure that eliminates or reduces dishing and/or non-uniformity
in the surface of the substrate. The interface pressure is
preferably less than about 150 kPa, more preferably less than about
100 kPa, even more preferably less than about 60 kPa, and most
preferably less than 40 kPa and even as low as 20 kPa or less.
Also, two or more processing conditions within a planarization
process may be used. For example, a first processing segment may
comprise a higher interface pressure than a second processing
segment. The interface pressure may be a combination of downforce
between the polishing pad (platen) and the substrate, and
backpressure exerted behind the substrate. Typically, between about
10-70 kPa of each of downforce pressure and backpressure will be
used to eliminate or reduce dishing and/or non-uniformity in the
substrate surface.
[0035] Any suitable platen speed can be used to polish according to
the present method. The platen can rotate about 5-10,000 rpm,
typically about 10-1000 rpm, preferably about 20-300 rpm, more
preferably about 30-150 rpm. The substrate holder (carrier) also
may rotate in the same or opposite direction as the platen and in
any circular or non-circular manner. The carrier generally rotates
about 5-300 rpm, preferably about 10-100 rpm, more preferably about
20-50 rpm.
[0036] The following examples further illustrate the present
invention but, of course, should not be construed as in any way
limiting its scope.
EXAMPLE 1
[0037] This example demonstrates a method of polishing the ILD of a
semiconductor device according to the present invention. Two
semiconductor devices (Device Nos. 1A and 1B) comprising ILD test
patterns (MIT design mask) having systematically varied pattern
densities ranging from 8-100%, a 250 micron pitch, and an initial
step height of 9000 .ANG. were polished on an IPEC 472 polishing
machine using a down force of 51.75 kPa, a back pressure of 20.7
kPa, a platen speed of 37 rpm, a carrier speed of 24 rpm, and a
slurry flow rate of 220 ml/min. A perforated polyurethane polishing
pad was used comprising a polishing surface having a multiplicity
of cavities arranged in a non-circular pattern and a single groove
to facilitate removal of the semiconductor substrate from the
platen after polishing. Only ex situ conditioning was
performed.
[0038] The first semiconductor device (Device No.1 A) was polished
using a commercially available fumed silica slurry (Cabot
Semi-Sperse.RTM. 12 (12% solids)) having an average particle size
(by number) of 90 nm. Measurements of the step height were taken in
regions of the semiconductor device having 52% pattern density.
After 90 seconds, the semiconductor device was polished to about
2000 Angstroms with about 700 Angstroms of field loss. After 150
seconds, the semiconductor device was polished to a step height of
about 500 Angstroms with about 2400 Angstroms of field loss.
[0039] The second semiconductor device (Device No. 1B) was polished
in the same manner, except that the polishing slurry used was
prepared by diluting an ammonia stabilized precipitated colloidal
silica suspension having an average particle size (by number) of
about 20 nm (Nyacol.RTM. 20NH40 manufactured by Akzo Nobel) with
deionized water to a solids concentration of 30 wt. % and adjusting
the pH to about 10.5 with KOH, in accordance with the present
invention. Measurements of the step height were taken in regions of
the semiconductor device having 52% pattern density. After 90
seconds, the semiconductor device was polished to a step height of
about 3000 Angstroms with about 250 Angstroms of field loss. After
150 seconds, the semiconductor device was polished to a step height
of 500 Angstroms with about 700 Angstroms of field loss.
[0040] This example demonstrates the effectiveness and efficiency
of the present method of polishing a substrate in polishing a
semiconductor device as compared to conventional methods. The
device polished according to the present method (Device No. 1B) was
polished to approximately the same step height in about the same
amount of time as the device polished according to the conventional
method (Device No. 1A), but with greater than a 3-fold reduction in
field-loss.
EXAMPLE 2
[0041] This example demonstrates a method of polishing a
semiconductor device according to the present invention. Two
semiconductor devices (Devices Nos. 2A and 2B) having the same
characteristics as those described in Example 1 were polished in
the same manner as described in Example 1. Device 2A was polished
using a conventional 90 nm average particle size fumed silica
slurry. Device 2B was polished using a polishing slurry prepared by
diluting an ammonia stabilized precipitated colloidal silica
suspension having an average particle size of about 20 nm
(Nyacol.RTM. 20NH40 manufactured by Akzo Nobel) with deionized
water to a solids concentration of 30 wt. % and adjusting the pH to
about 10.5 with KOH, in accordance with the present invention.
[0042] The step height was measured after polishing for 60 seconds,
90 seconds, 120 seconds, and 150 seconds in two regions of each
semiconductor device: the array field (regions of 52% pattern
density) and the open field (regions of 8% pattern density). The
step height was plotted against time to yield a planarization rate
curve for each substrate in each region. By extrapolation,the time
at which the substrate would have been 95% planarized was
determined. The planarization efficiency (sp) at each polishing
interval also was calculated according to the following
equation:
.epsilon.p=1-(.DELTA. field thickness/.DELTA. stack thickness).
[0043] The calculated planarization efficiency was plotted against
time to yield a planarization efficiency curve for each substrate
in each region. The planarization efficiency for each substrate at
each region at the time 95% planarization would have been achieved,
as identified using the planarization rate curve, is set forth in
Table 1.
1 TABLE 1 Open Field Array Field Substrate Efficiency Efficiency
Device No. 2A 49.7% 81.1% Device No. 2B 68.7% 90.1%
[0044] As is apparent from the data recited in Table 1, the method
of the present invention can be used to polish a semiconductor
device with improved planarization efficiency in both array and
open field dielectric regions.
EXAMPLE 3
[0045] This example demonstrates the effect of conditioning on the
present method of polishing. A semiconductor device having the same
characteristics as the devices described in Example 1 was polished
in the same manner as Device No. 1B of Example 1, except that the
polishing surface of the polishing pad was conditioned in situ
using a diamond conditioning pad. Step height measurements were
taken in regions of the semiconductor device having 32% pattern
densities. After about 150 seconds, the semiconductor device was
polished to a step height of about 0 Angstroms with about 1200
Angstroms of field loss. Another similar semiconductor device was
polished according to the same method without conditioning (ex situ
conditioning)to a step height of about 0 Angstroms with about 750
Angstroms of field loss. Using ex situ conditioning in conjunction
with the present invention reduced field loss by about 37%.
EXAMPLE 4
[0046] This example demonstrates the effect that concentric grooves
formed upon a substantial portion of the polishing surface of the
polishing pad have on the polishing rate. Two semiconductor devices
were polished in the same manner as Device No. 1B of Example 1. The
first device (Device No. 4A) was polished using a perforated
polyurethane polishing pad comprising a polishing surface having
concentric grooves formed in the surface of the pad (Mirra.TM.
IC-1000 K-groove available from Applied Materials). The second
device (Device No. 4B) was polished using a polishing pad that was
the same in all respects, except that the polishing surface of the
pad had a multiplicity of cavities arranged in a non-circular
pattern and only a single groove to facilitate removal of the
semiconductor substrate from the platen after polishing (Mirra.TM.
IC-1000 available from Applied Materials). The step height was
measured in regions of the semiconductor devices having 52% pattern
density at 0 seconds, 90 seconds, 120 seconds, 1 50 seconds, and
210 seconds. The results are set forth in Table 2.
2TABLE 2 Step Height (.ANG.)/Time 90 120 150 210 Device 0 seconds
seconds seconds seconds seconds 4A 9000 7200 6800 6500 6100 4B 9000
4500 2700 1900 1700
[0047] The step height was plotted against time for each device to
yield the planarization rate curves depicted in FIG. 3. As
illustrated in FIG. 3, the polishing rate using the perforated pad
(Device 4B) is initially greater than the rate using the grooved
pad. However, as polishing continues, the polishing rate using the
perforated pad slows as the substrate becomes more planar, whereas
the polishing rate using the grooved pad (Device 4A) continues at
approximately the same rate over time. This example demonstrates
the desirable "self-stopping" behavior of a preferred mode of
practicing the present invention.
[0048] All of the references cited herein, including patents,
patent applications, and publications, are hereby incorporated in
their entireties by reference.
[0049] While this invention has been described with an emphasis
upon preferred embodiments, it will be obvious to those of ordinary
skill in the art that variations of the preferred embodiments may
be used and that it is intended that the invention may be practiced
otherwise than as specifically described herein. Accordingly, this
invention includes all modifications encompassed within the spirit
and scope of the invention as defined by the following claims.
* * * * *