U.S. patent application number 10/191435 was filed with the patent office on 2002-12-12 for compound semiconductor device with delta doped layer under etching stopper layer for decreasing resistance between active layer and ohmic electrode and process of fabrication thereof.
This patent application is currently assigned to NEC Corporation. Invention is credited to Negishi, Hitoshi, Oikawa, Hirokazu.
Application Number | 20020187623 10/191435 |
Document ID | / |
Family ID | 18185070 |
Filed Date | 2002-12-12 |
United States Patent
Application |
20020187623 |
Kind Code |
A1 |
Oikawa, Hirokazu ; et
al. |
December 12, 2002 |
Compound semiconductor device with delta doped layer under etching
stopper layer for decreasing resistance between active layer and
ohmic electrode and process of fabrication thereof
Abstract
A high electron mobility transistor has a channel layer overlain
by an electron supply layer held in contact with a gate electrode,
and source/drain electrodes form ohmic contact together with cap
layers, and resistive etching stopper are inserted between the cap
layers and the electron supply layers for preventing the electron
supply layer from over-etching, wherein extremely thin delta-doped
layers are formed between the etching stopper layers and the
electron supply layer so that the resistance between the electron
supply layer and the source/drain electrodes are reduced.
Inventors: |
Oikawa, Hirokazu; (Tokyo,
JP) ; Negishi, Hitoshi; (Tokyo, JP) |
Correspondence
Address: |
MCGINN & GIBB, PLLC
8321 OLD COURTHOUSE ROAD
SUITE 200
VIENNA
VA
22182-3817
US
|
Assignee: |
NEC Corporation
Tokyo
JP
|
Family ID: |
18185070 |
Appl. No.: |
10/191435 |
Filed: |
July 10, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10191435 |
Jul 10, 2002 |
|
|
|
09711505 |
Nov 14, 2000 |
|
|
|
Current U.S.
Class: |
438/590 ;
257/E21.172; 257/E21.407; 257/E29.251 |
Current CPC
Class: |
H01L 21/28575 20130101;
H01L 21/28587 20130101; H01L 29/66462 20130101; H01L 29/7784
20130101 |
Class at
Publication: |
438/590 |
International
Class: |
H01L 021/3205; H01L
021/4763 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 16, 1999 |
JP |
11-326193 |
Claims
What is claimed is:
1. A compound semiconductor device fabricated on a substrate,
comprising: a multiple-layered structure including an active layer;
plural cap layers respectively located over plural portions of said
active layer; plural highly-resistive layers formed between said
multiple-layered structure and said plural cap layers so as to form
a recess located over a part of said multiple-layered structure and
between said plural cap layers; plural delta-doped layers formed
between said plural highly-resistive layers and said
multiple-layered structure for decreasing potential barriers of
said plural highly-resistive layers; a first electrode held in
contact with said part of said multiple-layered structure for
controlling the amount of current flowing through said active
layer; and second electrodes respectively formed on said plural cap
layers for providing current paths from and to said active layer
through said plural cap layers, said plural highly-resistive layers
and said plural delta-doped layers.
2. The compound semiconductor device as set forth in claim 1, in
which said plural delta-doped layers are thin so that a tunneling
phenomenon takes place.
3. The compound semiconductor device as set forth in claim 1, in
which the thickness of said plural delta-doped layers is equal to a
single atom to several atoms.
4. The compound semiconductor device as set forth in claim 1, in
which said plural delta doped layers contain only one kind of
dopant impurity.
5. The compound semiconductor device as set forth in claim 1, in
which said active layer has a conductive channel layer for said
current.
6. The compound semiconductor device as set forth in claim 5, in
which said active layer further has a carrier supply layer for
producing an inversion layer at the boundary between said carrier
supply layer and said conductive channel layer.
7. The compound semiconductor device as set forth in claim 6, in
which said carrier supply layer has a large dopant concentration in
a first portion close to the boundary formed with said channel
layer and a small dopant concentration in a second portion close to
said gate electrode.
8. The compound semiconductor device as set forth in claim 1, in
which said plural highly-resistive layers serve as an etching
stopper for preventing said active layer from an etchant used for
patterning said plural cap layers.
9. The compound semiconductor device as set forth in claim 1, in
which said plural highly-resistive layers are formed of undoped
compound semiconductor.
10. A process for fabricating a compound semiconductor device,
comprising the steps of: a) producing a multiple-layered structure
having an active layer, a delta-doped layer over said active layer,
a highly resistive layer over said delta-doped layer and a highly
conductive layer over said delta-doped layer on a semi-insulating
substrate; b) removing a part of said highly conductive layer so as
to expose a part of said highly resistive layer to a first opening
formed between remaining portions of said highly conductive layer
serving as plural can layers; c) removing said part of said highly
resistive layer and a part of said delta-doped layer thereunder so
as to expose a part of said active layer to a second opening formed
between plural delta doped layers respectively overlain by highly
resistive layers; and d) completing a compound semiconductor device
having a first electrode held in contact with said part of said
active layer and second electrodes respectively held in contact
with said plural cap layers.
11. The process as set forth in claim 10, in which said highly
resistive layer serves as an etching stopper carried out in said
step b) so as to prevent said active layer from a first
etchant.
12. The process as set forth in claim 11, in which step b) includes
the sub-steps of b-1) forming an etching mask on said highly
conductive layer, and b-2) exposing said highly conductive layer to
said first etchant having a large selectivity to a first kind of
compound semiconductor forming said highly conductive layer with
respect to a second kind of compound semiconductor forming said
highly resistive layer.
13. The process as set forth in claim 12, in which said first
etchant contains an oxidizing agent for producing an oxide from
said second kind of compound semiconductor.
14. The process as set forth in claim 13, in which a second etchant
is used for removing said oxide and said part of said delta-doped
layer, and has a large selectivity to said oxide and said
delta-doped layer with respect to a third kind of compound
semiconductor forming said active layer.
15. The process as set forth in claim 13, in which said oxidizing
agent is hydrogen peroxide, and said first kind of compound
semiconductor and said second kind of compound semiconductor
contain a negligible amount of aluminum and a large amount of
aluminum, respectively.
16. The process as set forth in claim 15, in which said first
etchant further contains citric acid, and said first kind of
compound semiconductor and said second kind of compound
semiconductor are gallium arsenide and aluminum gallium arsenide,
respectively.
17. The process as set forth in claim 10, in which said step b)
includes the sub-steps of b-1) depositing an oxide over said highly
conductive layer for forming an oxide layer, b-2) partially
removing said oxide layer for forming an etching mask, and b-3)
etching said part of said highly conductive layer by using said
etching mask.
18. The process as set forth in claim 17, in which said etching
mask serves as a protective layer surrounding said first electrode.
Description
FIELD OF THE INVENTION
[0001] This invention relates to a compound semiconductor and, more
particularly, to a compound semiconductor device having an etching
stopper layer between an active layer and an ohmic electrode.
DESCRIPTION OF THE RELATED ART
[0002] A heterojunction metal-semiconductor field effect transistor
is a typical example of the compound semiconductor device. The high
electron mobility transistor is a kind of heterojunction metal-
semiconductor field effect transistor, and is featured by an
inversion layer at the boundary between an electron supply layer
and a channel layer. The heterojunction metal-semiconductor field
effect transistor finds a wide variety of application such as, for
example, a DBS (Direct Broadcasting Satellite). The compound
semiconductor device is expected to have low- noise characteristics
and achieve a high-gain.
[0003] In order to enhance the mutual conductance, it is known to
increase the dopant impurity in the electron supply layer.
Reduction of source resistance is also appropriate. However, when
the dopant concentration is uniformly increased in the electron
supply layer, a problem is encountered in the heterojunction
metal-semiconductor field effect transistor in low withstand
voltage between the gate electrode and the electron supply
layer.
[0004] A stepped doping concentration structure has been proposed.
When the stepped dopant concentration structure is applied to the
electron supply layer, the electron supply layer has a relatively
heavy dopant concentration close to the channel layer and a
relatively light dopant concentration close to the gate
electrode.
[0005] FIG. 1 illustrates the prior art high electron mobility
transistor with the stepped dopant concentration structure. The
prior art high electron mobility transistor is fabricated on a
semi-insulating substrate 1, which is formed of gallium arsenide.
The prior art high electron mobility transistor comprises a buffer
layer 2, a channel layer 3, an electron supply layer 4/5, cap
layers 8, ohmic electrodes 9 and a gate electrode 10. Gallium
arsenide is epitaxially grown on the semi-insulating substrate 1,
and forms a gallium arsenide layer. The gallium arsenide layer
serves as the buffer layer 2. On the gallium arsenide layer is
epitaxially grown indium gallium arsenide which forms an indium
gallium arsenide layer serving as the channel layer 3.
Heavily-doped n-type aluminum gallium arsenide, i.e.,
n.sup.+Al.sub.0.2Ga.sub.0.8As and lightly-doped n-type aluminum
gallium arsenide, i.e., n.sup.-Al.sub.0.2Ga.sub.0.8As are
successively epitaxially grown to 10 nanometers thick and 20
nanometers thick on the indium gallium arsenide layer, and form a
heavily-doped n-type aluminum gallium arsenide layer 4 and a
lightly doped n-type aluminum gallium arsenide layer 5. The dopant
concentration is 4.times.10.sup.18/cm.sup.3 (4×
10.sup.-18/cm.sup.3) in the heavily-doped n-type aluminum gallium
arsenide layer 4 and 1.times.10.sup.17/cm.sup.3 in the
lightly-doped n-type aluminum gallium arsenide layer 5. The
heavily-doped n-type aluminum gallium arsenide layer 4 and the
lightly-doped n-type aluminum gallium arsenide layer 5 form in
combination the electron supply layer 4/5. The heavily-doped n-type
aluminum gallium arsenide layer 4 is contiguous to the channel
layer 3, and the gate electrode 10 is held in contact with the
lightly-doped n-type aluminum gallium arsenide layer 5. The n-type
dopant concentration is changed at the boundary between the
heavily-doped n-type aluminum gallium arsenide layer 4 and the
lightly-doped n-type aluminum gallium arsenide layer 5. Thus, the
electron supply layer 4/5 has the stepped dopant concentration
structure.
[0006] On the lightly-doped aluminum gallium arsenide layer 5 is
epitaxially grown heavily-doped n-type gallium arsenide from which
forms the cap layers 8 of 80 nanometers thick are formed. The
dopant concentration is 3.times.10.sup.18/cm.sup.3 in the
heavily-doped n-type gallium arsenide layer. Namely, the
heavily-doped n-type gallium arsenide layer is partially etched so
as to expose the electron supply layer 4/5 to a recess between the
cap layers 8. The gate electrode 10 is held in contact with the
exposed portion of the electron supply layer 5. On the other hand,
the ohmic electrodes 9 are held in contact with the cap layers on
both sides of the recess, and serve as a source electrode and a
drain electrode.
[0007] The prior art high electron mobility transistor achieves a
large mutual conductance by virtue of the heavily-doped n-type
aluminum gallium arsenide layer 4 as well as a high withstand
voltage by virtue of the lightly-doped n-type aluminum gallium
arsenide layer 5. However, the threshold voltage and, accordingly,
the amount of channel current are liable to fluctuate among the
products. This is because of the fact that the etchant is liable to
partially remove the lightly-doped n-type aluminum gallium arsenide
layer 5 during the formation of the recess.
[0008] An etching stopper has been proposed as a countermeasure
against the problem. The recess is formed by using mixture of
citric acid and H.sub.2O.sub.2 as wet etchant. Upon completion of
the fabrication process, the prior art high electron mobility
transistor has the structure shown in FIG. 2.
[0009] The prior art high electron mobility transistor is
fabricated on a semi-insulating substrate 1, which is formed of
gallium arsenide. The prior art high electron mobility transistor
comprises a buffer layer 2, a channel layer 3, an electron supply
layer 4/5, etching stopper layers 7, cap layers 8, ohmic electrodes
9 and a gate electrode 10. Gallium arsenide is epitaxially grown on
the semi-insulating substrate 1, and forms a gallium arsenide
layer. The gallium arsenide layer serves as the buffer layer 2. On
the gallium arsenide layer is epitaxially grown indium gallium
arsenide which forms an indium gallium arsenide layer serving as
the channel layer 3. Heavily-doped n-type aluminum gallium
arsenide, i.e., n.sup.+Al.sub.0.2Ga.sub.0 8As and lightly-doped
n-type aluminum gallium arsenide, i.e.,
n.sup.-Al.sub.0.2Ga.sub.0.8As are successively epitaxially grown to
10 nanometers thick and 20 nanometers thick on the indium gallium
arsenide layer, and form a heavily-doped n-type aluminum gallium
arsenide layer 4 and a lightly-doped n-type aluminum gallium
arsenide layer 5. The dopant concentration is
4.times.10.sup.18/cm.sup.3 in the heavily-doped n-type aluminum
gallium arsenide layer 4 and 1.times.10.sup.17/cm.sup.3 in the
lightly-doped n-type aluminum gallium arsenide layer 5. The
heavily-doped n-type aluminum gallium arsenide layer 4 and the
lightly-doped n- type aluminum gallium arsenide layer 5 form in
combination the electron supply layer 4/5. The heavily-doped n-type
aluminum gallium arsenide layer 4 is contiguous to the channel
layer 3, and the gate electrode 10 is held in contact with the
lightly-doped n-type aluminum gallium arsenide layer 5. The n-type
dopant concentration is changed at the boundary between the
heavily-doped n-type aluminum gallium arsenide layer 4 and the
lightly-doped n-type aluminum gallium arsenide layer 5. Thus, the
electron supply layer 4/5 has the stepped dopant concentration
structure.
[0010] On the lightly-doped aluminum gallium arsenide layer 5 is
grown lightly-doped n-type aluminum gallium arsenide
n.sup.-Al.sub.0.7Ga.sub.0.- 3As which forms a lightly-doped n-type
aluminum gallium arsenide layer. The etching stopper layers 7 are
formed from the lightly-doped n-type aluminum gallium arsenide
layer. Heavily-doped n-type gallium arsenide is epitaxially grown
to 80 nanometers thick on the lightly-doped n-type aluminum gallium
arsenide layer 7, and forms a heavily-doped n-type gallium arsenide
layer. The cap layers 8 are formed from the heavily-doped n-type
gallium arsenide layer. The dopant concentration is
3.times.10.sup.18/cm.sup.3 in the heavily-doped n-type gallium
arsenide layer. The heavily-doped n-type gallium arsenide layer 8
and the lightly-doped aluminum gallium arsenide layer 7 are
partially etched so as to expose the electron supply layer 4/5 to a
recess between the cap layers 8. The gate electrode 10 is held in
contact with the exposed portion of the electron supply layer 5. On
the other hand, the ohmic electrodes 9 are held in contact with the
cap layers on both sides of the recess, and serve as a source
electrode and a drain electrode.
[0011] The lightly-doped n-type Al.sub.0.7Ga.sub.0.3As layer 7
gives an end point to the wet etchant in the formation of the
recess, and prevents the lightly doped Al.sub.0.8Ga.sub.0 2As layer
5 from the wet etchant. As a result, the electron supply layer 4/5
is constant in thickness, and the electron supply layer 4/5 keeps
the threshold constant among products.
[0012] However, a problem is encountered in the prior art high
electron mobility transistor shown in FIG. 2 in the high source
resistance.
SUMMARY OF THE INVENTION
[0013] It is therefore an important object of the present invention
to provide a compound semiconductor device, which is reduced in
source resistance without sacrifice of the constant thickness of
the active layer.
[0014] It is also an important object of the present invention to
provide a process for fabricating the compound semiconductor
device.
[0015] The present inventors contemplated the problem inherent in
the prior art high electron mobility transistor shown in FIG. 2,
and noticed that the n.sup.-Al.sub.0.7Ga.sub.0.3As etching stopper
layers 7 were left between the electron supply layer 5 and the cap
layers 8. Aluminum had the large composition ratio in the
n.sup.-Al.sub.0.7Ga.sub.0.3As. The aluminum was a large amount of
dx center, and the dx centers were not activated with the n-type
dopant impurity, i.e., silicon. Even though the silicon was doped
in the Al.sub.0.7Ga.sub.0.3As, a non-ignoreable amount of n-type
dopant impurities were invalid, and the lightly-doped
Al.sub.0.7Ga.sub.0.3As layer exhibited high resistivity. The
present inventors replaced the lightly-doped
n.sup.-Al.sub.0.7Ga.sub.0.3As etching stopper layers 7 with
non-doped etching stopper layers. The high electron mobility
transistor also exhibited large source resistance. The present
inventors concluded that the resistance was to be reduced without
deleting the etching stopper layer was required.
[0016] To accomplish the object, the present invention proposes to
reduce the potential barrier between cap layers and an active layer
by using delta-doped layers.
[0017] In accordance with one aspect of the present invention,
there is provided a compound semiconductor device fabricated on a
substrate comprising a multiple-layered structure including an
active layer, plural cap layers respectively located over plural
portions of the active layer, plural highly-resistive layers formed
between the multiple-layered structure and the plural cap layers so
as to form a recess located over a part of the multiple- layered
structure and between the plural cap layers, plural delta-doped
layers formed between the plural highly-resistive layers and the
multiple- layered structure for decreasing potential barriers of
the plural highly-resistive layers, a first electrode held in
contact with the part of the multiple- layered structure for
controlling the amount of current flowing through the active layer,
and second electrodes respectively formed on the plural cap layers
for providing current paths from and to the active layer through
the plural cap layers, the plural highly-resistive layers and the
plural delta-doped layers.
[0018] In accordance with another aspect of the present invention,
there is provided a process for fabricating a compound
semiconductor device comprising the steps of a) producing a
multiple-layered structure having an active layer, a delta-doped
layer over the active layer, a highly resistive layer over the
delta-doped layer and a highly conductive layer over the
delta-doped layer on a semi-insulating substrate, b) removing a
part of the highly conductive layer so as to expose a part of the
highly resistive layer to a first opening formed between remaining
portions of the highly conductive layer serving as plural cap
layers, c) removing the part of the highly resistive layer and a
part of the delta-doped layer thereunder so as to expose a part of
the active layer to a second opening formed between plural delta
doped layers respectively overlain by highly resistive layers and
d) completing a compound semiconductor device having a first
electrode held in contact with the part of the active layer and
second electrodes respectively held in contact with the plural cap
layers.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The features and advantages of the compound semiconductor
device and the fabrication process will be more clearly understood
from the following description taken in conjunction with the
accompanying drawings in which:
[0020] FIG. 1 is a cross sectional view showing the prior art high
electron mobility transistor with the stepped dopant concentration
structure;
[0021] FIG. 2 is a cross sectional view showing the prior art high
electron mobility transistor with the etching stopper between the
electron supply layer and the cap layers;
[0022] FIG. 3 is a cross sectional view showing the structure of a
high electron mobility transistor according to the present
invention;
[0023] FIGS. 4 is an energy band diagram showing the energy band
created in the high electron mobility transistor;
[0024] FIGS. 5A to 5C are cross sectional views showing a process
for fabricating the high electron mobility transistor according to
the present invention;
[0025] FIG. 6 is a cross sectional view showing the structure of a
heterojunction metal-semiconductor field effect transistor
according to the present invention; and
[0026] FIGS. 7A to 7D are cross sectional views showing a process
for fabricating the heterojunction metal-semiconductor field effect
transistor according to the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0027] First Embodiment
[0028] Referring to FIG. 3 of the drawings, a high electron
mobility transistor embodying the present invention is fabricated
on a semi- insulating substrate 1 of gallium arsenide. The high
electron mobility transistor comprises a buffer layer 2, a channel
layer 3, an electron supply layer 4/5, delta doped layers 6,
etching stopper layers 7, cap layers 8, ohmic electrodes 9 and a
gate electrode 10. The delta doped layers are referred to as
"planar dope layer" or "pulse dope layer" in several articles. In
other words, the term "delta doped layer" is synonymous with the
term "planar dope layer" and the term "pulse dope layer". The delta
doped layers 6 are hereinlater described in detail.
[0029] The buffer layer 2 is formed of gallium arsenide epitaxially
grown on the semi-insulating substrate 1 of gallium arsenide. The
channel layer 3 is formed of indium gallium arsenide epitaxially
grown on the gallium arsenide buffer layer 2. The electron supply
layer 4/5 has the stepped dopant concentration structure, and the
stepped dopant concentration structure is implemented by a
heavily-doped n-type aluminum gallium arsenide layer 4 and a
lightly-doped n-type aluminum gallium arsenide layer 5. The
heavily-doped n- type aluminum gallium arsenide and the
lightly-doped n-type aluminum gallium arsenide have the composition
expressed as Al.sub.0.2Ga.sub.0.8As. The heavily-doped n-type
aluminum gallium arsenide layer 4 is 10 nanometers thick, and the
dopant concentration is 4.times.10.sup.18/cm.sup.3 in the
heavily-doped n-type aluminum gallium arsenide layer 4. On the
other hand, the lightly-doped n-type aluminum gallium arsenide
layer 5 is 20 nanometers thick, and the dopant concentration is
1.times.10.sup.17/cm.sup.3 in the lightly-doped n-type aluminum
gallium arsenide layer 5.
[0030] The delta doped layers 6 are formed by supplying Group-V
element, i.e., arsenic (As) and silicon, only, and are as thin as a
single atom to several atoms. The silicon is delta doped. For this
reason, the dopant impurity, i.e., silicon is heavily contained in
the delta doped layer 6. The dopant impurity concentration of the
delta-doped layers 6 are heavier than that of the electron supply
layer. In this instance, the delta doped layers 6 contain the
silicon at 6.times.10.sup.12/cm.sup.2. The delta doped layers 6
contain only one kind of dopant impurity so that the tunneling
phenomenon takes place at the boundaries. For this reason, the
carriers can pass a potential barrier larger in height than the
energy thereof.
[0031] The etching stopper layers 7 are formed of lightly-doped
aluminum gallium arsenide epitaxially grown on the delta doped
layers 6. The lightly-doped aluminum gallium arsenide is different
in composition from that of the electron supply layer 4/5, and is
expressed as Al.sub.0.7Ga.sub.0.3As. Although silicon is lightly
doped into the aluminum gallium arsenide Al.sub.0.7Ga.sub.0.3As,
the aluminum gallium arsenide Al.sub.0.7Ga.sub.0.3As contains a
large amount of dx centers, and the dx centers deactivate the
silicon. For this reason, the effective carrier density is
drastically decreased in the aluminum gallium arsenide etching
stopper layers 7.
[0032] The cap layers 8 are formed from a heavily-doped n-type
gallium arsenide layer epitaxially grown on the aluminum gallium
arsenide etching stopper layers 7. The cap layers 8 are 80
nanometers thick, and the dopant concentration is
3.times.10.sup.18/cm.sup.3.
[0033] The heavily-doped n-type gallium arsenide layer 8, the
lightly-doped aluminum gallium arsenide layer 7 and the delta doped
layer 6 are partially etched away so that the electron supply layer
5 is exposed to a recess between the cap layers 8. The ohmic
electrodes 9 are held in contact with the cap layers 8, and the
gate electrode 10 is held in contact with the lightly-doped
aluminum gallium arsenide layer 5 of the electron supply layer.
[0034] The energy band shown in FIG. 4 is created in the high
electron mobility transistor according to the present invention. If
the delta doped layers 6 are not inserted between the electron
supply layer 4/5 and the etching stopper layers, the bottom edge of
conduction band is represented by broken line. The potential
barriers between the cap layers 8 and the etching stopper layers 7
and between the etching stopper layers 7 and the electron supply
layer 5 are wide. The delta doped layers 6 make the potential level
of the etching stopper layers 7 lower. The potential barriers
between the cap layers 8 and the etching stopper layers 7 and
between the etching stopper layers 7 and the electron supply layer
5 are made narrow. As a result, the carriers or electrons are
smoothly moved between the ohmic electrodes 9 and the channel layer
3, and, accordingly, the resistance is decreased.
[0035] The etching stopper 7 keeps the electron supply layer 4/5
constant in thickness among the products. The electron supply layer
4/5 with constant thickness is effective against the fluctuation of
threshold voltage. Thus, the high electron mobility transistor
according to the present invention achieves the low resistance
without sacrifice of the constant thickness of the electron supply
layer 4/5.
[0036] The high electron mobility transistor shown in FIG. 3 is
fabricated through a process shown in FIGS. 5A to 5C. In the
following description, compound semiconductor layers are labeled
with the references designating the layers of the high electron
mobility transistor shown in FIG. 3.
[0037] The process starts with preparation of the semi- insulating
substrate 1. The gallium arsenide layer 2, the indium gallium
arsenide layer 3, the heavily-doped aluminum gallium arsenide layer
4, the lightly-doped aluminum gallium arsenide layer 5, the delta
doped layers 6, the aluminum gallium arsenide layer 7 and the
heavily-doped gallium arsenide layer 8 are epitaxially grown on the
semi-insulating substrate 1 in succession. Nickel-gold-germanium
alloy Ni/AuGe is grown on the heavily-doped gallium arsenide layer
8, and the ohmic electrodes 9 are formed from the nickel-gold-
germanium alloy layer. The resultant semiconductor structure in
this stage is shown in FIG. 5A.
[0038] Subsequently, a photo-resist mask 11 is provided on the
resultant semiconductor structure by using a photo- lithography.
Namely, photo-resist solution is spread over the resultant
semiconductor structure, and is baked so as to form a photo-resist
layer. A pattern image is transferred from a photo-mask to the
photo-resist layer so as to produce a latent image in the
photoresist layer. The latent image is developed. Then, the
photo-resist mask 11 is left on the resultant semiconductor
structure. A part of the heavily-doped gallium arsenide layer 8 is
exposed to the opening formed in the photo-resist mask 11. Using
wet etchant containing citric acid and hydrogen peroxide
H.sub.2O.sub.2, the heavily-doped gallium arsenide layer 8 is
partially removed. Since the wet etchant has the selectivity larger
to the gallium arsenide than to the lightly-doped n-type aluminum
gallium arsenide Al.sub.0.7Ga.sub.0.3As, the wet etching is
terminated on the lightly-doped n- type aluminum gallium arsenide
Al.sub.0.7Ga.sub.0.3As layer 7, and a recess 12 is formed in the
heavily-doped n-type gallium arsenide layer 8 as shown in FIG. 5B.
Thus, the lightly-doped n-type aluminum gallium arsenide
Al.sub.0.7Ga.sub.0.3As layer 7 serves as an etching stopper. While
the lightly.-doped n- type aluminum gallium arsenide
Al.sub.0.7Ga.sub.0.3As layer 7 is being etched with the wet
etchant, the exposed portion of the lightly-doped n-type aluminum
gallium arsenide Al.sub.0.7Ga.sub.0.3As etching stopper layer 7 is
oxidized, and aluminum oxide Al.sub.2O.sub.3 is left on the
delta-doped layers 6.
[0039] As described hereinbefore, the lightly-doped n- type
aluminum gallium arsenide Al.sub.0.7Ga.sub.0.3As layer 7 contains a
large amount of dx centers. For this reason, the dopant impurity,
i.e., silicon atoms are hardly activated, and the actual carrier
concentration is drastically reduced. This means that the
lightly-doped n-type aluminum gallium arsenide
Al.sub.0.7Ga.sub.0.3As layer 7 is highly resistive.
[0040] The aluminum oxide layer and the delta-doped layers 6 under
the aluminum oxide layer are etched away by using hydrochloric
acid. The lightly-doped n-type aluminum gallium arsenide layer 5 is
hardly etched so that the high electron mobility transistor is
constant in threshold and the amount of channel current among
products. Finally, titanium- aluminum alloy is deposited over the
entire surface by using an evaporation technique, and the
photo-resist mask 11 is stripped off together with the
titanium-aluminum alloy deposited thereover. The gate electrode 10
is left on the electron supply layer 4/5 as shown in FIG. 5C.
[0041] As will be understood from the foregoing description, the
potential barrier of the etching stopper layer 7 is lowered by
virtue of the delta-doped layers 6, and the resistance between the
ohmic electrodes 9 and the electron supply layer 4/5 is decreased.
As a result, the source resistance of the high electron mobility
transistor is reduced, and the high-frequency characteristics such
as, for example, the noise factor and the gain are improved.
[0042] The delta-doped layers are removed from the upper surface of
the electron supply layer 4/5 exposed to the recess 12. This means
that the gate electrode 10 is directly held in contact with the
electron supply layer 4/5. This results in a small amount of gate
leakage current and a high gate-and-drain withstand voltage.
[0043] In the first embodiment, the channel layer 3 and the
electron supply layer 4/5 as a whole constitute an active
layer.
[0044] Second Embodiment
[0045] FIG. 6 illustrates another high electron mobility transistor
embodying the present invention. The high electron mobility
transistor is fabricated on a semi- insulating substrate 1 of
gallium arsenide. The high electron mobility transistor comprises a
buffer layer 2, a channel layer 3, an electron supply layer 4a,
delta doped layers 6, undoped gallium arsenide layer 7a, cap layers
8, ohmic electrodes 9, a gate electrode 10 and a protective layer
14.
[0046] The buffer layer 2 is formed of gallium arsenide epitaxially
grown on the semi-insulating substrate 1 of gallium arsenide. The
channel layer 3 is formed of indium gallium arsenide epitaxially
grown on the gallium arsenide buffer layer 2. The electron supply
layer 4a is formed of n-type gallium arsenide, and the dopant
concentration is 1.times.10.sup.18/cm.su- p.3 in the n-type gallium
arsenide electron supply layer 4a. The n-type gallium arsenide
electron supply layer 4a is 30 nanometers thick.
[0047] The delta doped layers 6 are similar to those of the first
embodiment, and no further description is incorporated hereinbelow
for avoiding repetition. The undoped gallium arsenide layers 7a are
20 nanometers thick. An etching stopper layer may be inserted
between the cap layers 8 and the undoped gallium arsenide layers
7a.
[0048] The cap layers 8 are formed from a heavily-doped n-type
gallium arsenide layer epitaxially grown on the undoped gallium
arsenide layers 7a. The cap layers 8 are 80 nanometers thick, and
the dopant concentration is 3.times.10.sup.18/cm.sup.3.
[0049] The heavily-doped n-type gallium arsenide layer 8, the
undoped gallium arsenide layer 7a and the delta doped layer 6 are
partially removed, and a part of the n-type gallium arsenide layer
4a is exposed to a recess between the undoped gallium arsenide
layers 7a. The ohmic electrodes 9 are held in contact with the cap
layers 8, and the gate electrode 10 is held in contact with the
n-type gallium arsenide electron supply layer 4a. The protective
layer 14 is formed of silicon dioxide, and fills an upper portion
of the recess.
[0050] The high electron mobility transistor is fabricated as
follows. The process starts with preparation of the semi-insulating
substrate 1. The gallium arsenide layer 2, the indium gallium
arsenide layer 3, the n-type gallium arsenide layer 4a, the delta
doped layer 6, the undoped gallium arsenide layer 7a and the
heavily-doped n-type gallium arsenide layer 8 are enitaxially grown
on the major surface of the semi-insulating substrate 1.
[0051] A photo-resist etching mask 11a is formed on the
heavily-doped n-type gallium arsenide layer 8 through the
photo-lithographic techniques. Using the photo-resist etching mask
11a, the heavily-doped n- type gallium arsenide layer 8 is
partially etched away, and a wide recess 12a takes place in the
heavily-doped n- type gallium arsenide layer 8. The remaining
portions of the heavily-doped n-type gallium arsenide layer 8 serve
as the cap layers 8. The resultant semiconductor structure is shown
in FIG. 7A. In the case where the etching stopper layer of aluminum
gallium arsenide layer is inserted between the undoped gallium
arsenide layer 7a and the heavily-doped n-type gallium arsenide
layer 8, the etching is exactly terminated at the etching stopper
layer.
[0052] Silicon dioxide is deposited over the entire surface of the
resultant semiconductor structure by using a chemical vapor
deposition. The silicon dioxide forms a silicon dioxide layer 14. A
photo-resist etching mask (not shown) is formed on the silicon
dioxide layer 14, and has an opening over the n-type gallium
arsenide layer where the gate electrode 10 is to be formed. Using
the photo-resist etching mask, the silicon dioxide layer is
partially etched away, and a gate opening 15 is formed in the
silicon dioxide layer 14 as shown in FIG. 7B.
[0053] Subsequently, the undoped gallium arsenide layer 7a and the
delta-doped layer 6 are partially etched away by using the
photo-resist etching mask. This results in a gate recess 12b, and
the part of the n-type gallium arsenide electron supply layer 4a is
exposed to the gate recess 12b as shown in FIG. 7C.
[0054] WSi--TiN--Pt--Au alloy is deposited over the entire surface
of the resultant semiconductor structure by using a sputtering
technique, and the alloy is patterned into the gate electrode 10 by
using the photo- lithographic techniques followed by an etching.
Finally, the ohmic electrodes 9 of Ni--AuGe alloy is formed on the
cap layers 8, and the high electron mobility transistor is obtained
as shown in FIG. 7D.
[0055] As similar to the high electron mobility transistor
implementing the first embodiment, the delta-doped layers 6 lower
the potential barriers of the undoped gallium arsenide layers 7a,
and decrease the resistance between the channel layer 3 and the
ohmic electrodes 9. Even though the delta-doped layers 6 are
inserted between the undoped gallium arsenide layers 7a and the
n-type gallium arsenide electron supply layer 4a, the gate
electrode 10 is directly held in contact with the n-type gallium
arsenide electron supply layer 4a. For this reason, the leakage
current is not increased, and the gate-and-drain withstand voltage
(BVgd) is not lowered.
[0056] Although particular embodiments of the present invention
have been shown and described, it will be apparent to those skilled
in the art that various changes and modifications may be made
without departing from the spirit and scope of the present
invention.
[0057] In the first embodiment, the etching stopper layers 7 are
formed of Al.sub.0.7Ga.sub.0.3As. The composition ratio of aluminum
is allowed to be different from 0.7 in so far as the aluminum
gallium arsenide gives the end point to the etchant.
[0058] A dry etching technique is available for the step for
patterning the heavily-doped n-type gallium arsenide layer 8. The
heavily-doped n-type gallium arsenide layer 8 may be patterned by
using another kind of etchant such as, for example, gaseous mixture
of BCl.sub.3 and SF.sub.6 or another kind of gaseous mixture of
SiCl.sub.4 and SF.sub.6.
[0059] The metal-semiconductor field effect transistor implementing
the first embodiment may not be equipped with any electron supply
layer. The standard metal-semiconductor field effect transistor may
have the structure comprising a gallium arsenide buffer layer 2, an
n.sup.+Al.sub.0.2Ga.sub.0.8As /n.sup.-Al.sub.0.2Ga.sub.0.8As
channel layer 4/5, delta doped layers 6,
n.sup.-Al.sub.0.7Ga.sub.0.3As etching stopper layers 7 and
n.sup.+GaAs cap layers 8. The standard metal- semiconductor field
effect transistor may be categorized in the metal-semiconductor
Schottky field effect transistor. The metal-semiconductor Schottky
field effect transistor may comprise a gallium arsenide buffer
layer 2, an n.sup.+Al.sub.0.2Ga.sub.0.8As
/n.sup.-Al.sub.0.2Ga.sub.0 8As channel layer 4/5, delta doped
layers 6, n.sup.-Al.sub.0.7Ga.sub.0.3As etching stopper layers 7
and n.sup.+GaAs cap layers 8.
[0060] The undoped gallium arsenide layer 7a may be replaced with
another kind of undoped compound semiconductor layer such as, for
example, undoped aluminum gallium arsenide layer or undoped indium
gallium arsenide layer.
* * * * *